?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge 3.1-rc1 into usb-linus
[zen-stable.git] / drivers / video / omap2 / dss / dsi.c
blob7adbbeb84334f3a9ec857c8f7d00b394b2082f6c
1 /*
2 * linux/drivers/video/omap2/dss/dsi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #define DSS_SUBSYS_NAME "DSI"
21
22 #include <linux/kernel.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/semaphore.h>
31 #include <linux/seq_file.h>
32 #include <linux/platform_device.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/wait.h>
35 #include <linux/workqueue.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
38 #include <linux/debugfs.h>
39 #include <linux/pm_runtime.h>
40
41 #include <video/omapdss.h>
42 #include <plat/clock.h>
43
44 #include "dss.h"
45 #include "dss_features.h"
46
47 /*#define VERBOSE_IRQ*/
48 #define DSI_CATCH_MISSING_TE
49
50 struct dsi_reg { u16 idx; };
51
52 #define DSI_REG(idx) ((const struct dsi_reg) { idx })
53
54 #define DSI_SZ_REGS SZ_1K
55 /* DSI Protocol Engine */
56
57 #define DSI_REVISION DSI_REG(0x0000)
58 #define DSI_SYSCONFIG DSI_REG(0x0010)
59 #define DSI_SYSSTATUS DSI_REG(0x0014)
60 #define DSI_IRQSTATUS DSI_REG(0x0018)
61 #define DSI_IRQENABLE DSI_REG(0x001C)
62 #define DSI_CTRL DSI_REG(0x0040)
63 #define DSI_GNQ DSI_REG(0x0044)
64 #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
65 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
66 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
67 #define DSI_CLK_CTRL DSI_REG(0x0054)
68 #define DSI_TIMING1 DSI_REG(0x0058)
69 #define DSI_TIMING2 DSI_REG(0x005C)
70 #define DSI_VM_TIMING1 DSI_REG(0x0060)
71 #define DSI_VM_TIMING2 DSI_REG(0x0064)
72 #define DSI_VM_TIMING3 DSI_REG(0x0068)
73 #define DSI_CLK_TIMING DSI_REG(0x006C)
74 #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
75 #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
76 #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
77 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
78 #define DSI_VM_TIMING4 DSI_REG(0x0080)
79 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
80 #define DSI_VM_TIMING5 DSI_REG(0x0088)
81 #define DSI_VM_TIMING6 DSI_REG(0x008C)
82 #define DSI_VM_TIMING7 DSI_REG(0x0090)
83 #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
84 #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
85 #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
86 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
87 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
88 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
89 #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
90 #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
91
92 /* DSIPHY_SCP */
93
94 #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
95 #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
96 #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
97 #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
98 #define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028)
99
100 /* DSI_PLL_CTRL_SCP */
101
102 #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
103 #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
104 #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
105 #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
106 #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
107
108 #define REG_GET(dsidev, idx, start, end) \
109 FLD_GET(dsi_read_reg(dsidev, idx), start, end)
110
111 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
112 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
113
114 /* Global interrupts */
115 #define DSI_IRQ_VC0 (1 << 0)
116 #define DSI_IRQ_VC1 (1 << 1)
117 #define DSI_IRQ_VC2 (1 << 2)
118 #define DSI_IRQ_VC3 (1 << 3)
119 #define DSI_IRQ_WAKEUP (1 << 4)
120 #define DSI_IRQ_RESYNC (1 << 5)
121 #define DSI_IRQ_PLL_LOCK (1 << 7)
122 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
123 #define DSI_IRQ_PLL_RECALL (1 << 9)
124 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
125 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
126 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
127 #define DSI_IRQ_TE_TRIGGER (1 << 16)
128 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
129 #define DSI_IRQ_SYNC_LOST (1 << 18)
130 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
131 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
132 #define DSI_IRQ_ERROR_MASK \
133 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
134 DSI_IRQ_TA_TIMEOUT)
135 #define DSI_IRQ_CHANNEL_MASK 0xf
136
137 /* Virtual channel interrupts */
138 #define DSI_VC_IRQ_CS (1 << 0)
139 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
140 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
141 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
142 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
143 #define DSI_VC_IRQ_BTA (1 << 5)
144 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
145 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
146 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
147 #define DSI_VC_IRQ_ERROR_MASK \
148 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
149 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
150 DSI_VC_IRQ_FIFO_TX_UDF)
151
152 /* ComplexIO interrupts */
153 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
154 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
155 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
156 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
157 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
158 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
159 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
160 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
161 #define DSI_CIO_IRQ_ERRESC4 (1 << 8)
162 #define DSI_CIO_IRQ_ERRESC5 (1 << 9)
163 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
164 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
165 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
166 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
167 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
168 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
169 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
170 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
171 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
172 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
173 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
174 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
175 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
176 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
177 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
178 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
179 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
180 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
181 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
182 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
183 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
184 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
185 #define DSI_CIO_IRQ_ERROR_MASK \
186 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
187 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
188 DSI_CIO_IRQ_ERRSYNCESC5 | \
189 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
190 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
191 DSI_CIO_IRQ_ERRESC5 | \
192 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
193 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
194 DSI_CIO_IRQ_ERRCONTROL5 | \
195 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
196 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
197 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
198 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
199 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
200
201 #define DSI_DT_DCS_SHORT_WRITE_0 0x05
202 #define DSI_DT_DCS_SHORT_WRITE_1 0x15
203 #define DSI_DT_DCS_READ 0x06
204 #define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37
205 #define DSI_DT_NULL_PACKET 0x09
206 #define DSI_DT_DCS_LONG_WRITE 0x39
207
208 #define DSI_DT_RX_ACK_WITH_ERR 0x02
209 #define DSI_DT_RX_DCS_LONG_READ 0x1c
210 #define DSI_DT_RX_SHORT_READ_1 0x21
211 #define DSI_DT_RX_SHORT_READ_2 0x22
212
213 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
214
215 #define DSI_MAX_NR_ISRS 2
216
217 struct dsi_isr_data {
218 omap_dsi_isr_t isr;
219 void *arg;
220 u32 mask;
221 };
222
223 enum fifo_size {
224 DSI_FIFO_SIZE_0 = 0,
225 DSI_FIFO_SIZE_32 = 1,
226 DSI_FIFO_SIZE_64 = 2,
227 DSI_FIFO_SIZE_96 = 3,
228 DSI_FIFO_SIZE_128 = 4,
229 };
230
231 enum dsi_vc_mode {
232 DSI_VC_MODE_L4 = 0,
233 DSI_VC_MODE_VP,
234 };
235
236 enum dsi_lane {
237 DSI_CLK_P = 1 << 0,
238 DSI_CLK_N = 1 << 1,
239 DSI_DATA1_P = 1 << 2,
240 DSI_DATA1_N = 1 << 3,
241 DSI_DATA2_P = 1 << 4,
242 DSI_DATA2_N = 1 << 5,
243 DSI_DATA3_P = 1 << 6,
244 DSI_DATA3_N = 1 << 7,
245 DSI_DATA4_P = 1 << 8,
246 DSI_DATA4_N = 1 << 9,
247 };
248
249 struct dsi_update_region {
250 u16 x, y, w, h;
251 struct omap_dss_device *device;
252 };
253
254 struct dsi_irq_stats {
255 unsigned long last_reset;
256 unsigned irq_count;
257 unsigned dsi_irqs[32];
258 unsigned vc_irqs[4][32];
259 unsigned cio_irqs[32];
260 };
261
262 struct dsi_isr_tables {
263 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
264 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
265 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
266 };
267
268 struct dsi_data {
269 struct platform_device *pdev;
270 void __iomem *base;
271
272 int irq;
273
274 struct clk *dss_clk;
275 struct clk *sys_clk;
276
277 void (*dsi_mux_pads)(bool enable);
278
279 struct dsi_clock_info current_cinfo;
280
281 bool vdds_dsi_enabled;
282 struct regulator *vdds_dsi_reg;
283
284 struct {
285 enum dsi_vc_mode mode;
286 struct omap_dss_device *dssdev;
287 enum fifo_size fifo_size;
288 int vc_id;
289 } vc[4];
290
291 struct mutex lock;
292 struct semaphore bus_lock;
293
294 unsigned pll_locked;
295
296 spinlock_t irq_lock;
297 struct dsi_isr_tables isr_tables;
298 /* space for a copy used by the interrupt handler */
299 struct dsi_isr_tables isr_tables_copy;
300
301 int update_channel;
302 struct dsi_update_region update_region;
303
304 bool te_enabled;
305 bool ulps_enabled;
306
307 void (*framedone_callback)(int, void *);
308 void *framedone_data;
309
310 struct delayed_work framedone_timeout_work;
311
312 #ifdef DSI_CATCH_MISSING_TE
313 struct timer_list te_timer;
314 #endif
315
316 unsigned long cache_req_pck;
317 unsigned long cache_clk_freq;
318 struct dsi_clock_info cache_cinfo;
319
320 u32 errors;
321 spinlock_t errors_lock;
322 #ifdef DEBUG
323 ktime_t perf_setup_time;
324 ktime_t perf_start_time;
325 #endif
326 int debug_read;
327 int debug_write;
328
329 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
330 spinlock_t irq_stats_lock;
331 struct dsi_irq_stats irq_stats;
332 #endif
333 /* DSI PLL Parameter Ranges */
334 unsigned long regm_max, regn_max;
335 unsigned long regm_dispc_max, regm_dsi_max;
336 unsigned long fint_min, fint_max;
337 unsigned long lpdiv_max;
338
339 int num_data_lanes;
340
341 unsigned scp_clk_refcount;
342 };
343
344 struct dsi_packet_sent_handler_data {
345 struct platform_device *dsidev;
346 struct completion *completion;
347 };
348
349 static struct platform_device *dsi_pdev_map[MAX_NUM_DSI];
350
351 #ifdef DEBUG
352 static unsigned int dsi_perf;
353 module_param_named(dsi_perf, dsi_perf, bool, 0644);
354 #endif
355
356 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
357 {
358 return dev_get_drvdata(&dsidev->dev);
359 }
360
361 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
362 {
363 return dsi_pdev_map[dssdev->phy.dsi.module];
364 }
365
366 struct platform_device *dsi_get_dsidev_from_id(int module)
367 {
368 return dsi_pdev_map[module];
369 }
370
371 static int dsi_get_dsidev_id(struct platform_device *dsidev)
372 {
373 /* TEMP: Pass 0 as the dsi module index till the time the dsi platform
374 * device names aren't changed to the form "omapdss_dsi.0",
375 * "omapdss_dsi.1" and so on */
376 BUG_ON(dsidev->id != -1);
377
378 return 0;
379 }
380
381 static inline void dsi_write_reg(struct platform_device *dsidev,
382 const struct dsi_reg idx, u32 val)
383 {
384 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
385
386 __raw_writel(val, dsi->base + idx.idx);
387 }
388
389 static inline u32 dsi_read_reg(struct platform_device *dsidev,
390 const struct dsi_reg idx)
391 {
392 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
393
394 return __raw_readl(dsi->base + idx.idx);
395 }
396
397 void dsi_bus_lock(struct omap_dss_device *dssdev)
398 {
399 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
400 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
401
402 down(&dsi->bus_lock);
403 }
404 EXPORT_SYMBOL(dsi_bus_lock);
405
406 void dsi_bus_unlock(struct omap_dss_device *dssdev)
407 {
408 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
409 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
410
411 up(&dsi->bus_lock);
412 }
413 EXPORT_SYMBOL(dsi_bus_unlock);
414
415 static bool dsi_bus_is_locked(struct platform_device *dsidev)
416 {
417 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
418
419 return dsi->bus_lock.count == 0;
420 }
421
422 static void dsi_completion_handler(void *data, u32 mask)
423 {
424 complete((struct completion *)data);
425 }
426
427 static inline int wait_for_bit_change(struct platform_device *dsidev,
428 const struct dsi_reg idx, int bitnum, int value)
429 {
430 int t = 100000;
431
432 while (REG_GET(dsidev, idx, bitnum, bitnum) != value) {
433 if (--t == 0)
434 return !value;
435 }
436
437 return value;
438 }
439
440 #ifdef DEBUG
441 static void dsi_perf_mark_setup(struct platform_device *dsidev)
442 {
443 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
444 dsi->perf_setup_time = ktime_get();
445 }
446
447 static void dsi_perf_mark_start(struct platform_device *dsidev)
448 {
449 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
450 dsi->perf_start_time = ktime_get();
451 }
452
453 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
454 {
455 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
456 ktime_t t, setup_time, trans_time;
457 u32 total_bytes;
458 u32 setup_us, trans_us, total_us;
459
460 if (!dsi_perf)
461 return;
462
463 t = ktime_get();
464
465 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
466 setup_us = (u32)ktime_to_us(setup_time);
467 if (setup_us == 0)
468 setup_us = 1;
469
470 trans_time = ktime_sub(t, dsi->perf_start_time);
471 trans_us = (u32)ktime_to_us(trans_time);
472 if (trans_us == 0)
473 trans_us = 1;
474
475 total_us = setup_us + trans_us;
476
477 total_bytes = dsi->update_region.w *
478 dsi->update_region.h *
479 dsi->update_region.device->ctrl.pixel_size / 8;
480
481 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
482 "%u bytes, %u kbytes/sec\n",
483 name,
484 setup_us,
485 trans_us,
486 total_us,
487 1000*1000 / total_us,
488 total_bytes,
489 total_bytes * 1000 / total_us);
490 }
491 #else
492 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
493 {
494 }
495
496 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
497 {
498 }
499
500 static inline void dsi_perf_show(struct platform_device *dsidev,
501 const char *name)
502 {
503 }
504 #endif
505
506 static void print_irq_status(u32 status)
507 {
508 if (status == 0)
509 return;
510
511 #ifndef VERBOSE_IRQ
512 if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
513 return;
514 #endif
515 printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
516
517 #define PIS(x) \
518 if (status & DSI_IRQ_##x) \
519 printk(#x " ");
520 #ifdef VERBOSE_IRQ
521 PIS(VC0);
522 PIS(VC1);
523 PIS(VC2);
524 PIS(VC3);
525 #endif
526 PIS(WAKEUP);
527 PIS(RESYNC);
528 PIS(PLL_LOCK);
529 PIS(PLL_UNLOCK);
530 PIS(PLL_RECALL);
531 PIS(COMPLEXIO_ERR);
532 PIS(HS_TX_TIMEOUT);
533 PIS(LP_RX_TIMEOUT);
534 PIS(TE_TRIGGER);
535 PIS(ACK_TRIGGER);
536 PIS(SYNC_LOST);
537 PIS(LDO_POWER_GOOD);
538 PIS(TA_TIMEOUT);
539 #undef PIS
540
541 printk("\n");
542 }
543
544 static void print_irq_status_vc(int channel, u32 status)
545 {
546 if (status == 0)
547 return;
548
549 #ifndef VERBOSE_IRQ
550 if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
551 return;
552 #endif
553 printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
554
555 #define PIS(x) \
556 if (status & DSI_VC_IRQ_##x) \
557 printk(#x " ");
558 PIS(CS);
559 PIS(ECC_CORR);
560 #ifdef VERBOSE_IRQ
561 PIS(PACKET_SENT);
562 #endif
563 PIS(FIFO_TX_OVF);
564 PIS(FIFO_RX_OVF);
565 PIS(BTA);
566 PIS(ECC_NO_CORR);
567 PIS(FIFO_TX_UDF);
568 PIS(PP_BUSY_CHANGE);
569 #undef PIS
570 printk("\n");
571 }
572
573 static void print_irq_status_cio(u32 status)
574 {
575 if (status == 0)
576 return;
577
578 printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
579
580 #define PIS(x) \
581 if (status & DSI_CIO_IRQ_##x) \
582 printk(#x " ");
583 PIS(ERRSYNCESC1);
584 PIS(ERRSYNCESC2);
585 PIS(ERRSYNCESC3);
586 PIS(ERRESC1);
587 PIS(ERRESC2);
588 PIS(ERRESC3);
589 PIS(ERRCONTROL1);
590 PIS(ERRCONTROL2);
591 PIS(ERRCONTROL3);
592 PIS(STATEULPS1);
593 PIS(STATEULPS2);
594 PIS(STATEULPS3);
595 PIS(ERRCONTENTIONLP0_1);
596 PIS(ERRCONTENTIONLP1_1);
597 PIS(ERRCONTENTIONLP0_2);
598 PIS(ERRCONTENTIONLP1_2);
599 PIS(ERRCONTENTIONLP0_3);
600 PIS(ERRCONTENTIONLP1_3);
601 PIS(ULPSACTIVENOT_ALL0);
602 PIS(ULPSACTIVENOT_ALL1);
603 #undef PIS
604
605 printk("\n");
606 }
607
608 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
609 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
610 u32 *vcstatus, u32 ciostatus)
611 {
612 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
613 int i;
614
615 spin_lock(&dsi->irq_stats_lock);
616
617 dsi->irq_stats.irq_count++;
618 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
619
620 for (i = 0; i < 4; ++i)
621 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
622
623 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
624
625 spin_unlock(&dsi->irq_stats_lock);
626 }
627 #else
628 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
629 #endif
630
631 static int debug_irq;
632
633 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
634 u32 *vcstatus, u32 ciostatus)
635 {
636 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
637 int i;
638
639 if (irqstatus & DSI_IRQ_ERROR_MASK) {
640 DSSERR("DSI error, irqstatus %x\n", irqstatus);
641 print_irq_status(irqstatus);
642 spin_lock(&dsi->errors_lock);
643 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
644 spin_unlock(&dsi->errors_lock);
645 } else if (debug_irq) {
646 print_irq_status(irqstatus);
647 }
648
649 for (i = 0; i < 4; ++i) {
650 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
651 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
652 i, vcstatus[i]);
653 print_irq_status_vc(i, vcstatus[i]);
654 } else if (debug_irq) {
655 print_irq_status_vc(i, vcstatus[i]);
656 }
657 }
658
659 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
660 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
661 print_irq_status_cio(ciostatus);
662 } else if (debug_irq) {
663 print_irq_status_cio(ciostatus);
664 }
665 }
666
667 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
668 unsigned isr_array_size, u32 irqstatus)
669 {
670 struct dsi_isr_data *isr_data;
671 int i;
672
673 for (i = 0; i < isr_array_size; i++) {
674 isr_data = &isr_array[i];
675 if (isr_data->isr && isr_data->mask & irqstatus)
676 isr_data->isr(isr_data->arg, irqstatus);
677 }
678 }
679
680 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
681 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
682 {
683 int i;
684
685 dsi_call_isrs(isr_tables->isr_table,
686 ARRAY_SIZE(isr_tables->isr_table),
687 irqstatus);
688
689 for (i = 0; i < 4; ++i) {
690 if (vcstatus[i] == 0)
691 continue;
692 dsi_call_isrs(isr_tables->isr_table_vc[i],
693 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
694 vcstatus[i]);
695 }
696
697 if (ciostatus != 0)
698 dsi_call_isrs(isr_tables->isr_table_cio,
699 ARRAY_SIZE(isr_tables->isr_table_cio),
700 ciostatus);
701 }
702
703 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
704 {
705 struct platform_device *dsidev;
706 struct dsi_data *dsi;
707 u32 irqstatus, vcstatus[4], ciostatus;
708 int i;
709
710 dsidev = (struct platform_device *) arg;
711 dsi = dsi_get_dsidrv_data(dsidev);
712
713 spin_lock(&dsi->irq_lock);
714
715 irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
716
717 /* IRQ is not for us */
718 if (!irqstatus) {
719 spin_unlock(&dsi->irq_lock);
720 return IRQ_NONE;
721 }
722
723 dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
724 /* flush posted write */
725 dsi_read_reg(dsidev, DSI_IRQSTATUS);
726
727 for (i = 0; i < 4; ++i) {
728 if ((irqstatus & (1 << i)) == 0) {
729 vcstatus[i] = 0;
730 continue;
731 }
732
733 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
734
735 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
736 /* flush posted write */
737 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
738 }
739
740 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
741 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
742
743 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
744 /* flush posted write */
745 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
746 } else {
747 ciostatus = 0;
748 }
749
750 #ifdef DSI_CATCH_MISSING_TE
751 if (irqstatus & DSI_IRQ_TE_TRIGGER)
752 del_timer(&dsi->te_timer);
753 #endif
754
755 /* make a copy and unlock, so that isrs can unregister
756 * themselves */
757 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
758 sizeof(dsi->isr_tables));
759
760 spin_unlock(&dsi->irq_lock);
761
762 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
763
764 dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
765
766 dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
767
768 return IRQ_HANDLED;
769 }
770
771 /* dsi->irq_lock has to be locked by the caller */
772 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
773 struct dsi_isr_data *isr_array,
774 unsigned isr_array_size, u32 default_mask,
775 const struct dsi_reg enable_reg,
776 const struct dsi_reg status_reg)
777 {
778 struct dsi_isr_data *isr_data;
779 u32 mask;
780 u32 old_mask;
781 int i;
782
783 mask = default_mask;
784
785 for (i = 0; i < isr_array_size; i++) {
786 isr_data = &isr_array[i];
787
788 if (isr_data->isr == NULL)
789 continue;
790
791 mask |= isr_data->mask;
792 }
793
794 old_mask = dsi_read_reg(dsidev, enable_reg);
795 /* clear the irqstatus for newly enabled irqs */
796 dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
797 dsi_write_reg(dsidev, enable_reg, mask);
798
799 /* flush posted writes */
800 dsi_read_reg(dsidev, enable_reg);
801 dsi_read_reg(dsidev, status_reg);
802 }
803
804 /* dsi->irq_lock has to be locked by the caller */
805 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
806 {
807 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
808 u32 mask = DSI_IRQ_ERROR_MASK;
809 #ifdef DSI_CATCH_MISSING_TE
810 mask |= DSI_IRQ_TE_TRIGGER;
811 #endif
812 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
813 ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
814 DSI_IRQENABLE, DSI_IRQSTATUS);
815 }
816
817 /* dsi->irq_lock has to be locked by the caller */
818 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
819 {
820 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
821
822 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
823 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
824 DSI_VC_IRQ_ERROR_MASK,
825 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
826 }
827
828 /* dsi->irq_lock has to be locked by the caller */
829 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
830 {
831 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
832
833 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
834 ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
835 DSI_CIO_IRQ_ERROR_MASK,
836 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
837 }
838
839 static void _dsi_initialize_irq(struct platform_device *dsidev)
840 {
841 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
842 unsigned long flags;
843 int vc;
844
845 spin_lock_irqsave(&dsi->irq_lock, flags);
846
847 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
848
849 _omap_dsi_set_irqs(dsidev);
850 for (vc = 0; vc < 4; ++vc)
851 _omap_dsi_set_irqs_vc(dsidev, vc);
852 _omap_dsi_set_irqs_cio(dsidev);
853
854 spin_unlock_irqrestore(&dsi->irq_lock, flags);
855 }
856
857 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
858 struct dsi_isr_data *isr_array, unsigned isr_array_size)
859 {
860 struct dsi_isr_data *isr_data;
861 int free_idx;
862 int i;
863
864 BUG_ON(isr == NULL);
865
866 /* check for duplicate entry and find a free slot */
867 free_idx = -1;
868 for (i = 0; i < isr_array_size; i++) {
869 isr_data = &isr_array[i];
870
871 if (isr_data->isr == isr && isr_data->arg == arg &&
872 isr_data->mask == mask) {
873 return -EINVAL;
874 }
875
876 if (isr_data->isr == NULL && free_idx == -1)
877 free_idx = i;
878 }
879
880 if (free_idx == -1)
881 return -EBUSY;
882
883 isr_data = &isr_array[free_idx];
884 isr_data->isr = isr;
885 isr_data->arg = arg;
886 isr_data->mask = mask;
887
888 return 0;
889 }
890
891 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
892 struct dsi_isr_data *isr_array, unsigned isr_array_size)
893 {
894 struct dsi_isr_data *isr_data;
895 int i;
896
897 for (i = 0; i < isr_array_size; i++) {
898 isr_data = &isr_array[i];
899 if (isr_data->isr != isr || isr_data->arg != arg ||
900 isr_data->mask != mask)
901 continue;
902
903 isr_data->isr = NULL;
904 isr_data->arg = NULL;
905 isr_data->mask = 0;
906
907 return 0;
908 }
909
910 return -EINVAL;
911 }
912
913 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
914 void *arg, u32 mask)
915 {
916 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
917 unsigned long flags;
918 int r;
919
920 spin_lock_irqsave(&dsi->irq_lock, flags);
921
922 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
923 ARRAY_SIZE(dsi->isr_tables.isr_table));
924
925 if (r == 0)
926 _omap_dsi_set_irqs(dsidev);
927
928 spin_unlock_irqrestore(&dsi->irq_lock, flags);
929
930 return r;
931 }
932
933 static int dsi_unregister_isr(struct platform_device *dsidev,
934 omap_dsi_isr_t isr, void *arg, u32 mask)
935 {
936 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
937 unsigned long flags;
938 int r;
939
940 spin_lock_irqsave(&dsi->irq_lock, flags);
941
942 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
943 ARRAY_SIZE(dsi->isr_tables.isr_table));
944
945 if (r == 0)
946 _omap_dsi_set_irqs(dsidev);
947
948 spin_unlock_irqrestore(&dsi->irq_lock, flags);
949
950 return r;
951 }
952
953 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
954 omap_dsi_isr_t isr, void *arg, u32 mask)
955 {
956 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
957 unsigned long flags;
958 int r;
959
960 spin_lock_irqsave(&dsi->irq_lock, flags);
961
962 r = _dsi_register_isr(isr, arg, mask,
963 dsi->isr_tables.isr_table_vc[channel],
964 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
965
966 if (r == 0)
967 _omap_dsi_set_irqs_vc(dsidev, channel);
968
969 spin_unlock_irqrestore(&dsi->irq_lock, flags);
970
971 return r;
972 }
973
974 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
975 omap_dsi_isr_t isr, void *arg, u32 mask)
976 {
977 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
978 unsigned long flags;
979 int r;
980
981 spin_lock_irqsave(&dsi->irq_lock, flags);
982
983 r = _dsi_unregister_isr(isr, arg, mask,
984 dsi->isr_tables.isr_table_vc[channel],
985 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
986
987 if (r == 0)
988 _omap_dsi_set_irqs_vc(dsidev, channel);
989
990 spin_unlock_irqrestore(&dsi->irq_lock, flags);
991
992 return r;
993 }
994
995 static int dsi_register_isr_cio(struct platform_device *dsidev,
996 omap_dsi_isr_t isr, void *arg, u32 mask)
997 {
998 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
999 unsigned long flags;
1000 int r;
1001
1002 spin_lock_irqsave(&dsi->irq_lock, flags);
1003
1004 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1005 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1006
1007 if (r == 0)
1008 _omap_dsi_set_irqs_cio(dsidev);
1009
1010 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1011
1012 return r;
1013 }
1014
1015 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1016 omap_dsi_isr_t isr, void *arg, u32 mask)
1017 {
1018 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1019 unsigned long flags;
1020 int r;
1021
1022 spin_lock_irqsave(&dsi->irq_lock, flags);
1023
1024 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1025 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1026
1027 if (r == 0)
1028 _omap_dsi_set_irqs_cio(dsidev);
1029
1030 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1031
1032 return r;
1033 }
1034
1035 static u32 dsi_get_errors(struct platform_device *dsidev)
1036 {
1037 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1038 unsigned long flags;
1039 u32 e;
1040 spin_lock_irqsave(&dsi->errors_lock, flags);
1041 e = dsi->errors;
1042 dsi->errors = 0;
1043 spin_unlock_irqrestore(&dsi->errors_lock, flags);
1044 return e;
1045 }
1046
1047 int dsi_runtime_get(struct platform_device *dsidev)
1048 {
1049 int r;
1050 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1051
1052 DSSDBG("dsi_runtime_get\n");
1053
1054 r = pm_runtime_get_sync(&dsi->pdev->dev);
1055 WARN_ON(r < 0);
1056 return r < 0 ? r : 0;
1057 }
1058
1059 void dsi_runtime_put(struct platform_device *dsidev)
1060 {
1061 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1062 int r;
1063
1064 DSSDBG("dsi_runtime_put\n");
1065
1066 r = pm_runtime_put(&dsi->pdev->dev);
1067 WARN_ON(r < 0);
1068 }
1069
1070 /* source clock for DSI PLL. this could also be PCLKFREE */
1071 static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
1072 bool enable)
1073 {
1074 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1075
1076 if (enable)
1077 clk_enable(dsi->sys_clk);
1078 else
1079 clk_disable(dsi->sys_clk);
1080
1081 if (enable && dsi->pll_locked) {
1082 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
1083 DSSERR("cannot lock PLL when enabling clocks\n");
1084 }
1085 }
1086
1087 #ifdef DEBUG
1088 static void _dsi_print_reset_status(struct platform_device *dsidev)
1089 {
1090 u32 l;
1091 int b0, b1, b2;
1092
1093 if (!dss_debug)
1094 return;
1095
1096 /* A dummy read using the SCP interface to any DSIPHY register is
1097 * required after DSIPHY reset to complete the reset of the DSI complex
1098 * I/O. */
1099 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1100
1101 printk(KERN_DEBUG "DSI resets: ");
1102
1103 l = dsi_read_reg(dsidev, DSI_PLL_STATUS);
1104 printk("PLL (%d) ", FLD_GET(l, 0, 0));
1105
1106 l = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
1107 printk("CIO (%d) ", FLD_GET(l, 29, 29));
1108
1109 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1110 b0 = 28;
1111 b1 = 27;
1112 b2 = 26;
1113 } else {
1114 b0 = 24;
1115 b1 = 25;
1116 b2 = 26;
1117 }
1118
1119 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1120 printk("PHY (%x%x%x, %d, %d, %d)\n",
1121 FLD_GET(l, b0, b0),
1122 FLD_GET(l, b1, b1),
1123 FLD_GET(l, b2, b2),
1124 FLD_GET(l, 29, 29),
1125 FLD_GET(l, 30, 30),
1126 FLD_GET(l, 31, 31));
1127 }
1128 #else
1129 #define _dsi_print_reset_status(x)
1130 #endif
1131
1132 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1133 {
1134 DSSDBG("dsi_if_enable(%d)\n", enable);
1135
1136 enable = enable ? 1 : 0;
1137 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1138
1139 if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1140 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1141 return -EIO;
1142 }
1143
1144 return 0;
1145 }
1146
1147 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1148 {
1149 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1150
1151 return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
1152 }
1153
1154 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1155 {
1156 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1157
1158 return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
1159 }
1160
1161 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1162 {
1163 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1164
1165 return dsi->current_cinfo.clkin4ddr / 16;
1166 }
1167
1168 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1169 {
1170 unsigned long r;
1171 int dsi_module = dsi_get_dsidev_id(dsidev);
1172 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1173
1174 if (dss_get_dsi_clk_source(dsi_module) == OMAP_DSS_CLK_SRC_FCK) {
1175 /* DSI FCLK source is DSS_CLK_FCK */
1176 r = clk_get_rate(dsi->dss_clk);
1177 } else {
1178 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1179 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1180 }
1181
1182 return r;
1183 }
1184
1185 static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
1186 {
1187 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1188 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1189 unsigned long dsi_fclk;
1190 unsigned lp_clk_div;
1191 unsigned long lp_clk;
1192
1193 lp_clk_div = dssdev->clocks.dsi.lp_clk_div;
1194
1195 if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
1196 return -EINVAL;
1197
1198 dsi_fclk = dsi_fclk_rate(dsidev);
1199
1200 lp_clk = dsi_fclk / 2 / lp_clk_div;
1201
1202 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1203 dsi->current_cinfo.lp_clk = lp_clk;
1204 dsi->current_cinfo.lp_clk_div = lp_clk_div;
1205
1206 /* LP_CLK_DIVISOR */
1207 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1208
1209 /* LP_RX_SYNCHRO_ENABLE */
1210 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1211
1212 return 0;
1213 }
1214
1215 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1216 {
1217 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1218
1219 if (dsi->scp_clk_refcount++ == 0)
1220 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1221 }
1222
1223 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1224 {
1225 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1226
1227 WARN_ON(dsi->scp_clk_refcount == 0);
1228 if (--dsi->scp_clk_refcount == 0)
1229 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1230 }
1231
1232 enum dsi_pll_power_state {
1233 DSI_PLL_POWER_OFF = 0x0,
1234 DSI_PLL_POWER_ON_HSCLK = 0x1,
1235 DSI_PLL_POWER_ON_ALL = 0x2,
1236 DSI_PLL_POWER_ON_DIV = 0x3,
1237 };
1238
1239 static int dsi_pll_power(struct platform_device *dsidev,
1240 enum dsi_pll_power_state state)
1241 {
1242 int t = 0;
1243
1244 /* DSI-PLL power command 0x3 is not working */
1245 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1246 state == DSI_PLL_POWER_ON_DIV)
1247 state = DSI_PLL_POWER_ON_ALL;
1248
1249 /* PLL_PWR_CMD */
1250 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1251
1252 /* PLL_PWR_STATUS */
1253 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1254 if (++t > 1000) {
1255 DSSERR("Failed to set DSI PLL power mode to %d\n",
1256 state);
1257 return -ENODEV;
1258 }
1259 udelay(1);
1260 }
1261
1262 return 0;
1263 }
1264
1265 /* calculate clock rates using dividers in cinfo */
1266 static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
1267 struct dsi_clock_info *cinfo)
1268 {
1269 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1270 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1271
1272 if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
1273 return -EINVAL;
1274
1275 if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
1276 return -EINVAL;
1277
1278 if (cinfo->regm_dispc > dsi->regm_dispc_max)
1279 return -EINVAL;
1280
1281 if (cinfo->regm_dsi > dsi->regm_dsi_max)
1282 return -EINVAL;
1283
1284 if (cinfo->use_sys_clk) {
1285 cinfo->clkin = clk_get_rate(dsi->sys_clk);
1286 /* XXX it is unclear if highfreq should be used
1287 * with DSS_SYS_CLK source also */
1288 cinfo->highfreq = 0;
1289 } else {
1290 cinfo->clkin = dispc_pclk_rate(dssdev->manager->id);
1291
1292 if (cinfo->clkin < 32000000)
1293 cinfo->highfreq = 0;
1294 else
1295 cinfo->highfreq = 1;
1296 }
1297
1298 cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
1299
1300 if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
1301 return -EINVAL;
1302
1303 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1304
1305 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1306 return -EINVAL;
1307
1308 if (cinfo->regm_dispc > 0)
1309 cinfo->dsi_pll_hsdiv_dispc_clk =
1310 cinfo->clkin4ddr / cinfo->regm_dispc;
1311 else
1312 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1313
1314 if (cinfo->regm_dsi > 0)
1315 cinfo->dsi_pll_hsdiv_dsi_clk =
1316 cinfo->clkin4ddr / cinfo->regm_dsi;
1317 else
1318 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1319
1320 return 0;
1321 }
1322
1323 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
1324 unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
1325 struct dispc_clock_info *dispc_cinfo)
1326 {
1327 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1328 struct dsi_clock_info cur, best;
1329 struct dispc_clock_info best_dispc;
1330 int min_fck_per_pck;
1331 int match = 0;
1332 unsigned long dss_sys_clk, max_dss_fck;
1333
1334 dss_sys_clk = clk_get_rate(dsi->sys_clk);
1335
1336 max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1337
1338 if (req_pck == dsi->cache_req_pck &&
1339 dsi->cache_cinfo.clkin == dss_sys_clk) {
1340 DSSDBG("DSI clock info found from cache\n");
1341 *dsi_cinfo = dsi->cache_cinfo;
1342 dispc_find_clk_divs(is_tft, req_pck,
1343 dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo);
1344 return 0;
1345 }
1346
1347 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1348
1349 if (min_fck_per_pck &&
1350 req_pck * min_fck_per_pck > max_dss_fck) {
1351 DSSERR("Requested pixel clock not possible with the current "
1352 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1353 "the constraint off.\n");
1354 min_fck_per_pck = 0;
1355 }
1356
1357 DSSDBG("dsi_pll_calc\n");
1358
1359 retry:
1360 memset(&best, 0, sizeof(best));
1361 memset(&best_dispc, 0, sizeof(best_dispc));
1362
1363 memset(&cur, 0, sizeof(cur));
1364 cur.clkin = dss_sys_clk;
1365 cur.use_sys_clk = 1;
1366 cur.highfreq = 0;
1367
1368 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
1369 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
1370 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1371 for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
1372 if (cur.highfreq == 0)
1373 cur.fint = cur.clkin / cur.regn;
1374 else
1375 cur.fint = cur.clkin / (2 * cur.regn);
1376
1377 if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
1378 continue;
1379
1380 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
1381 for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
1382 unsigned long a, b;
1383
1384 a = 2 * cur.regm * (cur.clkin/1000);
1385 b = cur.regn * (cur.highfreq + 1);
1386 cur.clkin4ddr = a / b * 1000;
1387
1388 if (cur.clkin4ddr > 1800 * 1000 * 1000)
1389 break;
1390
1391 /* dsi_pll_hsdiv_dispc_clk(MHz) =
1392 * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */
1393 for (cur.regm_dispc = 1; cur.regm_dispc <
1394 dsi->regm_dispc_max; ++cur.regm_dispc) {
1395 struct dispc_clock_info cur_dispc;
1396 cur.dsi_pll_hsdiv_dispc_clk =
1397 cur.clkin4ddr / cur.regm_dispc;
1398
1399 /* this will narrow down the search a bit,
1400 * but still give pixclocks below what was
1401 * requested */
1402 if (cur.dsi_pll_hsdiv_dispc_clk < req_pck)
1403 break;
1404
1405 if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
1406 continue;
1407
1408 if (min_fck_per_pck &&
1409 cur.dsi_pll_hsdiv_dispc_clk <
1410 req_pck * min_fck_per_pck)
1411 continue;
1412
1413 match = 1;
1414
1415 dispc_find_clk_divs(is_tft, req_pck,
1416 cur.dsi_pll_hsdiv_dispc_clk,
1417 &cur_dispc);
1418
1419 if (abs(cur_dispc.pck - req_pck) <
1420 abs(best_dispc.pck - req_pck)) {
1421 best = cur;
1422 best_dispc = cur_dispc;
1423
1424 if (cur_dispc.pck == req_pck)
1425 goto found;
1426 }
1427 }
1428 }
1429 }
1430 found:
1431 if (!match) {
1432 if (min_fck_per_pck) {
1433 DSSERR("Could not find suitable clock settings.\n"
1434 "Turning FCK/PCK constraint off and"
1435 "trying again.\n");
1436 min_fck_per_pck = 0;
1437 goto retry;
1438 }
1439
1440 DSSERR("Could not find suitable clock settings.\n");
1441
1442 return -EINVAL;
1443 }
1444
1445 /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
1446 best.regm_dsi = 0;
1447 best.dsi_pll_hsdiv_dsi_clk = 0;
1448
1449 if (dsi_cinfo)
1450 *dsi_cinfo = best;
1451 if (dispc_cinfo)
1452 *dispc_cinfo = best_dispc;
1453
1454 dsi->cache_req_pck = req_pck;
1455 dsi->cache_clk_freq = 0;
1456 dsi->cache_cinfo = best;
1457
1458 return 0;
1459 }
1460
1461 int dsi_pll_set_clock_div(struct platform_device *dsidev,
1462 struct dsi_clock_info *cinfo)
1463 {
1464 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1465 int r = 0;
1466 u32 l;
1467 int f = 0;
1468 u8 regn_start, regn_end, regm_start, regm_end;
1469 u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1470
1471 DSSDBGF();
1472
1473 dsi->current_cinfo.use_sys_clk = cinfo->use_sys_clk;
1474 dsi->current_cinfo.highfreq = cinfo->highfreq;
1475
1476 dsi->current_cinfo.fint = cinfo->fint;
1477 dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1478 dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1479 cinfo->dsi_pll_hsdiv_dispc_clk;
1480 dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1481 cinfo->dsi_pll_hsdiv_dsi_clk;
1482
1483 dsi->current_cinfo.regn = cinfo->regn;
1484 dsi->current_cinfo.regm = cinfo->regm;
1485 dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
1486 dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
1487
1488 DSSDBG("DSI Fint %ld\n", cinfo->fint);
1489
1490 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
1491 cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree",
1492 cinfo->clkin,
1493 cinfo->highfreq);
1494
1495 /* DSIPHY == CLKIN4DDR */
1496 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
1497 cinfo->regm,
1498 cinfo->regn,
1499 cinfo->clkin,
1500 cinfo->highfreq + 1,
1501 cinfo->clkin4ddr);
1502
1503 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1504 cinfo->clkin4ddr / 1000 / 1000 / 2);
1505
1506 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1507
1508 DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1509 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1510 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1511 cinfo->dsi_pll_hsdiv_dispc_clk);
1512 DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1513 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1514 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1515 cinfo->dsi_pll_hsdiv_dsi_clk);
1516
1517 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, &regn_start, &regn_end);
1518 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, &regm_start, &regm_end);
1519 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, &regm_dispc_start,
1520 &regm_dispc_end);
1521 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, &regm_dsi_start,
1522 &regm_dsi_end);
1523
1524 /* DSI_PLL_AUTOMODE = manual */
1525 REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
1526
1527 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
1528 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1529 /* DSI_PLL_REGN */
1530 l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1531 /* DSI_PLL_REGM */
1532 l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1533 /* DSI_CLOCK_DIV */
1534 l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1535 regm_dispc_start, regm_dispc_end);
1536 /* DSIPROTO_CLOCK_DIV */
1537 l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1538 regm_dsi_start, regm_dsi_end);
1539 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
1540
1541 BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1542
1543 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
1544 f = cinfo->fint < 1000000 ? 0x3 :
1545 cinfo->fint < 1250000 ? 0x4 :
1546 cinfo->fint < 1500000 ? 0x5 :
1547 cinfo->fint < 1750000 ? 0x6 :
1548 0x7;
1549 }
1550
1551 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1552
1553 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL))
1554 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1555 l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1,
1556 11, 11); /* DSI_PLL_CLKSEL */
1557 l = FLD_MOD(l, cinfo->highfreq,
1558 12, 12); /* DSI_PLL_HIGHFREQ */
1559 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1560 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1561 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1562 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1563
1564 REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1565
1566 if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
1567 DSSERR("dsi pll go bit not going down.\n");
1568 r = -EIO;
1569 goto err;
1570 }
1571
1572 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
1573 DSSERR("cannot lock PLL\n");
1574 r = -EIO;
1575 goto err;
1576 }
1577
1578 dsi->pll_locked = 1;
1579
1580 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1581 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1582 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1583 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1584 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1585 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1586 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1587 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1588 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1589 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1590 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1591 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1592 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1593 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1594 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1595 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1596
1597 DSSDBG("PLL config done\n");
1598 err:
1599 return r;
1600 }
1601
1602 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
1603 bool enable_hsdiv)
1604 {
1605 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1606 int r = 0;
1607 enum dsi_pll_power_state pwstate;
1608
1609 DSSDBG("PLL init\n");
1610
1611 if (dsi->vdds_dsi_reg == NULL) {
1612 struct regulator *vdds_dsi;
1613
1614 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
1615
1616 if (IS_ERR(vdds_dsi)) {
1617 DSSERR("can't get VDDS_DSI regulator\n");
1618 return PTR_ERR(vdds_dsi);
1619 }
1620
1621 dsi->vdds_dsi_reg = vdds_dsi;
1622 }
1623
1624 dsi_enable_pll_clock(dsidev, 1);
1625 /*
1626 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1627 */
1628 dsi_enable_scp_clk(dsidev);
1629
1630 if (!dsi->vdds_dsi_enabled) {
1631 r = regulator_enable(dsi->vdds_dsi_reg);
1632 if (r)
1633 goto err0;
1634 dsi->vdds_dsi_enabled = true;
1635 }
1636
1637 /* XXX PLL does not come out of reset without this... */
1638 dispc_pck_free_enable(1);
1639
1640 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1641 DSSERR("PLL not coming out of reset.\n");
1642 r = -ENODEV;
1643 dispc_pck_free_enable(0);
1644 goto err1;
1645 }
1646
1647 /* XXX ... but if left on, we get problems when planes do not
1648 * fill the whole display. No idea about this */
1649 dispc_pck_free_enable(0);
1650
1651 if (enable_hsclk && enable_hsdiv)
1652 pwstate = DSI_PLL_POWER_ON_ALL;
1653 else if (enable_hsclk)
1654 pwstate = DSI_PLL_POWER_ON_HSCLK;
1655 else if (enable_hsdiv)
1656 pwstate = DSI_PLL_POWER_ON_DIV;
1657 else
1658 pwstate = DSI_PLL_POWER_OFF;
1659
1660 r = dsi_pll_power(dsidev, pwstate);
1661
1662 if (r)
1663 goto err1;
1664
1665 DSSDBG("PLL init done\n");
1666
1667 return 0;
1668 err1:
1669 if (dsi->vdds_dsi_enabled) {
1670 regulator_disable(dsi->vdds_dsi_reg);
1671 dsi->vdds_dsi_enabled = false;
1672 }
1673 err0:
1674 dsi_disable_scp_clk(dsidev);
1675 dsi_enable_pll_clock(dsidev, 0);
1676 return r;
1677 }
1678
1679 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1680 {
1681 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1682
1683 dsi->pll_locked = 0;
1684 dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1685 if (disconnect_lanes) {
1686 WARN_ON(!dsi->vdds_dsi_enabled);
1687 regulator_disable(dsi->vdds_dsi_reg);
1688 dsi->vdds_dsi_enabled = false;
1689 }
1690
1691 dsi_disable_scp_clk(dsidev);
1692 dsi_enable_pll_clock(dsidev, 0);
1693
1694 DSSDBG("PLL uninit done\n");
1695 }
1696
1697 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1698 struct seq_file *s)
1699 {
1700 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1701 struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1702 enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1703 int dsi_module = dsi_get_dsidev_id(dsidev);
1704
1705 dispc_clk_src = dss_get_dispc_clk_source();
1706 dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1707
1708 if (dsi_runtime_get(dsidev))
1709 return;
1710
1711 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
1712
1713 seq_printf(s, "dsi pll source = %s\n",
1714 cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree");
1715
1716 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1717
1718 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1719 cinfo->clkin4ddr, cinfo->regm);
1720
1721 seq_printf(s, "%s (%s)\t%-16luregm_dispc %u\t(%s)\n",
1722 dss_get_generic_clk_source_name(dispc_clk_src),
1723 dss_feat_get_clk_source_name(dispc_clk_src),
1724 cinfo->dsi_pll_hsdiv_dispc_clk,
1725 cinfo->regm_dispc,
1726 dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1727 "off" : "on");
1728
1729 seq_printf(s, "%s (%s)\t%-16luregm_dsi %u\t(%s)\n",
1730 dss_get_generic_clk_source_name(dsi_clk_src),
1731 dss_feat_get_clk_source_name(dsi_clk_src),
1732 cinfo->dsi_pll_hsdiv_dsi_clk,
1733 cinfo->regm_dsi,
1734 dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1735 "off" : "on");
1736
1737 seq_printf(s, "- DSI%d -\n", dsi_module + 1);
1738
1739 seq_printf(s, "dsi fclk source = %s (%s)\n",
1740 dss_get_generic_clk_source_name(dsi_clk_src),
1741 dss_feat_get_clk_source_name(dsi_clk_src));
1742
1743 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1744
1745 seq_printf(s, "DDR_CLK\t\t%lu\n",
1746 cinfo->clkin4ddr / 4);
1747
1748 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1749
1750 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1751
1752 dsi_runtime_put(dsidev);
1753 }
1754
1755 void dsi_dump_clocks(struct seq_file *s)
1756 {
1757 struct platform_device *dsidev;
1758 int i;
1759
1760 for (i = 0; i < MAX_NUM_DSI; i++) {
1761 dsidev = dsi_get_dsidev_from_id(i);
1762 if (dsidev)
1763 dsi_dump_dsidev_clocks(dsidev, s);
1764 }
1765 }
1766
1767 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1768 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1769 struct seq_file *s)
1770 {
1771 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1772 unsigned long flags;
1773 struct dsi_irq_stats stats;
1774 int dsi_module = dsi_get_dsidev_id(dsidev);
1775
1776 spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1777
1778 stats = dsi->irq_stats;
1779 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1780 dsi->irq_stats.last_reset = jiffies;
1781
1782 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1783
1784 seq_printf(s, "period %u ms\n",
1785 jiffies_to_msecs(jiffies - stats.last_reset));
1786
1787 seq_printf(s, "irqs %d\n", stats.irq_count);
1788 #define PIS(x) \
1789 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1790
1791 seq_printf(s, "-- DSI%d interrupts --\n", dsi_module + 1);
1792 PIS(VC0);
1793 PIS(VC1);
1794 PIS(VC2);
1795 PIS(VC3);
1796 PIS(WAKEUP);
1797 PIS(RESYNC);
1798 PIS(PLL_LOCK);
1799 PIS(PLL_UNLOCK);
1800 PIS(PLL_RECALL);
1801 PIS(COMPLEXIO_ERR);
1802 PIS(HS_TX_TIMEOUT);
1803 PIS(LP_RX_TIMEOUT);
1804 PIS(TE_TRIGGER);
1805 PIS(ACK_TRIGGER);
1806 PIS(SYNC_LOST);
1807 PIS(LDO_POWER_GOOD);
1808 PIS(TA_TIMEOUT);
1809 #undef PIS
1810
1811 #define PIS(x) \
1812 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1813 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1814 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1815 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1816 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1817
1818 seq_printf(s, "-- VC interrupts --\n");
1819 PIS(CS);
1820 PIS(ECC_CORR);
1821 PIS(PACKET_SENT);
1822 PIS(FIFO_TX_OVF);
1823 PIS(FIFO_RX_OVF);
1824 PIS(BTA);
1825 PIS(ECC_NO_CORR);
1826 PIS(FIFO_TX_UDF);
1827 PIS(PP_BUSY_CHANGE);
1828 #undef PIS
1829
1830 #define PIS(x) \
1831 seq_printf(s, "%-20s %10d\n", #x, \
1832 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1833
1834 seq_printf(s, "-- CIO interrupts --\n");
1835 PIS(ERRSYNCESC1);
1836 PIS(ERRSYNCESC2);
1837 PIS(ERRSYNCESC3);
1838 PIS(ERRESC1);
1839 PIS(ERRESC2);
1840 PIS(ERRESC3);
1841 PIS(ERRCONTROL1);
1842 PIS(ERRCONTROL2);
1843 PIS(ERRCONTROL3);
1844 PIS(STATEULPS1);
1845 PIS(STATEULPS2);
1846 PIS(STATEULPS3);
1847 PIS(ERRCONTENTIONLP0_1);
1848 PIS(ERRCONTENTIONLP1_1);
1849 PIS(ERRCONTENTIONLP0_2);
1850 PIS(ERRCONTENTIONLP1_2);
1851 PIS(ERRCONTENTIONLP0_3);
1852 PIS(ERRCONTENTIONLP1_3);
1853 PIS(ULPSACTIVENOT_ALL0);
1854 PIS(ULPSACTIVENOT_ALL1);
1855 #undef PIS
1856 }
1857
1858 static void dsi1_dump_irqs(struct seq_file *s)
1859 {
1860 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1861
1862 dsi_dump_dsidev_irqs(dsidev, s);
1863 }
1864
1865 static void dsi2_dump_irqs(struct seq_file *s)
1866 {
1867 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1868
1869 dsi_dump_dsidev_irqs(dsidev, s);
1870 }
1871
1872 void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir,
1873 const struct file_operations *debug_fops)
1874 {
1875 struct platform_device *dsidev;
1876
1877 dsidev = dsi_get_dsidev_from_id(0);
1878 if (dsidev)
1879 debugfs_create_file("dsi1_irqs", S_IRUGO, debugfs_dir,
1880 &dsi1_dump_irqs, debug_fops);
1881
1882 dsidev = dsi_get_dsidev_from_id(1);
1883 if (dsidev)
1884 debugfs_create_file("dsi2_irqs", S_IRUGO, debugfs_dir,
1885 &dsi2_dump_irqs, debug_fops);
1886 }
1887 #endif
1888
1889 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1890 struct seq_file *s)
1891 {
1892 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1893
1894 if (dsi_runtime_get(dsidev))
1895 return;
1896 dsi_enable_scp_clk(dsidev);
1897
1898 DUMPREG(DSI_REVISION);
1899 DUMPREG(DSI_SYSCONFIG);
1900 DUMPREG(DSI_SYSSTATUS);
1901 DUMPREG(DSI_IRQSTATUS);
1902 DUMPREG(DSI_IRQENABLE);
1903 DUMPREG(DSI_CTRL);
1904 DUMPREG(DSI_COMPLEXIO_CFG1);
1905 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1906 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1907 DUMPREG(DSI_CLK_CTRL);
1908 DUMPREG(DSI_TIMING1);
1909 DUMPREG(DSI_TIMING2);
1910 DUMPREG(DSI_VM_TIMING1);
1911 DUMPREG(DSI_VM_TIMING2);
1912 DUMPREG(DSI_VM_TIMING3);
1913 DUMPREG(DSI_CLK_TIMING);
1914 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1915 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1916 DUMPREG(DSI_COMPLEXIO_CFG2);
1917 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1918 DUMPREG(DSI_VM_TIMING4);
1919 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1920 DUMPREG(DSI_VM_TIMING5);
1921 DUMPREG(DSI_VM_TIMING6);
1922 DUMPREG(DSI_VM_TIMING7);
1923 DUMPREG(DSI_STOPCLK_TIMING);
1924
1925 DUMPREG(DSI_VC_CTRL(0));
1926 DUMPREG(DSI_VC_TE(0));
1927 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1928 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1929 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1930 DUMPREG(DSI_VC_IRQSTATUS(0));
1931 DUMPREG(DSI_VC_IRQENABLE(0));
1932
1933 DUMPREG(DSI_VC_CTRL(1));
1934 DUMPREG(DSI_VC_TE(1));
1935 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1936 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1937 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1938 DUMPREG(DSI_VC_IRQSTATUS(1));
1939 DUMPREG(DSI_VC_IRQENABLE(1));
1940
1941 DUMPREG(DSI_VC_CTRL(2));
1942 DUMPREG(DSI_VC_TE(2));
1943 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1944 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1945 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1946 DUMPREG(DSI_VC_IRQSTATUS(2));
1947 DUMPREG(DSI_VC_IRQENABLE(2));
1948
1949 DUMPREG(DSI_VC_CTRL(3));
1950 DUMPREG(DSI_VC_TE(3));
1951 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1952 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1953 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1954 DUMPREG(DSI_VC_IRQSTATUS(3));
1955 DUMPREG(DSI_VC_IRQENABLE(3));
1956
1957 DUMPREG(DSI_DSIPHY_CFG0);
1958 DUMPREG(DSI_DSIPHY_CFG1);
1959 DUMPREG(DSI_DSIPHY_CFG2);
1960 DUMPREG(DSI_DSIPHY_CFG5);
1961
1962 DUMPREG(DSI_PLL_CONTROL);
1963 DUMPREG(DSI_PLL_STATUS);
1964 DUMPREG(DSI_PLL_GO);
1965 DUMPREG(DSI_PLL_CONFIGURATION1);
1966 DUMPREG(DSI_PLL_CONFIGURATION2);
1967
1968 dsi_disable_scp_clk(dsidev);
1969 dsi_runtime_put(dsidev);
1970 #undef DUMPREG
1971 }
1972
1973 static void dsi1_dump_regs(struct seq_file *s)
1974 {
1975 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1976
1977 dsi_dump_dsidev_regs(dsidev, s);
1978 }
1979
1980 static void dsi2_dump_regs(struct seq_file *s)
1981 {
1982 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1983
1984 dsi_dump_dsidev_regs(dsidev, s);
1985 }
1986
1987 void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir,
1988 const struct file_operations *debug_fops)
1989 {
1990 struct platform_device *dsidev;
1991
1992 dsidev = dsi_get_dsidev_from_id(0);
1993 if (dsidev)
1994 debugfs_create_file("dsi1_regs", S_IRUGO, debugfs_dir,
1995 &dsi1_dump_regs, debug_fops);
1996
1997 dsidev = dsi_get_dsidev_from_id(1);
1998 if (dsidev)
1999 debugfs_create_file("dsi2_regs", S_IRUGO, debugfs_dir,
2000 &dsi2_dump_regs, debug_fops);
2001 }
2002 enum dsi_cio_power_state {
2003 DSI_COMPLEXIO_POWER_OFF = 0x0,
2004 DSI_COMPLEXIO_POWER_ON = 0x1,
2005 DSI_COMPLEXIO_POWER_ULPS = 0x2,
2006 };
2007
2008 static int dsi_cio_power(struct platform_device *dsidev,
2009 enum dsi_cio_power_state state)
2010 {
2011 int t = 0;
2012
2013 /* PWR_CMD */
2014 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
2015
2016 /* PWR_STATUS */
2017 while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
2018 26, 25) != state) {
2019 if (++t > 1000) {
2020 DSSERR("failed to set complexio power state to "
2021 "%d\n", state);
2022 return -ENODEV;
2023 }
2024 udelay(1);
2025 }
2026
2027 return 0;
2028 }
2029
2030 /* Number of data lanes present on DSI interface */
2031 static inline int dsi_get_num_data_lanes(struct platform_device *dsidev)
2032 {
2033 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
2034 * of data lanes as 2 by default */
2035 if (dss_has_feature(FEAT_DSI_GNQ))
2036 return REG_GET(dsidev, DSI_GNQ, 11, 9); /* NB_DATA_LANES */
2037 else
2038 return 2;
2039 }
2040
2041 /* Number of data lanes used by the dss device */
2042 static inline int dsi_get_num_data_lanes_dssdev(struct omap_dss_device *dssdev)
2043 {
2044 int num_data_lanes = 0;
2045
2046 if (dssdev->phy.dsi.data1_lane != 0)
2047 num_data_lanes++;
2048 if (dssdev->phy.dsi.data2_lane != 0)
2049 num_data_lanes++;
2050 if (dssdev->phy.dsi.data3_lane != 0)
2051 num_data_lanes++;
2052 if (dssdev->phy.dsi.data4_lane != 0)
2053 num_data_lanes++;
2054
2055 return num_data_lanes;
2056 }
2057
2058 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
2059 {
2060 int val;
2061
2062 /* line buffer on OMAP3 is 1024 x 24bits */
2063 /* XXX: for some reason using full buffer size causes
2064 * considerable TX slowdown with update sizes that fill the
2065 * whole buffer */
2066 if (!dss_has_feature(FEAT_DSI_GNQ))
2067 return 1023 * 3;
2068
2069 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
2070
2071 switch (val) {
2072 case 1:
2073 return 512 * 3; /* 512x24 bits */
2074 case 2:
2075 return 682 * 3; /* 682x24 bits */
2076 case 3:
2077 return 853 * 3; /* 853x24 bits */
2078 case 4:
2079 return 1024 * 3; /* 1024x24 bits */
2080 case 5:
2081 return 1194 * 3; /* 1194x24 bits */
2082 case 6:
2083 return 1365 * 3; /* 1365x24 bits */
2084 default:
2085 BUG();
2086 }
2087 }
2088
2089 static void dsi_set_lane_config(struct omap_dss_device *dssdev)
2090 {
2091 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2092 u32 r;
2093 int num_data_lanes_dssdev = dsi_get_num_data_lanes_dssdev(dssdev);
2094
2095 int clk_lane = dssdev->phy.dsi.clk_lane;
2096 int data1_lane = dssdev->phy.dsi.data1_lane;
2097 int data2_lane = dssdev->phy.dsi.data2_lane;
2098 int clk_pol = dssdev->phy.dsi.clk_pol;
2099 int data1_pol = dssdev->phy.dsi.data1_pol;
2100 int data2_pol = dssdev->phy.dsi.data2_pol;
2101
2102 r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
2103 r = FLD_MOD(r, clk_lane, 2, 0);
2104 r = FLD_MOD(r, clk_pol, 3, 3);
2105 r = FLD_MOD(r, data1_lane, 6, 4);
2106 r = FLD_MOD(r, data1_pol, 7, 7);
2107 r = FLD_MOD(r, data2_lane, 10, 8);
2108 r = FLD_MOD(r, data2_pol, 11, 11);
2109 if (num_data_lanes_dssdev > 2) {
2110 int data3_lane = dssdev->phy.dsi.data3_lane;
2111 int data3_pol = dssdev->phy.dsi.data3_pol;
2112
2113 r = FLD_MOD(r, data3_lane, 14, 12);
2114 r = FLD_MOD(r, data3_pol, 15, 15);
2115 }
2116 if (num_data_lanes_dssdev > 3) {
2117 int data4_lane = dssdev->phy.dsi.data4_lane;
2118 int data4_pol = dssdev->phy.dsi.data4_pol;
2119
2120 r = FLD_MOD(r, data4_lane, 18, 16);
2121 r = FLD_MOD(r, data4_pol, 19, 19);
2122 }
2123 dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
2124
2125 /* The configuration of the DSI complex I/O (number of data lanes,
2126 position, differential order) should not be changed while
2127 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
2128 the hardware to take into account a new configuration of the complex
2129 I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
2130 follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
2131 then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
2132 DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
2133 DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
2134 DSI complex I/O configuration is unknown. */
2135
2136 /*
2137 REG_FLD_MOD(dsidev, DSI_CTRL, 1, 0, 0);
2138 REG_FLD_MOD(dsidev, DSI_CTRL, 0, 0, 0);
2139 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20);
2140 REG_FLD_MOD(dsidev, DSI_CTRL, 1, 0, 0);
2141 */
2142 }
2143
2144 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
2145 {
2146 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2147
2148 /* convert time in ns to ddr ticks, rounding up */
2149 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2150 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
2151 }
2152
2153 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
2154 {
2155 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2156
2157 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2158 return ddr * 1000 * 1000 / (ddr_clk / 1000);
2159 }
2160
2161 static void dsi_cio_timings(struct platform_device *dsidev)
2162 {
2163 u32 r;
2164 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
2165 u32 tlpx_half, tclk_trail, tclk_zero;
2166 u32 tclk_prepare;
2167
2168 /* calculate timings */
2169
2170 /* 1 * DDR_CLK = 2 * UI */
2171
2172 /* min 40ns + 4*UI max 85ns + 6*UI */
2173 ths_prepare = ns2ddr(dsidev, 70) + 2;
2174
2175 /* min 145ns + 10*UI */
2176 ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
2177
2178 /* min max(8*UI, 60ns+4*UI) */
2179 ths_trail = ns2ddr(dsidev, 60) + 5;
2180
2181 /* min 100ns */
2182 ths_exit = ns2ddr(dsidev, 145);
2183
2184 /* tlpx min 50n */
2185 tlpx_half = ns2ddr(dsidev, 25);
2186
2187 /* min 60ns */
2188 tclk_trail = ns2ddr(dsidev, 60) + 2;
2189
2190 /* min 38ns, max 95ns */
2191 tclk_prepare = ns2ddr(dsidev, 65);
2192
2193 /* min tclk-prepare + tclk-zero = 300ns */
2194 tclk_zero = ns2ddr(dsidev, 260);
2195
2196 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2197 ths_prepare, ddr2ns(dsidev, ths_prepare),
2198 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
2199 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2200 ths_trail, ddr2ns(dsidev, ths_trail),
2201 ths_exit, ddr2ns(dsidev, ths_exit));
2202
2203 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2204 "tclk_zero %u (%uns)\n",
2205 tlpx_half, ddr2ns(dsidev, tlpx_half),
2206 tclk_trail, ddr2ns(dsidev, tclk_trail),
2207 tclk_zero, ddr2ns(dsidev, tclk_zero));
2208 DSSDBG("tclk_prepare %u (%uns)\n",
2209 tclk_prepare, ddr2ns(dsidev, tclk_prepare));
2210
2211 /* program timings */
2212
2213 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
2214 r = FLD_MOD(r, ths_prepare, 31, 24);
2215 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
2216 r = FLD_MOD(r, ths_trail, 15, 8);
2217 r = FLD_MOD(r, ths_exit, 7, 0);
2218 dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
2219
2220 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
2221 r = FLD_MOD(r, tlpx_half, 22, 16);
2222 r = FLD_MOD(r, tclk_trail, 15, 8);
2223 r = FLD_MOD(r, tclk_zero, 7, 0);
2224 dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
2225
2226 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
2227 r = FLD_MOD(r, tclk_prepare, 7, 0);
2228 dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
2229 }
2230
2231 static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev,
2232 enum dsi_lane lanes)
2233 {
2234 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2235 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2236 int clk_lane = dssdev->phy.dsi.clk_lane;
2237 int data1_lane = dssdev->phy.dsi.data1_lane;
2238 int data2_lane = dssdev->phy.dsi.data2_lane;
2239 int data3_lane = dssdev->phy.dsi.data3_lane;
2240 int data4_lane = dssdev->phy.dsi.data4_lane;
2241 int clk_pol = dssdev->phy.dsi.clk_pol;
2242 int data1_pol = dssdev->phy.dsi.data1_pol;
2243 int data2_pol = dssdev->phy.dsi.data2_pol;
2244 int data3_pol = dssdev->phy.dsi.data3_pol;
2245 int data4_pol = dssdev->phy.dsi.data4_pol;
2246
2247 u32 l = 0;
2248 u8 lptxscp_start = dsi->num_data_lanes == 2 ? 22 : 26;
2249
2250 if (lanes & DSI_CLK_P)
2251 l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 0 : 1));
2252 if (lanes & DSI_CLK_N)
2253 l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 1 : 0));
2254
2255 if (lanes & DSI_DATA1_P)
2256 l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 0 : 1));
2257 if (lanes & DSI_DATA1_N)
2258 l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 1 : 0));
2259
2260 if (lanes & DSI_DATA2_P)
2261 l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 0 : 1));
2262 if (lanes & DSI_DATA2_N)
2263 l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 1 : 0));
2264
2265 if (lanes & DSI_DATA3_P)
2266 l |= 1 << ((data3_lane - 1) * 2 + (data3_pol ? 0 : 1));
2267 if (lanes & DSI_DATA3_N)
2268 l |= 1 << ((data3_lane - 1) * 2 + (data3_pol ? 1 : 0));
2269
2270 if (lanes & DSI_DATA4_P)
2271 l |= 1 << ((data4_lane - 1) * 2 + (data4_pol ? 0 : 1));
2272 if (lanes & DSI_DATA4_N)
2273 l |= 1 << ((data4_lane - 1) * 2 + (data4_pol ? 1 : 0));
2274 /*
2275 * Bits in REGLPTXSCPDAT4TO0DXDY:
2276 * 17: DY0 18: DX0
2277 * 19: DY1 20: DX1
2278 * 21: DY2 22: DX2
2279 * 23: DY3 24: DX3
2280 * 25: DY4 26: DX4
2281 */
2282
2283 /* Set the lane override configuration */
2284
2285 /* REGLPTXSCPDAT4TO0DXDY */
2286 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2287
2288 /* Enable lane override */
2289
2290 /* ENLPTXSCPDAT */
2291 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2292 }
2293
2294 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2295 {
2296 /* Disable lane override */
2297 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2298 /* Reset the lane override configuration */
2299 /* REGLPTXSCPDAT4TO0DXDY */
2300 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2301 }
2302
2303 static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device *dssdev)
2304 {
2305 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2306 int t;
2307 int bits[3];
2308 bool in_use[3];
2309
2310 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
2311 bits[0] = 28;
2312 bits[1] = 27;
2313 bits[2] = 26;
2314 } else {
2315 bits[0] = 24;
2316 bits[1] = 25;
2317 bits[2] = 26;
2318 }
2319
2320 in_use[0] = false;
2321 in_use[1] = false;
2322 in_use[2] = false;
2323
2324 if (dssdev->phy.dsi.clk_lane != 0)
2325 in_use[dssdev->phy.dsi.clk_lane - 1] = true;
2326 if (dssdev->phy.dsi.data1_lane != 0)
2327 in_use[dssdev->phy.dsi.data1_lane - 1] = true;
2328 if (dssdev->phy.dsi.data2_lane != 0)
2329 in_use[dssdev->phy.dsi.data2_lane - 1] = true;
2330
2331 t = 100000;
2332 while (true) {
2333 u32 l;
2334 int i;
2335 int ok;
2336
2337 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2338
2339 ok = 0;
2340 for (i = 0; i < 3; ++i) {
2341 if (!in_use[i] || (l & (1 << bits[i])))
2342 ok++;
2343 }
2344
2345 if (ok == 3)
2346 break;
2347
2348 if (--t == 0) {
2349 for (i = 0; i < 3; ++i) {
2350 if (!in_use[i] || (l & (1 << bits[i])))
2351 continue;
2352
2353 DSSERR("CIO TXCLKESC%d domain not coming " \
2354 "out of reset\n", i);
2355 }
2356 return -EIO;
2357 }
2358 }
2359
2360 return 0;
2361 }
2362
2363 static int dsi_cio_init(struct omap_dss_device *dssdev)
2364 {
2365 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2366 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2367 int r;
2368 int num_data_lanes_dssdev = dsi_get_num_data_lanes_dssdev(dssdev);
2369 u32 l;
2370
2371 DSSDBGF();
2372
2373 if (dsi->dsi_mux_pads)
2374 dsi->dsi_mux_pads(true);
2375
2376 dsi_enable_scp_clk(dsidev);
2377
2378 /* A dummy read using the SCP interface to any DSIPHY register is
2379 * required after DSIPHY reset to complete the reset of the DSI complex
2380 * I/O. */
2381 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2382
2383 if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2384 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2385 r = -EIO;
2386 goto err_scp_clk_dom;
2387 }
2388
2389 dsi_set_lane_config(dssdev);
2390
2391 /* set TX STOP MODE timer to maximum for this operation */
2392 l = dsi_read_reg(dsidev, DSI_TIMING1);
2393 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2394 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
2395 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
2396 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2397 dsi_write_reg(dsidev, DSI_TIMING1, l);
2398
2399 if (dsi->ulps_enabled) {
2400 u32 lane_mask = DSI_CLK_P | DSI_DATA1_P | DSI_DATA2_P;
2401
2402 DSSDBG("manual ulps exit\n");
2403
2404 /* ULPS is exited by Mark-1 state for 1ms, followed by
2405 * stop state. DSS HW cannot do this via the normal
2406 * ULPS exit sequence, as after reset the DSS HW thinks
2407 * that we are not in ULPS mode, and refuses to send the
2408 * sequence. So we need to send the ULPS exit sequence
2409 * manually.
2410 */
2411
2412 if (num_data_lanes_dssdev > 2)
2413 lane_mask |= DSI_DATA3_P;
2414
2415 if (num_data_lanes_dssdev > 3)
2416 lane_mask |= DSI_DATA4_P;
2417
2418 dsi_cio_enable_lane_override(dssdev, lane_mask);
2419 }
2420
2421 r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2422 if (r)
2423 goto err_cio_pwr;
2424
2425 if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2426 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2427 r = -ENODEV;
2428 goto err_cio_pwr_dom;
2429 }
2430
2431 dsi_if_enable(dsidev, true);
2432 dsi_if_enable(dsidev, false);
2433 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2434
2435 r = dsi_cio_wait_tx_clk_esc_reset(dssdev);
2436 if (r)
2437 goto err_tx_clk_esc_rst;
2438
2439 if (dsi->ulps_enabled) {
2440 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2441 ktime_t wait = ns_to_ktime(1000 * 1000);
2442 set_current_state(TASK_UNINTERRUPTIBLE);
2443 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2444
2445 /* Disable the override. The lanes should be set to Mark-11
2446 * state by the HW */
2447 dsi_cio_disable_lane_override(dsidev);
2448 }
2449
2450 /* FORCE_TX_STOP_MODE_IO */
2451 REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2452
2453 dsi_cio_timings(dsidev);
2454
2455 dsi->ulps_enabled = false;
2456
2457 DSSDBG("CIO init done\n");
2458
2459 return 0;
2460
2461 err_tx_clk_esc_rst:
2462 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2463 err_cio_pwr_dom:
2464 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2465 err_cio_pwr:
2466 if (dsi->ulps_enabled)
2467 dsi_cio_disable_lane_override(dsidev);
2468 err_scp_clk_dom:
2469 dsi_disable_scp_clk(dsidev);
2470 if (dsi->dsi_mux_pads)
2471 dsi->dsi_mux_pads(false);
2472 return r;
2473 }
2474
2475 static void dsi_cio_uninit(struct platform_device *dsidev)
2476 {
2477 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2478
2479 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2480 dsi_disable_scp_clk(dsidev);
2481 if (dsi->dsi_mux_pads)
2482 dsi->dsi_mux_pads(false);
2483 }
2484
2485 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2486 enum fifo_size size1, enum fifo_size size2,
2487 enum fifo_size size3, enum fifo_size size4)
2488 {
2489 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2490 u32 r = 0;
2491 int add = 0;
2492 int i;
2493
2494 dsi->vc[0].fifo_size = size1;
2495 dsi->vc[1].fifo_size = size2;
2496 dsi->vc[2].fifo_size = size3;
2497 dsi->vc[3].fifo_size = size4;
2498
2499 for (i = 0; i < 4; i++) {
2500 u8 v;
2501 int size = dsi->vc[i].fifo_size;
2502
2503 if (add + size > 4) {
2504 DSSERR("Illegal FIFO configuration\n");
2505 BUG();
2506 }
2507
2508 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2509 r |= v << (8 * i);
2510 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2511 add += size;
2512 }
2513
2514 dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2515 }
2516
2517 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2518 enum fifo_size size1, enum fifo_size size2,
2519 enum fifo_size size3, enum fifo_size size4)
2520 {
2521 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2522 u32 r = 0;
2523 int add = 0;
2524 int i;
2525
2526 dsi->vc[0].fifo_size = size1;
2527 dsi->vc[1].fifo_size = size2;
2528 dsi->vc[2].fifo_size = size3;
2529 dsi->vc[3].fifo_size = size4;
2530
2531 for (i = 0; i < 4; i++) {
2532 u8 v;
2533 int size = dsi->vc[i].fifo_size;
2534
2535 if (add + size > 4) {
2536 DSSERR("Illegal FIFO configuration\n");
2537 BUG();
2538 }
2539
2540 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2541 r |= v << (8 * i);
2542 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2543 add += size;
2544 }
2545
2546 dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2547 }
2548
2549 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2550 {
2551 u32 r;
2552
2553 r = dsi_read_reg(dsidev, DSI_TIMING1);
2554 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2555 dsi_write_reg(dsidev, DSI_TIMING1, r);
2556
2557 if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2558 DSSERR("TX_STOP bit not going down\n");
2559 return -EIO;
2560 }
2561
2562 return 0;
2563 }
2564
2565 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2566 {
2567 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2568 }
2569
2570 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2571 {
2572 struct dsi_packet_sent_handler_data *vp_data =
2573 (struct dsi_packet_sent_handler_data *) data;
2574 struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2575 const int channel = dsi->update_channel;
2576 u8 bit = dsi->te_enabled ? 30 : 31;
2577
2578 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2579 complete(vp_data->completion);
2580 }
2581
2582 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2583 {
2584 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2585 DECLARE_COMPLETION_ONSTACK(completion);
2586 struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2587 int r = 0;
2588 u8 bit;
2589
2590 bit = dsi->te_enabled ? 30 : 31;
2591
2592 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2593 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2594 if (r)
2595 goto err0;
2596
2597 /* Wait for completion only if TE_EN/TE_START is still set */
2598 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2599 if (wait_for_completion_timeout(&completion,
2600 msecs_to_jiffies(10)) == 0) {
2601 DSSERR("Failed to complete previous frame transfer\n");
2602 r = -EIO;
2603 goto err1;
2604 }
2605 }
2606
2607 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2608 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2609
2610 return 0;
2611 err1:
2612 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2613 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2614 err0:
2615 return r;
2616 }
2617
2618 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2619 {
2620 struct dsi_packet_sent_handler_data *l4_data =
2621 (struct dsi_packet_sent_handler_data *) data;
2622 struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2623 const int channel = dsi->update_channel;
2624
2625 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2626 complete(l4_data->completion);
2627 }
2628
2629 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2630 {
2631 DECLARE_COMPLETION_ONSTACK(completion);
2632 struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
2633 int r = 0;
2634
2635 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2636 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2637 if (r)
2638 goto err0;
2639
2640 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2641 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2642 if (wait_for_completion_timeout(&completion,
2643 msecs_to_jiffies(10)) == 0) {
2644 DSSERR("Failed to complete previous l4 transfer\n");
2645 r = -EIO;
2646 goto err1;
2647 }
2648 }
2649
2650 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2651 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2652
2653 return 0;
2654 err1:
2655 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2656 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2657 err0:
2658 return r;
2659 }
2660
2661 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2662 {
2663 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2664
2665 WARN_ON(!dsi_bus_is_locked(dsidev));
2666
2667 WARN_ON(in_interrupt());
2668
2669 if (!dsi_vc_is_enabled(dsidev, channel))
2670 return 0;
2671
2672 switch (dsi->vc[channel].mode) {
2673 case DSI_VC_MODE_VP:
2674 return dsi_sync_vc_vp(dsidev, channel);
2675 case DSI_VC_MODE_L4:
2676 return dsi_sync_vc_l4(dsidev, channel);
2677 default:
2678 BUG();
2679 }
2680 }
2681
2682 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2683 bool enable)
2684 {
2685 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2686 channel, enable);
2687
2688 enable = enable ? 1 : 0;
2689
2690 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2691
2692 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2693 0, enable) != enable) {
2694 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2695 return -EIO;
2696 }
2697
2698 return 0;
2699 }
2700
2701 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2702 {
2703 u32 r;
2704
2705 DSSDBGF("%d", channel);
2706
2707 r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2708
2709 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2710 DSSERR("VC(%d) busy when trying to configure it!\n",
2711 channel);
2712
2713 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2714 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
2715 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2716 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2717 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2718 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2719 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2720 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2721 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2722
2723 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2724 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2725
2726 dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2727 }
2728
2729 static int dsi_vc_config_l4(struct platform_device *dsidev, int channel)
2730 {
2731 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2732
2733 if (dsi->vc[channel].mode == DSI_VC_MODE_L4)
2734 return 0;
2735
2736 DSSDBGF("%d", channel);
2737
2738 dsi_sync_vc(dsidev, channel);
2739
2740 dsi_vc_enable(dsidev, channel, 0);
2741
2742 /* VC_BUSY */
2743 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2744 DSSERR("vc(%d) busy when trying to config for L4\n", channel);
2745 return -EIO;
2746 }
2747
2748 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */
2749
2750 /* DCS_CMD_ENABLE */
2751 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC))
2752 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 30, 30);
2753
2754 dsi_vc_enable(dsidev, channel, 1);
2755
2756 dsi->vc[channel].mode = DSI_VC_MODE_L4;
2757
2758 return 0;
2759 }
2760
2761 static int dsi_vc_config_vp(struct platform_device *dsidev, int channel)
2762 {
2763 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2764
2765 if (dsi->vc[channel].mode == DSI_VC_MODE_VP)
2766 return 0;
2767
2768 DSSDBGF("%d", channel);
2769
2770 dsi_sync_vc(dsidev, channel);
2771
2772 dsi_vc_enable(dsidev, channel, 0);
2773
2774 /* VC_BUSY */
2775 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2776 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2777 return -EIO;
2778 }
2779
2780 /* SOURCE, 1 = video port */
2781 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 1, 1);
2782
2783 /* DCS_CMD_ENABLE */
2784 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC))
2785 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 30, 30);
2786
2787 dsi_vc_enable(dsidev, channel, 1);
2788
2789 dsi->vc[channel].mode = DSI_VC_MODE_VP;
2790
2791 return 0;
2792 }
2793
2794
2795 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2796 bool enable)
2797 {
2798 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2799
2800 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2801
2802 WARN_ON(!dsi_bus_is_locked(dsidev));
2803
2804 dsi_vc_enable(dsidev, channel, 0);
2805 dsi_if_enable(dsidev, 0);
2806
2807 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2808
2809 dsi_vc_enable(dsidev, channel, 1);
2810 dsi_if_enable(dsidev, 1);
2811
2812 dsi_force_tx_stop_mode_io(dsidev);
2813 }
2814 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
2815
2816 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2817 {
2818 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2819 u32 val;
2820 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2821 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2822 (val >> 0) & 0xff,
2823 (val >> 8) & 0xff,
2824 (val >> 16) & 0xff,
2825 (val >> 24) & 0xff);
2826 }
2827 }
2828
2829 static void dsi_show_rx_ack_with_err(u16 err)
2830 {
2831 DSSERR("\tACK with ERROR (%#x):\n", err);
2832 if (err & (1 << 0))
2833 DSSERR("\t\tSoT Error\n");
2834 if (err & (1 << 1))
2835 DSSERR("\t\tSoT Sync Error\n");
2836 if (err & (1 << 2))
2837 DSSERR("\t\tEoT Sync Error\n");
2838 if (err & (1 << 3))
2839 DSSERR("\t\tEscape Mode Entry Command Error\n");
2840 if (err & (1 << 4))
2841 DSSERR("\t\tLP Transmit Sync Error\n");
2842 if (err & (1 << 5))
2843 DSSERR("\t\tHS Receive Timeout Error\n");
2844 if (err & (1 << 6))
2845 DSSERR("\t\tFalse Control Error\n");
2846 if (err & (1 << 7))
2847 DSSERR("\t\t(reserved7)\n");
2848 if (err & (1 << 8))
2849 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2850 if (err & (1 << 9))
2851 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2852 if (err & (1 << 10))
2853 DSSERR("\t\tChecksum Error\n");
2854 if (err & (1 << 11))
2855 DSSERR("\t\tData type not recognized\n");
2856 if (err & (1 << 12))
2857 DSSERR("\t\tInvalid VC ID\n");
2858 if (err & (1 << 13))
2859 DSSERR("\t\tInvalid Transmission Length\n");
2860 if (err & (1 << 14))
2861 DSSERR("\t\t(reserved14)\n");
2862 if (err & (1 << 15))
2863 DSSERR("\t\tDSI Protocol Violation\n");
2864 }
2865
2866 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2867 int channel)
2868 {
2869 /* RX_FIFO_NOT_EMPTY */
2870 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2871 u32 val;
2872 u8 dt;
2873 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2874 DSSERR("\trawval %#08x\n", val);
2875 dt = FLD_GET(val, 5, 0);
2876 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
2877 u16 err = FLD_GET(val, 23, 8);
2878 dsi_show_rx_ack_with_err(err);
2879 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
2880 DSSERR("\tDCS short response, 1 byte: %#x\n",
2881 FLD_GET(val, 23, 8));
2882 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
2883 DSSERR("\tDCS short response, 2 byte: %#x\n",
2884 FLD_GET(val, 23, 8));
2885 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
2886 DSSERR("\tDCS long response, len %d\n",
2887 FLD_GET(val, 23, 8));
2888 dsi_vc_flush_long_data(dsidev, channel);
2889 } else {
2890 DSSERR("\tunknown datatype 0x%02x\n", dt);
2891 }
2892 }
2893 return 0;
2894 }
2895
2896 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2897 {
2898 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2899
2900 if (dsi->debug_write || dsi->debug_read)
2901 DSSDBG("dsi_vc_send_bta %d\n", channel);
2902
2903 WARN_ON(!dsi_bus_is_locked(dsidev));
2904
2905 /* RX_FIFO_NOT_EMPTY */
2906 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2907 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2908 dsi_vc_flush_receive_data(dsidev, channel);
2909 }
2910
2911 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2912
2913 return 0;
2914 }
2915
2916 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2917 {
2918 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2919 DECLARE_COMPLETION_ONSTACK(completion);
2920 int r = 0;
2921 u32 err;
2922
2923 r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2924 &completion, DSI_VC_IRQ_BTA);
2925 if (r)
2926 goto err0;
2927
2928 r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2929 DSI_IRQ_ERROR_MASK);
2930 if (r)
2931 goto err1;
2932
2933 r = dsi_vc_send_bta(dsidev, channel);
2934 if (r)
2935 goto err2;
2936
2937 if (wait_for_completion_timeout(&completion,
2938 msecs_to_jiffies(500)) == 0) {
2939 DSSERR("Failed to receive BTA\n");
2940 r = -EIO;
2941 goto err2;
2942 }
2943
2944 err = dsi_get_errors(dsidev);
2945 if (err) {
2946 DSSERR("Error while sending BTA: %x\n", err);
2947 r = -EIO;
2948 goto err2;
2949 }
2950 err2:
2951 dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2952 DSI_IRQ_ERROR_MASK);
2953 err1:
2954 dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2955 &completion, DSI_VC_IRQ_BTA);
2956 err0:
2957 return r;
2958 }
2959 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
2960
2961 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2962 int channel, u8 data_type, u16 len, u8 ecc)
2963 {
2964 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2965 u32 val;
2966 u8 data_id;
2967
2968 WARN_ON(!dsi_bus_is_locked(dsidev));
2969
2970 data_id = data_type | dsi->vc[channel].vc_id << 6;
2971
2972 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2973 FLD_VAL(ecc, 31, 24);
2974
2975 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2976 }
2977
2978 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2979 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2980 {
2981 u32 val;
2982
2983 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
2984
2985 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2986 b1, b2, b3, b4, val); */
2987
2988 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2989 }
2990
2991 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2992 u8 data_type, u8 *data, u16 len, u8 ecc)
2993 {
2994 /*u32 val; */
2995 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2996 int i;
2997 u8 *p;
2998 int r = 0;
2999 u8 b1, b2, b3, b4;
3000
3001 if (dsi->debug_write)
3002 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
3003
3004 /* len + header */
3005 if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
3006 DSSERR("unable to send long packet: packet too long.\n");
3007 return -EINVAL;
3008 }
3009
3010 dsi_vc_config_l4(dsidev, channel);
3011
3012 dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
3013
3014 p = data;
3015 for (i = 0; i < len >> 2; i++) {
3016 if (dsi->debug_write)
3017 DSSDBG("\tsending full packet %d\n", i);
3018
3019 b1 = *p++;
3020 b2 = *p++;
3021 b3 = *p++;
3022 b4 = *p++;
3023
3024 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
3025 }
3026
3027 i = len % 4;
3028 if (i) {
3029 b1 = 0; b2 = 0; b3 = 0;
3030
3031 if (dsi->debug_write)
3032 DSSDBG("\tsending remainder bytes %d\n", i);
3033
3034 switch (i) {
3035 case 3:
3036 b1 = *p++;
3037 b2 = *p++;
3038 b3 = *p++;
3039 break;
3040 case 2:
3041 b1 = *p++;
3042 b2 = *p++;
3043 break;
3044 case 1:
3045 b1 = *p++;
3046 break;
3047 }
3048
3049 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
3050 }
3051
3052 return r;
3053 }
3054
3055 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
3056 u8 data_type, u16 data, u8 ecc)
3057 {
3058 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3059 u32 r;
3060 u8 data_id;
3061
3062 WARN_ON(!dsi_bus_is_locked(dsidev));
3063
3064 if (dsi->debug_write)
3065 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
3066 channel,
3067 data_type, data & 0xff, (data >> 8) & 0xff);
3068
3069 dsi_vc_config_l4(dsidev, channel);
3070
3071 if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
3072 DSSERR("ERROR FIFO FULL, aborting transfer\n");
3073 return -EINVAL;
3074 }
3075
3076 data_id = data_type | dsi->vc[channel].vc_id << 6;
3077
3078 r = (data_id << 0) | (data << 8) | (ecc << 24);
3079
3080 dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
3081
3082 return 0;
3083 }
3084
3085 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
3086 {
3087 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3088 u8 nullpkg[] = {0, 0, 0, 0};
3089
3090 return dsi_vc_send_long(dsidev, channel, DSI_DT_NULL_PACKET, nullpkg,
3091 4, 0);
3092 }
3093 EXPORT_SYMBOL(dsi_vc_send_null);
3094
3095 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
3096 u8 *data, int len)
3097 {
3098 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3099 int r;
3100
3101 BUG_ON(len == 0);
3102
3103 if (len == 1) {
3104 r = dsi_vc_send_short(dsidev, channel, DSI_DT_DCS_SHORT_WRITE_0,
3105 data[0], 0);
3106 } else if (len == 2) {
3107 r = dsi_vc_send_short(dsidev, channel, DSI_DT_DCS_SHORT_WRITE_1,
3108 data[0] | (data[1] << 8), 0);
3109 } else {
3110 /* 0x39 = DCS Long Write */
3111 r = dsi_vc_send_long(dsidev, channel, DSI_DT_DCS_LONG_WRITE,
3112 data, len, 0);
3113 }
3114
3115 return r;
3116 }
3117 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
3118
3119 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3120 int len)
3121 {
3122 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3123 int r;
3124
3125 r = dsi_vc_dcs_write_nosync(dssdev, channel, data, len);
3126 if (r)
3127 goto err;
3128
3129 r = dsi_vc_send_bta_sync(dssdev, channel);
3130 if (r)
3131 goto err;
3132
3133 /* RX_FIFO_NOT_EMPTY */
3134 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3135 DSSERR("rx fifo not empty after write, dumping data:\n");
3136 dsi_vc_flush_receive_data(dsidev, channel);
3137 r = -EIO;
3138 goto err;
3139 }
3140
3141 return 0;
3142 err:
3143 DSSERR("dsi_vc_dcs_write(ch %d, cmd 0x%02x, len %d) failed\n",
3144 channel, data[0], len);
3145 return r;
3146 }
3147 EXPORT_SYMBOL(dsi_vc_dcs_write);
3148
3149 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd)
3150 {
3151 return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1);
3152 }
3153 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
3154
3155 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3156 u8 param)
3157 {
3158 u8 buf[2];
3159 buf[0] = dcs_cmd;
3160 buf[1] = param;
3161 return dsi_vc_dcs_write(dssdev, channel, buf, 2);
3162 }
3163 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
3164
3165 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3166 u8 *buf, int buflen)
3167 {
3168 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3169 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3170 u32 val;
3171 u8 dt;
3172 int r;
3173
3174 if (dsi->debug_read)
3175 DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel, dcs_cmd);
3176
3177 r = dsi_vc_send_short(dsidev, channel, DSI_DT_DCS_READ, dcs_cmd, 0);
3178 if (r)
3179 goto err;
3180
3181 r = dsi_vc_send_bta_sync(dssdev, channel);
3182 if (r)
3183 goto err;
3184
3185 /* RX_FIFO_NOT_EMPTY */
3186 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
3187 DSSERR("RX fifo empty when trying to read.\n");
3188 r = -EIO;
3189 goto err;
3190 }
3191
3192 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3193 if (dsi->debug_read)
3194 DSSDBG("\theader: %08x\n", val);
3195 dt = FLD_GET(val, 5, 0);
3196 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
3197 u16 err = FLD_GET(val, 23, 8);
3198 dsi_show_rx_ack_with_err(err);
3199 r = -EIO;
3200 goto err;
3201
3202 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
3203 u8 data = FLD_GET(val, 15, 8);
3204 if (dsi->debug_read)
3205 DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
3206
3207 if (buflen < 1) {
3208 r = -EIO;
3209 goto err;
3210 }
3211
3212 buf[0] = data;
3213
3214 return 1;
3215 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
3216 u16 data = FLD_GET(val, 23, 8);
3217 if (dsi->debug_read)
3218 DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
3219
3220 if (buflen < 2) {
3221 r = -EIO;
3222 goto err;
3223 }
3224
3225 buf[0] = data & 0xff;
3226 buf[1] = (data >> 8) & 0xff;
3227
3228 return 2;
3229 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
3230 int w;
3231 int len = FLD_GET(val, 23, 8);
3232 if (dsi->debug_read)
3233 DSSDBG("\tDCS long response, len %d\n", len);
3234
3235 if (len > buflen) {
3236 r = -EIO;
3237 goto err;
3238 }
3239
3240 /* two byte checksum ends the packet, not included in len */
3241 for (w = 0; w < len + 2;) {
3242 int b;
3243 val = dsi_read_reg(dsidev,
3244 DSI_VC_SHORT_PACKET_HEADER(channel));
3245 if (dsi->debug_read)
3246 DSSDBG("\t\t%02x %02x %02x %02x\n",
3247 (val >> 0) & 0xff,
3248 (val >> 8) & 0xff,
3249 (val >> 16) & 0xff,
3250 (val >> 24) & 0xff);
3251
3252 for (b = 0; b < 4; ++b) {
3253 if (w < len)
3254 buf[w] = (val >> (b * 8)) & 0xff;
3255 /* we discard the 2 byte checksum */
3256 ++w;
3257 }
3258 }
3259
3260 return len;
3261 } else {
3262 DSSERR("\tunknown datatype 0x%02x\n", dt);
3263 r = -EIO;
3264 goto err;
3265 }
3266
3267 BUG();
3268 err:
3269 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n",
3270 channel, dcs_cmd);
3271 return r;
3272
3273 }
3274 EXPORT_SYMBOL(dsi_vc_dcs_read);
3275
3276 int dsi_vc_dcs_read_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3277 u8 *data)
3278 {
3279 int r;
3280
3281 r = dsi_vc_dcs_read(dssdev, channel, dcs_cmd, data, 1);
3282
3283 if (r < 0)
3284 return r;
3285
3286 if (r != 1)
3287 return -EIO;
3288
3289 return 0;
3290 }
3291 EXPORT_SYMBOL(dsi_vc_dcs_read_1);
3292
3293 int dsi_vc_dcs_read_2(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3294 u8 *data1, u8 *data2)
3295 {
3296 u8 buf[2];
3297 int r;
3298
3299 r = dsi_vc_dcs_read(dssdev, channel, dcs_cmd, buf, 2);
3300
3301 if (r < 0)
3302 return r;
3303
3304 if (r != 2)
3305 return -EIO;
3306
3307 *data1 = buf[0];
3308 *data2 = buf[1];
3309
3310 return 0;
3311 }
3312 EXPORT_SYMBOL(dsi_vc_dcs_read_2);
3313
3314 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3315 u16 len)
3316 {
3317 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3318
3319 return dsi_vc_send_short(dsidev, channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
3320 len, 0);
3321 }
3322 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
3323
3324 static int dsi_enter_ulps(struct platform_device *dsidev)
3325 {
3326 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3327 DECLARE_COMPLETION_ONSTACK(completion);
3328 int r;
3329
3330 DSSDBGF();
3331
3332 WARN_ON(!dsi_bus_is_locked(dsidev));
3333
3334 WARN_ON(dsi->ulps_enabled);
3335
3336 if (dsi->ulps_enabled)
3337 return 0;
3338
3339 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3340 DSSERR("DDR_CLK_ALWAYS_ON enabled when entering ULPS\n");
3341 return -EIO;
3342 }
3343
3344 dsi_sync_vc(dsidev, 0);
3345 dsi_sync_vc(dsidev, 1);
3346 dsi_sync_vc(dsidev, 2);
3347 dsi_sync_vc(dsidev, 3);
3348
3349 dsi_force_tx_stop_mode_io(dsidev);
3350
3351 dsi_vc_enable(dsidev, 0, false);
3352 dsi_vc_enable(dsidev, 1, false);
3353 dsi_vc_enable(dsidev, 2, false);
3354 dsi_vc_enable(dsidev, 3, false);
3355
3356 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
3357 DSSERR("HS busy when enabling ULPS\n");
3358 return -EIO;
3359 }
3360
3361 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
3362 DSSERR("LP busy when enabling ULPS\n");
3363 return -EIO;
3364 }
3365
3366 r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3367 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3368 if (r)
3369 return r;
3370
3371 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3372 /* LANEx_ULPS_SIG2 */
3373 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (1 << 0) | (1 << 1) | (1 << 2),
3374 7, 5);
3375
3376 if (wait_for_completion_timeout(&completion,
3377 msecs_to_jiffies(1000)) == 0) {
3378 DSSERR("ULPS enable timeout\n");
3379 r = -EIO;
3380 goto err;
3381 }
3382
3383 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3384 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3385
3386 /* Reset LANEx_ULPS_SIG2 */
3387 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (0 << 0) | (0 << 1) | (0 << 2),
3388 7, 5);
3389
3390 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3391
3392 dsi_if_enable(dsidev, false);
3393
3394 dsi->ulps_enabled = true;
3395
3396 return 0;
3397
3398 err:
3399 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3400 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3401 return r;
3402 }
3403
3404 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3405 unsigned ticks, bool x4, bool x16)
3406 {
3407 unsigned long fck;
3408 unsigned long total_ticks;
3409 u32 r;
3410
3411 BUG_ON(ticks > 0x1fff);
3412
3413 /* ticks in DSI_FCK */
3414 fck = dsi_fclk_rate(dsidev);
3415
3416 r = dsi_read_reg(dsidev, DSI_TIMING2);
3417 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
3418 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3419 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3420 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
3421 dsi_write_reg(dsidev, DSI_TIMING2, r);
3422
3423 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3424
3425 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3426 total_ticks,
3427 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3428 (total_ticks * 1000) / (fck / 1000 / 1000));
3429 }
3430
3431 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3432 bool x8, bool x16)
3433 {
3434 unsigned long fck;
3435 unsigned long total_ticks;
3436 u32 r;
3437
3438 BUG_ON(ticks > 0x1fff);
3439
3440 /* ticks in DSI_FCK */
3441 fck = dsi_fclk_rate(dsidev);
3442
3443 r = dsi_read_reg(dsidev, DSI_TIMING1);
3444 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
3445 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
3446 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3447 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
3448 dsi_write_reg(dsidev, DSI_TIMING1, r);
3449
3450 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3451
3452 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3453 total_ticks,
3454 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3455 (total_ticks * 1000) / (fck / 1000 / 1000));
3456 }
3457
3458 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3459 unsigned ticks, bool x4, bool x16)
3460 {
3461 unsigned long fck;
3462 unsigned long total_ticks;
3463 u32 r;
3464
3465 BUG_ON(ticks > 0x1fff);
3466
3467 /* ticks in DSI_FCK */
3468 fck = dsi_fclk_rate(dsidev);
3469
3470 r = dsi_read_reg(dsidev, DSI_TIMING1);
3471 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3472 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3473 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3474 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
3475 dsi_write_reg(dsidev, DSI_TIMING1, r);
3476
3477 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3478
3479 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3480 total_ticks,
3481 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3482 (total_ticks * 1000) / (fck / 1000 / 1000));
3483 }
3484
3485 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3486 unsigned ticks, bool x4, bool x16)
3487 {
3488 unsigned long fck;
3489 unsigned long total_ticks;
3490 u32 r;
3491
3492 BUG_ON(ticks > 0x1fff);
3493
3494 /* ticks in TxByteClkHS */
3495 fck = dsi_get_txbyteclkhs(dsidev);
3496
3497 r = dsi_read_reg(dsidev, DSI_TIMING2);
3498 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
3499 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3500 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3501 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
3502 dsi_write_reg(dsidev, DSI_TIMING2, r);
3503
3504 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3505
3506 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3507 total_ticks,
3508 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3509 (total_ticks * 1000) / (fck / 1000 / 1000));
3510 }
3511 static int dsi_proto_config(struct omap_dss_device *dssdev)
3512 {
3513 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3514 u32 r;
3515 int buswidth = 0;
3516
3517 dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3518 DSI_FIFO_SIZE_32,
3519 DSI_FIFO_SIZE_32,
3520 DSI_FIFO_SIZE_32);
3521
3522 dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3523 DSI_FIFO_SIZE_32,
3524 DSI_FIFO_SIZE_32,
3525 DSI_FIFO_SIZE_32);
3526
3527 /* XXX what values for the timeouts? */
3528 dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3529 dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3530 dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3531 dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3532
3533 switch (dssdev->ctrl.pixel_size) {
3534 case 16:
3535 buswidth = 0;
3536 break;
3537 case 18:
3538 buswidth = 1;
3539 break;
3540 case 24:
3541 buswidth = 2;
3542 break;
3543 default:
3544 BUG();
3545 }
3546
3547 r = dsi_read_reg(dsidev, DSI_CTRL);
3548 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
3549 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
3550 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
3551 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
3552 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3553 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
3554 r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
3555 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
3556 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
3557 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3558 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
3559 /* DCS_CMD_CODE, 1=start, 0=continue */
3560 r = FLD_MOD(r, 0, 25, 25);
3561 }
3562
3563 dsi_write_reg(dsidev, DSI_CTRL, r);
3564
3565 dsi_vc_initial_config(dsidev, 0);
3566 dsi_vc_initial_config(dsidev, 1);
3567 dsi_vc_initial_config(dsidev, 2);
3568 dsi_vc_initial_config(dsidev, 3);
3569
3570 return 0;
3571 }
3572
3573 static void dsi_proto_timings(struct omap_dss_device *dssdev)
3574 {
3575 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3576 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
3577 unsigned tclk_pre, tclk_post;
3578 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3579 unsigned ths_trail, ths_exit;
3580 unsigned ddr_clk_pre, ddr_clk_post;
3581 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3582 unsigned ths_eot;
3583 u32 r;
3584
3585 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3586 ths_prepare = FLD_GET(r, 31, 24);
3587 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3588 ths_zero = ths_prepare_ths_zero - ths_prepare;
3589 ths_trail = FLD_GET(r, 15, 8);
3590 ths_exit = FLD_GET(r, 7, 0);
3591
3592 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3593 tlpx = FLD_GET(r, 22, 16) * 2;
3594 tclk_trail = FLD_GET(r, 15, 8);
3595 tclk_zero = FLD_GET(r, 7, 0);
3596
3597 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3598 tclk_prepare = FLD_GET(r, 7, 0);
3599
3600 /* min 8*UI */
3601 tclk_pre = 20;
3602 /* min 60ns + 52*UI */
3603 tclk_post = ns2ddr(dsidev, 60) + 26;
3604
3605 ths_eot = DIV_ROUND_UP(4, dsi_get_num_data_lanes_dssdev(dssdev));
3606
3607 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3608 4);
3609 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3610
3611 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3612 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3613
3614 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3615 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3616 r = FLD_MOD(r, ddr_clk_post, 7, 0);
3617 dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3618
3619 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3620 ddr_clk_pre,
3621 ddr_clk_post);
3622
3623 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3624 DIV_ROUND_UP(ths_prepare, 4) +
3625 DIV_ROUND_UP(ths_zero + 3, 4);
3626
3627 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3628
3629 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3630 FLD_VAL(exit_hs_mode_lat, 15, 0);
3631 dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3632
3633 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3634 enter_hs_mode_lat, exit_hs_mode_lat);
3635 }
3636
3637
3638 #define DSI_DECL_VARS \
3639 int __dsi_cb = 0; u32 __dsi_cv = 0;
3640
3641 #define DSI_FLUSH(dsidev, ch) \
3642 if (__dsi_cb > 0) { \
3643 /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
3644 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
3645 __dsi_cb = __dsi_cv = 0; \
3646 }
3647
3648 #define DSI_PUSH(dsidev, ch, data) \
3649 do { \
3650 __dsi_cv |= (data) << (__dsi_cb * 8); \
3651 /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
3652 if (++__dsi_cb > 3) \
3653 DSI_FLUSH(dsidev, ch); \
3654 } while (0)
3655
3656 static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
3657 int x, int y, int w, int h)
3658 {
3659 /* Note: supports only 24bit colors in 32bit container */
3660 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3661 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3662 int first = 1;
3663 int fifo_stalls = 0;
3664 int max_dsi_packet_size;
3665 int max_data_per_packet;
3666 int max_pixels_per_packet;
3667 int pixels_left;
3668 int bytespp = dssdev->ctrl.pixel_size / 8;
3669 int scr_width;
3670 u32 __iomem *data;
3671 int start_offset;
3672 int horiz_inc;
3673 int current_x;
3674 struct omap_overlay *ovl;
3675
3676 debug_irq = 0;
3677
3678 DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
3679 x, y, w, h);
3680
3681 ovl = dssdev->manager->overlays[0];
3682
3683 if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
3684 return -EINVAL;
3685
3686 if (dssdev->ctrl.pixel_size != 24)
3687 return -EINVAL;
3688
3689 scr_width = ovl->info.screen_width;
3690 data = ovl->info.vaddr;
3691
3692 start_offset = scr_width * y + x;
3693 horiz_inc = scr_width - w;
3694 current_x = x;
3695
3696 /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
3697 * in fifo */
3698
3699 /* When using CPU, max long packet size is TX buffer size */
3700 max_dsi_packet_size = dsi->vc[0].fifo_size * 32 * 4;
3701
3702 /* we seem to get better perf if we divide the tx fifo to half,
3703 and while the other half is being sent, we fill the other half
3704 max_dsi_packet_size /= 2; */
3705
3706 max_data_per_packet = max_dsi_packet_size - 4 - 1;
3707
3708 max_pixels_per_packet = max_data_per_packet / bytespp;
3709
3710 DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
3711
3712 pixels_left = w * h;
3713
3714 DSSDBG("total pixels %d\n", pixels_left);
3715
3716 data += start_offset;
3717
3718 while (pixels_left > 0) {
3719 /* 0x2c = write_memory_start */
3720 /* 0x3c = write_memory_continue */
3721 u8 dcs_cmd = first ? 0x2c : 0x3c;
3722 int pixels;
3723 DSI_DECL_VARS;
3724 first = 0;
3725
3726 #if 1
3727 /* using fifo not empty */
3728 /* TX_FIFO_NOT_EMPTY */
3729 while (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(0)), 5, 5)) {
3730 fifo_stalls++;
3731 if (fifo_stalls > 0xfffff) {
3732 DSSERR("fifo stalls overflow, pixels left %d\n",
3733 pixels_left);
3734 dsi_if_enable(dsidev, 0);
3735 return -EIO;
3736 }
3737 udelay(1);
3738 }
3739 #elif 1
3740 /* using fifo emptiness */
3741 while ((REG_GET(dsidev, DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
3742 max_dsi_packet_size) {
3743 fifo_stalls++;
3744 if (fifo_stalls > 0xfffff) {
3745 DSSERR("fifo stalls overflow, pixels left %d\n",
3746 pixels_left);
3747 dsi_if_enable(dsidev, 0);
3748 return -EIO;
3749 }
3750 }
3751 #else
3752 while ((REG_GET(dsidev, DSI_TX_FIFO_VC_EMPTINESS,
3753 7, 0) + 1) * 4 == 0) {
3754 fifo_stalls++;
3755 if (fifo_stalls > 0xfffff) {
3756 DSSERR("fifo stalls overflow, pixels left %d\n",
3757 pixels_left);
3758 dsi_if_enable(dsidev, 0);
3759 return -EIO;
3760 }
3761 }
3762 #endif
3763 pixels = min(max_pixels_per_packet, pixels_left);
3764
3765 pixels_left -= pixels;
3766
3767 dsi_vc_write_long_header(dsidev, 0, DSI_DT_DCS_LONG_WRITE,
3768 1 + pixels * bytespp, 0);
3769
3770 DSI_PUSH(dsidev, 0, dcs_cmd);
3771
3772 while (pixels-- > 0) {
3773 u32 pix = __raw_readl(data++);
3774
3775 DSI_PUSH(dsidev, 0, (pix >> 16) & 0xff);
3776 DSI_PUSH(dsidev, 0, (pix >> 8) & 0xff);
3777 DSI_PUSH(dsidev, 0, (pix >> 0) & 0xff);
3778
3779 current_x++;
3780 if (current_x == x+w) {
3781 current_x = x;
3782 data += horiz_inc;
3783 }
3784 }
3785
3786 DSI_FLUSH(dsidev, 0);
3787 }
3788
3789 return 0;
3790 }
3791
3792 static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
3793 u16 x, u16 y, u16 w, u16 h)
3794 {
3795 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3796 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3797 unsigned bytespp;
3798 unsigned bytespl;
3799 unsigned bytespf;
3800 unsigned total_len;
3801 unsigned packet_payload;
3802 unsigned packet_len;
3803 u32 l;
3804 int r;
3805 const unsigned channel = dsi->update_channel;
3806 const unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
3807
3808 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
3809 x, y, w, h);
3810
3811 dsi_vc_config_vp(dsidev, channel);
3812
3813 bytespp = dssdev->ctrl.pixel_size / 8;
3814 bytespl = w * bytespp;
3815 bytespf = bytespl * h;
3816
3817 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
3818 * number of lines in a packet. See errata about VP_CLK_RATIO */
3819
3820 if (bytespf < line_buf_size)
3821 packet_payload = bytespf;
3822 else
3823 packet_payload = (line_buf_size) / bytespl * bytespl;
3824
3825 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
3826 total_len = (bytespf / packet_payload) * packet_len;
3827
3828 if (bytespf % packet_payload)
3829 total_len += (bytespf % packet_payload) + 1;
3830
3831 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
3832 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
3833
3834 dsi_vc_write_long_header(dsidev, channel, DSI_DT_DCS_LONG_WRITE,
3835 packet_len, 0);
3836
3837 if (dsi->te_enabled)
3838 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
3839 else
3840 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
3841 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
3842
3843 /* We put SIDLEMODE to no-idle for the duration of the transfer,
3844 * because DSS interrupts are not capable of waking up the CPU and the
3845 * framedone interrupt could be delayed for quite a long time. I think
3846 * the same goes for any DSS interrupts, but for some reason I have not
3847 * seen the problem anywhere else than here.
3848 */
3849 dispc_disable_sidle();
3850
3851 dsi_perf_mark_start(dsidev);
3852
3853 r = schedule_delayed_work(&dsi->framedone_timeout_work,
3854 msecs_to_jiffies(250));
3855 BUG_ON(r == 0);
3856
3857 dss_start_update(dssdev);
3858
3859 if (dsi->te_enabled) {
3860 /* disable LP_RX_TO, so that we can receive TE. Time to wait
3861 * for TE is longer than the timer allows */
3862 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
3863
3864 dsi_vc_send_bta(dsidev, channel);
3865
3866 #ifdef DSI_CATCH_MISSING_TE
3867 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
3868 #endif
3869 }
3870 }
3871
3872 #ifdef DSI_CATCH_MISSING_TE
3873 static void dsi_te_timeout(unsigned long arg)
3874 {
3875 DSSERR("TE not received for 250ms!\n");
3876 }
3877 #endif
3878
3879 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
3880 {
3881 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3882
3883 /* SIDLEMODE back to smart-idle */
3884 dispc_enable_sidle();
3885
3886 if (dsi->te_enabled) {
3887 /* enable LP_RX_TO again after the TE */
3888 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
3889 }
3890
3891 dsi->framedone_callback(error, dsi->framedone_data);
3892
3893 if (!error)
3894 dsi_perf_show(dsidev, "DISPC");
3895 }
3896
3897 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
3898 {
3899 struct dsi_data *dsi = container_of(work, struct dsi_data,
3900 framedone_timeout_work.work);
3901 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
3902 * 250ms which would conflict with this timeout work. What should be
3903 * done is first cancel the transfer on the HW, and then cancel the
3904 * possibly scheduled framedone work. However, cancelling the transfer
3905 * on the HW is buggy, and would probably require resetting the whole
3906 * DSI */
3907
3908 DSSERR("Framedone not received for 250ms!\n");
3909
3910 dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
3911 }
3912
3913 static void dsi_framedone_irq_callback(void *data, u32 mask)
3914 {
3915 struct omap_dss_device *dssdev = (struct omap_dss_device *) data;
3916 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3917 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3918
3919 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
3920 * turns itself off. However, DSI still has the pixels in its buffers,
3921 * and is sending the data.
3922 */
3923
3924 __cancel_delayed_work(&dsi->framedone_timeout_work);
3925
3926 dsi_handle_framedone(dsidev, 0);
3927
3928 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3929 dispc_fake_vsync_irq();
3930 #endif
3931 }
3932
3933 int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
3934 u16 *x, u16 *y, u16 *w, u16 *h,
3935 bool enlarge_update_area)
3936 {
3937 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3938 u16 dw, dh;
3939
3940 dssdev->driver->get_resolution(dssdev, &dw, &dh);
3941
3942 if (*x > dw || *y > dh)
3943 return -EINVAL;
3944
3945 if (*x + *w > dw)
3946 return -EINVAL;
3947
3948 if (*y + *h > dh)
3949 return -EINVAL;
3950
3951 if (*w == 1)
3952 return -EINVAL;
3953
3954 if (*w == 0 || *h == 0)
3955 return -EINVAL;
3956
3957 dsi_perf_mark_setup(dsidev);
3958
3959 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
3960 dss_setup_partial_planes(dssdev, x, y, w, h,
3961 enlarge_update_area);
3962 dispc_set_lcd_size(dssdev->manager->id, *w, *h);
3963 }
3964
3965 return 0;
3966 }
3967 EXPORT_SYMBOL(omap_dsi_prepare_update);
3968
3969 int omap_dsi_update(struct omap_dss_device *dssdev,
3970 int channel,
3971 u16 x, u16 y, u16 w, u16 h,
3972 void (*callback)(int, void *), void *data)
3973 {
3974 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3975 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3976
3977 dsi->update_channel = channel;
3978
3979 /* OMAP DSS cannot send updates of odd widths.
3980 * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON
3981 * here to make sure we catch erroneous updates. Otherwise we'll only
3982 * see rather obscure HW error happening, as DSS halts. */
3983 BUG_ON(x % 2 == 1);
3984
3985 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
3986 dsi->framedone_callback = callback;
3987 dsi->framedone_data = data;
3988
3989 dsi->update_region.x = x;
3990 dsi->update_region.y = y;
3991 dsi->update_region.w = w;
3992 dsi->update_region.h = h;
3993 dsi->update_region.device = dssdev;
3994
3995 dsi_update_screen_dispc(dssdev, x, y, w, h);
3996 } else {
3997 int r;
3998
3999 r = dsi_update_screen_l4(dssdev, x, y, w, h);
4000 if (r)
4001 return r;
4002
4003 dsi_perf_show(dsidev, "L4");
4004 callback(0, data);
4005 }
4006
4007 return 0;
4008 }
4009 EXPORT_SYMBOL(omap_dsi_update);
4010
4011 /* Display funcs */
4012
4013 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
4014 {
4015 int r;
4016 u32 irq;
4017
4018 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4019 DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4020
4021 r = omap_dispc_register_isr(dsi_framedone_irq_callback, (void *) dssdev,
4022 irq);
4023 if (r) {
4024 DSSERR("can't get FRAMEDONE irq\n");
4025 return r;
4026 }
4027
4028 dispc_set_lcd_display_type(dssdev->manager->id,
4029 OMAP_DSS_LCD_DISPLAY_TFT);
4030
4031 dispc_set_parallel_interface_mode(dssdev->manager->id,
4032 OMAP_DSS_PARALLELMODE_DSI);
4033 dispc_enable_fifohandcheck(dssdev->manager->id, 1);
4034
4035 dispc_set_tft_data_lines(dssdev->manager->id, dssdev->ctrl.pixel_size);
4036
4037 {
4038 struct omap_video_timings timings = {
4039 .hsw = 1,
4040 .hfp = 1,
4041 .hbp = 1,
4042 .vsw = 1,
4043 .vfp = 0,
4044 .vbp = 0,
4045 };
4046
4047 dispc_set_lcd_timings(dssdev->manager->id, &timings);
4048 }
4049
4050 return 0;
4051 }
4052
4053 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
4054 {
4055 u32 irq;
4056
4057 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4058 DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4059
4060 omap_dispc_unregister_isr(dsi_framedone_irq_callback, (void *) dssdev,
4061 irq);
4062 }
4063
4064 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
4065 {
4066 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4067 struct dsi_clock_info cinfo;
4068 int r;
4069
4070 /* we always use DSS_CLK_SYSCK as input clock */
4071 cinfo.use_sys_clk = true;
4072 cinfo.regn = dssdev->clocks.dsi.regn;
4073 cinfo.regm = dssdev->clocks.dsi.regm;
4074 cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc;
4075 cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi;
4076 r = dsi_calc_clock_rates(dssdev, &cinfo);
4077 if (r) {
4078 DSSERR("Failed to calc dsi clocks\n");
4079 return r;
4080 }
4081
4082 r = dsi_pll_set_clock_div(dsidev, &cinfo);
4083 if (r) {
4084 DSSERR("Failed to set dsi clocks\n");
4085 return r;
4086 }
4087
4088 return 0;
4089 }
4090
4091 static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
4092 {
4093 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4094 struct dispc_clock_info dispc_cinfo;
4095 int r;
4096 unsigned long long fck;
4097
4098 fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4099
4100 dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div;
4101 dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div;
4102
4103 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4104 if (r) {
4105 DSSERR("Failed to calc dispc clocks\n");
4106 return r;
4107 }
4108
4109 r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
4110 if (r) {
4111 DSSERR("Failed to set dispc clocks\n");
4112 return r;
4113 }
4114
4115 return 0;
4116 }
4117
4118 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
4119 {
4120 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4121 int dsi_module = dsi_get_dsidev_id(dsidev);
4122 int r;
4123
4124 r = dsi_pll_init(dsidev, true, true);
4125 if (r)
4126 goto err0;
4127
4128 r = dsi_configure_dsi_clocks(dssdev);
4129 if (r)
4130 goto err1;
4131
4132 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
4133 dss_select_dsi_clk_source(dsi_module, dssdev->clocks.dsi.dsi_fclk_src);
4134 dss_select_lcd_clk_source(dssdev->manager->id,
4135 dssdev->clocks.dispc.channel.lcd_clk_src);
4136
4137 DSSDBG("PLL OK\n");
4138
4139 r = dsi_configure_dispc_clocks(dssdev);
4140 if (r)
4141 goto err2;
4142
4143 r = dsi_cio_init(dssdev);
4144 if (r)
4145 goto err2;
4146
4147 _dsi_print_reset_status(dsidev);
4148
4149 dsi_proto_timings(dssdev);
4150 dsi_set_lp_clk_divisor(dssdev);
4151
4152 if (1)
4153 _dsi_print_reset_status(dsidev);
4154
4155 r = dsi_proto_config(dssdev);
4156 if (r)
4157 goto err3;
4158
4159 /* enable interface */
4160 dsi_vc_enable(dsidev, 0, 1);
4161 dsi_vc_enable(dsidev, 1, 1);
4162 dsi_vc_enable(dsidev, 2, 1);
4163 dsi_vc_enable(dsidev, 3, 1);
4164 dsi_if_enable(dsidev, 1);
4165 dsi_force_tx_stop_mode_io(dsidev);
4166
4167 return 0;
4168 err3:
4169 dsi_cio_uninit(dsidev);
4170 err2:
4171 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4172 dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4173 err1:
4174 dsi_pll_uninit(dsidev, true);
4175 err0:
4176 return r;
4177 }
4178
4179 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev,
4180 bool disconnect_lanes, bool enter_ulps)
4181 {
4182 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4183 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4184 int dsi_module = dsi_get_dsidev_id(dsidev);
4185
4186 if (enter_ulps && !dsi->ulps_enabled)
4187 dsi_enter_ulps(dsidev);
4188
4189 /* disable interface */
4190 dsi_if_enable(dsidev, 0);
4191 dsi_vc_enable(dsidev, 0, 0);
4192 dsi_vc_enable(dsidev, 1, 0);
4193 dsi_vc_enable(dsidev, 2, 0);
4194 dsi_vc_enable(dsidev, 3, 0);
4195
4196 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4197 dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4198 dsi_cio_uninit(dsidev);
4199 dsi_pll_uninit(dsidev, disconnect_lanes);
4200 }
4201
4202 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
4203 {
4204 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4205 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4206 int r = 0;
4207
4208 DSSDBG("dsi_display_enable\n");
4209
4210 WARN_ON(!dsi_bus_is_locked(dsidev));
4211
4212 mutex_lock(&dsi->lock);
4213
4214 r = omap_dss_start_device(dssdev);
4215 if (r) {
4216 DSSERR("failed to start device\n");
4217 goto err_start_dev;
4218 }
4219
4220 r = dsi_runtime_get(dsidev);
4221 if (r)
4222 goto err_get_dsi;
4223
4224 dsi_enable_pll_clock(dsidev, 1);
4225
4226 _dsi_initialize_irq(dsidev);
4227
4228 r = dsi_display_init_dispc(dssdev);
4229 if (r)
4230 goto err_init_dispc;
4231
4232 r = dsi_display_init_dsi(dssdev);
4233 if (r)
4234 goto err_init_dsi;
4235
4236 mutex_unlock(&dsi->lock);
4237
4238 return 0;
4239
4240 err_init_dsi:
4241 dsi_display_uninit_dispc(dssdev);
4242 err_init_dispc:
4243 dsi_enable_pll_clock(dsidev, 0);
4244 dsi_runtime_put(dsidev);
4245 err_get_dsi:
4246 omap_dss_stop_device(dssdev);
4247 err_start_dev:
4248 mutex_unlock(&dsi->lock);
4249 DSSDBG("dsi_display_enable FAILED\n");
4250 return r;
4251 }
4252 EXPORT_SYMBOL(omapdss_dsi_display_enable);
4253
4254 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
4255 bool disconnect_lanes, bool enter_ulps)
4256 {
4257 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4258 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4259
4260 DSSDBG("dsi_display_disable\n");
4261
4262 WARN_ON(!dsi_bus_is_locked(dsidev));
4263
4264 mutex_lock(&dsi->lock);
4265
4266 dsi_sync_vc(dsidev, 0);
4267 dsi_sync_vc(dsidev, 1);
4268 dsi_sync_vc(dsidev, 2);
4269 dsi_sync_vc(dsidev, 3);
4270
4271 dsi_display_uninit_dispc(dssdev);
4272
4273 dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps);
4274
4275 dsi_runtime_put(dsidev);
4276 dsi_enable_pll_clock(dsidev, 0);
4277
4278 omap_dss_stop_device(dssdev);
4279
4280 mutex_unlock(&dsi->lock);
4281 }
4282 EXPORT_SYMBOL(omapdss_dsi_display_disable);
4283
4284 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4285 {
4286 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4287 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4288
4289 dsi->te_enabled = enable;
4290 return 0;
4291 }
4292 EXPORT_SYMBOL(omapdss_dsi_enable_te);
4293
4294 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
4295 u32 fifo_size, u32 burst_size,
4296 u32 *fifo_low, u32 *fifo_high)
4297 {
4298 *fifo_high = fifo_size - burst_size;
4299 *fifo_low = fifo_size - burst_size * 2;
4300 }
4301
4302 int dsi_init_display(struct omap_dss_device *dssdev)
4303 {
4304 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4305 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4306 int dsi_module = dsi_get_dsidev_id(dsidev);
4307
4308 DSSDBG("DSI init\n");
4309
4310 /* XXX these should be figured out dynamically */
4311 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
4312 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
4313
4314 if (dsi->vdds_dsi_reg == NULL) {
4315 struct regulator *vdds_dsi;
4316
4317 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
4318
4319 if (IS_ERR(vdds_dsi)) {
4320 DSSERR("can't get VDDS_DSI regulator\n");
4321 return PTR_ERR(vdds_dsi);
4322 }
4323
4324 dsi->vdds_dsi_reg = vdds_dsi;
4325 }
4326
4327 if (dsi_get_num_data_lanes_dssdev(dssdev) > dsi->num_data_lanes) {
4328 DSSERR("DSI%d can't support more than %d data lanes\n",
4329 dsi_module + 1, dsi->num_data_lanes);
4330 return -EINVAL;
4331 }
4332
4333 return 0;
4334 }
4335
4336 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4337 {
4338 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4339 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4340 int i;
4341
4342 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4343 if (!dsi->vc[i].dssdev) {
4344 dsi->vc[i].dssdev = dssdev;
4345 *channel = i;
4346 return 0;
4347 }
4348 }
4349
4350 DSSERR("cannot get VC for display %s", dssdev->name);
4351 return -ENOSPC;
4352 }
4353 EXPORT_SYMBOL(omap_dsi_request_vc);
4354
4355 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
4356 {
4357 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4358 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4359
4360 if (vc_id < 0 || vc_id > 3) {
4361 DSSERR("VC ID out of range\n");
4362 return -EINVAL;
4363 }
4364
4365 if (channel < 0 || channel > 3) {
4366 DSSERR("Virtual Channel out of range\n");
4367 return -EINVAL;
4368 }
4369
4370 if (dsi->vc[channel].dssdev != dssdev) {
4371 DSSERR("Virtual Channel not allocated to display %s\n",
4372 dssdev->name);
4373 return -EINVAL;
4374 }
4375
4376 dsi->vc[channel].vc_id = vc_id;
4377
4378 return 0;
4379 }
4380 EXPORT_SYMBOL(omap_dsi_set_vc_id);
4381
4382 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
4383 {
4384 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4385 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4386
4387 if ((channel >= 0 && channel <= 3) &&
4388 dsi->vc[channel].dssdev == dssdev) {
4389 dsi->vc[channel].dssdev = NULL;
4390 dsi->vc[channel].vc_id = 0;
4391 }
4392 }
4393 EXPORT_SYMBOL(omap_dsi_release_vc);
4394
4395 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
4396 {
4397 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
4398 DSSERR("%s (%s) not active\n",
4399 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
4400 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
4401 }
4402
4403 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
4404 {
4405 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
4406 DSSERR("%s (%s) not active\n",
4407 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
4408 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
4409 }
4410
4411 static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
4412 {
4413 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4414
4415 dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
4416 dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
4417 dsi->regm_dispc_max =
4418 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
4419 dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
4420 dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
4421 dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
4422 dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
4423 }
4424
4425 static int dsi_get_clocks(struct platform_device *dsidev)
4426 {
4427 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4428 struct clk *clk;
4429
4430 clk = clk_get(&dsidev->dev, "fck");
4431 if (IS_ERR(clk)) {
4432 DSSERR("can't get fck\n");
4433 return PTR_ERR(clk);
4434 }
4435
4436 dsi->dss_clk = clk;
4437
4438 if (cpu_is_omap34xx() || cpu_is_omap3630())
4439 clk = clk_get(&dsidev->dev, "dss2_alwon_fck");
4440 else
4441 clk = clk_get(&dsidev->dev, "sys_clk");
4442 if (IS_ERR(clk)) {
4443 DSSERR("can't get sys_clk\n");
4444 clk_put(dsi->dss_clk);
4445 dsi->dss_clk = NULL;
4446 return PTR_ERR(clk);
4447 }
4448
4449 dsi->sys_clk = clk;
4450
4451 return 0;
4452 }
4453
4454 static void dsi_put_clocks(struct platform_device *dsidev)
4455 {
4456 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4457
4458 if (dsi->dss_clk)
4459 clk_put(dsi->dss_clk);
4460 if (dsi->sys_clk)
4461 clk_put(dsi->sys_clk);
4462 }
4463
4464 /* DSI1 HW IP initialisation */
4465 static int omap_dsi1hw_probe(struct platform_device *dsidev)
4466 {
4467 struct omap_display_platform_data *dss_plat_data;
4468 struct omap_dss_board_info *board_info;
4469 u32 rev;
4470 int r, i, dsi_module = dsi_get_dsidev_id(dsidev);
4471 struct resource *dsi_mem;
4472 struct dsi_data *dsi;
4473
4474 dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
4475 if (!dsi) {
4476 r = -ENOMEM;
4477 goto err_alloc;
4478 }
4479
4480 dsi->pdev = dsidev;
4481 dsi_pdev_map[dsi_module] = dsidev;
4482 dev_set_drvdata(&dsidev->dev, dsi);
4483
4484 dss_plat_data = dsidev->dev.platform_data;
4485 board_info = dss_plat_data->board_data;
4486 dsi->dsi_mux_pads = board_info->dsi_mux_pads;
4487
4488 spin_lock_init(&dsi->irq_lock);
4489 spin_lock_init(&dsi->errors_lock);
4490 dsi->errors = 0;
4491
4492 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4493 spin_lock_init(&dsi->irq_stats_lock);
4494 dsi->irq_stats.last_reset = jiffies;
4495 #endif
4496
4497 mutex_init(&dsi->lock);
4498 sema_init(&dsi->bus_lock, 1);
4499
4500 r = dsi_get_clocks(dsidev);
4501 if (r)
4502 goto err_get_clk;
4503
4504 pm_runtime_enable(&dsidev->dev);
4505
4506 INIT_DELAYED_WORK_DEFERRABLE(&dsi->framedone_timeout_work,
4507 dsi_framedone_timeout_work_callback);
4508
4509 #ifdef DSI_CATCH_MISSING_TE
4510 init_timer(&dsi->te_timer);
4511 dsi->te_timer.function = dsi_te_timeout;
4512 dsi->te_timer.data = 0;
4513 #endif
4514 dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
4515 if (!dsi_mem) {
4516 DSSERR("can't get IORESOURCE_MEM DSI\n");
4517 r = -EINVAL;
4518 goto err_ioremap;
4519 }
4520 dsi->base = ioremap(dsi_mem->start, resource_size(dsi_mem));
4521 if (!dsi->base) {
4522 DSSERR("can't ioremap DSI\n");
4523 r = -ENOMEM;
4524 goto err_ioremap;
4525 }
4526 dsi->irq = platform_get_irq(dsi->pdev, 0);
4527 if (dsi->irq < 0) {
4528 DSSERR("platform_get_irq failed\n");
4529 r = -ENODEV;
4530 goto err_get_irq;
4531 }
4532
4533 r = request_irq(dsi->irq, omap_dsi_irq_handler, IRQF_SHARED,
4534 dev_name(&dsidev->dev), dsi->pdev);
4535 if (r < 0) {
4536 DSSERR("request_irq failed\n");
4537 goto err_get_irq;
4538 }
4539
4540 /* DSI VCs initialization */
4541 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4542 dsi->vc[i].mode = DSI_VC_MODE_L4;
4543 dsi->vc[i].dssdev = NULL;
4544 dsi->vc[i].vc_id = 0;
4545 }
4546
4547 dsi_calc_clock_param_ranges(dsidev);
4548
4549 r = dsi_runtime_get(dsidev);
4550 if (r)
4551 goto err_get_dsi;
4552
4553 rev = dsi_read_reg(dsidev, DSI_REVISION);
4554 dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
4555 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4556
4557 dsi->num_data_lanes = dsi_get_num_data_lanes(dsidev);
4558
4559 dsi_runtime_put(dsidev);
4560
4561 return 0;
4562
4563 err_get_dsi:
4564 free_irq(dsi->irq, dsi->pdev);
4565 err_get_irq:
4566 iounmap(dsi->base);
4567 err_ioremap:
4568 pm_runtime_disable(&dsidev->dev);
4569 err_get_clk:
4570 kfree(dsi);
4571 err_alloc:
4572 return r;
4573 }
4574
4575 static int omap_dsi1hw_remove(struct platform_device *dsidev)
4576 {
4577 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4578
4579 WARN_ON(dsi->scp_clk_refcount > 0);
4580
4581 pm_runtime_disable(&dsidev->dev);
4582
4583 dsi_put_clocks(dsidev);
4584
4585 if (dsi->vdds_dsi_reg != NULL) {
4586 if (dsi->vdds_dsi_enabled) {
4587 regulator_disable(dsi->vdds_dsi_reg);
4588 dsi->vdds_dsi_enabled = false;
4589 }
4590
4591 regulator_put(dsi->vdds_dsi_reg);
4592 dsi->vdds_dsi_reg = NULL;
4593 }
4594
4595 free_irq(dsi->irq, dsi->pdev);
4596 iounmap(dsi->base);
4597
4598 kfree(dsi);
4599
4600 return 0;
4601 }
4602
4603 static int dsi_runtime_suspend(struct device *dev)
4604 {
4605 struct dsi_data *dsi = dsi_get_dsidrv_data(to_platform_device(dev));
4606
4607 clk_disable(dsi->dss_clk);
4608
4609 dispc_runtime_put();
4610 dss_runtime_put();
4611
4612 return 0;
4613 }
4614
4615 static int dsi_runtime_resume(struct device *dev)
4616 {
4617 struct dsi_data *dsi = dsi_get_dsidrv_data(to_platform_device(dev));
4618 int r;
4619
4620 r = dss_runtime_get();
4621 if (r)
4622 goto err_get_dss;
4623
4624 r = dispc_runtime_get();
4625 if (r)
4626 goto err_get_dispc;
4627
4628 clk_enable(dsi->dss_clk);
4629
4630 return 0;
4631
4632 err_get_dispc:
4633 dss_runtime_put();
4634 err_get_dss:
4635 return r;
4636 }
4637
4638 static const struct dev_pm_ops dsi_pm_ops = {
4639 .runtime_suspend = dsi_runtime_suspend,
4640 .runtime_resume = dsi_runtime_resume,
4641 };
4642
4643 static struct platform_driver omap_dsi1hw_driver = {
4644 .probe = omap_dsi1hw_probe,
4645 .remove = omap_dsi1hw_remove,
4646 .driver = {
4647 .name = "omapdss_dsi1",
4648 .owner = THIS_MODULE,
4649 .pm = &dsi_pm_ops,
4650 },
4651 };
4652
4653 int dsi_init_platform_driver(void)
4654 {
4655 return platform_driver_register(&omap_dsi1hw_driver);
4656 }
4657
4658 void dsi_uninit_platform_driver(void)
4659 {
4660 return platform_driver_unregister(&omap_dsi1hw_driver);
4661 }