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driver core: remove __must_check from device_create_file
[zen-stable.git] / arch / arm / plat-s3c24xx / s3c2443-clock.c
blob5a21b15b2a978e01b016b7309a4e5585a6ee995a
1 /* linux/arch/arm/plat-s3c24xx/s3c2443-clock.c
2 *
3 * Copyright (c) 2007, 2010 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2443 Clock control suport - common code
7 */
8
9 #include <linux/init.h>
10 #include <linux/clk.h>
11 #include <linux/io.h>
12
13 #include <mach/regs-s3c2443-clock.h>
14
15 #include <plat/s3c2443.h>
16 #include <plat/clock.h>
17 #include <plat/clock-clksrc.h>
18 #include <plat/cpu.h>
19
20 #include <plat/cpu-freq.h>
21
22
23 static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable)
24 {
25 u32 ctrlbit = clk->ctrlbit;
26 u32 con = __raw_readl(reg);
27
28 if (enable)
29 con |= ctrlbit;
30 else
31 con &= ~ctrlbit;
32
33 __raw_writel(con, reg);
34 return 0;
35 }
36
37 int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
38 {
39 return s3c2443_gate(S3C2443_HCLKCON, clk, enable);
40 }
41
42 int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
43 {
44 return s3c2443_gate(S3C2443_PCLKCON, clk, enable);
45 }
46
47 int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
48 {
49 return s3c2443_gate(S3C2443_SCLKCON, clk, enable);
50 }
51
52 /* mpllref is a direct descendant of clk_xtal by default, but it is not
53 * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
54 * such directly equating the two source clocks is impossible.
55 */
56 struct clk clk_mpllref = {
57 .name = "mpllref",
58 .parent = &clk_xtal,
59 };
60
61 static struct clk *clk_epllref_sources[] = {
62 [0] = &clk_mpllref,
63 [1] = &clk_mpllref,
64 [2] = &clk_xtal,
65 [3] = &clk_ext,
66 };
67
68 struct clksrc_clk clk_epllref = {
69 .clk = {
70 .name = "epllref",
71 },
72 .sources = &(struct clksrc_sources) {
73 .sources = clk_epllref_sources,
74 .nr_sources = ARRAY_SIZE(clk_epllref_sources),
75 },
76 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 },
77 };
78
79 /* esysclk
80 *
81 * this is sourced from either the EPLL or the EPLLref clock
82 */
83
84 static struct clk *clk_sysclk_sources[] = {
85 [0] = &clk_epllref.clk,
86 [1] = &clk_epll,
87 };
88
89 struct clksrc_clk clk_esysclk = {
90 .clk = {
91 .name = "esysclk",
92 .parent = &clk_epll,
93 },
94 .sources = &(struct clksrc_sources) {
95 .sources = clk_sysclk_sources,
96 .nr_sources = ARRAY_SIZE(clk_sysclk_sources),
97 },
98 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 },
99 };
100
101 static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
102 {
103 unsigned long parent_rate = clk_get_rate(clk->parent);
104 unsigned long div = __raw_readl(S3C2443_CLKDIV0);
105
106 div &= S3C2443_CLKDIV0_EXTDIV_MASK;
107 div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */
108
109 return parent_rate / (div + 1);
110 }
111
112 static struct clk clk_mdivclk = {
113 .name = "mdivclk",
114 .parent = &clk_mpllref,
115 .ops = &(struct clk_ops) {
116 .get_rate = s3c2443_getrate_mdivclk,
117 },
118 };
119
120 static struct clk *clk_msysclk_sources[] = {
121 [0] = &clk_mpllref,
122 [1] = &clk_mpll,
123 [2] = &clk_mdivclk,
124 [3] = &clk_mpllref,
125 };
126
127 struct clksrc_clk clk_msysclk = {
128 .clk = {
129 .name = "msysclk",
130 .parent = &clk_xtal,
131 },
132 .sources = &(struct clksrc_sources) {
133 .sources = clk_msysclk_sources,
134 .nr_sources = ARRAY_SIZE(clk_msysclk_sources),
135 },
136 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 },
137 };
138
139 /* prediv
140 *
141 * this divides the msysclk down to pass to h/p/etc.
142 */
143
144 static unsigned long s3c2443_prediv_getrate(struct clk *clk)
145 {
146 unsigned long rate = clk_get_rate(clk->parent);
147 unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
148
149 clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
150 clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
151
152 return rate / (clkdiv0 + 1);
153 }
154
155 static struct clk clk_prediv = {
156 .name = "prediv",
157 .parent = &clk_msysclk.clk,
158 .ops = &(struct clk_ops) {
159 .get_rate = s3c2443_prediv_getrate,
160 },
161 };
162
163 /* armdiv
164 *
165 * this clock is sourced from msysclk and can have a number of
166 * divider values applied to it to then be fed into armclk.
167 */
168
169 static unsigned int *armdiv;
170 static int nr_armdiv;
171 static int armdivmask;
172
173 static unsigned long s3c2443_armclk_roundrate(struct clk *clk,
174 unsigned long rate)
175 {
176 unsigned long parent = clk_get_rate(clk->parent);
177 unsigned long calc;
178 unsigned best = 256; /* bigger than any value */
179 unsigned div;
180 int ptr;
181
182 if (!nr_armdiv)
183 return -EINVAL;
184
185 for (ptr = 0; ptr < nr_armdiv; ptr++) {
186 div = armdiv[ptr];
187 if (div) {
188 /* cpufreq provides 266mhz as 266666000 not 266666666 */
189 calc = (parent / div / 1000) * 1000;
190 if (calc <= rate && div < best)
191 best = div;
192 }
193 }
194
195 return parent / best;
196 }
197
198 static unsigned long s3c2443_armclk_getrate(struct clk *clk)
199 {
200 unsigned long rate = clk_get_rate(clk->parent);
201 unsigned long clkcon0;
202 int val;
203
204 if (!nr_armdiv || !armdivmask)
205 return -EINVAL;
206
207 clkcon0 = __raw_readl(S3C2443_CLKDIV0);
208 clkcon0 &= armdivmask;
209 val = clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT;
210
211 return rate / armdiv[val];
212 }
213
214 static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
215 {
216 unsigned long parent = clk_get_rate(clk->parent);
217 unsigned long calc;
218 unsigned div;
219 unsigned best = 256; /* bigger than any value */
220 int ptr;
221 int val = -1;
222
223 if (!nr_armdiv || !armdivmask)
224 return -EINVAL;
225
226 for (ptr = 0; ptr < nr_armdiv; ptr++) {
227 div = armdiv[ptr];
228 if (div) {
229 /* cpufreq provides 266mhz as 266666000 not 266666666 */
230 calc = (parent / div / 1000) * 1000;
231 if (calc <= rate && div < best) {
232 best = div;
233 val = ptr;
234 }
235 }
236 }
237
238 if (val >= 0) {
239 unsigned long clkcon0;
240
241 clkcon0 = __raw_readl(S3C2443_CLKDIV0);
242 clkcon0 &= ~armdivmask;
243 clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
244 __raw_writel(clkcon0, S3C2443_CLKDIV0);
245 }
246
247 return (val == -1) ? -EINVAL : 0;
248 }
249
250 static struct clk clk_armdiv = {
251 .name = "armdiv",
252 .parent = &clk_msysclk.clk,
253 .ops = &(struct clk_ops) {
254 .round_rate = s3c2443_armclk_roundrate,
255 .get_rate = s3c2443_armclk_getrate,
256 .set_rate = s3c2443_armclk_setrate,
257 },
258 };
259
260 /* armclk
261 *
262 * this is the clock fed into the ARM core itself, from armdiv or from hclk.
263 */
264
265 static struct clk *clk_arm_sources[] = {
266 [0] = &clk_armdiv,
267 [1] = &clk_h,
268 };
269
270 static struct clksrc_clk clk_arm = {
271 .clk = {
272 .name = "armclk",
273 },
274 .sources = &(struct clksrc_sources) {
275 .sources = clk_arm_sources,
276 .nr_sources = ARRAY_SIZE(clk_arm_sources),
277 },
278 .reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 },
279 };
280
281 /* usbhost
282 *
283 * usb host bus-clock, usually 48MHz to provide USB bus clock timing
284 */
285
286 static struct clksrc_clk clk_usb_bus_host = {
287 .clk = {
288 .name = "usb-bus-host-parent",
289 .parent = &clk_esysclk.clk,
290 .ctrlbit = S3C2443_SCLKCON_USBHOST,
291 .enable = s3c2443_clkcon_enable_s,
292 },
293 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
294 };
295
296 /* common clksrc clocks */
297
298 static struct clksrc_clk clksrc_clks[] = {
299 {
300 /* ART baud-rate clock sourced from esysclk via a divisor */
301 .clk = {
302 .name = "uartclk",
303 .parent = &clk_esysclk.clk,
304 },
305 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
306 }, {
307 /* camera interface bus-clock, divided down from esysclk */
308 .clk = {
309 .name = "camif-upll", /* same as 2440 name */
310 .parent = &clk_esysclk.clk,
311 .ctrlbit = S3C2443_SCLKCON_CAMCLK,
312 .enable = s3c2443_clkcon_enable_s,
313 },
314 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 },
315 }, {
316 .clk = {
317 .name = "display-if",
318 .parent = &clk_esysclk.clk,
319 .ctrlbit = S3C2443_SCLKCON_DISPCLK,
320 .enable = s3c2443_clkcon_enable_s,
321 },
322 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 },
323 },
324 };
325
326 static struct clk clk_i2s_ext = {
327 .name = "i2s-ext",
328 };
329
330 /* i2s_eplldiv
331 *
332 * This clock is the output from the I2S divisor of ESYSCLK, and is separate
333 * from the mux that comes after it (cannot merge into one single clock)
334 */
335
336 static struct clksrc_clk clk_i2s_eplldiv = {
337 .clk = {
338 .name = "i2s-eplldiv",
339 .parent = &clk_esysclk.clk,
340 },
341 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
342 };
343
344 /* i2s-ref
345 *
346 * i2s bus reference clock, selectable from external, esysclk or epllref
347 *
348 * Note, this used to be two clocks, but was compressed into one.
349 */
350
351 static struct clk *clk_i2s_srclist[] = {
352 [0] = &clk_i2s_eplldiv.clk,
353 [1] = &clk_i2s_ext,
354 [2] = &clk_epllref.clk,
355 [3] = &clk_epllref.clk,
356 };
357
358 static struct clksrc_clk clk_i2s = {
359 .clk = {
360 .name = "i2s-if",
361 .ctrlbit = S3C2443_SCLKCON_I2SCLK,
362 .enable = s3c2443_clkcon_enable_s,
363
364 },
365 .sources = &(struct clksrc_sources) {
366 .sources = clk_i2s_srclist,
367 .nr_sources = ARRAY_SIZE(clk_i2s_srclist),
368 },
369 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
370 };
371
372 static struct clk init_clocks_off[] = {
373 {
374 .name = "iis",
375 .parent = &clk_p,
376 .enable = s3c2443_clkcon_enable_p,
377 .ctrlbit = S3C2443_PCLKCON_IIS,
378 }, {
379 .name = "hsspi",
380 .parent = &clk_p,
381 .enable = s3c2443_clkcon_enable_p,
382 .ctrlbit = S3C2443_PCLKCON_HSSPI,
383 }, {
384 .name = "adc",
385 .parent = &clk_p,
386 .enable = s3c2443_clkcon_enable_p,
387 .ctrlbit = S3C2443_PCLKCON_ADC,
388 }, {
389 .name = "i2c",
390 .parent = &clk_p,
391 .enable = s3c2443_clkcon_enable_p,
392 .ctrlbit = S3C2443_PCLKCON_IIC,
393 }
394 };
395
396 static struct clk init_clocks[] = {
397 {
398 .name = "dma",
399 .parent = &clk_h,
400 .enable = s3c2443_clkcon_enable_h,
401 .ctrlbit = S3C2443_HCLKCON_DMA0,
402 }, {
403 .name = "dma",
404 .parent = &clk_h,
405 .enable = s3c2443_clkcon_enable_h,
406 .ctrlbit = S3C2443_HCLKCON_DMA1,
407 }, {
408 .name = "dma",
409 .parent = &clk_h,
410 .enable = s3c2443_clkcon_enable_h,
411 .ctrlbit = S3C2443_HCLKCON_DMA2,
412 }, {
413 .name = "dma",
414 .parent = &clk_h,
415 .enable = s3c2443_clkcon_enable_h,
416 .ctrlbit = S3C2443_HCLKCON_DMA3,
417 }, {
418 .name = "dma",
419 .parent = &clk_h,
420 .enable = s3c2443_clkcon_enable_h,
421 .ctrlbit = S3C2443_HCLKCON_DMA4,
422 }, {
423 .name = "dma",
424 .parent = &clk_h,
425 .enable = s3c2443_clkcon_enable_h,
426 .ctrlbit = S3C2443_HCLKCON_DMA5,
427 }, {
428 .name = "hsmmc",
429 .devname = "s3c-sdhci.1",
430 .parent = &clk_h,
431 .enable = s3c2443_clkcon_enable_h,
432 .ctrlbit = S3C2443_HCLKCON_HSMMC,
433 }, {
434 .name = "gpio",
435 .parent = &clk_p,
436 .enable = s3c2443_clkcon_enable_p,
437 .ctrlbit = S3C2443_PCLKCON_GPIO,
438 }, {
439 .name = "usb-host",
440 .parent = &clk_h,
441 .enable = s3c2443_clkcon_enable_h,
442 .ctrlbit = S3C2443_HCLKCON_USBH,
443 }, {
444 .name = "usb-device",
445 .parent = &clk_h,
446 .enable = s3c2443_clkcon_enable_h,
447 .ctrlbit = S3C2443_HCLKCON_USBD,
448 }, {
449 .name = "lcd",
450 .parent = &clk_h,
451 .enable = s3c2443_clkcon_enable_h,
452 .ctrlbit = S3C2443_HCLKCON_LCDC,
453
454 }, {
455 .name = "timers",
456 .parent = &clk_p,
457 .enable = s3c2443_clkcon_enable_p,
458 .ctrlbit = S3C2443_PCLKCON_PWMT,
459 }, {
460 .name = "cfc",
461 .parent = &clk_h,
462 .enable = s3c2443_clkcon_enable_h,
463 .ctrlbit = S3C2443_HCLKCON_CFC,
464 }, {
465 .name = "ssmc",
466 .parent = &clk_h,
467 .enable = s3c2443_clkcon_enable_h,
468 .ctrlbit = S3C2443_HCLKCON_SSMC,
469 }, {
470 .name = "uart",
471 .devname = "s3c2440-uart.0",
472 .parent = &clk_p,
473 .enable = s3c2443_clkcon_enable_p,
474 .ctrlbit = S3C2443_PCLKCON_UART0,
475 }, {
476 .name = "uart",
477 .devname = "s3c2440-uart.1",
478 .parent = &clk_p,
479 .enable = s3c2443_clkcon_enable_p,
480 .ctrlbit = S3C2443_PCLKCON_UART1,
481 }, {
482 .name = "uart",
483 .devname = "s3c2440-uart.2",
484 .parent = &clk_p,
485 .enable = s3c2443_clkcon_enable_p,
486 .ctrlbit = S3C2443_PCLKCON_UART2,
487 }, {
488 .name = "uart",
489 .devname = "s3c2440-uart.3",
490 .parent = &clk_p,
491 .enable = s3c2443_clkcon_enable_p,
492 .ctrlbit = S3C2443_PCLKCON_UART3,
493 }, {
494 .name = "rtc",
495 .parent = &clk_p,
496 .enable = s3c2443_clkcon_enable_p,
497 .ctrlbit = S3C2443_PCLKCON_RTC,
498 }, {
499 .name = "watchdog",
500 .parent = &clk_p,
501 .ctrlbit = S3C2443_PCLKCON_WDT,
502 }, {
503 .name = "ac97",
504 .parent = &clk_p,
505 .ctrlbit = S3C2443_PCLKCON_AC97,
506 }, {
507 .name = "nand",
508 .parent = &clk_h,
509 }, {
510 .name = "usb-bus-host",
511 .parent = &clk_usb_bus_host.clk,
512 }
513 };
514
515 static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
516 {
517 clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
518
519 return clkcon0 + 1;
520 }
521
522 /* EPLLCON compatible enough to get on/off information */
523
524 void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
525 {
526 unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
527 unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
528 unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
529 struct clk *xtal_clk;
530 unsigned long xtal;
531 unsigned long pll;
532 unsigned long fclk;
533 unsigned long hclk;
534 unsigned long pclk;
535 int ptr;
536
537 xtal_clk = clk_get(NULL, "xtal");
538 xtal = clk_get_rate(xtal_clk);
539 clk_put(xtal_clk);
540
541 pll = get_mpll(mpllcon, xtal);
542 clk_msysclk.clk.rate = pll;
543
544 fclk = clk_get_rate(&clk_armdiv);
545 hclk = s3c2443_prediv_getrate(&clk_prediv);
546 hclk /= s3c2443_get_hdiv(clkdiv0);
547 pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
548
549 s3c24xx_setup_clocks(fclk, hclk, pclk);
550
551 printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
552 (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
553 print_mhz(pll), print_mhz(fclk),
554 print_mhz(hclk), print_mhz(pclk));
555
556 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
557 s3c_set_clksrc(&clksrc_clks[ptr], true);
558
559 /* ensure usb bus clock is within correct rate of 48MHz */
560
561 if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) {
562 printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
563 clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000);
564 }
565
566 printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
567 (epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
568 print_mhz(clk_get_rate(&clk_epll)),
569 print_mhz(clk_get_rate(&clk_usb_bus)));
570 }
571
572 static struct clk *clks[] __initdata = {
573 &clk_prediv,
574 &clk_mpllref,
575 &clk_mdivclk,
576 &clk_ext,
577 &clk_epll,
578 &clk_usb_bus,
579 &clk_armdiv,
580 };
581
582 static struct clksrc_clk *clksrcs[] __initdata = {
583 &clk_i2s_eplldiv,
584 &clk_i2s,
585 &clk_usb_bus_host,
586 &clk_epllref,
587 &clk_esysclk,
588 &clk_msysclk,
589 &clk_arm,
590 };
591
592 void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
593 unsigned int *divs, int nr_divs,
594 int divmask)
595 {
596 int ptr;
597
598 armdiv = divs;
599 nr_armdiv = nr_divs;
600 armdivmask = divmask;
601
602 /* s3c2443 parents h and p clocks from prediv */
603 clk_h.parent = &clk_prediv;
604 clk_p.parent = &clk_prediv;
605
606 clk_usb_bus.parent = &clk_usb_bus_host.clk;
607 clk_epll.parent = &clk_epllref.clk;
608
609 s3c24xx_register_baseclocks(xtal);
610 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
611
612 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
613 s3c_register_clksrc(clksrcs[ptr], 1);
614
615 s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks));
616 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
617
618 /* See s3c2443/etc notes on disabling clocks at init time */
619 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
620 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
621
622 s3c2443_common_setup_clocks(get_mpll);
623 }