arch/arm/mach-omap2/omap-smp.c

   1 /*
   2  * OMAP4 SMP source file. It contains platform specific fucntions
   3  * needed for the linux smp kernel.
   4  *
   5  * Copyright (C) 2009 Texas Instruments, Inc.
   6  *
   7  * Author:
   8  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
   9  *
  10  * Platform file needed for the OMAP4 SMP. This file is based on arm
  11  * realview smp platform.
  12  * * Copyright (c) 2002 ARM Limited.
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18 #include <linux/init.h>
  19 #include <linux/device.h>
  20 #include <linux/smp.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/cacheflush.h>
  24 #include <asm/hardware/gic.h>
  25 #include <asm/smp_scu.h>
  26 #include <mach/hardware.h>
  27 #include <mach/omap4-common.h>
  28
  29 /* SCU base address */
  30 static void __iomem *scu_base;
  31
  32 static DEFINE_SPINLOCK(boot_lock);
  33
  34 void __cpuinit platform_secondary_init(unsigned int cpu)
  35 {
  36         /*
  37          * If any interrupts are already enabled for the primary
  38          * core (e.g. timer irq), then they will not have been enabled
  39          * for us: do so
  40          */
  41         gic_secondary_init(0);
  42
  43         /*
  44          * Synchronise with the boot thread.
  45          */
  46         spin_lock(&boot_lock);
  47         spin_unlock(&boot_lock);
  48 }
  49
  50 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
  51 {
  52         /*
  53          * Set synchronisation state between this boot processor
  54          * and the secondary one
  55          */
  56         spin_lock(&boot_lock);
  57
  58         /*
  59          * Update the AuxCoreBoot0 with boot state for secondary core.
  60          * omap_secondary_startup() routine will hold the secondary core till
  61          * the AuxCoreBoot1 register is updated with cpu state
  62          * A barrier is added to ensure that write buffer is drained
  63          */
  64         omap_modify_auxcoreboot0(0x200, 0xfffffdff);
  65         flush_cache_all();
  66         smp_wmb();
  67         gic_raise_softirq(cpumask_of(cpu), 1);
  68
  69         /*
  70          * Now the secondary core is starting up let it run its
  71          * calibrations, then wait for it to finish
  72          */
  73         spin_unlock(&boot_lock);
  74
  75         return 0;
  76 }
  77
  78 static void __init wakeup_secondary(void)
  79 {
  80         /*
  81          * Write the address of secondary startup routine into the
  82          * AuxCoreBoot1 where ROM code will jump and start executing
  83          * on secondary core once out of WFE
  84          * A barrier is added to ensure that write buffer is drained
  85          */
  86         omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
  87         smp_wmb();
  88
  89         /*
  90          * Send a 'sev' to wake the secondary core from WFE.
  91          * Drain the outstanding writes to memory
  92          */
  93         dsb_sev();
  94         mb();
  95 }
  96
  97 /*
  98  * Initialise the CPU possible map early - this describes the CPUs
  99  * which may be present or become present in the system.
 100  */
 101 void __init smp_init_cpus(void)
 102 {
 103         unsigned int i, ncores;
 104
 105         /* Never released */
 106         scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
 107         BUG_ON(!scu_base);
 108
 109         ncores = scu_get_core_count(scu_base);
 110
 111         /* sanity check */
 112         if (ncores > NR_CPUS) {
 113                 printk(KERN_WARNING
 114                        "OMAP4: no. of cores (%d) greater than configured "
 115                        "maximum of %d - clipping\n",
 116                        ncores, NR_CPUS);
 117                 ncores = NR_CPUS;
 118         }
 119
 120         for (i = 0; i < ncores; i++)
 121                 set_cpu_possible(i, true);
 122
 123         set_smp_cross_call(gic_raise_softirq);
 124 }
 125
 126 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 127 {
 128
 129         /*
 130          * Initialise the SCU and wake up the secondary core using
 131          * wakeup_secondary().
 132          */
 133         scu_enable(scu_base);
 134         wakeup_secondary();
 135 }