Staging: hv: mousevsc: Cleanup alloc_input_device()
[zen-stable.git] / arch / arm / mach-prima2 / rstc.c
blobd074786e83d469e3ed4aac8f6a182a12a3434776
1 /*
2 * reset controller for CSR SiRFprimaII
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6 * Licensed under GPLv2 or later.
7 */
9 #include <linux/kernel.h>
10 #include <linux/mutex.h>
11 #include <linux/io.h>
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
17 void __iomem *sirfsoc_rstc_base;
18 static DEFINE_MUTEX(rstc_lock);
20 static struct of_device_id rstc_ids[] = {
21 { .compatible = "sirf,prima2-rstc" },
24 static int __init sirfsoc_of_rstc_init(void)
26 struct device_node *np;
28 np = of_find_matching_node(NULL, rstc_ids);
29 if (!np)
30 panic("unable to find compatible rstc node in dtb\n");
32 sirfsoc_rstc_base = of_iomap(np, 0);
33 if (!sirfsoc_rstc_base)
34 panic("unable to map rstc cpu registers\n");
36 of_node_put(np);
38 return 0;
40 early_initcall(sirfsoc_of_rstc_init);
42 int sirfsoc_reset_device(struct device *dev)
44 const unsigned int *prop = of_get_property(dev->of_node, "reset-bit", NULL);
45 unsigned int reset_bit;
47 if (!prop)
48 return -ENODEV;
50 reset_bit = be32_to_cpup(prop);
52 mutex_lock(&rstc_lock);
55 * Writing 1 to this bit resets corresponding block. Writing 0 to this
56 * bit de-asserts reset signal of the corresponding block.
57 * datasheet doesn't require explicit delay between the set and clear
58 * of reset bit. it could be shorter if tests pass.
60 writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | reset_bit,
61 sirfsoc_rstc_base + (reset_bit / 32) * 4);
62 msleep(10);
63 writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~reset_bit,
64 sirfsoc_rstc_base + (reset_bit / 32) * 4);
66 mutex_unlock(&rstc_lock);
68 return 0;