arch/arm/mach-u300/include/mach/u300-regs.h

   1 /*
   2  *
   3  * arch/arm/mach-u300/include/mach/u300-regs.h
   4  *
   5  *
   6  * Copyright (C) 2006-2009 ST-Ericsson AB
   7  * License terms: GNU General Public License (GPL) version 2
   8  * Basic register address definitions in physical memory and
   9  * some block definitions for core devices like the timer.
  10  * Author: Linus Walleij <linus.walleij@stericsson.com>
  11  */
  12
  13 #ifndef __MACH_U300_REGS_H
  14 #define __MACH_U300_REGS_H
  15
  16 /*
  17  * These are the large blocks of memory allocated for I/O.
  18  * the defines are used for setting up the I/O memory mapping.
  19  */
  20
  21 #ifdef __ASSEMBLER__
  22 #define IOMEM(a) (a)
  23 #else
  24 #define IOMEM(a) (void __iomem *) a
  25 #endif
  26
  27 /* NAND Flash CS0 */
  28 #define U300_NAND_CS0_PHYS_BASE         0x80000000
  29
  30 /* NFIF */
  31 #define U300_NAND_IF_PHYS_BASE          0x9f800000
  32
  33 /* AHB Peripherals */
  34 #define U300_AHB_PER_PHYS_BASE          0xa0000000
  35 #define U300_AHB_PER_VIRT_BASE          0xff010000
  36
  37 /* FAST Peripherals */
  38 #define U300_FAST_PER_PHYS_BASE         0xc0000000
  39 #define U300_FAST_PER_VIRT_BASE         0xff020000
  40
  41 /* SLOW Peripherals */
  42 #define U300_SLOW_PER_PHYS_BASE         0xc0010000
  43 #define U300_SLOW_PER_VIRT_BASE         0xff000000
  44
  45 /* Boot ROM */
  46 #define U300_BOOTROM_PHYS_BASE          0xffff0000
  47 #define U300_BOOTROM_VIRT_BASE          0xffff0000
  48
  49 /* SEMI config base */
  50 #ifdef CONFIG_MACH_U300_BS335
  51 #define U300_SEMI_CONFIG_BASE           0x2FFE0000
  52 #else
  53 #define U300_SEMI_CONFIG_BASE           0x30000000
  54 #endif
  55
  56 /*
  57  * AHB peripherals
  58  */
  59
  60 /* AHB Peripherals Bridge Controller */
  61 #define U300_AHB_BRIDGE_BASE            (U300_AHB_PER_PHYS_BASE+0x0000)
  62
  63 /* Vectored Interrupt Controller 0, servicing 32 interrupts */
  64 #define U300_INTCON0_BASE               (U300_AHB_PER_PHYS_BASE+0x1000)
  65 #define U300_INTCON0_VBASE              IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
  66
  67 /* Vectored Interrupt Controller 1, servicing 32 interrupts */
  68 #define U300_INTCON1_BASE               (U300_AHB_PER_PHYS_BASE+0x2000)
  69 #define U300_INTCON1_VBASE              IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
  70
  71 /* Memory Stick Pro (MSPRO) controller */
  72 #define U300_MSPRO_BASE                 (U300_AHB_PER_PHYS_BASE+0x3000)
  73
  74 /* EMIF Configuration Area */
  75 #define U300_EMIF_CFG_BASE              (U300_AHB_PER_PHYS_BASE+0x4000)
  76
  77
  78 /*
  79  * FAST peripherals
  80  */
  81
  82 /* FAST bridge control */
  83 #define U300_FAST_BRIDGE_BASE           (U300_FAST_PER_PHYS_BASE+0x0000)
  84
  85 /* MMC/SD controller */
  86 #define U300_MMCSD_BASE                 (U300_FAST_PER_PHYS_BASE+0x1000)
  87
  88 /* PCM I2S0 controller */
  89 #define U300_PCM_I2S0_BASE              (U300_FAST_PER_PHYS_BASE+0x2000)
  90
  91 /* PCM I2S1 controller */
  92 #define U300_PCM_I2S1_BASE              (U300_FAST_PER_PHYS_BASE+0x3000)
  93
  94 /* I2C0 controller */
  95 #define U300_I2C0_BASE                  (U300_FAST_PER_PHYS_BASE+0x4000)
  96
  97 /* I2C1 controller */
  98 #define U300_I2C1_BASE                  (U300_FAST_PER_PHYS_BASE+0x5000)
  99
 100 /* SPI controller */
 101 #define U300_SPI_BASE                   (U300_FAST_PER_PHYS_BASE+0x6000)
 102
 103 #ifdef CONFIG_MACH_U300_BS335
 104 /* Fast UART1 on U335 only */
 105 #define U300_UART1_BASE                 (U300_SLOW_PER_PHYS_BASE+0x7000)
 106 #endif
 107
 108 /*
 109  * SLOW peripherals
 110  */
 111
 112 /* SLOW bridge control */
 113 #define U300_SLOW_BRIDGE_BASE           (U300_SLOW_PER_PHYS_BASE)
 114
 115 /* SYSCON */
 116 #define U300_SYSCON_BASE                (U300_SLOW_PER_PHYS_BASE+0x1000)
 117 #define U300_SYSCON_VBASE               IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
 118
 119 /* Watchdog */
 120 #define U300_WDOG_BASE                  (U300_SLOW_PER_PHYS_BASE+0x2000)
 121
 122 /* UART0 */
 123 #define U300_UART0_BASE                 (U300_SLOW_PER_PHYS_BASE+0x3000)
 124
 125 /* APP side special timer */
 126 #define U300_TIMER_APP_BASE             (U300_SLOW_PER_PHYS_BASE+0x4000)
 127 #define U300_TIMER_APP_VBASE            IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
 128
 129 /* Keypad */
 130 #define U300_KEYPAD_BASE                (U300_SLOW_PER_PHYS_BASE+0x5000)
 131
 132 /* GPIO */
 133 #define U300_GPIO_BASE                  (U300_SLOW_PER_PHYS_BASE+0x6000)
 134
 135 /* RTC */
 136 #define U300_RTC_BASE                   (U300_SLOW_PER_PHYS_BASE+0x7000)
 137
 138 /* Bus tracer */
 139 #define U300_BUSTR_BASE                 (U300_SLOW_PER_PHYS_BASE+0x8000)
 140
 141 /* Event handler (hardware queue) */
 142 #define U300_EVHIST_BASE                (U300_SLOW_PER_PHYS_BASE+0x9000)
 143
 144 /* Genric Timer */
 145 #define U300_TIMER_BASE                 (U300_SLOW_PER_PHYS_BASE+0xa000)
 146
 147 /* PPM */
 148 #define U300_PPM_BASE                   (U300_SLOW_PER_PHYS_BASE+0xb000)
 149
 150
 151 /*
 152  * REST peripherals
 153  */
 154
 155 /* ISP (image signal processor) is only available in U335 */
 156 #ifdef CONFIG_MACH_U300_BS335
 157 #define U300_ISP_BASE                   (0xA0008000)
 158 #endif
 159
 160 /* DMA Controller base */
 161 #define U300_DMAC_BASE                  (0xC0020000)
 162
 163 /* MSL Base */
 164 #define U300_MSL_BASE                   (0xc0022000)
 165
 166 /* APEX Base */
 167 #define U300_APEX_BASE                  (0xc0030000)
 168
 169 /* Video Encoder Base */
 170 #ifdef CONFIG_MACH_U300_BS335
 171 #define U300_VIDEOENC_BASE              (0xc0080000)
 172 #else
 173 #define U300_VIDEOENC_BASE              (0xc0040000)
 174 #endif
 175
 176 /* XGAM Base */
 177 #define U300_XGAM_BASE                  (0xd0000000)
 178
 179 /*
 180  * Virtual accessor macros for static devices
 181  */
 182
 183 #endif