arch/arm/plat-s3c24xx/cpu.c

   1 /* linux/arch/arm/plat-s3c24xx/cpu.c
   2  *
   3  * Copyright (c) 2004-2005 Simtec Electronics
   4  *      http://www.simtec.co.uk/products/SWLINUX/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * S3C24XX CPU Support
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22 */
  23
  24
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/ioport.h>
  29 #include <linux/serial_core.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/delay.h>
  32
  33 #include <mach/hardware.h>
  34 #include <asm/irq.h>
  35 #include <asm/io.h>
  36 #include <asm/delay.h>
  37 #include <asm/cacheflush.h>
  38
  39 #include <asm/mach/arch.h>
  40 #include <asm/mach/map.h>
  41
  42 #include <mach/system-reset.h>
  43
  44 #include <mach/regs-gpio.h>
  45 #include <asm/plat-s3c/regs-serial.h>
  46
  47 #include <asm/plat-s3c24xx/cpu.h>
  48 #include <asm/plat-s3c24xx/devs.h>
  49 #include <asm/plat-s3c24xx/clock.h>
  50 #include <asm/plat-s3c24xx/s3c2400.h>
  51 #include <asm/plat-s3c24xx/s3c2410.h>
  52 #include <asm/plat-s3c24xx/s3c2412.h>
  53 #include "s3c244x.h"
  54 #include <asm/plat-s3c24xx/s3c2440.h>
  55 #include <asm/plat-s3c24xx/s3c2442.h>
  56 #include <asm/plat-s3c24xx/s3c2443.h>
  57
  58 struct cpu_table {
  59         unsigned long   idcode;
  60         unsigned long   idmask;
  61         void            (*map_io)(struct map_desc *mach_desc, int size);
  62         void            (*init_uarts)(struct s3c2410_uartcfg *cfg, int no);
  63         void            (*init_clocks)(int xtal);
  64         int             (*init)(void);
  65         const char      *name;
  66 };
  67
  68 /* table of supported CPUs */
  69
  70 static const char name_s3c2400[]  = "S3C2400";
  71 static const char name_s3c2410[]  = "S3C2410";
  72 static const char name_s3c2412[]  = "S3C2412";
  73 static const char name_s3c2440[]  = "S3C2440";
  74 static const char name_s3c2442[]  = "S3C2442";
  75 static const char name_s3c2443[]  = "S3C2443";
  76 static const char name_s3c2410a[] = "S3C2410A";
  77 static const char name_s3c2440a[] = "S3C2440A";
  78
  79 static struct cpu_table cpu_ids[] __initdata = {
  80         {
  81                 .idcode         = 0x32410000,
  82                 .idmask         = 0xffffffff,
  83                 .map_io         = s3c2410_map_io,
  84                 .init_clocks    = s3c2410_init_clocks,
  85                 .init_uarts     = s3c2410_init_uarts,
  86                 .init           = s3c2410_init,
  87                 .name           = name_s3c2410
  88         },
  89         {
  90                 .idcode         = 0x32410002,
  91                 .idmask         = 0xffffffff,
  92                 .map_io         = s3c2410_map_io,
  93                 .init_clocks    = s3c2410_init_clocks,
  94                 .init_uarts     = s3c2410_init_uarts,
  95                 .init           = s3c2410_init,
  96                 .name           = name_s3c2410a
  97         },
  98         {
  99                 .idcode         = 0x32440000,
 100                 .idmask         = 0xffffffff,
 101                 .map_io         = s3c244x_map_io,
 102                 .init_clocks    = s3c244x_init_clocks,
 103                 .init_uarts     = s3c244x_init_uarts,
 104                 .init           = s3c2440_init,
 105                 .name           = name_s3c2440
 106         },
 107         {
 108                 .idcode         = 0x32440001,
 109                 .idmask         = 0xffffffff,
 110                 .map_io         = s3c244x_map_io,
 111                 .init_clocks    = s3c244x_init_clocks,
 112                 .init_uarts     = s3c244x_init_uarts,
 113                 .init           = s3c2440_init,
 114                 .name           = name_s3c2440a
 115         },
 116         {
 117                 .idcode         = 0x32440aaa,
 118                 .idmask         = 0xffffffff,
 119                 .map_io         = s3c244x_map_io,
 120                 .init_clocks    = s3c244x_init_clocks,
 121                 .init_uarts     = s3c244x_init_uarts,
 122                 .init           = s3c2442_init,
 123                 .name           = name_s3c2442
 124         },
 125         {
 126                 .idcode         = 0x32412001,
 127                 .idmask         = 0xffffffff,
 128                 .map_io         = s3c2412_map_io,
 129                 .init_clocks    = s3c2412_init_clocks,
 130                 .init_uarts     = s3c2412_init_uarts,
 131                 .init           = s3c2412_init,
 132                 .name           = name_s3c2412,
 133         },
 134         {                       /* a newer version of the s3c2412 */
 135                 .idcode         = 0x32412003,
 136                 .idmask         = 0xffffffff,
 137                 .map_io         = s3c2412_map_io,
 138                 .init_clocks    = s3c2412_init_clocks,
 139                 .init_uarts     = s3c2412_init_uarts,
 140                 .init           = s3c2412_init,
 141                 .name           = name_s3c2412,
 142         },
 143         {
 144                 .idcode         = 0x32443001,
 145                 .idmask         = 0xffffffff,
 146                 .map_io         = s3c2443_map_io,
 147                 .init_clocks    = s3c2443_init_clocks,
 148                 .init_uarts     = s3c2443_init_uarts,
 149                 .init           = s3c2443_init,
 150                 .name           = name_s3c2443,
 151         },
 152         {
 153                 .idcode         = 0x0,   /* S3C2400 doesn't have an idcode */
 154                 .idmask         = 0xffffffff,
 155                 .map_io         = s3c2400_map_io,
 156                 .init_clocks    = s3c2400_init_clocks,
 157                 .init_uarts     = s3c2400_init_uarts,
 158                 .init           = s3c2400_init,
 159                 .name           = name_s3c2400
 160         },
 161 };
 162
 163 /* minimal IO mapping */
 164
 165 static struct map_desc s3c_iodesc[] __initdata = {
 166         IODESC_ENT(GPIO),
 167         IODESC_ENT(IRQ),
 168         IODESC_ENT(MEMCTRL),
 169         IODESC_ENT(UART)
 170 };
 171
 172 static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode)
 173 {
 174         struct cpu_table *tab;
 175         int count;
 176
 177         tab = cpu_ids;
 178         for (count = 0; count < ARRAY_SIZE(cpu_ids); count++, tab++) {
 179                 if ((idcode & tab->idmask) == tab->idcode)
 180                         return tab;
 181         }
 182
 183         return NULL;
 184 }
 185
 186 /* cpu information */
 187
 188 static struct cpu_table *cpu;
 189
 190 static unsigned long s3c24xx_read_idcode_v5(void)
 191 {
 192 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
 193         return __raw_readl(S3C2412_GSTATUS1);
 194 #else
 195         return 1UL;     /* don't look like an 2400 */
 196 #endif
 197 }
 198
 199 static unsigned long s3c24xx_read_idcode_v4(void)
 200 {
 201 #ifndef CONFIG_CPU_S3C2400
 202         return __raw_readl(S3C2410_GSTATUS1);
 203 #else
 204         return 0UL;
 205 #endif
 206 }
 207
 208 /* Hook for arm_pm_restart to ensure we execute the reset code
 209  * with the caches enabled. It seems at least the S3C2440 has a problem
 210  * resetting if there is bus activity interrupted by the reset.
 211  */
 212 static void s3c24xx_pm_restart(char mode)
 213 {
 214         if (mode != 's') {
 215                 unsigned long flags;
 216
 217                 local_irq_save(flags);
 218                 __cpuc_flush_kern_all();
 219                 __cpuc_flush_user_all();
 220
 221                 arch_reset(mode);
 222                 local_irq_restore(flags);
 223         }
 224
 225         /* fallback, or unhandled */
 226         arm_machine_restart(mode);
 227 }
 228
 229 void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
 230 {
 231         unsigned long idcode = 0x0;
 232
 233         /* initialise the io descriptors we need for initialisation */
 234         iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
 235
 236         if (cpu_architecture() >= CPU_ARCH_ARMv5) {
 237                 idcode = s3c24xx_read_idcode_v5();
 238         } else {
 239                 idcode = s3c24xx_read_idcode_v4();
 240         }
 241
 242         cpu = s3c_lookup_cpu(idcode);
 243
 244         if (cpu == NULL) {
 245                 printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode);
 246                 panic("Unknown S3C24XX CPU");
 247         }
 248
 249         printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
 250
 251         if (cpu->map_io == NULL || cpu->init == NULL) {
 252                 printk(KERN_ERR "CPU %s support not enabled\n", cpu->name);
 253                 panic("Unsupported S3C24XX CPU");
 254         }
 255
 256         arm_pm_restart = s3c24xx_pm_restart;
 257
 258         (cpu->map_io)(mach_desc, size);
 259 }
 260
 261 /* s3c24xx_init_clocks
 262  *
 263  * Initialise the clock subsystem and associated information from the
 264  * given master crystal value.
 265  *
 266  * xtal  = 0 -> use default PLL crystal value (normally 12MHz)
 267  *      != 0 -> PLL crystal value in Hz
 268 */
 269
 270 void __init s3c24xx_init_clocks(int xtal)
 271 {
 272         if (xtal == 0)
 273                 xtal = 12*1000*1000;
 274
 275         if (cpu == NULL)
 276                 panic("s3c24xx_init_clocks: no cpu setup?\n");
 277
 278         if (cpu->init_clocks == NULL)
 279                 panic("s3c24xx_init_clocks: cpu has no clock init\n");
 280         else
 281                 (cpu->init_clocks)(xtal);
 282 }
 283
 284 /* uart management */
 285
 286 static int nr_uarts __initdata = 0;
 287
 288 static struct s3c2410_uartcfg uart_cfgs[3];
 289
 290 /* s3c24xx_init_uartdevs
 291  *
 292  * copy the specified platform data and configuration into our central
 293  * set of devices, before the data is thrown away after the init process.
 294  *
 295  * This also fills in the array passed to the serial driver for the
 296  * early initialisation of the console.
 297 */
 298
 299 void __init s3c24xx_init_uartdevs(char *name,
 300                                   struct s3c24xx_uart_resources *res,
 301                                   struct s3c2410_uartcfg *cfg, int no)
 302 {
 303         struct platform_device *platdev;
 304         struct s3c2410_uartcfg *cfgptr = uart_cfgs;
 305         struct s3c24xx_uart_resources *resp;
 306         int uart;
 307
 308         memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no);
 309
 310         for (uart = 0; uart < no; uart++, cfg++, cfgptr++) {
 311                 platdev = s3c24xx_uart_src[cfgptr->hwport];
 312
 313                 resp = res + cfgptr->hwport;
 314
 315                 s3c24xx_uart_devs[uart] = platdev;
 316
 317                 platdev->name = name;
 318                 platdev->resource = resp->resources;
 319                 platdev->num_resources = resp->nr_resources;
 320
 321                 platdev->dev.platform_data = cfgptr;
 322         }
 323
 324         nr_uarts = no;
 325 }
 326
 327 void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 328 {
 329         if (cpu == NULL)
 330                 return;
 331
 332         if (cpu->init_uarts == NULL) {
 333                 printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
 334         } else
 335                 (cpu->init_uarts)(cfg, no);
 336 }
 337
 338 static int __init s3c_arch_init(void)
 339 {
 340         int ret;
 341
 342         // do the correct init for cpu
 343
 344         if (cpu == NULL)
 345                 panic("s3c_arch_init: NULL cpu\n");
 346
 347         ret = (cpu->init)();
 348         if (ret != 0)
 349                 return ret;
 350
 351         ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
 352         return ret;
 353 }
 354
 355 arch_initcall(s3c_arch_init);