arch/blackfin/include/asm/bfin_sport.h

   1 /*
   2  * File:         include/asm-blackfin/bfin_sport.h
   3  * Based on:
   4  * Author:       Roy Huang (roy.huang@analog.com)
   5  *
   6  * Created:      Thu Aug. 24 2006
   7  * Description:
   8  *
   9  * Modified:
  10  *               Copyright 2004-2006 Analog Devices Inc.
  11  *
  12  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, see the file COPYING, or write
  26  * to the Free Software Foundation, Inc.,
  27  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  28  */
  29
  30 #ifndef __BFIN_SPORT_H__
  31 #define __BFIN_SPORT_H__
  32
  33 #define SPORT_MAJOR     237
  34 #define SPORT_NR_DEVS   2
  35
  36 /* Sport mode: it can be set to TDM, i2s or others */
  37 #define NORM_MODE       0x0
  38 #define TDM_MODE        0x1
  39 #define I2S_MODE        0x2
  40
  41 /* Data format, normal, a-law or u-law */
  42 #define NORM_FORMAT     0x0
  43 #define ALAW_FORMAT     0x2
  44 #define ULAW_FORMAT     0x3
  45 struct sport_register;
  46
  47 /* Function driver which use sport must initialize the structure */
  48 struct sport_config {
  49         /*TDM (multichannels), I2S or other mode */
  50         unsigned int mode:3;
  51
  52         /* if TDM mode is selected, channels must be set */
  53         int channels;           /* Must be in 8 units */
  54         unsigned int frame_delay:4;     /* Delay between frame sync pulse and first bit */
  55
  56         /* I2S mode */
  57         unsigned int right_first:1;     /* Right stereo channel first */
  58
  59         /* In mormal mode, the following item need to be set */
  60         unsigned int lsb_first:1;       /* order of transmit or receive data */
  61         unsigned int fsync:1;   /* Frame sync required */
  62         unsigned int data_indep:1;      /* data independent frame sync generated */
  63         unsigned int act_low:1; /* Active low TFS */
  64         unsigned int late_fsync:1;      /* Late frame sync */
  65         unsigned int tckfe:1;
  66         unsigned int sec_en:1;  /* Secondary side enabled */
  67
  68         /* Choose clock source */
  69         unsigned int int_clk:1; /* Internal or external clock */
  70
  71         /* If external clock is used, the following fields are ignored */
  72         int serial_clk;
  73         int fsync_clk;
  74
  75         unsigned int data_format:2;     /*Normal, u-law or a-law */
  76
  77         int word_len;           /* How length of the word in bits, 3-32 bits */
  78         int dma_enabled;
  79 };
  80
  81 struct sport_register {
  82         unsigned short tcr1;
  83         unsigned short reserved0;
  84         unsigned short tcr2;
  85         unsigned short reserved1;
  86         unsigned short tclkdiv;
  87         unsigned short reserved2;
  88         unsigned short tfsdiv;
  89         unsigned short reserved3;
  90         unsigned long tx;
  91         unsigned long reserved_l0;
  92         unsigned long rx;
  93         unsigned long reserved_l1;
  94         unsigned short rcr1;
  95         unsigned short reserved4;
  96         unsigned short rcr2;
  97         unsigned short reserved5;
  98         unsigned short rclkdiv;
  99         unsigned short reserved6;
 100         unsigned short rfsdiv;
 101         unsigned short reserved7;
 102         unsigned short stat;
 103         unsigned short reserved8;
 104         unsigned short chnl;
 105         unsigned short reserved9;
 106         unsigned short mcmc1;
 107         unsigned short reserved10;
 108         unsigned short mcmc2;
 109         unsigned short reserved11;
 110         unsigned long mtcs0;
 111         unsigned long mtcs1;
 112         unsigned long mtcs2;
 113         unsigned long mtcs3;
 114         unsigned long mrcs0;
 115         unsigned long mrcs1;
 116         unsigned long mrcs2;
 117         unsigned long mrcs3;
 118 };
 119
 120 #define SPORT_IOC_MAGIC         'P'
 121 #define SPORT_IOC_CONFIG        _IOWR('P', 0x01, struct sport_config)
 122
 123 /* Test purpose */
 124 #define ENABLE_AD73311          _IOWR('P', 0x02, int)
 125
 126 struct sport_dev {
 127         struct cdev cdev;       /* Char device structure */
 128
 129         int sport_num;
 130
 131         int dma_rx_chan;
 132         int dma_tx_chan;
 133
 134         int rx_irq;
 135         unsigned char *rx_buf;  /* Buffer store the received data */
 136         int rx_len;             /* How many bytes will be received */
 137         int rx_received;        /* How many bytes has been received */
 138
 139         int tx_irq;
 140         const unsigned char *tx_buf;
 141         int tx_len;
 142         int tx_sent;
 143
 144         int sport_err_irq;
 145
 146         struct mutex mutex;     /* mutual exclusion semaphore */
 147         struct task_struct *task;
 148
 149         wait_queue_head_t waitq;
 150         int     wait_con;
 151         struct sport_register *regs;
 152         struct sport_config config;
 153 };
 154
 155 #define SPORT_TCR1      0
 156 #define SPORT_TCR2      1
 157 #define SPORT_TCLKDIV   2
 158 #define SPORT_TFSDIV    3
 159 #define SPORT_RCR1      8
 160 #define SPORT_RCR2      9
 161 #define SPORT_RCLKDIV   10
 162 #define SPORT_RFSDIV    11
 163 #define SPORT_CHANNEL   13
 164 #define SPORT_MCMC1     14
 165 #define SPORT_MCMC2     15
 166 #define SPORT_MTCS0     16
 167 #define SPORT_MTCS1     17
 168 #define SPORT_MTCS2     18
 169 #define SPORT_MTCS3     19
 170 #define SPORT_MRCS0     20
 171 #define SPORT_MRCS1     21
 172 #define SPORT_MRCS2     22
 173 #define SPORT_MRCS3     23
 174
 175 #endif                          /*__BFIN_SPORT_H__*/