arch/arm/mach-kirkwood/common.c

   1 /*
   2  * arch/arm/mach-kirkwood/common.c
   3  *
   4  * Core functions for Marvell Kirkwood SoCs
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/serial_8250.h>
  15 #include <linux/ata_platform.h>
  16 #include <linux/mtd/nand.h>
  17 #include <linux/dma-mapping.h>
  18 #include <net/dsa.h>
  19 #include <asm/page.h>
  20 #include <asm/timex.h>
  21 #include <asm/kexec.h>
  22 #include <asm/mach/map.h>
  23 #include <asm/mach/time.h>
  24 #include <mach/kirkwood.h>
  25 #include <mach/bridge-regs.h>
  26 #include <plat/audio.h>
  27 #include <plat/cache-feroceon-l2.h>
  28 #include <plat/mvsdio.h>
  29 #include <plat/orion_nand.h>
  30 #include <plat/common.h>
  31 #include <plat/time.h>
  32 #include <plat/addr-map.h>
  33 #include "common.h"
  34
  35 /*****************************************************************************
  36  * I/O Address Mapping
  37  ****************************************************************************/
  38 static struct map_desc kirkwood_io_desc[] __initdata = {
  39         {
  40                 .virtual        = KIRKWOOD_PCIE_IO_VIRT_BASE,
  41                 .pfn            = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
  42                 .length         = KIRKWOOD_PCIE_IO_SIZE,
  43                 .type           = MT_DEVICE,
  44         }, {
  45                 .virtual        = KIRKWOOD_PCIE1_IO_VIRT_BASE,
  46                 .pfn            = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
  47                 .length         = KIRKWOOD_PCIE1_IO_SIZE,
  48                 .type           = MT_DEVICE,
  49         }, {
  50                 .virtual        = KIRKWOOD_REGS_VIRT_BASE,
  51                 .pfn            = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
  52                 .length         = KIRKWOOD_REGS_SIZE,
  53                 .type           = MT_DEVICE,
  54         },
  55 };
  56
  57 void __init kirkwood_map_io(void)
  58 {
  59         iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
  60 }
  61
  62 /*
  63  * Default clock control bits.  Any bit _not_ set in this variable
  64  * will be cleared from the hardware after platform devices have been
  65  * registered.  Some reserved bits must be set to 1.
  66  */
  67 unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
  68
  69
  70 /*****************************************************************************
  71  * EHCI0
  72  ****************************************************************************/
  73 void __init kirkwood_ehci_init(void)
  74 {
  75         kirkwood_clk_ctrl |= CGC_USB0;
  76         orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB);
  77 }
  78
  79
  80 /*****************************************************************************
  81  * GE00
  82  ****************************************************************************/
  83 void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
  84 {
  85         kirkwood_clk_ctrl |= CGC_GE0;
  86
  87         orion_ge00_init(eth_data,
  88                         GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
  89                         IRQ_KIRKWOOD_GE00_ERR, kirkwood_tclk);
  90 }
  91
  92
  93 /*****************************************************************************
  94  * GE01
  95  ****************************************************************************/
  96 void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
  97 {
  98
  99         kirkwood_clk_ctrl |= CGC_GE1;
 100
 101         orion_ge01_init(eth_data,
 102                         GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
 103                         IRQ_KIRKWOOD_GE01_ERR, kirkwood_tclk);
 104 }
 105
 106
 107 /*****************************************************************************
 108  * Ethernet switch
 109  ****************************************************************************/
 110 void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq)
 111 {
 112         orion_ge00_switch_init(d, irq);
 113 }
 114
 115
 116 /*****************************************************************************
 117  * NAND flash
 118  ****************************************************************************/
 119 static struct resource kirkwood_nand_resource = {
 120         .flags          = IORESOURCE_MEM,
 121         .start          = KIRKWOOD_NAND_MEM_PHYS_BASE,
 122         .end            = KIRKWOOD_NAND_MEM_PHYS_BASE +
 123                                 KIRKWOOD_NAND_MEM_SIZE - 1,
 124 };
 125
 126 static struct orion_nand_data kirkwood_nand_data = {
 127         .cle            = 0,
 128         .ale            = 1,
 129         .width          = 8,
 130 };
 131
 132 static struct platform_device kirkwood_nand_flash = {
 133         .name           = "orion_nand",
 134         .id             = -1,
 135         .dev            = {
 136                 .platform_data  = &kirkwood_nand_data,
 137         },
 138         .resource       = &kirkwood_nand_resource,
 139         .num_resources  = 1,
 140 };
 141
 142 void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts,
 143                                int chip_delay)
 144 {
 145         kirkwood_clk_ctrl |= CGC_RUNIT;
 146         kirkwood_nand_data.parts = parts;
 147         kirkwood_nand_data.nr_parts = nr_parts;
 148         kirkwood_nand_data.chip_delay = chip_delay;
 149         platform_device_register(&kirkwood_nand_flash);
 150 }
 151
 152 void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
 153                                    int (*dev_ready)(struct mtd_info *))
 154 {
 155         kirkwood_clk_ctrl |= CGC_RUNIT;
 156         kirkwood_nand_data.parts = parts;
 157         kirkwood_nand_data.nr_parts = nr_parts;
 158         kirkwood_nand_data.dev_ready = dev_ready;
 159         platform_device_register(&kirkwood_nand_flash);
 160 }
 161
 162 /*****************************************************************************
 163  * SoC RTC
 164  ****************************************************************************/
 165 static void __init kirkwood_rtc_init(void)
 166 {
 167         orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
 168 }
 169
 170
 171 /*****************************************************************************
 172  * SATA
 173  ****************************************************************************/
 174 void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
 175 {
 176         kirkwood_clk_ctrl |= CGC_SATA0;
 177         if (sata_data->n_ports > 1)
 178                 kirkwood_clk_ctrl |= CGC_SATA1;
 179
 180         orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
 181 }
 182
 183
 184 /*****************************************************************************
 185  * SD/SDIO/MMC
 186  ****************************************************************************/
 187 static struct resource mvsdio_resources[] = {
 188         [0] = {
 189                 .start  = SDIO_PHYS_BASE,
 190                 .end    = SDIO_PHYS_BASE + SZ_1K - 1,
 191                 .flags  = IORESOURCE_MEM,
 192         },
 193         [1] = {
 194                 .start  = IRQ_KIRKWOOD_SDIO,
 195                 .end    = IRQ_KIRKWOOD_SDIO,
 196                 .flags  = IORESOURCE_IRQ,
 197         },
 198 };
 199
 200 static u64 mvsdio_dmamask = DMA_BIT_MASK(32);
 201
 202 static struct platform_device kirkwood_sdio = {
 203         .name           = "mvsdio",
 204         .id             = -1,
 205         .dev            = {
 206                 .dma_mask = &mvsdio_dmamask,
 207                 .coherent_dma_mask = DMA_BIT_MASK(32),
 208         },
 209         .num_resources  = ARRAY_SIZE(mvsdio_resources),
 210         .resource       = mvsdio_resources,
 211 };
 212
 213 void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
 214 {
 215         u32 dev, rev;
 216
 217         kirkwood_pcie_id(&dev, &rev);
 218         if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */
 219                 mvsdio_data->clock = 100000000;
 220         else
 221                 mvsdio_data->clock = 200000000;
 222         kirkwood_clk_ctrl |= CGC_SDIO;
 223         kirkwood_sdio.dev.platform_data = mvsdio_data;
 224         platform_device_register(&kirkwood_sdio);
 225 }
 226
 227
 228 /*****************************************************************************
 229  * SPI
 230  ****************************************************************************/
 231 void __init kirkwood_spi_init()
 232 {
 233         kirkwood_clk_ctrl |= CGC_RUNIT;
 234         orion_spi_init(SPI_PHYS_BASE, kirkwood_tclk);
 235 }
 236
 237
 238 /*****************************************************************************
 239  * I2C
 240  ****************************************************************************/
 241 void __init kirkwood_i2c_init(void)
 242 {
 243         orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8);
 244 }
 245
 246
 247 /*****************************************************************************
 248  * UART0
 249  ****************************************************************************/
 250
 251 void __init kirkwood_uart0_init(void)
 252 {
 253         orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
 254                          IRQ_KIRKWOOD_UART_0, kirkwood_tclk);
 255 }
 256
 257
 258 /*****************************************************************************
 259  * UART1
 260  ****************************************************************************/
 261 void __init kirkwood_uart1_init(void)
 262 {
 263         orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
 264                          IRQ_KIRKWOOD_UART_1, kirkwood_tclk);
 265 }
 266
 267 /*****************************************************************************
 268  * Cryptographic Engines and Security Accelerator (CESA)
 269  ****************************************************************************/
 270 void __init kirkwood_crypto_init(void)
 271 {
 272         kirkwood_clk_ctrl |= CGC_CRYPTO;
 273         orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE,
 274                           KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO);
 275 }
 276
 277
 278 /*****************************************************************************
 279  * XOR0
 280  ****************************************************************************/
 281 static void __init kirkwood_xor0_init(void)
 282 {
 283         kirkwood_clk_ctrl |= CGC_XOR0;
 284
 285         orion_xor0_init(XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
 286                         IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
 287 }
 288
 289
 290 /*****************************************************************************
 291  * XOR1
 292  ****************************************************************************/
 293 static void __init kirkwood_xor1_init(void)
 294 {
 295         kirkwood_clk_ctrl |= CGC_XOR1;
 296
 297         orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE,
 298                         IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11);
 299 }
 300
 301
 302 /*****************************************************************************
 303  * Watchdog
 304  ****************************************************************************/
 305 static void __init kirkwood_wdt_init(void)
 306 {
 307         orion_wdt_init(kirkwood_tclk);
 308 }
 309
 310
 311 /*****************************************************************************
 312  * Time handling
 313  ****************************************************************************/
 314 void __init kirkwood_init_early(void)
 315 {
 316         orion_time_set_base(TIMER_VIRT_BASE);
 317 }
 318
 319 int kirkwood_tclk;
 320
 321 static int __init kirkwood_find_tclk(void)
 322 {
 323         u32 dev, rev;
 324
 325         kirkwood_pcie_id(&dev, &rev);
 326
 327         if (dev == MV88F6281_DEV_ID || dev == MV88F6282_DEV_ID)
 328                 if (((readl(SAMPLE_AT_RESET) >> 21) & 1) == 0)
 329                         return 200000000;
 330
 331         return 166666667;
 332 }
 333
 334 static void __init kirkwood_timer_init(void)
 335 {
 336         kirkwood_tclk = kirkwood_find_tclk();
 337
 338         orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
 339                         IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
 340 }
 341
 342 struct sys_timer kirkwood_timer = {
 343         .init = kirkwood_timer_init,
 344 };
 345
 346 /*****************************************************************************
 347  * Audio
 348  ****************************************************************************/
 349 static struct resource kirkwood_i2s_resources[] = {
 350         [0] = {
 351                 .start  = AUDIO_PHYS_BASE,
 352                 .end    = AUDIO_PHYS_BASE + SZ_16K - 1,
 353                 .flags  = IORESOURCE_MEM,
 354         },
 355         [1] = {
 356                 .start  = IRQ_KIRKWOOD_I2S,
 357                 .end    = IRQ_KIRKWOOD_I2S,
 358                 .flags  = IORESOURCE_IRQ,
 359         },
 360 };
 361
 362 static struct kirkwood_asoc_platform_data kirkwood_i2s_data = {
 363         .burst       = 128,
 364 };
 365
 366 static struct platform_device kirkwood_i2s_device = {
 367         .name           = "kirkwood-i2s",
 368         .id             = -1,
 369         .num_resources  = ARRAY_SIZE(kirkwood_i2s_resources),
 370         .resource       = kirkwood_i2s_resources,
 371         .dev            = {
 372                 .platform_data  = &kirkwood_i2s_data,
 373         },
 374 };
 375
 376 static struct platform_device kirkwood_pcm_device = {
 377         .name           = "kirkwood-pcm-audio",
 378         .id             = -1,
 379 };
 380
 381 void __init kirkwood_audio_init(void)
 382 {
 383         kirkwood_clk_ctrl |= CGC_AUDIO;
 384         platform_device_register(&kirkwood_i2s_device);
 385         platform_device_register(&kirkwood_pcm_device);
 386 }
 387
 388 /*****************************************************************************
 389  * General
 390  ****************************************************************************/
 391 /*
 392  * Identify device ID and revision.
 393  */
 394 static char * __init kirkwood_id(void)
 395 {
 396         u32 dev, rev;
 397
 398         kirkwood_pcie_id(&dev, &rev);
 399
 400         if (dev == MV88F6281_DEV_ID) {
 401                 if (rev == MV88F6281_REV_Z0)
 402                         return "MV88F6281-Z0";
 403                 else if (rev == MV88F6281_REV_A0)
 404                         return "MV88F6281-A0";
 405                 else if (rev == MV88F6281_REV_A1)
 406                         return "MV88F6281-A1";
 407                 else
 408                         return "MV88F6281-Rev-Unsupported";
 409         } else if (dev == MV88F6192_DEV_ID) {
 410                 if (rev == MV88F6192_REV_Z0)
 411                         return "MV88F6192-Z0";
 412                 else if (rev == MV88F6192_REV_A0)
 413                         return "MV88F6192-A0";
 414                 else if (rev == MV88F6192_REV_A1)
 415                         return "MV88F6192-A1";
 416                 else
 417                         return "MV88F6192-Rev-Unsupported";
 418         } else if (dev == MV88F6180_DEV_ID) {
 419                 if (rev == MV88F6180_REV_A0)
 420                         return "MV88F6180-Rev-A0";
 421                 else if (rev == MV88F6180_REV_A1)
 422                         return "MV88F6180-Rev-A1";
 423                 else
 424                         return "MV88F6180-Rev-Unsupported";
 425         } else if (dev == MV88F6282_DEV_ID) {
 426                 if (rev == MV88F6282_REV_A0)
 427                         return "MV88F6282-Rev-A0";
 428                 else if (rev == MV88F6282_REV_A1)
 429                         return "MV88F6282-Rev-A1";
 430                 else
 431                         return "MV88F6282-Rev-Unsupported";
 432         } else {
 433                 return "Device-Unknown";
 434         }
 435 }
 436
 437 static void __init kirkwood_l2_init(void)
 438 {
 439 #ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
 440         writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
 441         feroceon_l2_init(1);
 442 #else
 443         writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG);
 444         feroceon_l2_init(0);
 445 #endif
 446 }
 447
 448 void __init kirkwood_init(void)
 449 {
 450         printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
 451                 kirkwood_id(), kirkwood_tclk);
 452         kirkwood_i2s_data.tclk = kirkwood_tclk;
 453
 454         /*
 455          * Disable propagation of mbus errors to the CPU local bus,
 456          * as this causes mbus errors (which can occur for example
 457          * for PCI aborts) to throw CPU aborts, which we're not set
 458          * up to deal with.
 459          */
 460         writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
 461
 462         kirkwood_setup_cpu_mbus();
 463
 464 #ifdef CONFIG_CACHE_FEROCEON_L2
 465         kirkwood_l2_init();
 466 #endif
 467
 468         /* internal devices that every board has */
 469         kirkwood_rtc_init();
 470         kirkwood_wdt_init();
 471         kirkwood_xor0_init();
 472         kirkwood_xor1_init();
 473         kirkwood_crypto_init();
 474
 475 #ifdef CONFIG_KEXEC
 476         kexec_reinit = kirkwood_enable_pcie;
 477 #endif
 478 }
 479
 480 static int __init kirkwood_clock_gate(void)
 481 {
 482         unsigned int curr = readl(CLOCK_GATING_CTRL);
 483         u32 dev, rev;
 484
 485         kirkwood_pcie_id(&dev, &rev);
 486         printk(KERN_DEBUG "Gating clock of unused units\n");
 487         printk(KERN_DEBUG "before: 0x%08x\n", curr);
 488
 489         /* Make sure those units are accessible */
 490         writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
 491
 492         /* For SATA: first shutdown the phy */
 493         if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
 494                 /* Disable PLL and IVREF */
 495                 writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
 496                 /* Disable PHY */
 497                 writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
 498         }
 499         if (!(kirkwood_clk_ctrl & CGC_SATA1)) {
 500                 /* Disable PLL and IVREF */
 501                 writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
 502                 /* Disable PHY */
 503                 writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
 504         }
 505
 506         /* For PCIe: first shutdown the phy */
 507         if (!(kirkwood_clk_ctrl & CGC_PEX0)) {
 508                 writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
 509                 while (1)
 510                         if (readl(PCIE_STATUS) & 0x1)
 511                                 break;
 512                 writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
 513         }
 514
 515         /* For PCIe 1: first shutdown the phy */
 516         if (dev == MV88F6282_DEV_ID) {
 517                 if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
 518                         writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
 519                         while (1)
 520                                 if (readl(PCIE1_STATUS) & 0x1)
 521                                         break;
 522                         writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
 523                 }
 524         } else  /* keep this bit set for devices that don't have PCIe1 */
 525                 kirkwood_clk_ctrl |= CGC_PEX1;
 526
 527         /* Now gate clock the required units */
 528         writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
 529         printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
 530
 531         return 0;
 532 }
 533 late_initcall(kirkwood_clock_gate);
 534
 535 void kirkwood_restart(char mode, const char *cmd)
 536 {
 537         /*
 538          * Enable soft reset to assert RSTOUTn.
 539          */
 540         writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
 541
 542         /*
 543          * Assert soft reset.
 544          */
 545         writel(SOFT_RESET, SYSTEM_SOFT_RESET);
 546
 547         while (1)
 548                 ;
 549 }