arch/arm/mach-omap2/omap4-common.c

   1 /*
   2  * OMAP4 specific common source file.
   3  *
   4  * Copyright (C) 2010 Texas Instruments, Inc.
   5  * Author:
   6  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
   7  *
   8  *
   9  * This program is free software,you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/io.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/memblock.h>
  19
  20 #include <asm/hardware/gic.h>
  21 #include <asm/hardware/cache-l2x0.h>
  22 #include <asm/mach/map.h>
  23 #include <asm/memblock.h>
  24
  25 #include <plat/irqs.h>
  26 #include <plat/sram.h>
  27
  28 #include <mach/hardware.h>
  29 #include <mach/omap-wakeupgen.h>
  30
  31 #include "common.h"
  32 #include "omap4-sar-layout.h"
  33
  34 #ifdef CONFIG_CACHE_L2X0
  35 static void __iomem *l2cache_base;
  36 #endif
  37
  38 static void __iomem *sar_ram_base;
  39
  40 #ifdef CONFIG_OMAP4_ERRATA_I688
  41 /* Used to implement memory barrier on DRAM path */
  42 #define OMAP4_DRAM_BARRIER_VA                   0xfe600000
  43
  44 void __iomem *dram_sync, *sram_sync;
  45
  46 void omap_bus_sync(void)
  47 {
  48         if (dram_sync && sram_sync) {
  49                 writel_relaxed(readl_relaxed(dram_sync), dram_sync);
  50                 writel_relaxed(readl_relaxed(sram_sync), sram_sync);
  51                 isb();
  52         }
  53 }
  54
  55 static int __init omap_barriers_init(void)
  56 {
  57         struct map_desc dram_io_desc[1];
  58         phys_addr_t paddr;
  59         u32 size;
  60
  61         if (!cpu_is_omap44xx())
  62                 return -ENODEV;
  63
  64         size = ALIGN(PAGE_SIZE, SZ_1M);
  65         paddr = arm_memblock_steal(size, SZ_1M);
  66
  67         dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
  68         dram_io_desc[0].pfn = __phys_to_pfn(paddr);
  69         dram_io_desc[0].length = size;
  70         dram_io_desc[0].type = MT_MEMORY_SO;
  71         iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
  72         dram_sync = (void __iomem *) dram_io_desc[0].virtual;
  73         sram_sync = (void __iomem *) OMAP4_SRAM_VA;
  74
  75         pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
  76                 (long long) paddr, dram_io_desc[0].virtual);
  77
  78         return 0;
  79 }
  80 core_initcall(omap_barriers_init);
  81 #endif
  82
  83 void __init gic_init_irq(void)
  84 {
  85         void __iomem *omap_irq_base;
  86         void __iomem *gic_dist_base_addr;
  87
  88         /* Static mapping, never released */
  89         gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
  90         BUG_ON(!gic_dist_base_addr);
  91
  92         /* Static mapping, never released */
  93         omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
  94         BUG_ON(!omap_irq_base);
  95
  96         omap_wakeupgen_init();
  97
  98         gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
  99 }
 100
 101 #ifdef CONFIG_CACHE_L2X0
 102
 103 void __iomem *omap4_get_l2cache_base(void)
 104 {
 105         return l2cache_base;
 106 }
 107
 108 static void omap4_l2x0_disable(void)
 109 {
 110         /* Disable PL310 L2 Cache controller */
 111         omap_smc1(0x102, 0x0);
 112 }
 113
 114 static void omap4_l2x0_set_debug(unsigned long val)
 115 {
 116         /* Program PL310 L2 Cache controller debug register */
 117         omap_smc1(0x100, val);
 118 }
 119
 120 static int __init omap_l2_cache_init(void)
 121 {
 122         u32 aux_ctrl = 0;
 123
 124         /*
 125          * To avoid code running on other OMAPs in
 126          * multi-omap builds
 127          */
 128         if (!cpu_is_omap44xx())
 129                 return -ENODEV;
 130
 131         /* Static mapping, never released */
 132         l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
 133         if (WARN_ON(!l2cache_base))
 134                 return -ENOMEM;
 135
 136         /*
 137          * 16-way associativity, parity disabled
 138          * Way size - 32KB (es1.0)
 139          * Way size - 64KB (es2.0 +)
 140          */
 141         aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
 142                         (0x1 << 25) |
 143                         (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
 144                         (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
 145
 146         if (omap_rev() == OMAP4430_REV_ES1_0) {
 147                 aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
 148         } else {
 149                 aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
 150                         (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
 151                         (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
 152                         (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
 153                         (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
 154         }
 155         if (omap_rev() != OMAP4430_REV_ES1_0)
 156                 omap_smc1(0x109, aux_ctrl);
 157
 158         /* Enable PL310 L2 Cache controller */
 159         omap_smc1(0x102, 0x1);
 160
 161         l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
 162
 163         /*
 164          * Override default outer_cache.disable with a OMAP4
 165          * specific one
 166         */
 167         outer_cache.disable = omap4_l2x0_disable;
 168         outer_cache.set_debug = omap4_l2x0_set_debug;
 169
 170         return 0;
 171 }
 172 early_initcall(omap_l2_cache_init);
 173 #endif
 174
 175 void __iomem *omap4_get_sar_ram_base(void)
 176 {
 177         return sar_ram_base;
 178 }
 179
 180 /*
 181  * SAR RAM used to save and restore the HW
 182  * context in low power modes
 183  */
 184 static int __init omap4_sar_ram_init(void)
 185 {
 186         /*
 187          * To avoid code running on other OMAPs in
 188          * multi-omap builds
 189          */
 190         if (!cpu_is_omap44xx())
 191                 return -ENOMEM;
 192
 193         /* Static mapping, never released */
 194         sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K);
 195         if (WARN_ON(!sar_ram_base))
 196                 return -ENOMEM;
 197
 198         return 0;
 199 }
 200 early_initcall(omap4_sar_ram_init);