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[zen-stable.git] / arch / arm / mach-omap2 / omap_hwmod_3xxx_data.c
blob5324e8d93bc0262d9019db6feb7f81fdc42a8f44
1 /*
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * The data in this file should be completely autogeneratable from
12 * the TI hardware database or other technical documentation.
13 *
14 * XXX these should be marked initdata for multi-OMAP kernels
15 */
16 #include <plat/omap_hwmod.h>
17 #include <mach/irqs.h>
18 #include <plat/cpu.h>
19 #include <plat/dma.h>
20 #include <plat/serial.h>
21 #include <plat/l3_3xxx.h>
22 #include <plat/l4_3xxx.h>
23 #include <plat/i2c.h>
24 #include <plat/gpio.h>
25 #include <plat/mmc.h>
26 #include <plat/mcbsp.h>
27 #include <plat/mcspi.h>
28 #include <plat/dmtimer.h>
29
30 #include "omap_hwmod_common_data.h"
31
32 #include "prm-regbits-34xx.h"
33 #include "cm-regbits-34xx.h"
34 #include "wd_timer.h"
35 #include <mach/am35xx.h>
36
37 /*
38 * OMAP3xxx hardware module integration data
39 *
40 * ALl of the data in this section should be autogeneratable from the
41 * TI hardware database or other technical documentation. Data that
42 * is driver-specific or driver-kernel integration-specific belongs
43 * elsewhere.
44 */
45
46 static struct omap_hwmod omap3xxx_mpu_hwmod;
47 static struct omap_hwmod omap3xxx_iva_hwmod;
48 static struct omap_hwmod omap3xxx_l3_main_hwmod;
49 static struct omap_hwmod omap3xxx_l4_core_hwmod;
50 static struct omap_hwmod omap3xxx_l4_per_hwmod;
51 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
52 static struct omap_hwmod omap3430es1_dss_core_hwmod;
53 static struct omap_hwmod omap3xxx_dss_core_hwmod;
54 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
55 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
56 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
57 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
58 static struct omap_hwmod omap3xxx_i2c1_hwmod;
59 static struct omap_hwmod omap3xxx_i2c2_hwmod;
60 static struct omap_hwmod omap3xxx_i2c3_hwmod;
61 static struct omap_hwmod omap3xxx_gpio1_hwmod;
62 static struct omap_hwmod omap3xxx_gpio2_hwmod;
63 static struct omap_hwmod omap3xxx_gpio3_hwmod;
64 static struct omap_hwmod omap3xxx_gpio4_hwmod;
65 static struct omap_hwmod omap3xxx_gpio5_hwmod;
66 static struct omap_hwmod omap3xxx_gpio6_hwmod;
67 static struct omap_hwmod omap34xx_sr1_hwmod;
68 static struct omap_hwmod omap34xx_sr2_hwmod;
69 static struct omap_hwmod omap34xx_mcspi1;
70 static struct omap_hwmod omap34xx_mcspi2;
71 static struct omap_hwmod omap34xx_mcspi3;
72 static struct omap_hwmod omap34xx_mcspi4;
73 static struct omap_hwmod omap3xxx_mmc1_hwmod;
74 static struct omap_hwmod omap3xxx_mmc2_hwmod;
75 static struct omap_hwmod omap3xxx_mmc3_hwmod;
76 static struct omap_hwmod am35xx_usbhsotg_hwmod;
77
78 static struct omap_hwmod omap3xxx_dma_system_hwmod;
79
80 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
81 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
82 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
83 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
84 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
85 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
86 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
87 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod;
88 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod;
89
90 /* L3 -> L4_CORE interface */
91 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
92 .master = &omap3xxx_l3_main_hwmod,
93 .slave = &omap3xxx_l4_core_hwmod,
94 .user = OCP_USER_MPU | OCP_USER_SDMA,
95 };
96
97 /* L3 -> L4_PER interface */
98 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
99 .master = &omap3xxx_l3_main_hwmod,
100 .slave = &omap3xxx_l4_per_hwmod,
101 .user = OCP_USER_MPU | OCP_USER_SDMA,
102 };
103
104 /* L3 taret configuration and error log registers */
105 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
106 { .irq = INT_34XX_L3_DBG_IRQ },
107 { .irq = INT_34XX_L3_APP_IRQ },
108 { .irq = -1 }
109 };
110
111 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
112 {
113 .pa_start = 0x68000000,
114 .pa_end = 0x6800ffff,
115 .flags = ADDR_TYPE_RT,
116 },
117 { }
118 };
119
120 /* MPU -> L3 interface */
121 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
122 .master = &omap3xxx_mpu_hwmod,
123 .slave = &omap3xxx_l3_main_hwmod,
124 .addr = omap3xxx_l3_main_addrs,
125 .user = OCP_USER_MPU,
126 };
127
128 /* Slave interfaces on the L3 interconnect */
129 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
130 &omap3xxx_mpu__l3_main,
131 };
132
133 /* DSS -> l3 */
134 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
135 .master = &omap3xxx_dss_core_hwmod,
136 .slave = &omap3xxx_l3_main_hwmod,
137 .fw = {
138 .omap2 = {
139 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
140 .flags = OMAP_FIREWALL_L3,
141 }
142 },
143 .user = OCP_USER_MPU | OCP_USER_SDMA,
144 };
145
146 /* Master interfaces on the L3 interconnect */
147 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
148 &omap3xxx_l3_main__l4_core,
149 &omap3xxx_l3_main__l4_per,
150 };
151
152 /* L3 */
153 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
154 .name = "l3_main",
155 .class = &l3_hwmod_class,
156 .mpu_irqs = omap3xxx_l3_main_irqs,
157 .masters = omap3xxx_l3_main_masters,
158 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
159 .slaves = omap3xxx_l3_main_slaves,
160 .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
161 .flags = HWMOD_NO_IDLEST,
162 };
163
164 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
165 static struct omap_hwmod omap3xxx_uart1_hwmod;
166 static struct omap_hwmod omap3xxx_uart2_hwmod;
167 static struct omap_hwmod omap3xxx_uart3_hwmod;
168 static struct omap_hwmod omap3xxx_uart4_hwmod;
169 static struct omap_hwmod am35xx_uart4_hwmod;
170 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
171
172 /* l3_core -> usbhsotg interface */
173 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
174 .master = &omap3xxx_usbhsotg_hwmod,
175 .slave = &omap3xxx_l3_main_hwmod,
176 .clk = "core_l3_ick",
177 .user = OCP_USER_MPU,
178 };
179
180 /* l3_core -> am35xx_usbhsotg interface */
181 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
182 .master = &am35xx_usbhsotg_hwmod,
183 .slave = &omap3xxx_l3_main_hwmod,
184 .clk = "core_l3_ick",
185 .user = OCP_USER_MPU,
186 };
187 /* L4_CORE -> L4_WKUP interface */
188 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
189 .master = &omap3xxx_l4_core_hwmod,
190 .slave = &omap3xxx_l4_wkup_hwmod,
191 .user = OCP_USER_MPU | OCP_USER_SDMA,
192 };
193
194 /* L4 CORE -> MMC1 interface */
195 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
196 .master = &omap3xxx_l4_core_hwmod,
197 .slave = &omap3xxx_mmc1_hwmod,
198 .clk = "mmchs1_ick",
199 .addr = omap2430_mmc1_addr_space,
200 .user = OCP_USER_MPU | OCP_USER_SDMA,
201 .flags = OMAP_FIREWALL_L4
202 };
203
204 /* L4 CORE -> MMC2 interface */
205 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
206 .master = &omap3xxx_l4_core_hwmod,
207 .slave = &omap3xxx_mmc2_hwmod,
208 .clk = "mmchs2_ick",
209 .addr = omap2430_mmc2_addr_space,
210 .user = OCP_USER_MPU | OCP_USER_SDMA,
211 .flags = OMAP_FIREWALL_L4
212 };
213
214 /* L4 CORE -> MMC3 interface */
215 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
216 {
217 .pa_start = 0x480ad000,
218 .pa_end = 0x480ad1ff,
219 .flags = ADDR_TYPE_RT,
220 },
221 { }
222 };
223
224 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
225 .master = &omap3xxx_l4_core_hwmod,
226 .slave = &omap3xxx_mmc3_hwmod,
227 .clk = "mmchs3_ick",
228 .addr = omap3xxx_mmc3_addr_space,
229 .user = OCP_USER_MPU | OCP_USER_SDMA,
230 .flags = OMAP_FIREWALL_L4
231 };
232
233 /* L4 CORE -> UART1 interface */
234 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
235 {
236 .pa_start = OMAP3_UART1_BASE,
237 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
238 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
239 },
240 { }
241 };
242
243 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
244 .master = &omap3xxx_l4_core_hwmod,
245 .slave = &omap3xxx_uart1_hwmod,
246 .clk = "uart1_ick",
247 .addr = omap3xxx_uart1_addr_space,
248 .user = OCP_USER_MPU | OCP_USER_SDMA,
249 };
250
251 /* L4 CORE -> UART2 interface */
252 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
253 {
254 .pa_start = OMAP3_UART2_BASE,
255 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
256 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
257 },
258 { }
259 };
260
261 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
262 .master = &omap3xxx_l4_core_hwmod,
263 .slave = &omap3xxx_uart2_hwmod,
264 .clk = "uart2_ick",
265 .addr = omap3xxx_uart2_addr_space,
266 .user = OCP_USER_MPU | OCP_USER_SDMA,
267 };
268
269 /* L4 PER -> UART3 interface */
270 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
271 {
272 .pa_start = OMAP3_UART3_BASE,
273 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
274 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
275 },
276 { }
277 };
278
279 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
280 .master = &omap3xxx_l4_per_hwmod,
281 .slave = &omap3xxx_uart3_hwmod,
282 .clk = "uart3_ick",
283 .addr = omap3xxx_uart3_addr_space,
284 .user = OCP_USER_MPU | OCP_USER_SDMA,
285 };
286
287 /* L4 PER -> UART4 interface */
288 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
289 {
290 .pa_start = OMAP3_UART4_BASE,
291 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
292 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
293 },
294 { }
295 };
296
297 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
298 .master = &omap3xxx_l4_per_hwmod,
299 .slave = &omap3xxx_uart4_hwmod,
300 .clk = "uart4_ick",
301 .addr = omap3xxx_uart4_addr_space,
302 .user = OCP_USER_MPU | OCP_USER_SDMA,
303 };
304
305 /* AM35xx: L4 CORE -> UART4 interface */
306 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
307 {
308 .pa_start = OMAP3_UART4_AM35XX_BASE,
309 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
310 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
311 },
312 };
313
314 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
315 .master = &omap3xxx_l4_core_hwmod,
316 .slave = &am35xx_uart4_hwmod,
317 .clk = "uart4_ick",
318 .addr = am35xx_uart4_addr_space,
319 .user = OCP_USER_MPU | OCP_USER_SDMA,
320 };
321
322 /* L4 CORE -> I2C1 interface */
323 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
324 .master = &omap3xxx_l4_core_hwmod,
325 .slave = &omap3xxx_i2c1_hwmod,
326 .clk = "i2c1_ick",
327 .addr = omap2_i2c1_addr_space,
328 .fw = {
329 .omap2 = {
330 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
331 .l4_prot_group = 7,
332 .flags = OMAP_FIREWALL_L4,
333 }
334 },
335 .user = OCP_USER_MPU | OCP_USER_SDMA,
336 };
337
338 /* L4 CORE -> I2C2 interface */
339 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
340 .master = &omap3xxx_l4_core_hwmod,
341 .slave = &omap3xxx_i2c2_hwmod,
342 .clk = "i2c2_ick",
343 .addr = omap2_i2c2_addr_space,
344 .fw = {
345 .omap2 = {
346 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
347 .l4_prot_group = 7,
348 .flags = OMAP_FIREWALL_L4,
349 }
350 },
351 .user = OCP_USER_MPU | OCP_USER_SDMA,
352 };
353
354 /* L4 CORE -> I2C3 interface */
355 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
356 {
357 .pa_start = 0x48060000,
358 .pa_end = 0x48060000 + SZ_128 - 1,
359 .flags = ADDR_TYPE_RT,
360 },
361 { }
362 };
363
364 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
365 .master = &omap3xxx_l4_core_hwmod,
366 .slave = &omap3xxx_i2c3_hwmod,
367 .clk = "i2c3_ick",
368 .addr = omap3xxx_i2c3_addr_space,
369 .fw = {
370 .omap2 = {
371 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
372 .l4_prot_group = 7,
373 .flags = OMAP_FIREWALL_L4,
374 }
375 },
376 .user = OCP_USER_MPU | OCP_USER_SDMA,
377 };
378
379 /* L4 CORE -> SR1 interface */
380 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
381 {
382 .pa_start = OMAP34XX_SR1_BASE,
383 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
384 .flags = ADDR_TYPE_RT,
385 },
386 { }
387 };
388
389 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
390 .master = &omap3xxx_l4_core_hwmod,
391 .slave = &omap34xx_sr1_hwmod,
392 .clk = "sr_l4_ick",
393 .addr = omap3_sr1_addr_space,
394 .user = OCP_USER_MPU,
395 };
396
397 /* L4 CORE -> SR1 interface */
398 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
399 {
400 .pa_start = OMAP34XX_SR2_BASE,
401 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
402 .flags = ADDR_TYPE_RT,
403 },
404 { }
405 };
406
407 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
408 .master = &omap3xxx_l4_core_hwmod,
409 .slave = &omap34xx_sr2_hwmod,
410 .clk = "sr_l4_ick",
411 .addr = omap3_sr2_addr_space,
412 .user = OCP_USER_MPU,
413 };
414
415 /*
416 * usbhsotg interface data
417 */
418
419 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
420 {
421 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
422 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
423 .flags = ADDR_TYPE_RT
424 },
425 { }
426 };
427
428 /* l4_core -> usbhsotg */
429 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
430 .master = &omap3xxx_l4_core_hwmod,
431 .slave = &omap3xxx_usbhsotg_hwmod,
432 .clk = "l4_ick",
433 .addr = omap3xxx_usbhsotg_addrs,
434 .user = OCP_USER_MPU,
435 };
436
437 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
438 &omap3xxx_usbhsotg__l3,
439 };
440
441 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
442 &omap3xxx_l4_core__usbhsotg,
443 };
444
445 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
446 {
447 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
448 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
449 .flags = ADDR_TYPE_RT
450 },
451 { }
452 };
453
454 /* l4_core -> usbhsotg */
455 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
456 .master = &omap3xxx_l4_core_hwmod,
457 .slave = &am35xx_usbhsotg_hwmod,
458 .clk = "l4_ick",
459 .addr = am35xx_usbhsotg_addrs,
460 .user = OCP_USER_MPU,
461 };
462
463 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
464 &am35xx_usbhsotg__l3,
465 };
466
467 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
468 &am35xx_l4_core__usbhsotg,
469 };
470 /* Slave interfaces on the L4_CORE interconnect */
471 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
472 &omap3xxx_l3_main__l4_core,
473 };
474
475 /* L4 CORE */
476 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
477 .name = "l4_core",
478 .class = &l4_hwmod_class,
479 .slaves = omap3xxx_l4_core_slaves,
480 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
481 .flags = HWMOD_NO_IDLEST,
482 };
483
484 /* Slave interfaces on the L4_PER interconnect */
485 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
486 &omap3xxx_l3_main__l4_per,
487 };
488
489 /* L4 PER */
490 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
491 .name = "l4_per",
492 .class = &l4_hwmod_class,
493 .slaves = omap3xxx_l4_per_slaves,
494 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
495 .flags = HWMOD_NO_IDLEST,
496 };
497
498 /* Slave interfaces on the L4_WKUP interconnect */
499 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
500 &omap3xxx_l4_core__l4_wkup,
501 };
502
503 /* L4 WKUP */
504 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
505 .name = "l4_wkup",
506 .class = &l4_hwmod_class,
507 .slaves = omap3xxx_l4_wkup_slaves,
508 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
509 .flags = HWMOD_NO_IDLEST,
510 };
511
512 /* Master interfaces on the MPU device */
513 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
514 &omap3xxx_mpu__l3_main,
515 };
516
517 /* MPU */
518 static struct omap_hwmod omap3xxx_mpu_hwmod = {
519 .name = "mpu",
520 .class = &mpu_hwmod_class,
521 .main_clk = "arm_fck",
522 .masters = omap3xxx_mpu_masters,
523 .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
524 };
525
526 /*
527 * IVA2_2 interface data
528 */
529
530 /* IVA2 <- L3 interface */
531 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
532 .master = &omap3xxx_l3_main_hwmod,
533 .slave = &omap3xxx_iva_hwmod,
534 .clk = "iva2_ck",
535 .user = OCP_USER_MPU | OCP_USER_SDMA,
536 };
537
538 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
539 &omap3xxx_l3__iva,
540 };
541
542 /*
543 * IVA2 (IVA2)
544 */
545
546 static struct omap_hwmod omap3xxx_iva_hwmod = {
547 .name = "iva",
548 .class = &iva_hwmod_class,
549 .masters = omap3xxx_iva_masters,
550 .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
551 };
552
553 /* timer class */
554 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
555 .rev_offs = 0x0000,
556 .sysc_offs = 0x0010,
557 .syss_offs = 0x0014,
558 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
559 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
560 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
561 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
562 .sysc_fields = &omap_hwmod_sysc_type1,
563 };
564
565 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
566 .name = "timer",
567 .sysc = &omap3xxx_timer_1ms_sysc,
568 .rev = OMAP_TIMER_IP_VERSION_1,
569 };
570
571 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
572 .rev_offs = 0x0000,
573 .sysc_offs = 0x0010,
574 .syss_offs = 0x0014,
575 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
576 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
577 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
578 .sysc_fields = &omap_hwmod_sysc_type1,
579 };
580
581 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
582 .name = "timer",
583 .sysc = &omap3xxx_timer_sysc,
584 .rev = OMAP_TIMER_IP_VERSION_1,
585 };
586
587 /* secure timers dev attribute */
588 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
589 .timer_capability = OMAP_TIMER_SECURE,
590 };
591
592 /* always-on timers dev attribute */
593 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
594 .timer_capability = OMAP_TIMER_ALWON,
595 };
596
597 /* pwm timers dev attribute */
598 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
599 .timer_capability = OMAP_TIMER_HAS_PWM,
600 };
601
602 /* timer1 */
603 static struct omap_hwmod omap3xxx_timer1_hwmod;
604
605 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
606 {
607 .pa_start = 0x48318000,
608 .pa_end = 0x48318000 + SZ_1K - 1,
609 .flags = ADDR_TYPE_RT
610 },
611 { }
612 };
613
614 /* l4_wkup -> timer1 */
615 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
616 .master = &omap3xxx_l4_wkup_hwmod,
617 .slave = &omap3xxx_timer1_hwmod,
618 .clk = "gpt1_ick",
619 .addr = omap3xxx_timer1_addrs,
620 .user = OCP_USER_MPU | OCP_USER_SDMA,
621 };
622
623 /* timer1 slave port */
624 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
625 &omap3xxx_l4_wkup__timer1,
626 };
627
628 /* timer1 hwmod */
629 static struct omap_hwmod omap3xxx_timer1_hwmod = {
630 .name = "timer1",
631 .mpu_irqs = omap2_timer1_mpu_irqs,
632 .main_clk = "gpt1_fck",
633 .prcm = {
634 .omap2 = {
635 .prcm_reg_id = 1,
636 .module_bit = OMAP3430_EN_GPT1_SHIFT,
637 .module_offs = WKUP_MOD,
638 .idlest_reg_id = 1,
639 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
640 },
641 },
642 .dev_attr = &capability_alwon_dev_attr,
643 .slaves = omap3xxx_timer1_slaves,
644 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
645 .class = &omap3xxx_timer_1ms_hwmod_class,
646 };
647
648 /* timer2 */
649 static struct omap_hwmod omap3xxx_timer2_hwmod;
650
651 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
652 {
653 .pa_start = 0x49032000,
654 .pa_end = 0x49032000 + SZ_1K - 1,
655 .flags = ADDR_TYPE_RT
656 },
657 { }
658 };
659
660 /* l4_per -> timer2 */
661 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
662 .master = &omap3xxx_l4_per_hwmod,
663 .slave = &omap3xxx_timer2_hwmod,
664 .clk = "gpt2_ick",
665 .addr = omap3xxx_timer2_addrs,
666 .user = OCP_USER_MPU | OCP_USER_SDMA,
667 };
668
669 /* timer2 slave port */
670 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
671 &omap3xxx_l4_per__timer2,
672 };
673
674 /* timer2 hwmod */
675 static struct omap_hwmod omap3xxx_timer2_hwmod = {
676 .name = "timer2",
677 .mpu_irqs = omap2_timer2_mpu_irqs,
678 .main_clk = "gpt2_fck",
679 .prcm = {
680 .omap2 = {
681 .prcm_reg_id = 1,
682 .module_bit = OMAP3430_EN_GPT2_SHIFT,
683 .module_offs = OMAP3430_PER_MOD,
684 .idlest_reg_id = 1,
685 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
686 },
687 },
688 .dev_attr = &capability_alwon_dev_attr,
689 .slaves = omap3xxx_timer2_slaves,
690 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
691 .class = &omap3xxx_timer_1ms_hwmod_class,
692 };
693
694 /* timer3 */
695 static struct omap_hwmod omap3xxx_timer3_hwmod;
696
697 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
698 {
699 .pa_start = 0x49034000,
700 .pa_end = 0x49034000 + SZ_1K - 1,
701 .flags = ADDR_TYPE_RT
702 },
703 { }
704 };
705
706 /* l4_per -> timer3 */
707 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
708 .master = &omap3xxx_l4_per_hwmod,
709 .slave = &omap3xxx_timer3_hwmod,
710 .clk = "gpt3_ick",
711 .addr = omap3xxx_timer3_addrs,
712 .user = OCP_USER_MPU | OCP_USER_SDMA,
713 };
714
715 /* timer3 slave port */
716 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
717 &omap3xxx_l4_per__timer3,
718 };
719
720 /* timer3 hwmod */
721 static struct omap_hwmod omap3xxx_timer3_hwmod = {
722 .name = "timer3",
723 .mpu_irqs = omap2_timer3_mpu_irqs,
724 .main_clk = "gpt3_fck",
725 .prcm = {
726 .omap2 = {
727 .prcm_reg_id = 1,
728 .module_bit = OMAP3430_EN_GPT3_SHIFT,
729 .module_offs = OMAP3430_PER_MOD,
730 .idlest_reg_id = 1,
731 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
732 },
733 },
734 .dev_attr = &capability_alwon_dev_attr,
735 .slaves = omap3xxx_timer3_slaves,
736 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
737 .class = &omap3xxx_timer_hwmod_class,
738 };
739
740 /* timer4 */
741 static struct omap_hwmod omap3xxx_timer4_hwmod;
742
743 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
744 {
745 .pa_start = 0x49036000,
746 .pa_end = 0x49036000 + SZ_1K - 1,
747 .flags = ADDR_TYPE_RT
748 },
749 { }
750 };
751
752 /* l4_per -> timer4 */
753 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
754 .master = &omap3xxx_l4_per_hwmod,
755 .slave = &omap3xxx_timer4_hwmod,
756 .clk = "gpt4_ick",
757 .addr = omap3xxx_timer4_addrs,
758 .user = OCP_USER_MPU | OCP_USER_SDMA,
759 };
760
761 /* timer4 slave port */
762 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
763 &omap3xxx_l4_per__timer4,
764 };
765
766 /* timer4 hwmod */
767 static struct omap_hwmod omap3xxx_timer4_hwmod = {
768 .name = "timer4",
769 .mpu_irqs = omap2_timer4_mpu_irqs,
770 .main_clk = "gpt4_fck",
771 .prcm = {
772 .omap2 = {
773 .prcm_reg_id = 1,
774 .module_bit = OMAP3430_EN_GPT4_SHIFT,
775 .module_offs = OMAP3430_PER_MOD,
776 .idlest_reg_id = 1,
777 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
778 },
779 },
780 .dev_attr = &capability_alwon_dev_attr,
781 .slaves = omap3xxx_timer4_slaves,
782 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
783 .class = &omap3xxx_timer_hwmod_class,
784 };
785
786 /* timer5 */
787 static struct omap_hwmod omap3xxx_timer5_hwmod;
788
789 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
790 {
791 .pa_start = 0x49038000,
792 .pa_end = 0x49038000 + SZ_1K - 1,
793 .flags = ADDR_TYPE_RT
794 },
795 { }
796 };
797
798 /* l4_per -> timer5 */
799 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
800 .master = &omap3xxx_l4_per_hwmod,
801 .slave = &omap3xxx_timer5_hwmod,
802 .clk = "gpt5_ick",
803 .addr = omap3xxx_timer5_addrs,
804 .user = OCP_USER_MPU | OCP_USER_SDMA,
805 };
806
807 /* timer5 slave port */
808 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
809 &omap3xxx_l4_per__timer5,
810 };
811
812 /* timer5 hwmod */
813 static struct omap_hwmod omap3xxx_timer5_hwmod = {
814 .name = "timer5",
815 .mpu_irqs = omap2_timer5_mpu_irqs,
816 .main_clk = "gpt5_fck",
817 .prcm = {
818 .omap2 = {
819 .prcm_reg_id = 1,
820 .module_bit = OMAP3430_EN_GPT5_SHIFT,
821 .module_offs = OMAP3430_PER_MOD,
822 .idlest_reg_id = 1,
823 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
824 },
825 },
826 .dev_attr = &capability_alwon_dev_attr,
827 .slaves = omap3xxx_timer5_slaves,
828 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
829 .class = &omap3xxx_timer_hwmod_class,
830 };
831
832 /* timer6 */
833 static struct omap_hwmod omap3xxx_timer6_hwmod;
834
835 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
836 {
837 .pa_start = 0x4903A000,
838 .pa_end = 0x4903A000 + SZ_1K - 1,
839 .flags = ADDR_TYPE_RT
840 },
841 { }
842 };
843
844 /* l4_per -> timer6 */
845 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
846 .master = &omap3xxx_l4_per_hwmod,
847 .slave = &omap3xxx_timer6_hwmod,
848 .clk = "gpt6_ick",
849 .addr = omap3xxx_timer6_addrs,
850 .user = OCP_USER_MPU | OCP_USER_SDMA,
851 };
852
853 /* timer6 slave port */
854 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
855 &omap3xxx_l4_per__timer6,
856 };
857
858 /* timer6 hwmod */
859 static struct omap_hwmod omap3xxx_timer6_hwmod = {
860 .name = "timer6",
861 .mpu_irqs = omap2_timer6_mpu_irqs,
862 .main_clk = "gpt6_fck",
863 .prcm = {
864 .omap2 = {
865 .prcm_reg_id = 1,
866 .module_bit = OMAP3430_EN_GPT6_SHIFT,
867 .module_offs = OMAP3430_PER_MOD,
868 .idlest_reg_id = 1,
869 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
870 },
871 },
872 .dev_attr = &capability_alwon_dev_attr,
873 .slaves = omap3xxx_timer6_slaves,
874 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
875 .class = &omap3xxx_timer_hwmod_class,
876 };
877
878 /* timer7 */
879 static struct omap_hwmod omap3xxx_timer7_hwmod;
880
881 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
882 {
883 .pa_start = 0x4903C000,
884 .pa_end = 0x4903C000 + SZ_1K - 1,
885 .flags = ADDR_TYPE_RT
886 },
887 { }
888 };
889
890 /* l4_per -> timer7 */
891 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
892 .master = &omap3xxx_l4_per_hwmod,
893 .slave = &omap3xxx_timer7_hwmod,
894 .clk = "gpt7_ick",
895 .addr = omap3xxx_timer7_addrs,
896 .user = OCP_USER_MPU | OCP_USER_SDMA,
897 };
898
899 /* timer7 slave port */
900 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
901 &omap3xxx_l4_per__timer7,
902 };
903
904 /* timer7 hwmod */
905 static struct omap_hwmod omap3xxx_timer7_hwmod = {
906 .name = "timer7",
907 .mpu_irqs = omap2_timer7_mpu_irqs,
908 .main_clk = "gpt7_fck",
909 .prcm = {
910 .omap2 = {
911 .prcm_reg_id = 1,
912 .module_bit = OMAP3430_EN_GPT7_SHIFT,
913 .module_offs = OMAP3430_PER_MOD,
914 .idlest_reg_id = 1,
915 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
916 },
917 },
918 .dev_attr = &capability_alwon_dev_attr,
919 .slaves = omap3xxx_timer7_slaves,
920 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
921 .class = &omap3xxx_timer_hwmod_class,
922 };
923
924 /* timer8 */
925 static struct omap_hwmod omap3xxx_timer8_hwmod;
926
927 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
928 {
929 .pa_start = 0x4903E000,
930 .pa_end = 0x4903E000 + SZ_1K - 1,
931 .flags = ADDR_TYPE_RT
932 },
933 { }
934 };
935
936 /* l4_per -> timer8 */
937 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
938 .master = &omap3xxx_l4_per_hwmod,
939 .slave = &omap3xxx_timer8_hwmod,
940 .clk = "gpt8_ick",
941 .addr = omap3xxx_timer8_addrs,
942 .user = OCP_USER_MPU | OCP_USER_SDMA,
943 };
944
945 /* timer8 slave port */
946 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
947 &omap3xxx_l4_per__timer8,
948 };
949
950 /* timer8 hwmod */
951 static struct omap_hwmod omap3xxx_timer8_hwmod = {
952 .name = "timer8",
953 .mpu_irqs = omap2_timer8_mpu_irqs,
954 .main_clk = "gpt8_fck",
955 .prcm = {
956 .omap2 = {
957 .prcm_reg_id = 1,
958 .module_bit = OMAP3430_EN_GPT8_SHIFT,
959 .module_offs = OMAP3430_PER_MOD,
960 .idlest_reg_id = 1,
961 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
962 },
963 },
964 .dev_attr = &capability_pwm_dev_attr,
965 .slaves = omap3xxx_timer8_slaves,
966 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
967 .class = &omap3xxx_timer_hwmod_class,
968 };
969
970 /* timer9 */
971 static struct omap_hwmod omap3xxx_timer9_hwmod;
972
973 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
974 {
975 .pa_start = 0x49040000,
976 .pa_end = 0x49040000 + SZ_1K - 1,
977 .flags = ADDR_TYPE_RT
978 },
979 { }
980 };
981
982 /* l4_per -> timer9 */
983 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
984 .master = &omap3xxx_l4_per_hwmod,
985 .slave = &omap3xxx_timer9_hwmod,
986 .clk = "gpt9_ick",
987 .addr = omap3xxx_timer9_addrs,
988 .user = OCP_USER_MPU | OCP_USER_SDMA,
989 };
990
991 /* timer9 slave port */
992 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
993 &omap3xxx_l4_per__timer9,
994 };
995
996 /* timer9 hwmod */
997 static struct omap_hwmod omap3xxx_timer9_hwmod = {
998 .name = "timer9",
999 .mpu_irqs = omap2_timer9_mpu_irqs,
1000 .main_clk = "gpt9_fck",
1001 .prcm = {
1002 .omap2 = {
1003 .prcm_reg_id = 1,
1004 .module_bit = OMAP3430_EN_GPT9_SHIFT,
1005 .module_offs = OMAP3430_PER_MOD,
1006 .idlest_reg_id = 1,
1007 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
1008 },
1009 },
1010 .dev_attr = &capability_pwm_dev_attr,
1011 .slaves = omap3xxx_timer9_slaves,
1012 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
1013 .class = &omap3xxx_timer_hwmod_class,
1014 };
1015
1016 /* timer10 */
1017 static struct omap_hwmod omap3xxx_timer10_hwmod;
1018
1019 /* l4_core -> timer10 */
1020 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1021 .master = &omap3xxx_l4_core_hwmod,
1022 .slave = &omap3xxx_timer10_hwmod,
1023 .clk = "gpt10_ick",
1024 .addr = omap2_timer10_addrs,
1025 .user = OCP_USER_MPU | OCP_USER_SDMA,
1026 };
1027
1028 /* timer10 slave port */
1029 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1030 &omap3xxx_l4_core__timer10,
1031 };
1032
1033 /* timer10 hwmod */
1034 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1035 .name = "timer10",
1036 .mpu_irqs = omap2_timer10_mpu_irqs,
1037 .main_clk = "gpt10_fck",
1038 .prcm = {
1039 .omap2 = {
1040 .prcm_reg_id = 1,
1041 .module_bit = OMAP3430_EN_GPT10_SHIFT,
1042 .module_offs = CORE_MOD,
1043 .idlest_reg_id = 1,
1044 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1045 },
1046 },
1047 .dev_attr = &capability_pwm_dev_attr,
1048 .slaves = omap3xxx_timer10_slaves,
1049 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
1050 .class = &omap3xxx_timer_1ms_hwmod_class,
1051 };
1052
1053 /* timer11 */
1054 static struct omap_hwmod omap3xxx_timer11_hwmod;
1055
1056 /* l4_core -> timer11 */
1057 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1058 .master = &omap3xxx_l4_core_hwmod,
1059 .slave = &omap3xxx_timer11_hwmod,
1060 .clk = "gpt11_ick",
1061 .addr = omap2_timer11_addrs,
1062 .user = OCP_USER_MPU | OCP_USER_SDMA,
1063 };
1064
1065 /* timer11 slave port */
1066 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1067 &omap3xxx_l4_core__timer11,
1068 };
1069
1070 /* timer11 hwmod */
1071 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1072 .name = "timer11",
1073 .mpu_irqs = omap2_timer11_mpu_irqs,
1074 .main_clk = "gpt11_fck",
1075 .prcm = {
1076 .omap2 = {
1077 .prcm_reg_id = 1,
1078 .module_bit = OMAP3430_EN_GPT11_SHIFT,
1079 .module_offs = CORE_MOD,
1080 .idlest_reg_id = 1,
1081 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1082 },
1083 },
1084 .dev_attr = &capability_pwm_dev_attr,
1085 .slaves = omap3xxx_timer11_slaves,
1086 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
1087 .class = &omap3xxx_timer_hwmod_class,
1088 };
1089
1090 /* timer12*/
1091 static struct omap_hwmod omap3xxx_timer12_hwmod;
1092 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1093 { .irq = 95, },
1094 { .irq = -1 }
1095 };
1096
1097 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1098 {
1099 .pa_start = 0x48304000,
1100 .pa_end = 0x48304000 + SZ_1K - 1,
1101 .flags = ADDR_TYPE_RT
1102 },
1103 { }
1104 };
1105
1106 /* l4_core -> timer12 */
1107 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1108 .master = &omap3xxx_l4_core_hwmod,
1109 .slave = &omap3xxx_timer12_hwmod,
1110 .clk = "gpt12_ick",
1111 .addr = omap3xxx_timer12_addrs,
1112 .user = OCP_USER_MPU | OCP_USER_SDMA,
1113 };
1114
1115 /* timer12 slave port */
1116 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1117 &omap3xxx_l4_core__timer12,
1118 };
1119
1120 /* timer12 hwmod */
1121 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1122 .name = "timer12",
1123 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
1124 .main_clk = "gpt12_fck",
1125 .prcm = {
1126 .omap2 = {
1127 .prcm_reg_id = 1,
1128 .module_bit = OMAP3430_EN_GPT12_SHIFT,
1129 .module_offs = WKUP_MOD,
1130 .idlest_reg_id = 1,
1131 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1132 },
1133 },
1134 .dev_attr = &capability_secure_dev_attr,
1135 .slaves = omap3xxx_timer12_slaves,
1136 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves),
1137 .class = &omap3xxx_timer_hwmod_class,
1138 };
1139
1140 /* l4_wkup -> wd_timer2 */
1141 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1142 {
1143 .pa_start = 0x48314000,
1144 .pa_end = 0x4831407f,
1145 .flags = ADDR_TYPE_RT
1146 },
1147 { }
1148 };
1149
1150 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1151 .master = &omap3xxx_l4_wkup_hwmod,
1152 .slave = &omap3xxx_wd_timer2_hwmod,
1153 .clk = "wdt2_ick",
1154 .addr = omap3xxx_wd_timer2_addrs,
1155 .user = OCP_USER_MPU | OCP_USER_SDMA,
1156 };
1157
1158 /*
1159 * 'wd_timer' class
1160 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1161 * overflow condition
1162 */
1163
1164 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1165 .rev_offs = 0x0000,
1166 .sysc_offs = 0x0010,
1167 .syss_offs = 0x0014,
1168 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1169 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1170 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1171 SYSS_HAS_RESET_STATUS),
1172 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1173 .sysc_fields = &omap_hwmod_sysc_type1,
1174 };
1175
1176 /* I2C common */
1177 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1178 .rev_offs = 0x00,
1179 .sysc_offs = 0x20,
1180 .syss_offs = 0x10,
1181 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1182 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1183 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1184 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1185 .clockact = CLOCKACT_TEST_ICLK,
1186 .sysc_fields = &omap_hwmod_sysc_type1,
1187 };
1188
1189 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1190 .name = "wd_timer",
1191 .sysc = &omap3xxx_wd_timer_sysc,
1192 .pre_shutdown = &omap2_wd_timer_disable
1193 };
1194
1195 /* wd_timer2 */
1196 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1197 &omap3xxx_l4_wkup__wd_timer2,
1198 };
1199
1200 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1201 .name = "wd_timer2",
1202 .class = &omap3xxx_wd_timer_hwmod_class,
1203 .main_clk = "wdt2_fck",
1204 .prcm = {
1205 .omap2 = {
1206 .prcm_reg_id = 1,
1207 .module_bit = OMAP3430_EN_WDT2_SHIFT,
1208 .module_offs = WKUP_MOD,
1209 .idlest_reg_id = 1,
1210 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1211 },
1212 },
1213 .slaves = omap3xxx_wd_timer2_slaves,
1214 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1215 /*
1216 * XXX: Use software supervised mode, HW supervised smartidle seems to
1217 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1218 */
1219 .flags = HWMOD_SWSUP_SIDLE,
1220 };
1221
1222 /* UART1 */
1223
1224 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1225 &omap3_l4_core__uart1,
1226 };
1227
1228 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1229 .name = "uart1",
1230 .mpu_irqs = omap2_uart1_mpu_irqs,
1231 .sdma_reqs = omap2_uart1_sdma_reqs,
1232 .main_clk = "uart1_fck",
1233 .prcm = {
1234 .omap2 = {
1235 .module_offs = CORE_MOD,
1236 .prcm_reg_id = 1,
1237 .module_bit = OMAP3430_EN_UART1_SHIFT,
1238 .idlest_reg_id = 1,
1239 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1240 },
1241 },
1242 .slaves = omap3xxx_uart1_slaves,
1243 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
1244 .class = &omap2_uart_class,
1245 };
1246
1247 /* UART2 */
1248
1249 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1250 &omap3_l4_core__uart2,
1251 };
1252
1253 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1254 .name = "uart2",
1255 .mpu_irqs = omap2_uart2_mpu_irqs,
1256 .sdma_reqs = omap2_uart2_sdma_reqs,
1257 .main_clk = "uart2_fck",
1258 .prcm = {
1259 .omap2 = {
1260 .module_offs = CORE_MOD,
1261 .prcm_reg_id = 1,
1262 .module_bit = OMAP3430_EN_UART2_SHIFT,
1263 .idlest_reg_id = 1,
1264 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1265 },
1266 },
1267 .slaves = omap3xxx_uart2_slaves,
1268 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
1269 .class = &omap2_uart_class,
1270 };
1271
1272 /* UART3 */
1273
1274 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1275 &omap3_l4_per__uart3,
1276 };
1277
1278 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1279 .name = "uart3",
1280 .mpu_irqs = omap2_uart3_mpu_irqs,
1281 .sdma_reqs = omap2_uart3_sdma_reqs,
1282 .main_clk = "uart3_fck",
1283 .prcm = {
1284 .omap2 = {
1285 .module_offs = OMAP3430_PER_MOD,
1286 .prcm_reg_id = 1,
1287 .module_bit = OMAP3430_EN_UART3_SHIFT,
1288 .idlest_reg_id = 1,
1289 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1290 },
1291 },
1292 .slaves = omap3xxx_uart3_slaves,
1293 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
1294 .class = &omap2_uart_class,
1295 };
1296
1297 /* UART4 */
1298
1299 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1300 { .irq = INT_36XX_UART4_IRQ, },
1301 { .irq = -1 }
1302 };
1303
1304 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1305 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1306 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1307 { .dma_req = -1 }
1308 };
1309
1310 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1311 &omap3_l4_per__uart4,
1312 };
1313
1314 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1315 .name = "uart4",
1316 .mpu_irqs = uart4_mpu_irqs,
1317 .sdma_reqs = uart4_sdma_reqs,
1318 .main_clk = "uart4_fck",
1319 .prcm = {
1320 .omap2 = {
1321 .module_offs = OMAP3430_PER_MOD,
1322 .prcm_reg_id = 1,
1323 .module_bit = OMAP3630_EN_UART4_SHIFT,
1324 .idlest_reg_id = 1,
1325 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1326 },
1327 },
1328 .slaves = omap3xxx_uart4_slaves,
1329 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
1330 .class = &omap2_uart_class,
1331 };
1332
1333 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
1334 { .irq = INT_35XX_UART4_IRQ, },
1335 };
1336
1337 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
1338 { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
1339 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
1340 };
1341
1342 static struct omap_hwmod_ocp_if *am35xx_uart4_slaves[] = {
1343 &am35xx_l4_core__uart4,
1344 };
1345
1346 static struct omap_hwmod am35xx_uart4_hwmod = {
1347 .name = "uart4",
1348 .mpu_irqs = am35xx_uart4_mpu_irqs,
1349 .sdma_reqs = am35xx_uart4_sdma_reqs,
1350 .main_clk = "uart4_fck",
1351 .prcm = {
1352 .omap2 = {
1353 .module_offs = CORE_MOD,
1354 .prcm_reg_id = 1,
1355 .module_bit = OMAP3430_EN_UART4_SHIFT,
1356 .idlest_reg_id = 1,
1357 .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT,
1358 },
1359 },
1360 .slaves = am35xx_uart4_slaves,
1361 .slaves_cnt = ARRAY_SIZE(am35xx_uart4_slaves),
1362 .class = &omap2_uart_class,
1363 };
1364
1365
1366 static struct omap_hwmod_class i2c_class = {
1367 .name = "i2c",
1368 .sysc = &i2c_sysc,
1369 .rev = OMAP_I2C_IP_VERSION_1,
1370 .reset = &omap_i2c_reset,
1371 };
1372
1373 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1374 { .name = "dispc", .dma_req = 5 },
1375 { .name = "dsi1", .dma_req = 74 },
1376 { .dma_req = -1 }
1377 };
1378
1379 /* dss */
1380 /* dss master ports */
1381 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1382 &omap3xxx_dss__l3,
1383 };
1384
1385 /* l4_core -> dss */
1386 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1387 .master = &omap3xxx_l4_core_hwmod,
1388 .slave = &omap3430es1_dss_core_hwmod,
1389 .clk = "dss_ick",
1390 .addr = omap2_dss_addrs,
1391 .fw = {
1392 .omap2 = {
1393 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1394 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1395 .flags = OMAP_FIREWALL_L4,
1396 }
1397 },
1398 .user = OCP_USER_MPU | OCP_USER_SDMA,
1399 };
1400
1401 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1402 .master = &omap3xxx_l4_core_hwmod,
1403 .slave = &omap3xxx_dss_core_hwmod,
1404 .clk = "dss_ick",
1405 .addr = omap2_dss_addrs,
1406 .fw = {
1407 .omap2 = {
1408 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1409 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1410 .flags = OMAP_FIREWALL_L4,
1411 }
1412 },
1413 .user = OCP_USER_MPU | OCP_USER_SDMA,
1414 };
1415
1416 /* dss slave ports */
1417 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1418 &omap3430es1_l4_core__dss,
1419 };
1420
1421 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1422 &omap3xxx_l4_core__dss,
1423 };
1424
1425 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1426 /*
1427 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
1428 * driver does not use these clocks.
1429 */
1430 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1431 { .role = "tv_clk", .clk = "dss_tv_fck" },
1432 /* required only on OMAP3430 */
1433 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1434 };
1435
1436 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1437 .name = "dss_core",
1438 .class = &omap2_dss_hwmod_class,
1439 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1440 .sdma_reqs = omap3xxx_dss_sdma_chs,
1441 .prcm = {
1442 .omap2 = {
1443 .prcm_reg_id = 1,
1444 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1445 .module_offs = OMAP3430_DSS_MOD,
1446 .idlest_reg_id = 1,
1447 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1448 },
1449 },
1450 .opt_clks = dss_opt_clks,
1451 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1452 .slaves = omap3430es1_dss_slaves,
1453 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
1454 .masters = omap3xxx_dss_masters,
1455 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1456 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1457 };
1458
1459 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1460 .name = "dss_core",
1461 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1462 .class = &omap2_dss_hwmod_class,
1463 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1464 .sdma_reqs = omap3xxx_dss_sdma_chs,
1465 .prcm = {
1466 .omap2 = {
1467 .prcm_reg_id = 1,
1468 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1469 .module_offs = OMAP3430_DSS_MOD,
1470 .idlest_reg_id = 1,
1471 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1472 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1473 },
1474 },
1475 .opt_clks = dss_opt_clks,
1476 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1477 .slaves = omap3xxx_dss_slaves,
1478 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves),
1479 .masters = omap3xxx_dss_masters,
1480 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1481 };
1482
1483 /* l4_core -> dss_dispc */
1484 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1485 .master = &omap3xxx_l4_core_hwmod,
1486 .slave = &omap3xxx_dss_dispc_hwmod,
1487 .clk = "dss_ick",
1488 .addr = omap2_dss_dispc_addrs,
1489 .fw = {
1490 .omap2 = {
1491 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1492 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1493 .flags = OMAP_FIREWALL_L4,
1494 }
1495 },
1496 .user = OCP_USER_MPU | OCP_USER_SDMA,
1497 };
1498
1499 /* dss_dispc slave ports */
1500 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1501 &omap3xxx_l4_core__dss_dispc,
1502 };
1503
1504 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1505 .name = "dss_dispc",
1506 .class = &omap2_dispc_hwmod_class,
1507 .mpu_irqs = omap2_dispc_irqs,
1508 .main_clk = "dss1_alwon_fck",
1509 .prcm = {
1510 .omap2 = {
1511 .prcm_reg_id = 1,
1512 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1513 .module_offs = OMAP3430_DSS_MOD,
1514 },
1515 },
1516 .slaves = omap3xxx_dss_dispc_slaves,
1517 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1518 .flags = HWMOD_NO_IDLEST,
1519 .dev_attr = &omap2_3_dss_dispc_dev_attr
1520 };
1521
1522 /*
1523 * 'dsi' class
1524 * display serial interface controller
1525 */
1526
1527 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1528 .name = "dsi",
1529 };
1530
1531 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1532 { .irq = 25 },
1533 { .irq = -1 }
1534 };
1535
1536 /* dss_dsi1 */
1537 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1538 {
1539 .pa_start = 0x4804FC00,
1540 .pa_end = 0x4804FFFF,
1541 .flags = ADDR_TYPE_RT
1542 },
1543 { }
1544 };
1545
1546 /* l4_core -> dss_dsi1 */
1547 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1548 .master = &omap3xxx_l4_core_hwmod,
1549 .slave = &omap3xxx_dss_dsi1_hwmod,
1550 .clk = "dss_ick",
1551 .addr = omap3xxx_dss_dsi1_addrs,
1552 .fw = {
1553 .omap2 = {
1554 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1555 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1556 .flags = OMAP_FIREWALL_L4,
1557 }
1558 },
1559 .user = OCP_USER_MPU | OCP_USER_SDMA,
1560 };
1561
1562 /* dss_dsi1 slave ports */
1563 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1564 &omap3xxx_l4_core__dss_dsi1,
1565 };
1566
1567 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1568 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1569 };
1570
1571 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1572 .name = "dss_dsi1",
1573 .class = &omap3xxx_dsi_hwmod_class,
1574 .mpu_irqs = omap3xxx_dsi1_irqs,
1575 .main_clk = "dss1_alwon_fck",
1576 .prcm = {
1577 .omap2 = {
1578 .prcm_reg_id = 1,
1579 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1580 .module_offs = OMAP3430_DSS_MOD,
1581 },
1582 },
1583 .opt_clks = dss_dsi1_opt_clks,
1584 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
1585 .slaves = omap3xxx_dss_dsi1_slaves,
1586 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1587 .flags = HWMOD_NO_IDLEST,
1588 };
1589
1590 /* l4_core -> dss_rfbi */
1591 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1592 .master = &omap3xxx_l4_core_hwmod,
1593 .slave = &omap3xxx_dss_rfbi_hwmod,
1594 .clk = "dss_ick",
1595 .addr = omap2_dss_rfbi_addrs,
1596 .fw = {
1597 .omap2 = {
1598 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1599 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1600 .flags = OMAP_FIREWALL_L4,
1601 }
1602 },
1603 .user = OCP_USER_MPU | OCP_USER_SDMA,
1604 };
1605
1606 /* dss_rfbi slave ports */
1607 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1608 &omap3xxx_l4_core__dss_rfbi,
1609 };
1610
1611 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1612 { .role = "ick", .clk = "dss_ick" },
1613 };
1614
1615 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1616 .name = "dss_rfbi",
1617 .class = &omap2_rfbi_hwmod_class,
1618 .main_clk = "dss1_alwon_fck",
1619 .prcm = {
1620 .omap2 = {
1621 .prcm_reg_id = 1,
1622 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1623 .module_offs = OMAP3430_DSS_MOD,
1624 },
1625 },
1626 .opt_clks = dss_rfbi_opt_clks,
1627 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1628 .slaves = omap3xxx_dss_rfbi_slaves,
1629 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1630 .flags = HWMOD_NO_IDLEST,
1631 };
1632
1633 /* l4_core -> dss_venc */
1634 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1635 .master = &omap3xxx_l4_core_hwmod,
1636 .slave = &omap3xxx_dss_venc_hwmod,
1637 .clk = "dss_ick",
1638 .addr = omap2_dss_venc_addrs,
1639 .fw = {
1640 .omap2 = {
1641 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1642 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1643 .flags = OMAP_FIREWALL_L4,
1644 }
1645 },
1646 .flags = OCPIF_SWSUP_IDLE,
1647 .user = OCP_USER_MPU | OCP_USER_SDMA,
1648 };
1649
1650 /* dss_venc slave ports */
1651 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1652 &omap3xxx_l4_core__dss_venc,
1653 };
1654
1655 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
1656 /* required only on OMAP3430 */
1657 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1658 };
1659
1660 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1661 .name = "dss_venc",
1662 .class = &omap2_venc_hwmod_class,
1663 .main_clk = "dss_tv_fck",
1664 .prcm = {
1665 .omap2 = {
1666 .prcm_reg_id = 1,
1667 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1668 .module_offs = OMAP3430_DSS_MOD,
1669 },
1670 },
1671 .opt_clks = dss_venc_opt_clks,
1672 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
1673 .slaves = omap3xxx_dss_venc_slaves,
1674 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1675 .flags = HWMOD_NO_IDLEST,
1676 };
1677
1678 /* I2C1 */
1679
1680 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1681 .fifo_depth = 8, /* bytes */
1682 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1683 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1684 OMAP_I2C_FLAG_BUS_SHIFT_2,
1685 };
1686
1687 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1688 &omap3_l4_core__i2c1,
1689 };
1690
1691 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1692 .name = "i2c1",
1693 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1694 .mpu_irqs = omap2_i2c1_mpu_irqs,
1695 .sdma_reqs = omap2_i2c1_sdma_reqs,
1696 .main_clk = "i2c1_fck",
1697 .prcm = {
1698 .omap2 = {
1699 .module_offs = CORE_MOD,
1700 .prcm_reg_id = 1,
1701 .module_bit = OMAP3430_EN_I2C1_SHIFT,
1702 .idlest_reg_id = 1,
1703 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1704 },
1705 },
1706 .slaves = omap3xxx_i2c1_slaves,
1707 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1708 .class = &i2c_class,
1709 .dev_attr = &i2c1_dev_attr,
1710 };
1711
1712 /* I2C2 */
1713
1714 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1715 .fifo_depth = 8, /* bytes */
1716 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1717 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1718 OMAP_I2C_FLAG_BUS_SHIFT_2,
1719 };
1720
1721 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1722 &omap3_l4_core__i2c2,
1723 };
1724
1725 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1726 .name = "i2c2",
1727 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1728 .mpu_irqs = omap2_i2c2_mpu_irqs,
1729 .sdma_reqs = omap2_i2c2_sdma_reqs,
1730 .main_clk = "i2c2_fck",
1731 .prcm = {
1732 .omap2 = {
1733 .module_offs = CORE_MOD,
1734 .prcm_reg_id = 1,
1735 .module_bit = OMAP3430_EN_I2C2_SHIFT,
1736 .idlest_reg_id = 1,
1737 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1738 },
1739 },
1740 .slaves = omap3xxx_i2c2_slaves,
1741 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1742 .class = &i2c_class,
1743 .dev_attr = &i2c2_dev_attr,
1744 };
1745
1746 /* I2C3 */
1747
1748 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1749 .fifo_depth = 64, /* bytes */
1750 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1751 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1752 OMAP_I2C_FLAG_BUS_SHIFT_2,
1753 };
1754
1755 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1756 { .irq = INT_34XX_I2C3_IRQ, },
1757 { .irq = -1 }
1758 };
1759
1760 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1761 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1762 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1763 { .dma_req = -1 }
1764 };
1765
1766 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1767 &omap3_l4_core__i2c3,
1768 };
1769
1770 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1771 .name = "i2c3",
1772 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1773 .mpu_irqs = i2c3_mpu_irqs,
1774 .sdma_reqs = i2c3_sdma_reqs,
1775 .main_clk = "i2c3_fck",
1776 .prcm = {
1777 .omap2 = {
1778 .module_offs = CORE_MOD,
1779 .prcm_reg_id = 1,
1780 .module_bit = OMAP3430_EN_I2C3_SHIFT,
1781 .idlest_reg_id = 1,
1782 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1783 },
1784 },
1785 .slaves = omap3xxx_i2c3_slaves,
1786 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1787 .class = &i2c_class,
1788 .dev_attr = &i2c3_dev_attr,
1789 };
1790
1791 /* l4_wkup -> gpio1 */
1792 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1793 {
1794 .pa_start = 0x48310000,
1795 .pa_end = 0x483101ff,
1796 .flags = ADDR_TYPE_RT
1797 },
1798 { }
1799 };
1800
1801 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1802 .master = &omap3xxx_l4_wkup_hwmod,
1803 .slave = &omap3xxx_gpio1_hwmod,
1804 .addr = omap3xxx_gpio1_addrs,
1805 .user = OCP_USER_MPU | OCP_USER_SDMA,
1806 };
1807
1808 /* l4_per -> gpio2 */
1809 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1810 {
1811 .pa_start = 0x49050000,
1812 .pa_end = 0x490501ff,
1813 .flags = ADDR_TYPE_RT
1814 },
1815 { }
1816 };
1817
1818 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1819 .master = &omap3xxx_l4_per_hwmod,
1820 .slave = &omap3xxx_gpio2_hwmod,
1821 .addr = omap3xxx_gpio2_addrs,
1822 .user = OCP_USER_MPU | OCP_USER_SDMA,
1823 };
1824
1825 /* l4_per -> gpio3 */
1826 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1827 {
1828 .pa_start = 0x49052000,
1829 .pa_end = 0x490521ff,
1830 .flags = ADDR_TYPE_RT
1831 },
1832 { }
1833 };
1834
1835 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1836 .master = &omap3xxx_l4_per_hwmod,
1837 .slave = &omap3xxx_gpio3_hwmod,
1838 .addr = omap3xxx_gpio3_addrs,
1839 .user = OCP_USER_MPU | OCP_USER_SDMA,
1840 };
1841
1842 /* l4_per -> gpio4 */
1843 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1844 {
1845 .pa_start = 0x49054000,
1846 .pa_end = 0x490541ff,
1847 .flags = ADDR_TYPE_RT
1848 },
1849 { }
1850 };
1851
1852 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1853 .master = &omap3xxx_l4_per_hwmod,
1854 .slave = &omap3xxx_gpio4_hwmod,
1855 .addr = omap3xxx_gpio4_addrs,
1856 .user = OCP_USER_MPU | OCP_USER_SDMA,
1857 };
1858
1859 /* l4_per -> gpio5 */
1860 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1861 {
1862 .pa_start = 0x49056000,
1863 .pa_end = 0x490561ff,
1864 .flags = ADDR_TYPE_RT
1865 },
1866 { }
1867 };
1868
1869 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1870 .master = &omap3xxx_l4_per_hwmod,
1871 .slave = &omap3xxx_gpio5_hwmod,
1872 .addr = omap3xxx_gpio5_addrs,
1873 .user = OCP_USER_MPU | OCP_USER_SDMA,
1874 };
1875
1876 /* l4_per -> gpio6 */
1877 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1878 {
1879 .pa_start = 0x49058000,
1880 .pa_end = 0x490581ff,
1881 .flags = ADDR_TYPE_RT
1882 },
1883 { }
1884 };
1885
1886 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1887 .master = &omap3xxx_l4_per_hwmod,
1888 .slave = &omap3xxx_gpio6_hwmod,
1889 .addr = omap3xxx_gpio6_addrs,
1890 .user = OCP_USER_MPU | OCP_USER_SDMA,
1891 };
1892
1893 /*
1894 * 'gpio' class
1895 * general purpose io module
1896 */
1897
1898 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1899 .rev_offs = 0x0000,
1900 .sysc_offs = 0x0010,
1901 .syss_offs = 0x0014,
1902 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1903 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1904 SYSS_HAS_RESET_STATUS),
1905 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1906 .sysc_fields = &omap_hwmod_sysc_type1,
1907 };
1908
1909 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1910 .name = "gpio",
1911 .sysc = &omap3xxx_gpio_sysc,
1912 .rev = 1,
1913 };
1914
1915 /* gpio_dev_attr*/
1916 static struct omap_gpio_dev_attr gpio_dev_attr = {
1917 .bank_width = 32,
1918 .dbck_flag = true,
1919 };
1920
1921 /* gpio1 */
1922 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1923 { .role = "dbclk", .clk = "gpio1_dbck", },
1924 };
1925
1926 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1927 &omap3xxx_l4_wkup__gpio1,
1928 };
1929
1930 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1931 .name = "gpio1",
1932 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1933 .mpu_irqs = omap2_gpio1_irqs,
1934 .main_clk = "gpio1_ick",
1935 .opt_clks = gpio1_opt_clks,
1936 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1937 .prcm = {
1938 .omap2 = {
1939 .prcm_reg_id = 1,
1940 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1941 .module_offs = WKUP_MOD,
1942 .idlest_reg_id = 1,
1943 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1944 },
1945 },
1946 .slaves = omap3xxx_gpio1_slaves,
1947 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1948 .class = &omap3xxx_gpio_hwmod_class,
1949 .dev_attr = &gpio_dev_attr,
1950 };
1951
1952 /* gpio2 */
1953 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1954 { .role = "dbclk", .clk = "gpio2_dbck", },
1955 };
1956
1957 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1958 &omap3xxx_l4_per__gpio2,
1959 };
1960
1961 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1962 .name = "gpio2",
1963 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1964 .mpu_irqs = omap2_gpio2_irqs,
1965 .main_clk = "gpio2_ick",
1966 .opt_clks = gpio2_opt_clks,
1967 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1968 .prcm = {
1969 .omap2 = {
1970 .prcm_reg_id = 1,
1971 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
1972 .module_offs = OMAP3430_PER_MOD,
1973 .idlest_reg_id = 1,
1974 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
1975 },
1976 },
1977 .slaves = omap3xxx_gpio2_slaves,
1978 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
1979 .class = &omap3xxx_gpio_hwmod_class,
1980 .dev_attr = &gpio_dev_attr,
1981 };
1982
1983 /* gpio3 */
1984 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1985 { .role = "dbclk", .clk = "gpio3_dbck", },
1986 };
1987
1988 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
1989 &omap3xxx_l4_per__gpio3,
1990 };
1991
1992 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
1993 .name = "gpio3",
1994 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1995 .mpu_irqs = omap2_gpio3_irqs,
1996 .main_clk = "gpio3_ick",
1997 .opt_clks = gpio3_opt_clks,
1998 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1999 .prcm = {
2000 .omap2 = {
2001 .prcm_reg_id = 1,
2002 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
2003 .module_offs = OMAP3430_PER_MOD,
2004 .idlest_reg_id = 1,
2005 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
2006 },
2007 },
2008 .slaves = omap3xxx_gpio3_slaves,
2009 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
2010 .class = &omap3xxx_gpio_hwmod_class,
2011 .dev_attr = &gpio_dev_attr,
2012 };
2013
2014 /* gpio4 */
2015 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2016 { .role = "dbclk", .clk = "gpio4_dbck", },
2017 };
2018
2019 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2020 &omap3xxx_l4_per__gpio4,
2021 };
2022
2023 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2024 .name = "gpio4",
2025 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2026 .mpu_irqs = omap2_gpio4_irqs,
2027 .main_clk = "gpio4_ick",
2028 .opt_clks = gpio4_opt_clks,
2029 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
2030 .prcm = {
2031 .omap2 = {
2032 .prcm_reg_id = 1,
2033 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2034 .module_offs = OMAP3430_PER_MOD,
2035 .idlest_reg_id = 1,
2036 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2037 },
2038 },
2039 .slaves = omap3xxx_gpio4_slaves,
2040 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2041 .class = &omap3xxx_gpio_hwmod_class,
2042 .dev_attr = &gpio_dev_attr,
2043 };
2044
2045 /* gpio5 */
2046 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2047 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2048 { .irq = -1 }
2049 };
2050
2051 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2052 { .role = "dbclk", .clk = "gpio5_dbck", },
2053 };
2054
2055 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2056 &omap3xxx_l4_per__gpio5,
2057 };
2058
2059 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2060 .name = "gpio5",
2061 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2062 .mpu_irqs = omap3xxx_gpio5_irqs,
2063 .main_clk = "gpio5_ick",
2064 .opt_clks = gpio5_opt_clks,
2065 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2066 .prcm = {
2067 .omap2 = {
2068 .prcm_reg_id = 1,
2069 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2070 .module_offs = OMAP3430_PER_MOD,
2071 .idlest_reg_id = 1,
2072 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2073 },
2074 },
2075 .slaves = omap3xxx_gpio5_slaves,
2076 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2077 .class = &omap3xxx_gpio_hwmod_class,
2078 .dev_attr = &gpio_dev_attr,
2079 };
2080
2081 /* gpio6 */
2082 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2083 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2084 { .irq = -1 }
2085 };
2086
2087 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2088 { .role = "dbclk", .clk = "gpio6_dbck", },
2089 };
2090
2091 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2092 &omap3xxx_l4_per__gpio6,
2093 };
2094
2095 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2096 .name = "gpio6",
2097 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2098 .mpu_irqs = omap3xxx_gpio6_irqs,
2099 .main_clk = "gpio6_ick",
2100 .opt_clks = gpio6_opt_clks,
2101 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2102 .prcm = {
2103 .omap2 = {
2104 .prcm_reg_id = 1,
2105 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2106 .module_offs = OMAP3430_PER_MOD,
2107 .idlest_reg_id = 1,
2108 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2109 },
2110 },
2111 .slaves = omap3xxx_gpio6_slaves,
2112 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2113 .class = &omap3xxx_gpio_hwmod_class,
2114 .dev_attr = &gpio_dev_attr,
2115 };
2116
2117 /* dma_system -> L3 */
2118 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2119 .master = &omap3xxx_dma_system_hwmod,
2120 .slave = &omap3xxx_l3_main_hwmod,
2121 .clk = "core_l3_ick",
2122 .user = OCP_USER_MPU | OCP_USER_SDMA,
2123 };
2124
2125 /* dma attributes */
2126 static struct omap_dma_dev_attr dma_dev_attr = {
2127 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2128 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2129 .lch_count = 32,
2130 };
2131
2132 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2133 .rev_offs = 0x0000,
2134 .sysc_offs = 0x002c,
2135 .syss_offs = 0x0028,
2136 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2137 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2138 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2139 SYSS_HAS_RESET_STATUS),
2140 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2141 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2142 .sysc_fields = &omap_hwmod_sysc_type1,
2143 };
2144
2145 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2146 .name = "dma",
2147 .sysc = &omap3xxx_dma_sysc,
2148 };
2149
2150 /* dma_system */
2151 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2152 {
2153 .pa_start = 0x48056000,
2154 .pa_end = 0x48056fff,
2155 .flags = ADDR_TYPE_RT
2156 },
2157 { }
2158 };
2159
2160 /* dma_system master ports */
2161 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2162 &omap3xxx_dma_system__l3,
2163 };
2164
2165 /* l4_cfg -> dma_system */
2166 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2167 .master = &omap3xxx_l4_core_hwmod,
2168 .slave = &omap3xxx_dma_system_hwmod,
2169 .clk = "core_l4_ick",
2170 .addr = omap3xxx_dma_system_addrs,
2171 .user = OCP_USER_MPU | OCP_USER_SDMA,
2172 };
2173
2174 /* dma_system slave ports */
2175 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2176 &omap3xxx_l4_core__dma_system,
2177 };
2178
2179 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2180 .name = "dma",
2181 .class = &omap3xxx_dma_hwmod_class,
2182 .mpu_irqs = omap2_dma_system_irqs,
2183 .main_clk = "core_l3_ick",
2184 .prcm = {
2185 .omap2 = {
2186 .module_offs = CORE_MOD,
2187 .prcm_reg_id = 1,
2188 .module_bit = OMAP3430_ST_SDMA_SHIFT,
2189 .idlest_reg_id = 1,
2190 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
2191 },
2192 },
2193 .slaves = omap3xxx_dma_system_slaves,
2194 .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2195 .masters = omap3xxx_dma_system_masters,
2196 .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
2197 .dev_attr = &dma_dev_attr,
2198 .flags = HWMOD_NO_IDLEST,
2199 };
2200
2201 /*
2202 * 'mcbsp' class
2203 * multi channel buffered serial port controller
2204 */
2205
2206 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2207 .sysc_offs = 0x008c,
2208 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2209 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2210 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2211 .sysc_fields = &omap_hwmod_sysc_type1,
2212 .clockact = 0x2,
2213 };
2214
2215 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2216 .name = "mcbsp",
2217 .sysc = &omap3xxx_mcbsp_sysc,
2218 .rev = MCBSP_CONFIG_TYPE3,
2219 };
2220
2221 /* mcbsp1 */
2222 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2223 { .name = "irq", .irq = 16 },
2224 { .name = "tx", .irq = 59 },
2225 { .name = "rx", .irq = 60 },
2226 { .irq = -1 }
2227 };
2228
2229 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2230 {
2231 .name = "mpu",
2232 .pa_start = 0x48074000,
2233 .pa_end = 0x480740ff,
2234 .flags = ADDR_TYPE_RT
2235 },
2236 { }
2237 };
2238
2239 /* l4_core -> mcbsp1 */
2240 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2241 .master = &omap3xxx_l4_core_hwmod,
2242 .slave = &omap3xxx_mcbsp1_hwmod,
2243 .clk = "mcbsp1_ick",
2244 .addr = omap3xxx_mcbsp1_addrs,
2245 .user = OCP_USER_MPU | OCP_USER_SDMA,
2246 };
2247
2248 /* mcbsp1 slave ports */
2249 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2250 &omap3xxx_l4_core__mcbsp1,
2251 };
2252
2253 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2254 .name = "mcbsp1",
2255 .class = &omap3xxx_mcbsp_hwmod_class,
2256 .mpu_irqs = omap3xxx_mcbsp1_irqs,
2257 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
2258 .main_clk = "mcbsp1_fck",
2259 .prcm = {
2260 .omap2 = {
2261 .prcm_reg_id = 1,
2262 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2263 .module_offs = CORE_MOD,
2264 .idlest_reg_id = 1,
2265 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2266 },
2267 },
2268 .slaves = omap3xxx_mcbsp1_slaves,
2269 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2270 };
2271
2272 /* mcbsp2 */
2273 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2274 { .name = "irq", .irq = 17 },
2275 { .name = "tx", .irq = 62 },
2276 { .name = "rx", .irq = 63 },
2277 { .irq = -1 }
2278 };
2279
2280 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2281 {
2282 .name = "mpu",
2283 .pa_start = 0x49022000,
2284 .pa_end = 0x490220ff,
2285 .flags = ADDR_TYPE_RT
2286 },
2287 { }
2288 };
2289
2290 /* l4_per -> mcbsp2 */
2291 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2292 .master = &omap3xxx_l4_per_hwmod,
2293 .slave = &omap3xxx_mcbsp2_hwmod,
2294 .clk = "mcbsp2_ick",
2295 .addr = omap3xxx_mcbsp2_addrs,
2296 .user = OCP_USER_MPU | OCP_USER_SDMA,
2297 };
2298
2299 /* mcbsp2 slave ports */
2300 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2301 &omap3xxx_l4_per__mcbsp2,
2302 };
2303
2304 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2305 .sidetone = "mcbsp2_sidetone",
2306 };
2307
2308 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2309 .name = "mcbsp2",
2310 .class = &omap3xxx_mcbsp_hwmod_class,
2311 .mpu_irqs = omap3xxx_mcbsp2_irqs,
2312 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
2313 .main_clk = "mcbsp2_fck",
2314 .prcm = {
2315 .omap2 = {
2316 .prcm_reg_id = 1,
2317 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2318 .module_offs = OMAP3430_PER_MOD,
2319 .idlest_reg_id = 1,
2320 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2321 },
2322 },
2323 .slaves = omap3xxx_mcbsp2_slaves,
2324 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2325 .dev_attr = &omap34xx_mcbsp2_dev_attr,
2326 };
2327
2328 /* mcbsp3 */
2329 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2330 { .name = "irq", .irq = 22 },
2331 { .name = "tx", .irq = 89 },
2332 { .name = "rx", .irq = 90 },
2333 { .irq = -1 }
2334 };
2335
2336 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2337 {
2338 .name = "mpu",
2339 .pa_start = 0x49024000,
2340 .pa_end = 0x490240ff,
2341 .flags = ADDR_TYPE_RT
2342 },
2343 { }
2344 };
2345
2346 /* l4_per -> mcbsp3 */
2347 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2348 .master = &omap3xxx_l4_per_hwmod,
2349 .slave = &omap3xxx_mcbsp3_hwmod,
2350 .clk = "mcbsp3_ick",
2351 .addr = omap3xxx_mcbsp3_addrs,
2352 .user = OCP_USER_MPU | OCP_USER_SDMA,
2353 };
2354
2355 /* mcbsp3 slave ports */
2356 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2357 &omap3xxx_l4_per__mcbsp3,
2358 };
2359
2360 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2361 .sidetone = "mcbsp3_sidetone",
2362 };
2363
2364 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2365 .name = "mcbsp3",
2366 .class = &omap3xxx_mcbsp_hwmod_class,
2367 .mpu_irqs = omap3xxx_mcbsp3_irqs,
2368 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
2369 .main_clk = "mcbsp3_fck",
2370 .prcm = {
2371 .omap2 = {
2372 .prcm_reg_id = 1,
2373 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2374 .module_offs = OMAP3430_PER_MOD,
2375 .idlest_reg_id = 1,
2376 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2377 },
2378 },
2379 .slaves = omap3xxx_mcbsp3_slaves,
2380 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2381 .dev_attr = &omap34xx_mcbsp3_dev_attr,
2382 };
2383
2384 /* mcbsp4 */
2385 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2386 { .name = "irq", .irq = 23 },
2387 { .name = "tx", .irq = 54 },
2388 { .name = "rx", .irq = 55 },
2389 { .irq = -1 }
2390 };
2391
2392 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2393 { .name = "rx", .dma_req = 20 },
2394 { .name = "tx", .dma_req = 19 },
2395 { .dma_req = -1 }
2396 };
2397
2398 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2399 {
2400 .name = "mpu",
2401 .pa_start = 0x49026000,
2402 .pa_end = 0x490260ff,
2403 .flags = ADDR_TYPE_RT
2404 },
2405 { }
2406 };
2407
2408 /* l4_per -> mcbsp4 */
2409 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2410 .master = &omap3xxx_l4_per_hwmod,
2411 .slave = &omap3xxx_mcbsp4_hwmod,
2412 .clk = "mcbsp4_ick",
2413 .addr = omap3xxx_mcbsp4_addrs,
2414 .user = OCP_USER_MPU | OCP_USER_SDMA,
2415 };
2416
2417 /* mcbsp4 slave ports */
2418 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2419 &omap3xxx_l4_per__mcbsp4,
2420 };
2421
2422 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2423 .name = "mcbsp4",
2424 .class = &omap3xxx_mcbsp_hwmod_class,
2425 .mpu_irqs = omap3xxx_mcbsp4_irqs,
2426 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
2427 .main_clk = "mcbsp4_fck",
2428 .prcm = {
2429 .omap2 = {
2430 .prcm_reg_id = 1,
2431 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2432 .module_offs = OMAP3430_PER_MOD,
2433 .idlest_reg_id = 1,
2434 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2435 },
2436 },
2437 .slaves = omap3xxx_mcbsp4_slaves,
2438 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2439 };
2440
2441 /* mcbsp5 */
2442 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2443 { .name = "irq", .irq = 27 },
2444 { .name = "tx", .irq = 81 },
2445 { .name = "rx", .irq = 82 },
2446 { .irq = -1 }
2447 };
2448
2449 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2450 { .name = "rx", .dma_req = 22 },
2451 { .name = "tx", .dma_req = 21 },
2452 { .dma_req = -1 }
2453 };
2454
2455 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2456 {
2457 .name = "mpu",
2458 .pa_start = 0x48096000,
2459 .pa_end = 0x480960ff,
2460 .flags = ADDR_TYPE_RT
2461 },
2462 { }
2463 };
2464
2465 /* l4_core -> mcbsp5 */
2466 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2467 .master = &omap3xxx_l4_core_hwmod,
2468 .slave = &omap3xxx_mcbsp5_hwmod,
2469 .clk = "mcbsp5_ick",
2470 .addr = omap3xxx_mcbsp5_addrs,
2471 .user = OCP_USER_MPU | OCP_USER_SDMA,
2472 };
2473
2474 /* mcbsp5 slave ports */
2475 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2476 &omap3xxx_l4_core__mcbsp5,
2477 };
2478
2479 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2480 .name = "mcbsp5",
2481 .class = &omap3xxx_mcbsp_hwmod_class,
2482 .mpu_irqs = omap3xxx_mcbsp5_irqs,
2483 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
2484 .main_clk = "mcbsp5_fck",
2485 .prcm = {
2486 .omap2 = {
2487 .prcm_reg_id = 1,
2488 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2489 .module_offs = CORE_MOD,
2490 .idlest_reg_id = 1,
2491 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2492 },
2493 },
2494 .slaves = omap3xxx_mcbsp5_slaves,
2495 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2496 };
2497 /* 'mcbsp sidetone' class */
2498
2499 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2500 .sysc_offs = 0x0010,
2501 .sysc_flags = SYSC_HAS_AUTOIDLE,
2502 .sysc_fields = &omap_hwmod_sysc_type1,
2503 };
2504
2505 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2506 .name = "mcbsp_sidetone",
2507 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2508 };
2509
2510 /* mcbsp2_sidetone */
2511 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2512 { .name = "irq", .irq = 4 },
2513 { .irq = -1 }
2514 };
2515
2516 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2517 {
2518 .name = "sidetone",
2519 .pa_start = 0x49028000,
2520 .pa_end = 0x490280ff,
2521 .flags = ADDR_TYPE_RT
2522 },
2523 { }
2524 };
2525
2526 /* l4_per -> mcbsp2_sidetone */
2527 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2528 .master = &omap3xxx_l4_per_hwmod,
2529 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2530 .clk = "mcbsp2_ick",
2531 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2532 .user = OCP_USER_MPU,
2533 };
2534
2535 /* mcbsp2_sidetone slave ports */
2536 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2537 &omap3xxx_l4_per__mcbsp2_sidetone,
2538 };
2539
2540 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2541 .name = "mcbsp2_sidetone",
2542 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2543 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
2544 .main_clk = "mcbsp2_fck",
2545 .prcm = {
2546 .omap2 = {
2547 .prcm_reg_id = 1,
2548 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2549 .module_offs = OMAP3430_PER_MOD,
2550 .idlest_reg_id = 1,
2551 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2552 },
2553 },
2554 .slaves = omap3xxx_mcbsp2_sidetone_slaves,
2555 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2556 };
2557
2558 /* mcbsp3_sidetone */
2559 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2560 { .name = "irq", .irq = 5 },
2561 { .irq = -1 }
2562 };
2563
2564 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2565 {
2566 .name = "sidetone",
2567 .pa_start = 0x4902A000,
2568 .pa_end = 0x4902A0ff,
2569 .flags = ADDR_TYPE_RT
2570 },
2571 { }
2572 };
2573
2574 /* l4_per -> mcbsp3_sidetone */
2575 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2576 .master = &omap3xxx_l4_per_hwmod,
2577 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2578 .clk = "mcbsp3_ick",
2579 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2580 .user = OCP_USER_MPU,
2581 };
2582
2583 /* mcbsp3_sidetone slave ports */
2584 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2585 &omap3xxx_l4_per__mcbsp3_sidetone,
2586 };
2587
2588 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2589 .name = "mcbsp3_sidetone",
2590 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2591 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
2592 .main_clk = "mcbsp3_fck",
2593 .prcm = {
2594 .omap2 = {
2595 .prcm_reg_id = 1,
2596 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2597 .module_offs = OMAP3430_PER_MOD,
2598 .idlest_reg_id = 1,
2599 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2600 },
2601 },
2602 .slaves = omap3xxx_mcbsp3_sidetone_slaves,
2603 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2604 };
2605
2606
2607 /* SR common */
2608 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2609 .clkact_shift = 20,
2610 };
2611
2612 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2613 .sysc_offs = 0x24,
2614 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2615 .clockact = CLOCKACT_TEST_ICLK,
2616 .sysc_fields = &omap34xx_sr_sysc_fields,
2617 };
2618
2619 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2620 .name = "smartreflex",
2621 .sysc = &omap34xx_sr_sysc,
2622 .rev = 1,
2623 };
2624
2625 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2626 .sidle_shift = 24,
2627 .enwkup_shift = 26
2628 };
2629
2630 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2631 .sysc_offs = 0x38,
2632 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2633 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2634 SYSC_NO_CACHE),
2635 .sysc_fields = &omap36xx_sr_sysc_fields,
2636 };
2637
2638 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2639 .name = "smartreflex",
2640 .sysc = &omap36xx_sr_sysc,
2641 .rev = 2,
2642 };
2643
2644 /* SR1 */
2645 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2646 &omap3_l4_core__sr1,
2647 };
2648
2649 static struct omap_hwmod omap34xx_sr1_hwmod = {
2650 .name = "sr1_hwmod",
2651 .class = &omap34xx_smartreflex_hwmod_class,
2652 .main_clk = "sr1_fck",
2653 .vdd_name = "mpu_iva",
2654 .prcm = {
2655 .omap2 = {
2656 .prcm_reg_id = 1,
2657 .module_bit = OMAP3430_EN_SR1_SHIFT,
2658 .module_offs = WKUP_MOD,
2659 .idlest_reg_id = 1,
2660 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2661 },
2662 },
2663 .slaves = omap3_sr1_slaves,
2664 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2665 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2666 };
2667
2668 static struct omap_hwmod omap36xx_sr1_hwmod = {
2669 .name = "sr1_hwmod",
2670 .class = &omap36xx_smartreflex_hwmod_class,
2671 .main_clk = "sr1_fck",
2672 .vdd_name = "mpu_iva",
2673 .prcm = {
2674 .omap2 = {
2675 .prcm_reg_id = 1,
2676 .module_bit = OMAP3430_EN_SR1_SHIFT,
2677 .module_offs = WKUP_MOD,
2678 .idlest_reg_id = 1,
2679 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2680 },
2681 },
2682 .slaves = omap3_sr1_slaves,
2683 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2684 };
2685
2686 /* SR2 */
2687 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2688 &omap3_l4_core__sr2,
2689 };
2690
2691 static struct omap_hwmod omap34xx_sr2_hwmod = {
2692 .name = "sr2_hwmod",
2693 .class = &omap34xx_smartreflex_hwmod_class,
2694 .main_clk = "sr2_fck",
2695 .vdd_name = "core",
2696 .prcm = {
2697 .omap2 = {
2698 .prcm_reg_id = 1,
2699 .module_bit = OMAP3430_EN_SR2_SHIFT,
2700 .module_offs = WKUP_MOD,
2701 .idlest_reg_id = 1,
2702 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2703 },
2704 },
2705 .slaves = omap3_sr2_slaves,
2706 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2707 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2708 };
2709
2710 static struct omap_hwmod omap36xx_sr2_hwmod = {
2711 .name = "sr2_hwmod",
2712 .class = &omap36xx_smartreflex_hwmod_class,
2713 .main_clk = "sr2_fck",
2714 .vdd_name = "core",
2715 .prcm = {
2716 .omap2 = {
2717 .prcm_reg_id = 1,
2718 .module_bit = OMAP3430_EN_SR2_SHIFT,
2719 .module_offs = WKUP_MOD,
2720 .idlest_reg_id = 1,
2721 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2722 },
2723 },
2724 .slaves = omap3_sr2_slaves,
2725 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2726 };
2727
2728 /*
2729 * 'mailbox' class
2730 * mailbox module allowing communication between the on-chip processors
2731 * using a queued mailbox-interrupt mechanism.
2732 */
2733
2734 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2735 .rev_offs = 0x000,
2736 .sysc_offs = 0x010,
2737 .syss_offs = 0x014,
2738 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2739 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2740 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2741 .sysc_fields = &omap_hwmod_sysc_type1,
2742 };
2743
2744 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2745 .name = "mailbox",
2746 .sysc = &omap3xxx_mailbox_sysc,
2747 };
2748
2749 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2750 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2751 { .irq = 26 },
2752 { .irq = -1 }
2753 };
2754
2755 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2756 {
2757 .pa_start = 0x48094000,
2758 .pa_end = 0x480941ff,
2759 .flags = ADDR_TYPE_RT,
2760 },
2761 { }
2762 };
2763
2764 /* l4_core -> mailbox */
2765 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2766 .master = &omap3xxx_l4_core_hwmod,
2767 .slave = &omap3xxx_mailbox_hwmod,
2768 .addr = omap3xxx_mailbox_addrs,
2769 .user = OCP_USER_MPU | OCP_USER_SDMA,
2770 };
2771
2772 /* mailbox slave ports */
2773 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2774 &omap3xxx_l4_core__mailbox,
2775 };
2776
2777 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2778 .name = "mailbox",
2779 .class = &omap3xxx_mailbox_hwmod_class,
2780 .mpu_irqs = omap3xxx_mailbox_irqs,
2781 .main_clk = "mailboxes_ick",
2782 .prcm = {
2783 .omap2 = {
2784 .prcm_reg_id = 1,
2785 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2786 .module_offs = CORE_MOD,
2787 .idlest_reg_id = 1,
2788 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2789 },
2790 },
2791 .slaves = omap3xxx_mailbox_slaves,
2792 .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2793 };
2794
2795 /* l4 core -> mcspi1 interface */
2796 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2797 .master = &omap3xxx_l4_core_hwmod,
2798 .slave = &omap34xx_mcspi1,
2799 .clk = "mcspi1_ick",
2800 .addr = omap2_mcspi1_addr_space,
2801 .user = OCP_USER_MPU | OCP_USER_SDMA,
2802 };
2803
2804 /* l4 core -> mcspi2 interface */
2805 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2806 .master = &omap3xxx_l4_core_hwmod,
2807 .slave = &omap34xx_mcspi2,
2808 .clk = "mcspi2_ick",
2809 .addr = omap2_mcspi2_addr_space,
2810 .user = OCP_USER_MPU | OCP_USER_SDMA,
2811 };
2812
2813 /* l4 core -> mcspi3 interface */
2814 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2815 .master = &omap3xxx_l4_core_hwmod,
2816 .slave = &omap34xx_mcspi3,
2817 .clk = "mcspi3_ick",
2818 .addr = omap2430_mcspi3_addr_space,
2819 .user = OCP_USER_MPU | OCP_USER_SDMA,
2820 };
2821
2822 /* l4 core -> mcspi4 interface */
2823 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2824 {
2825 .pa_start = 0x480ba000,
2826 .pa_end = 0x480ba0ff,
2827 .flags = ADDR_TYPE_RT,
2828 },
2829 { }
2830 };
2831
2832 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2833 .master = &omap3xxx_l4_core_hwmod,
2834 .slave = &omap34xx_mcspi4,
2835 .clk = "mcspi4_ick",
2836 .addr = omap34xx_mcspi4_addr_space,
2837 .user = OCP_USER_MPU | OCP_USER_SDMA,
2838 };
2839
2840 /*
2841 * 'mcspi' class
2842 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2843 * bus
2844 */
2845
2846 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2847 .rev_offs = 0x0000,
2848 .sysc_offs = 0x0010,
2849 .syss_offs = 0x0014,
2850 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2851 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2852 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2853 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2854 .sysc_fields = &omap_hwmod_sysc_type1,
2855 };
2856
2857 static struct omap_hwmod_class omap34xx_mcspi_class = {
2858 .name = "mcspi",
2859 .sysc = &omap34xx_mcspi_sysc,
2860 .rev = OMAP3_MCSPI_REV,
2861 };
2862
2863 /* mcspi1 */
2864 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2865 &omap34xx_l4_core__mcspi1,
2866 };
2867
2868 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2869 .num_chipselect = 4,
2870 };
2871
2872 static struct omap_hwmod omap34xx_mcspi1 = {
2873 .name = "mcspi1",
2874 .mpu_irqs = omap2_mcspi1_mpu_irqs,
2875 .sdma_reqs = omap2_mcspi1_sdma_reqs,
2876 .main_clk = "mcspi1_fck",
2877 .prcm = {
2878 .omap2 = {
2879 .module_offs = CORE_MOD,
2880 .prcm_reg_id = 1,
2881 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2882 .idlest_reg_id = 1,
2883 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2884 },
2885 },
2886 .slaves = omap34xx_mcspi1_slaves,
2887 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2888 .class = &omap34xx_mcspi_class,
2889 .dev_attr = &omap_mcspi1_dev_attr,
2890 };
2891
2892 /* mcspi2 */
2893 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2894 &omap34xx_l4_core__mcspi2,
2895 };
2896
2897 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2898 .num_chipselect = 2,
2899 };
2900
2901 static struct omap_hwmod omap34xx_mcspi2 = {
2902 .name = "mcspi2",
2903 .mpu_irqs = omap2_mcspi2_mpu_irqs,
2904 .sdma_reqs = omap2_mcspi2_sdma_reqs,
2905 .main_clk = "mcspi2_fck",
2906 .prcm = {
2907 .omap2 = {
2908 .module_offs = CORE_MOD,
2909 .prcm_reg_id = 1,
2910 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2911 .idlest_reg_id = 1,
2912 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2913 },
2914 },
2915 .slaves = omap34xx_mcspi2_slaves,
2916 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2917 .class = &omap34xx_mcspi_class,
2918 .dev_attr = &omap_mcspi2_dev_attr,
2919 };
2920
2921 /* mcspi3 */
2922 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2923 { .name = "irq", .irq = 91 }, /* 91 */
2924 { .irq = -1 }
2925 };
2926
2927 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2928 { .name = "tx0", .dma_req = 15 },
2929 { .name = "rx0", .dma_req = 16 },
2930 { .name = "tx1", .dma_req = 23 },
2931 { .name = "rx1", .dma_req = 24 },
2932 { .dma_req = -1 }
2933 };
2934
2935 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2936 &omap34xx_l4_core__mcspi3,
2937 };
2938
2939 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2940 .num_chipselect = 2,
2941 };
2942
2943 static struct omap_hwmod omap34xx_mcspi3 = {
2944 .name = "mcspi3",
2945 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
2946 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
2947 .main_clk = "mcspi3_fck",
2948 .prcm = {
2949 .omap2 = {
2950 .module_offs = CORE_MOD,
2951 .prcm_reg_id = 1,
2952 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2953 .idlest_reg_id = 1,
2954 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2955 },
2956 },
2957 .slaves = omap34xx_mcspi3_slaves,
2958 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
2959 .class = &omap34xx_mcspi_class,
2960 .dev_attr = &omap_mcspi3_dev_attr,
2961 };
2962
2963 /* SPI4 */
2964 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
2965 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2966 { .irq = -1 }
2967 };
2968
2969 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
2970 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
2971 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
2972 { .dma_req = -1 }
2973 };
2974
2975 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
2976 &omap34xx_l4_core__mcspi4,
2977 };
2978
2979 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
2980 .num_chipselect = 1,
2981 };
2982
2983 static struct omap_hwmod omap34xx_mcspi4 = {
2984 .name = "mcspi4",
2985 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
2986 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
2987 .main_clk = "mcspi4_fck",
2988 .prcm = {
2989 .omap2 = {
2990 .module_offs = CORE_MOD,
2991 .prcm_reg_id = 1,
2992 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
2993 .idlest_reg_id = 1,
2994 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
2995 },
2996 },
2997 .slaves = omap34xx_mcspi4_slaves,
2998 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
2999 .class = &omap34xx_mcspi_class,
3000 .dev_attr = &omap_mcspi4_dev_attr,
3001 };
3002
3003 /*
3004 * usbhsotg
3005 */
3006 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
3007 .rev_offs = 0x0400,
3008 .sysc_offs = 0x0404,
3009 .syss_offs = 0x0408,
3010 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
3011 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3012 SYSC_HAS_AUTOIDLE),
3013 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3014 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3015 .sysc_fields = &omap_hwmod_sysc_type1,
3016 };
3017
3018 static struct omap_hwmod_class usbotg_class = {
3019 .name = "usbotg",
3020 .sysc = &omap3xxx_usbhsotg_sysc,
3021 };
3022 /* usb_otg_hs */
3023 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3024
3025 { .name = "mc", .irq = 92 },
3026 { .name = "dma", .irq = 93 },
3027 { .irq = -1 }
3028 };
3029
3030 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3031 .name = "usb_otg_hs",
3032 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
3033 .main_clk = "hsotgusb_ick",
3034 .prcm = {
3035 .omap2 = {
3036 .prcm_reg_id = 1,
3037 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
3038 .module_offs = CORE_MOD,
3039 .idlest_reg_id = 1,
3040 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3041 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3042 },
3043 },
3044 .masters = omap3xxx_usbhsotg_masters,
3045 .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3046 .slaves = omap3xxx_usbhsotg_slaves,
3047 .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3048 .class = &usbotg_class,
3049
3050 /*
3051 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
3052 * broken when autoidle is enabled
3053 * workaround is to disable the autoidle bit at module level.
3054 */
3055 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3056 | HWMOD_SWSUP_MSTANDBY,
3057 };
3058
3059 /* usb_otg_hs */
3060 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3061
3062 { .name = "mc", .irq = 71 },
3063 { .irq = -1 }
3064 };
3065
3066 static struct omap_hwmod_class am35xx_usbotg_class = {
3067 .name = "am35xx_usbotg",
3068 .sysc = NULL,
3069 };
3070
3071 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3072 .name = "am35x_otg_hs",
3073 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
3074 .main_clk = NULL,
3075 .prcm = {
3076 .omap2 = {
3077 },
3078 },
3079 .masters = am35xx_usbhsotg_masters,
3080 .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
3081 .slaves = am35xx_usbhsotg_slaves,
3082 .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3083 .class = &am35xx_usbotg_class,
3084 };
3085
3086 /* MMC/SD/SDIO common */
3087
3088 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3089 .rev_offs = 0x1fc,
3090 .sysc_offs = 0x10,
3091 .syss_offs = 0x14,
3092 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3093 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3094 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3095 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3096 .sysc_fields = &omap_hwmod_sysc_type1,
3097 };
3098
3099 static struct omap_hwmod_class omap34xx_mmc_class = {
3100 .name = "mmc",
3101 .sysc = &omap34xx_mmc_sysc,
3102 };
3103
3104 /* MMC/SD/SDIO1 */
3105
3106 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3107 { .irq = 83, },
3108 { .irq = -1 }
3109 };
3110
3111 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3112 { .name = "tx", .dma_req = 61, },
3113 { .name = "rx", .dma_req = 62, },
3114 { .dma_req = -1 }
3115 };
3116
3117 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3118 { .role = "dbck", .clk = "omap_32k_fck", },
3119 };
3120
3121 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3122 &omap3xxx_l4_core__mmc1,
3123 };
3124
3125 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3126 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3127 };
3128
3129 /* See 35xx errata 2.1.1.128 in SPRZ278F */
3130 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
3131 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
3132 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
3133 };
3134
3135 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
3136 .name = "mmc1",
3137 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3138 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
3139 .opt_clks = omap34xx_mmc1_opt_clks,
3140 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3141 .main_clk = "mmchs1_fck",
3142 .prcm = {
3143 .omap2 = {
3144 .module_offs = CORE_MOD,
3145 .prcm_reg_id = 1,
3146 .module_bit = OMAP3430_EN_MMC1_SHIFT,
3147 .idlest_reg_id = 1,
3148 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3149 },
3150 },
3151 .dev_attr = &mmc1_pre_es3_dev_attr,
3152 .slaves = omap3xxx_mmc1_slaves,
3153 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3154 .class = &omap34xx_mmc_class,
3155 };
3156
3157 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
3158 .name = "mmc1",
3159 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3160 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
3161 .opt_clks = omap34xx_mmc1_opt_clks,
3162 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3163 .main_clk = "mmchs1_fck",
3164 .prcm = {
3165 .omap2 = {
3166 .module_offs = CORE_MOD,
3167 .prcm_reg_id = 1,
3168 .module_bit = OMAP3430_EN_MMC1_SHIFT,
3169 .idlest_reg_id = 1,
3170 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3171 },
3172 },
3173 .dev_attr = &mmc1_dev_attr,
3174 .slaves = omap3xxx_mmc1_slaves,
3175 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3176 .class = &omap34xx_mmc_class,
3177 };
3178
3179 /* MMC/SD/SDIO2 */
3180
3181 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3182 { .irq = INT_24XX_MMC2_IRQ, },
3183 { .irq = -1 }
3184 };
3185
3186 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3187 { .name = "tx", .dma_req = 47, },
3188 { .name = "rx", .dma_req = 48, },
3189 { .dma_req = -1 }
3190 };
3191
3192 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3193 { .role = "dbck", .clk = "omap_32k_fck", },
3194 };
3195
3196 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3197 &omap3xxx_l4_core__mmc2,
3198 };
3199
3200 /* See 35xx errata 2.1.1.128 in SPRZ278F */
3201 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
3202 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
3203 };
3204
3205 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
3206 .name = "mmc2",
3207 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3208 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
3209 .opt_clks = omap34xx_mmc2_opt_clks,
3210 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3211 .main_clk = "mmchs2_fck",
3212 .prcm = {
3213 .omap2 = {
3214 .module_offs = CORE_MOD,
3215 .prcm_reg_id = 1,
3216 .module_bit = OMAP3430_EN_MMC2_SHIFT,
3217 .idlest_reg_id = 1,
3218 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3219 },
3220 },
3221 .dev_attr = &mmc2_pre_es3_dev_attr,
3222 .slaves = omap3xxx_mmc2_slaves,
3223 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3224 .class = &omap34xx_mmc_class,
3225 };
3226
3227 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
3228 .name = "mmc2",
3229 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3230 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
3231 .opt_clks = omap34xx_mmc2_opt_clks,
3232 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3233 .main_clk = "mmchs2_fck",
3234 .prcm = {
3235 .omap2 = {
3236 .module_offs = CORE_MOD,
3237 .prcm_reg_id = 1,
3238 .module_bit = OMAP3430_EN_MMC2_SHIFT,
3239 .idlest_reg_id = 1,
3240 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3241 },
3242 },
3243 .slaves = omap3xxx_mmc2_slaves,
3244 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3245 .class = &omap34xx_mmc_class,
3246 };
3247
3248 /* MMC/SD/SDIO3 */
3249
3250 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3251 { .irq = 94, },
3252 { .irq = -1 }
3253 };
3254
3255 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3256 { .name = "tx", .dma_req = 77, },
3257 { .name = "rx", .dma_req = 78, },
3258 { .dma_req = -1 }
3259 };
3260
3261 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3262 { .role = "dbck", .clk = "omap_32k_fck", },
3263 };
3264
3265 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3266 &omap3xxx_l4_core__mmc3,
3267 };
3268
3269 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3270 .name = "mmc3",
3271 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
3272 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
3273 .opt_clks = omap34xx_mmc3_opt_clks,
3274 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3275 .main_clk = "mmchs3_fck",
3276 .prcm = {
3277 .omap2 = {
3278 .prcm_reg_id = 1,
3279 .module_bit = OMAP3430_EN_MMC3_SHIFT,
3280 .idlest_reg_id = 1,
3281 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3282 },
3283 },
3284 .slaves = omap3xxx_mmc3_slaves,
3285 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3286 .class = &omap34xx_mmc_class,
3287 };
3288
3289 /*
3290 * 'usb_host_hs' class
3291 * high-speed multi-port usb host controller
3292 */
3293 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3294 .master = &omap3xxx_usb_host_hs_hwmod,
3295 .slave = &omap3xxx_l3_main_hwmod,
3296 .clk = "core_l3_ick",
3297 .user = OCP_USER_MPU,
3298 };
3299
3300 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
3301 .rev_offs = 0x0000,
3302 .sysc_offs = 0x0010,
3303 .syss_offs = 0x0014,
3304 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
3305 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
3306 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
3307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3308 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3309 .sysc_fields = &omap_hwmod_sysc_type1,
3310 };
3311
3312 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
3313 .name = "usb_host_hs",
3314 .sysc = &omap3xxx_usb_host_hs_sysc,
3315 };
3316
3317 static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_masters[] = {
3318 &omap3xxx_usb_host_hs__l3_main_2,
3319 };
3320
3321 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3322 {
3323 .name = "uhh",
3324 .pa_start = 0x48064000,
3325 .pa_end = 0x480643ff,
3326 .flags = ADDR_TYPE_RT
3327 },
3328 {
3329 .name = "ohci",
3330 .pa_start = 0x48064400,
3331 .pa_end = 0x480647ff,
3332 },
3333 {
3334 .name = "ehci",
3335 .pa_start = 0x48064800,
3336 .pa_end = 0x48064cff,
3337 },
3338 {}
3339 };
3340
3341 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3342 .master = &omap3xxx_l4_core_hwmod,
3343 .slave = &omap3xxx_usb_host_hs_hwmod,
3344 .clk = "usbhost_ick",
3345 .addr = omap3xxx_usb_host_hs_addrs,
3346 .user = OCP_USER_MPU | OCP_USER_SDMA,
3347 };
3348
3349 static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_slaves[] = {
3350 &omap3xxx_l4_core__usb_host_hs,
3351 };
3352
3353 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
3354 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
3355 };
3356
3357 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
3358 { .name = "ohci-irq", .irq = 76 },
3359 { .name = "ehci-irq", .irq = 77 },
3360 { .irq = -1 }
3361 };
3362
3363 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
3364 .name = "usb_host_hs",
3365 .class = &omap3xxx_usb_host_hs_hwmod_class,
3366 .clkdm_name = "l3_init_clkdm",
3367 .mpu_irqs = omap3xxx_usb_host_hs_irqs,
3368 .main_clk = "usbhost_48m_fck",
3369 .prcm = {
3370 .omap2 = {
3371 .module_offs = OMAP3430ES2_USBHOST_MOD,
3372 .prcm_reg_id = 1,
3373 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
3374 .idlest_reg_id = 1,
3375 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
3376 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
3377 },
3378 },
3379 .opt_clks = omap3xxx_usb_host_hs_opt_clks,
3380 .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
3381 .slaves = omap3xxx_usb_host_hs_slaves,
3382 .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_slaves),
3383 .masters = omap3xxx_usb_host_hs_masters,
3384 .masters_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_masters),
3385
3386 /*
3387 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3388 * id: i660
3389 *
3390 * Description:
3391 * In the following configuration :
3392 * - USBHOST module is set to smart-idle mode
3393 * - PRCM asserts idle_req to the USBHOST module ( This typically
3394 * happens when the system is going to a low power mode : all ports
3395 * have been suspended, the master part of the USBHOST module has
3396 * entered the standby state, and SW has cut the functional clocks)
3397 * - an USBHOST interrupt occurs before the module is able to answer
3398 * idle_ack, typically a remote wakeup IRQ.
3399 * Then the USB HOST module will enter a deadlock situation where it
3400 * is no more accessible nor functional.
3401 *
3402 * Workaround:
3403 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3404 */
3405
3406 /*
3407 * Errata: USB host EHCI may stall when entering smart-standby mode
3408 * Id: i571
3409 *
3410 * Description:
3411 * When the USBHOST module is set to smart-standby mode, and when it is
3412 * ready to enter the standby state (i.e. all ports are suspended and
3413 * all attached devices are in suspend mode), then it can wrongly assert
3414 * the Mstandby signal too early while there are still some residual OCP
3415 * transactions ongoing. If this condition occurs, the internal state
3416 * machine may go to an undefined state and the USB link may be stuck
3417 * upon the next resume.
3418 *
3419 * Workaround:
3420 * Don't use smart standby; use only force standby,
3421 * hence HWMOD_SWSUP_MSTANDBY
3422 */
3423
3424 /*
3425 * During system boot; If the hwmod framework resets the module
3426 * the module will have smart idle settings; which can lead to deadlock
3427 * (above Errata Id:i660); so, dont reset the module during boot;
3428 * Use HWMOD_INIT_NO_RESET.
3429 */
3430
3431 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3432 HWMOD_INIT_NO_RESET,
3433 };
3434
3435 /*
3436 * 'usb_tll_hs' class
3437 * usb_tll_hs module is the adapter on the usb_host_hs ports
3438 */
3439 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
3440 .rev_offs = 0x0000,
3441 .sysc_offs = 0x0010,
3442 .syss_offs = 0x0014,
3443 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3444 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3445 SYSC_HAS_AUTOIDLE),
3446 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3447 .sysc_fields = &omap_hwmod_sysc_type1,
3448 };
3449
3450 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
3451 .name = "usb_tll_hs",
3452 .sysc = &omap3xxx_usb_tll_hs_sysc,
3453 };
3454
3455 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
3456 { .name = "tll-irq", .irq = 78 },
3457 { .irq = -1 }
3458 };
3459
3460 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3461 {
3462 .name = "tll",
3463 .pa_start = 0x48062000,
3464 .pa_end = 0x48062fff,
3465 .flags = ADDR_TYPE_RT
3466 },
3467 {}
3468 };
3469
3470 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3471 .master = &omap3xxx_l4_core_hwmod,
3472 .slave = &omap3xxx_usb_tll_hs_hwmod,
3473 .clk = "usbtll_ick",
3474 .addr = omap3xxx_usb_tll_hs_addrs,
3475 .user = OCP_USER_MPU | OCP_USER_SDMA,
3476 };
3477
3478 static struct omap_hwmod_ocp_if *omap3xxx_usb_tll_hs_slaves[] = {
3479 &omap3xxx_l4_core__usb_tll_hs,
3480 };
3481
3482 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
3483 .name = "usb_tll_hs",
3484 .class = &omap3xxx_usb_tll_hs_hwmod_class,
3485 .clkdm_name = "l3_init_clkdm",
3486 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
3487 .main_clk = "usbtll_fck",
3488 .prcm = {
3489 .omap2 = {
3490 .module_offs = CORE_MOD,
3491 .prcm_reg_id = 3,
3492 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
3493 .idlest_reg_id = 3,
3494 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
3495 },
3496 },
3497 .slaves = omap3xxx_usb_tll_hs_slaves,
3498 .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_tll_hs_slaves),
3499 };
3500
3501 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3502 &omap3xxx_l3_main_hwmod,
3503 &omap3xxx_l4_core_hwmod,
3504 &omap3xxx_l4_per_hwmod,
3505 &omap3xxx_l4_wkup_hwmod,
3506 &omap3xxx_mmc3_hwmod,
3507 &omap3xxx_mpu_hwmod,
3508
3509 &omap3xxx_timer1_hwmod,
3510 &omap3xxx_timer2_hwmod,
3511 &omap3xxx_timer3_hwmod,
3512 &omap3xxx_timer4_hwmod,
3513 &omap3xxx_timer5_hwmod,
3514 &omap3xxx_timer6_hwmod,
3515 &omap3xxx_timer7_hwmod,
3516 &omap3xxx_timer8_hwmod,
3517 &omap3xxx_timer9_hwmod,
3518 &omap3xxx_timer10_hwmod,
3519 &omap3xxx_timer11_hwmod,
3520
3521 &omap3xxx_wd_timer2_hwmod,
3522 &omap3xxx_uart1_hwmod,
3523 &omap3xxx_uart2_hwmod,
3524 &omap3xxx_uart3_hwmod,
3525
3526 /* dss class */
3527 &omap3xxx_dss_dispc_hwmod,
3528 &omap3xxx_dss_dsi1_hwmod,
3529 &omap3xxx_dss_rfbi_hwmod,
3530 &omap3xxx_dss_venc_hwmod,
3531
3532 /* i2c class */
3533 &omap3xxx_i2c1_hwmod,
3534 &omap3xxx_i2c2_hwmod,
3535 &omap3xxx_i2c3_hwmod,
3536
3537 /* gpio class */
3538 &omap3xxx_gpio1_hwmod,
3539 &omap3xxx_gpio2_hwmod,
3540 &omap3xxx_gpio3_hwmod,
3541 &omap3xxx_gpio4_hwmod,
3542 &omap3xxx_gpio5_hwmod,
3543 &omap3xxx_gpio6_hwmod,
3544
3545 /* dma_system class*/
3546 &omap3xxx_dma_system_hwmod,
3547
3548 /* mcbsp class */
3549 &omap3xxx_mcbsp1_hwmod,
3550 &omap3xxx_mcbsp2_hwmod,
3551 &omap3xxx_mcbsp3_hwmod,
3552 &omap3xxx_mcbsp4_hwmod,
3553 &omap3xxx_mcbsp5_hwmod,
3554 &omap3xxx_mcbsp2_sidetone_hwmod,
3555 &omap3xxx_mcbsp3_sidetone_hwmod,
3556
3557
3558 /* mcspi class */
3559 &omap34xx_mcspi1,
3560 &omap34xx_mcspi2,
3561 &omap34xx_mcspi3,
3562 &omap34xx_mcspi4,
3563
3564 NULL,
3565 };
3566
3567 /* GP-only hwmods */
3568 static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = {
3569 &omap3xxx_timer12_hwmod,
3570 NULL
3571 };
3572
3573 /* 3430ES1-only hwmods */
3574 static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
3575 &omap3430es1_dss_core_hwmod,
3576 NULL
3577 };
3578
3579 /* 3430ES2+-only hwmods */
3580 static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
3581 &omap3xxx_dss_core_hwmod,
3582 &omap3xxx_usbhsotg_hwmod,
3583 &omap3xxx_usb_host_hs_hwmod,
3584 &omap3xxx_usb_tll_hs_hwmod,
3585 NULL
3586 };
3587
3588 /* <= 3430ES3-only hwmods */
3589 static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = {
3590 &omap3xxx_pre_es3_mmc1_hwmod,
3591 &omap3xxx_pre_es3_mmc2_hwmod,
3592 NULL
3593 };
3594
3595 /* 3430ES3+-only hwmods */
3596 static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = {
3597 &omap3xxx_es3plus_mmc1_hwmod,
3598 &omap3xxx_es3plus_mmc2_hwmod,
3599 NULL
3600 };
3601
3602 /* 34xx-only hwmods (all ES revisions) */
3603 static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
3604 &omap3xxx_iva_hwmod,
3605 &omap34xx_sr1_hwmod,
3606 &omap34xx_sr2_hwmod,
3607 &omap3xxx_mailbox_hwmod,
3608 NULL
3609 };
3610
3611 /* 36xx-only hwmods (all ES revisions) */
3612 static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
3613 &omap3xxx_iva_hwmod,
3614 &omap3xxx_uart4_hwmod,
3615 &omap3xxx_dss_core_hwmod,
3616 &omap36xx_sr1_hwmod,
3617 &omap36xx_sr2_hwmod,
3618 &omap3xxx_usbhsotg_hwmod,
3619 &omap3xxx_mailbox_hwmod,
3620 &omap3xxx_usb_host_hs_hwmod,
3621 &omap3xxx_usb_tll_hs_hwmod,
3622 &omap3xxx_es3plus_mmc1_hwmod,
3623 &omap3xxx_es3plus_mmc2_hwmod,
3624 NULL
3625 };
3626
3627 static __initdata struct omap_hwmod *am35xx_hwmods[] = {
3628 &omap3xxx_dss_core_hwmod, /* XXX ??? */
3629 &am35xx_usbhsotg_hwmod,
3630 &am35xx_uart4_hwmod,
3631 &omap3xxx_usb_host_hs_hwmod,
3632 &omap3xxx_usb_tll_hs_hwmod,
3633 &omap3xxx_es3plus_mmc1_hwmod,
3634 &omap3xxx_es3plus_mmc2_hwmod,
3635 NULL
3636 };
3637
3638 int __init omap3xxx_hwmod_init(void)
3639 {
3640 int r;
3641 struct omap_hwmod **h = NULL;
3642 unsigned int rev;
3643
3644 /* Register hwmods common to all OMAP3 */
3645 r = omap_hwmod_register(omap3xxx_hwmods);
3646 if (r < 0)
3647 return r;
3648
3649 /* Register GP-only hwmods. */
3650 if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3651 r = omap_hwmod_register(omap3xxx_gp_hwmods);
3652 if (r < 0)
3653 return r;
3654 }
3655
3656 rev = omap_rev();
3657
3658 /*
3659 * Register hwmods common to individual OMAP3 families, all
3660 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3661 * All possible revisions should be included in this conditional.
3662 */
3663 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3664 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3665 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3666 h = omap34xx_hwmods;
3667 } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) {
3668 h = am35xx_hwmods;
3669 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3670 rev == OMAP3630_REV_ES1_2) {
3671 h = omap36xx_hwmods;
3672 } else {
3673 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3674 return -EINVAL;
3675 };
3676
3677 r = omap_hwmod_register(h);
3678 if (r < 0)
3679 return r;
3680
3681 /*
3682 * Register hwmods specific to certain ES levels of a
3683 * particular family of silicon (e.g., 34xx ES1.0)
3684 */
3685 h = NULL;
3686 if (rev == OMAP3430_REV_ES1_0) {
3687 h = omap3430es1_hwmods;
3688 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3689 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3690 rev == OMAP3430_REV_ES3_1_2) {
3691 h = omap3430es2plus_hwmods;
3692 };
3693
3694 if (h) {
3695 r = omap_hwmod_register(h);
3696 if (r < 0)
3697 return r;
3698 }
3699
3700 h = NULL;
3701 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3702 rev == OMAP3430_REV_ES2_1) {
3703 h = omap3430_pre_es3_hwmods;
3704 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3705 rev == OMAP3430_REV_ES3_1_2) {
3706 h = omap3430_es3plus_hwmods;
3707 };
3708
3709 if (h)
3710 r = omap_hwmod_register(h);
3711
3712 return r;
3713 }