arch/arm/mach-omap2/pm24xx.c

   1 /*
   2  * OMAP2 Power Management Routines
   3  *
   4  * Copyright (C) 2005 Texas Instruments, Inc.
   5  * Copyright (C) 2006-2008 Nokia Corporation
   6  *
   7  * Written by:
   8  * Richard Woodruff <r-woodruff2@ti.com>
   9  * Tony Lindgren
  10  * Juha Yrjola
  11  * Amit Kucheria <amit.kucheria@nokia.com>
  12  * Igor Stoppa <igor.stoppa@nokia.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/suspend.h>
  22 #include <linux/sched.h>
  23 #include <linux/proc_fs.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/sysfs.h>
  26 #include <linux/module.h>
  27 #include <linux/delay.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/irq.h>
  31 #include <linux/time.h>
  32 #include <linux/gpio.h>
  33
  34 #include <asm/mach/time.h>
  35 #include <asm/mach/irq.h>
  36 #include <asm/mach-types.h>
  37
  38 #include <mach/irqs.h>
  39 #include <plat/clock.h>
  40 #include <plat/sram.h>
  41 #include <plat/dma.h>
  42 #include <plat/board.h>
  43
  44 #include "common.h"
  45 #include "prm2xxx_3xxx.h"
  46 #include "prm-regbits-24xx.h"
  47 #include "cm2xxx_3xxx.h"
  48 #include "cm-regbits-24xx.h"
  49 #include "sdrc.h"
  50 #include "pm.h"
  51 #include "control.h"
  52
  53 #include "powerdomain.h"
  54 #include "clockdomain.h"
  55
  56 #ifdef CONFIG_SUSPEND
  57 static suspend_state_t suspend_state = PM_SUSPEND_ON;
  58 static inline bool is_suspending(void)
  59 {
  60         return (suspend_state != PM_SUSPEND_ON);
  61 }
  62 #else
  63 static inline bool is_suspending(void)
  64 {
  65         return false;
  66 }
  67 #endif
  68
  69 static void (*omap2_sram_idle)(void);
  70 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
  71                                   void __iomem *sdrc_power);
  72
  73 static struct powerdomain *mpu_pwrdm, *core_pwrdm;
  74 static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
  75
  76 static struct clk *osc_ck, *emul_ck;
  77
  78 static int omap2_fclks_active(void)
  79 {
  80         u32 f1, f2;
  81
  82         f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  83         f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
  84
  85         /* Ignore UART clocks.  These are handled by UART core (serial.c) */
  86         f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK);
  87         f2 &= ~OMAP24XX_EN_UART3_MASK;
  88
  89         if (f1 | f2)
  90                 return 1;
  91         return 0;
  92 }
  93
  94 static void omap2_enter_full_retention(void)
  95 {
  96         u32 l;
  97
  98         /* There is 1 reference hold for all children of the oscillator
  99          * clock, the following will remove it. If no one else uses the
 100          * oscillator itself it will be disabled if/when we enter retention
 101          * mode.
 102          */
 103         clk_disable(osc_ck);
 104
 105         /* Clear old wake-up events */
 106         /* REVISIT: These write to reserved bits? */
 107         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 108         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 109         omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 110
 111         /*
 112          * Set MPU powerdomain's next power state to RETENTION;
 113          * preserve logic state during retention
 114          */
 115         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 116         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 117
 118         /* Workaround to kill USB */
 119         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
 120         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
 121
 122         omap2_gpio_prepare_for_idle(0);
 123
 124         /* One last check for pending IRQs to avoid extra latency due
 125          * to sleeping unnecessarily. */
 126         if (omap_irq_pending())
 127                 goto no_sleep;
 128
 129         /* Jump to SRAM suspend code */
 130         omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
 131                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
 132                            OMAP_SDRC_REGADDR(SDRC_POWER));
 133
 134 no_sleep:
 135         omap2_gpio_resume_after_idle();
 136
 137         clk_enable(osc_ck);
 138
 139         /* clear CORE wake-up events */
 140         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 141         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 142
 143         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
 144         omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
 145
 146         /* MPU domain wake events */
 147         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 148         if (l & 0x01)
 149                 omap2_prm_write_mod_reg(0x01, OCP_MOD,
 150                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 151         if (l & 0x20)
 152                 omap2_prm_write_mod_reg(0x20, OCP_MOD,
 153                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 154
 155         /* Mask future PRCM-to-MPU interrupts */
 156         omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 157 }
 158
 159 static int omap2_i2c_active(void)
 160 {
 161         u32 l;
 162
 163         l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 164         return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
 165 }
 166
 167 static int sti_console_enabled;
 168
 169 static int omap2_allow_mpu_retention(void)
 170 {
 171         u32 l;
 172
 173         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
 174         l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 175         if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
 176                  OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
 177                  OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
 178                 return 0;
 179         /* Check for UART3. */
 180         l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 181         if (l & OMAP24XX_EN_UART3_MASK)
 182                 return 0;
 183         if (sti_console_enabled)
 184                 return 0;
 185
 186         return 1;
 187 }
 188
 189 static void omap2_enter_mpu_retention(void)
 190 {
 191         int only_idle = 0;
 192
 193         /* Putting MPU into the WFI state while a transfer is active
 194          * seems to cause the I2C block to timeout. Why? Good question. */
 195         if (omap2_i2c_active())
 196                 return;
 197
 198         /* The peripherals seem not to be able to wake up the MPU when
 199          * it is in retention mode. */
 200         if (omap2_allow_mpu_retention()) {
 201                 /* REVISIT: These write to reserved bits? */
 202                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 203                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 204                 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 205
 206                 /* Try to enter MPU retention */
 207                 omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 208                                   OMAP_LOGICRETSTATE_MASK,
 209                                   MPU_MOD, OMAP2_PM_PWSTCTRL);
 210         } else {
 211                 /* Block MPU retention */
 212
 213                 omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
 214                                                  OMAP2_PM_PWSTCTRL);
 215                 only_idle = 1;
 216         }
 217
 218         omap2_sram_idle();
 219 }
 220
 221 static int omap2_can_sleep(void)
 222 {
 223         if (omap2_fclks_active())
 224                 return 0;
 225         if (osc_ck->usecount > 1)
 226                 return 0;
 227         if (omap_dma_running())
 228                 return 0;
 229
 230         return 1;
 231 }
 232
 233 static void omap2_pm_idle(void)
 234 {
 235         local_irq_disable();
 236         local_fiq_disable();
 237
 238         if (!omap2_can_sleep()) {
 239                 if (omap_irq_pending())
 240                         goto out;
 241                 omap2_enter_mpu_retention();
 242                 goto out;
 243         }
 244
 245         if (omap_irq_pending())
 246                 goto out;
 247
 248         omap2_enter_full_retention();
 249
 250 out:
 251         local_fiq_enable();
 252         local_irq_enable();
 253 }
 254
 255 #ifdef CONFIG_SUSPEND
 256 static int omap2_pm_begin(suspend_state_t state)
 257 {
 258         disable_hlt();
 259         suspend_state = state;
 260         return 0;
 261 }
 262
 263 static int omap2_pm_suspend(void)
 264 {
 265         u32 wken_wkup, mir1;
 266
 267         wken_wkup = omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 268         wken_wkup &= ~OMAP24XX_EN_GPT1_MASK;
 269         omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 270
 271         /* Mask GPT1 */
 272         mir1 = omap_readl(0x480fe0a4);
 273         omap_writel(1 << 5, 0x480fe0ac);
 274
 275         omap2_enter_full_retention();
 276
 277         omap_writel(mir1, 0x480fe0a4);
 278         omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 279
 280         return 0;
 281 }
 282
 283 static int omap2_pm_enter(suspend_state_t state)
 284 {
 285         int ret = 0;
 286
 287         switch (state) {
 288         case PM_SUSPEND_STANDBY:
 289         case PM_SUSPEND_MEM:
 290                 ret = omap2_pm_suspend();
 291                 break;
 292         default:
 293                 ret = -EINVAL;
 294         }
 295
 296         return ret;
 297 }
 298
 299 static void omap2_pm_end(void)
 300 {
 301         suspend_state = PM_SUSPEND_ON;
 302         enable_hlt();
 303 }
 304
 305 static const struct platform_suspend_ops omap_pm_ops = {
 306         .begin          = omap2_pm_begin,
 307         .enter          = omap2_pm_enter,
 308         .end            = omap2_pm_end,
 309         .valid          = suspend_valid_only_mem,
 310 };
 311 #else
 312 static const struct platform_suspend_ops __initdata omap_pm_ops;
 313 #endif /* CONFIG_SUSPEND */
 314
 315 /* XXX This function should be shareable between OMAP2xxx and OMAP3 */
 316 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 317 {
 318         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 319                 clkdm_allow_idle(clkdm);
 320         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 321                  atomic_read(&clkdm->usecount) == 0)
 322                 clkdm_sleep(clkdm);
 323         return 0;
 324 }
 325
 326 static void __init prcm_setup_regs(void)
 327 {
 328         int i, num_mem_banks;
 329         struct powerdomain *pwrdm;
 330
 331         /*
 332          * Enable autoidle
 333          * XXX This should be handled by hwmod code or PRCM init code
 334          */
 335         omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
 336                           OMAP2_PRCM_SYSCONFIG_OFFSET);
 337
 338         /*
 339          * Set CORE powerdomain memory banks to retain their contents
 340          * during RETENTION
 341          */
 342         num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
 343         for (i = 0; i < num_mem_banks; i++)
 344                 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
 345
 346         /* Set CORE powerdomain's next power state to RETENTION */
 347         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
 348
 349         /*
 350          * Set MPU powerdomain's next power state to RETENTION;
 351          * preserve logic state during retention
 352          */
 353         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 354         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 355
 356         /* Force-power down DSP, GFX powerdomains */
 357
 358         pwrdm = clkdm_get_pwrdm(dsp_clkdm);
 359         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 360         clkdm_sleep(dsp_clkdm);
 361
 362         pwrdm = clkdm_get_pwrdm(gfx_clkdm);
 363         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 364         clkdm_sleep(gfx_clkdm);
 365
 366         /* Enable hardware-supervised idle for all clkdms */
 367         clkdm_for_each(clkdms_setup, NULL);
 368         clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
 369
 370         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 371          * stabilisation */
 372         omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 373                                 OMAP2_PRCM_CLKSSETUP_OFFSET);
 374
 375         /* Configure automatic voltage transition */
 376         omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 377                                 OMAP2_PRCM_VOLTSETUP_OFFSET);
 378         omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
 379                                 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
 380                                 OMAP24XX_MEMRETCTRL_MASK |
 381                                 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
 382                                 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
 383                                 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
 384
 385         /* Enable wake-up events */
 386         omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
 387                                 WKUP_MOD, PM_WKEN);
 388 }
 389
 390 static int __init omap2_pm_init(void)
 391 {
 392         u32 l;
 393
 394         if (!cpu_is_omap24xx())
 395                 return -ENODEV;
 396
 397         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 398         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
 399         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 400
 401         /* Look up important powerdomains */
 402
 403         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 404         if (!mpu_pwrdm)
 405                 pr_err("PM: mpu_pwrdm not found\n");
 406
 407         core_pwrdm = pwrdm_lookup("core_pwrdm");
 408         if (!core_pwrdm)
 409                 pr_err("PM: core_pwrdm not found\n");
 410
 411         /* Look up important clockdomains */
 412
 413         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 414         if (!mpu_clkdm)
 415                 pr_err("PM: mpu_clkdm not found\n");
 416
 417         wkup_clkdm = clkdm_lookup("wkup_clkdm");
 418         if (!wkup_clkdm)
 419                 pr_err("PM: wkup_clkdm not found\n");
 420
 421         dsp_clkdm = clkdm_lookup("dsp_clkdm");
 422         if (!dsp_clkdm)
 423                 pr_err("PM: dsp_clkdm not found\n");
 424
 425         gfx_clkdm = clkdm_lookup("gfx_clkdm");
 426         if (!gfx_clkdm)
 427                 pr_err("PM: gfx_clkdm not found\n");
 428
 429
 430         osc_ck = clk_get(NULL, "osc_ck");
 431         if (IS_ERR(osc_ck)) {
 432                 printk(KERN_ERR "could not get osc_ck\n");
 433                 return -ENODEV;
 434         }
 435
 436         if (cpu_is_omap242x()) {
 437                 emul_ck = clk_get(NULL, "emul_ck");
 438                 if (IS_ERR(emul_ck)) {
 439                         printk(KERN_ERR "could not get emul_ck\n");
 440                         clk_put(osc_ck);
 441                         return -ENODEV;
 442                 }
 443         }
 444
 445         prcm_setup_regs();
 446
 447         /* Hack to prevent MPU retention when STI console is enabled. */
 448         {
 449                 const struct omap_sti_console_config *sti;
 450
 451                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 452                                       struct omap_sti_console_config);
 453                 if (sti != NULL && sti->enable)
 454                         sti_console_enabled = 1;
 455         }
 456
 457         /*
 458          * We copy the assembler sleep/wakeup routines to SRAM.
 459          * These routines need to be in SRAM as that's the only
 460          * memory the MPU can see when it wakes up.
 461          */
 462         if (cpu_is_omap24xx()) {
 463                 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 464                                                  omap24xx_idle_loop_suspend_sz);
 465
 466                 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 467                                                     omap24xx_cpu_suspend_sz);
 468         }
 469
 470         suspend_set_ops(&omap_pm_ops);
 471         pm_idle = omap2_pm_idle;
 472
 473         return 0;
 474 }
 475
 476 late_initcall(omap2_pm_init);