arch/arm/mach-orion5x/common.c

   1 /*
   2  * arch/arm/mach-orion5x/common.c
   3  *
   4  * Core functions for Marvell Orion 5x SoCs
   5  *
   6  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/serial_8250.h>
  18 #include <linux/mv643xx_i2c.h>
  19 #include <linux/ata_platform.h>
  20 #include <linux/delay.h>
  21 #include <net/dsa.h>
  22 #include <asm/page.h>
  23 #include <asm/setup.h>
  24 #include <asm/timex.h>
  25 #include <asm/mach/arch.h>
  26 #include <asm/mach/map.h>
  27 #include <asm/mach/time.h>
  28 #include <mach/bridge-regs.h>
  29 #include <mach/hardware.h>
  30 #include <mach/orion5x.h>
  31 #include <plat/orion_nand.h>
  32 #include <plat/time.h>
  33 #include <plat/common.h>
  34 #include <plat/addr-map.h>
  35 #include "common.h"
  36
  37 /*****************************************************************************
  38  * I/O Address Mapping
  39  ****************************************************************************/
  40 static struct map_desc orion5x_io_desc[] __initdata = {
  41         {
  42                 .virtual        = ORION5X_REGS_VIRT_BASE,
  43                 .pfn            = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
  44                 .length         = ORION5X_REGS_SIZE,
  45                 .type           = MT_DEVICE,
  46         }, {
  47                 .virtual        = ORION5X_PCIE_IO_VIRT_BASE,
  48                 .pfn            = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
  49                 .length         = ORION5X_PCIE_IO_SIZE,
  50                 .type           = MT_DEVICE,
  51         }, {
  52                 .virtual        = ORION5X_PCI_IO_VIRT_BASE,
  53                 .pfn            = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
  54                 .length         = ORION5X_PCI_IO_SIZE,
  55                 .type           = MT_DEVICE,
  56         }, {
  57                 .virtual        = ORION5X_PCIE_WA_VIRT_BASE,
  58                 .pfn            = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
  59                 .length         = ORION5X_PCIE_WA_SIZE,
  60                 .type           = MT_DEVICE,
  61         },
  62 };
  63
  64 void __init orion5x_map_io(void)
  65 {
  66         iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
  67 }
  68
  69
  70 /*****************************************************************************
  71  * EHCI0
  72  ****************************************************************************/
  73 void __init orion5x_ehci0_init(void)
  74 {
  75         orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL);
  76 }
  77
  78
  79 /*****************************************************************************
  80  * EHCI1
  81  ****************************************************************************/
  82 void __init orion5x_ehci1_init(void)
  83 {
  84         orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
  85 }
  86
  87
  88 /*****************************************************************************
  89  * GE00
  90  ****************************************************************************/
  91 void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
  92 {
  93         orion_ge00_init(eth_data,
  94                         ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
  95                         IRQ_ORION5X_ETH_ERR, orion5x_tclk);
  96 }
  97
  98
  99 /*****************************************************************************
 100  * Ethernet switch
 101  ****************************************************************************/
 102 void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
 103 {
 104         orion_ge00_switch_init(d, irq);
 105 }
 106
 107
 108 /*****************************************************************************
 109  * I2C
 110  ****************************************************************************/
 111 void __init orion5x_i2c_init(void)
 112 {
 113         orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
 114
 115 }
 116
 117
 118 /*****************************************************************************
 119  * SATA
 120  ****************************************************************************/
 121 void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
 122 {
 123         orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
 124 }
 125
 126
 127 /*****************************************************************************
 128  * SPI
 129  ****************************************************************************/
 130 void __init orion5x_spi_init()
 131 {
 132         orion_spi_init(SPI_PHYS_BASE, orion5x_tclk);
 133 }
 134
 135
 136 /*****************************************************************************
 137  * UART0
 138  ****************************************************************************/
 139 void __init orion5x_uart0_init(void)
 140 {
 141         orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
 142                          IRQ_ORION5X_UART0, orion5x_tclk);
 143 }
 144
 145 /*****************************************************************************
 146  * UART1
 147  ****************************************************************************/
 148 void __init orion5x_uart1_init(void)
 149 {
 150         orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
 151                          IRQ_ORION5X_UART1, orion5x_tclk);
 152 }
 153
 154 /*****************************************************************************
 155  * XOR engine
 156  ****************************************************************************/
 157 void __init orion5x_xor_init(void)
 158 {
 159         orion_xor0_init(ORION5X_XOR_PHYS_BASE,
 160                         ORION5X_XOR_PHYS_BASE + 0x200,
 161                         IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
 162 }
 163
 164 /*****************************************************************************
 165  * Cryptographic Engines and Security Accelerator (CESA)
 166  ****************************************************************************/
 167 static void __init orion5x_crypto_init(void)
 168 {
 169         orion5x_setup_sram_win();
 170         orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
 171                           SZ_8K, IRQ_ORION5X_CESA);
 172 }
 173
 174 /*****************************************************************************
 175  * Watchdog
 176  ****************************************************************************/
 177 void __init orion5x_wdt_init(void)
 178 {
 179         orion_wdt_init(orion5x_tclk);
 180 }
 181
 182
 183 /*****************************************************************************
 184  * Time handling
 185  ****************************************************************************/
 186 void __init orion5x_init_early(void)
 187 {
 188         orion_time_set_base(TIMER_VIRT_BASE);
 189 }
 190
 191 int orion5x_tclk;
 192
 193 int __init orion5x_find_tclk(void)
 194 {
 195         u32 dev, rev;
 196
 197         orion5x_pcie_id(&dev, &rev);
 198         if (dev == MV88F6183_DEV_ID &&
 199             (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
 200                 return 133333333;
 201
 202         return 166666667;
 203 }
 204
 205 static void orion5x_timer_init(void)
 206 {
 207         orion5x_tclk = orion5x_find_tclk();
 208
 209         orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
 210                         IRQ_ORION5X_BRIDGE, orion5x_tclk);
 211 }
 212
 213 struct sys_timer orion5x_timer = {
 214         .init = orion5x_timer_init,
 215 };
 216
 217
 218 /*****************************************************************************
 219  * General
 220  ****************************************************************************/
 221 /*
 222  * Identify device ID and rev from PCIe configuration header space '0'.
 223  */
 224 static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
 225 {
 226         orion5x_pcie_id(dev, rev);
 227
 228         if (*dev == MV88F5281_DEV_ID) {
 229                 if (*rev == MV88F5281_REV_D2) {
 230                         *dev_name = "MV88F5281-D2";
 231                 } else if (*rev == MV88F5281_REV_D1) {
 232                         *dev_name = "MV88F5281-D1";
 233                 } else if (*rev == MV88F5281_REV_D0) {
 234                         *dev_name = "MV88F5281-D0";
 235                 } else {
 236                         *dev_name = "MV88F5281-Rev-Unsupported";
 237                 }
 238         } else if (*dev == MV88F5182_DEV_ID) {
 239                 if (*rev == MV88F5182_REV_A2) {
 240                         *dev_name = "MV88F5182-A2";
 241                 } else {
 242                         *dev_name = "MV88F5182-Rev-Unsupported";
 243                 }
 244         } else if (*dev == MV88F5181_DEV_ID) {
 245                 if (*rev == MV88F5181_REV_B1) {
 246                         *dev_name = "MV88F5181-Rev-B1";
 247                 } else if (*rev == MV88F5181L_REV_A1) {
 248                         *dev_name = "MV88F5181L-Rev-A1";
 249                 } else {
 250                         *dev_name = "MV88F5181(L)-Rev-Unsupported";
 251                 }
 252         } else if (*dev == MV88F6183_DEV_ID) {
 253                 if (*rev == MV88F6183_REV_B0) {
 254                         *dev_name = "MV88F6183-Rev-B0";
 255                 } else {
 256                         *dev_name = "MV88F6183-Rev-Unsupported";
 257                 }
 258         } else {
 259                 *dev_name = "Device-Unknown";
 260         }
 261 }
 262
 263 void __init orion5x_init(void)
 264 {
 265         char *dev_name;
 266         u32 dev, rev;
 267
 268         orion5x_id(&dev, &rev, &dev_name);
 269         printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
 270
 271         /*
 272          * Setup Orion address map
 273          */
 274         orion5x_setup_cpu_mbus_bridge();
 275
 276         /*
 277          * Don't issue "Wait for Interrupt" instruction if we are
 278          * running on D0 5281 silicon.
 279          */
 280         if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
 281                 printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
 282                 disable_hlt();
 283         }
 284
 285         /*
 286          * The 5082/5181l/5182/6082/6082l/6183 have crypto
 287          * while 5180n/5181/5281 don't have crypto.
 288          */
 289         if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
 290             dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
 291                 orion5x_crypto_init();
 292
 293         /*
 294          * Register watchdog driver
 295          */
 296         orion5x_wdt_init();
 297 }
 298
 299 void orion5x_restart(char mode, const char *cmd)
 300 {
 301         /*
 302          * Enable and issue soft reset
 303          */
 304         orion5x_setbits(RSTOUTn_MASK, (1 << 2));
 305         orion5x_setbits(CPU_SOFT_RESET, 1);
 306         mdelay(200);
 307         orion5x_clrbits(CPU_SOFT_RESET, 1);
 308 }
 309
 310 /*
 311  * Many orion-based systems have buggy bootloader implementations.
 312  * This is a common fixup for bogus memory tags.
 313  */
 314 void __init tag_fixup_mem32(struct tag *t, char **from,
 315                             struct meminfo *meminfo)
 316 {
 317         for (; t->hdr.size; t = tag_next(t))
 318                 if (t->hdr.tag == ATAG_MEM &&
 319                     (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
 320                      t->u.mem.start & ~PAGE_MASK)) {
 321                         printk(KERN_WARNING
 322                                "Clearing invalid memory bank %dKB@0x%08x\n",
 323                                t->u.mem.size / 1024, t->u.mem.start);
 324                         t->hdr.tag = 0;
 325                 }
 326 }