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sfc: Get port number from CS_PORT_NUM, not PCI function number
[zen-stable.git] / drivers / mmc / host / sdhci.c
blobc6d1bd8d4ac43d917e2772f2242dcdea03aa6040
1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/scatterlist.h>
22
23 #include <linux/leds.h>
24
25 #include <linux/mmc/host.h>
26
27 #include "sdhci.h"
28
29 #define DRIVER_NAME "sdhci"
30
31 #define DBG(f, x...) \
32 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
33
34 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
35 defined(CONFIG_MMC_SDHCI_MODULE))
36 #define SDHCI_USE_LEDS_CLASS
37 #endif
38
39 static unsigned int debug_quirks = 0;
40
41 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
42 static void sdhci_finish_data(struct sdhci_host *);
43
44 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
45 static void sdhci_finish_command(struct sdhci_host *);
46
47 static void sdhci_dumpregs(struct sdhci_host *host)
48 {
49 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
50
51 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
52 sdhci_readl(host, SDHCI_DMA_ADDRESS),
53 sdhci_readw(host, SDHCI_HOST_VERSION));
54 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
55 sdhci_readw(host, SDHCI_BLOCK_SIZE),
56 sdhci_readw(host, SDHCI_BLOCK_COUNT));
57 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
58 sdhci_readl(host, SDHCI_ARGUMENT),
59 sdhci_readw(host, SDHCI_TRANSFER_MODE));
60 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
61 sdhci_readl(host, SDHCI_PRESENT_STATE),
62 sdhci_readb(host, SDHCI_HOST_CONTROL));
63 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
64 sdhci_readb(host, SDHCI_POWER_CONTROL),
65 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
66 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
67 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
68 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
69 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
70 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
71 sdhci_readl(host, SDHCI_INT_STATUS));
72 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
73 sdhci_readl(host, SDHCI_INT_ENABLE),
74 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
75 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
76 sdhci_readw(host, SDHCI_ACMD12_ERR),
77 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
78 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
79 sdhci_readl(host, SDHCI_CAPABILITIES),
80 sdhci_readl(host, SDHCI_MAX_CURRENT));
81
82 if (host->flags & SDHCI_USE_ADMA)
83 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
84 readl(host->ioaddr + SDHCI_ADMA_ERROR),
85 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
86
87 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
88 }
89
90 /*****************************************************************************\
91 * *
92 * Low level functions *
93 * *
94 \*****************************************************************************/
95
96 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
97 {
98 u32 ier;
99
100 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
101 ier &= ~clear;
102 ier |= set;
103 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
104 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
105 }
106
107 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
108 {
109 sdhci_clear_set_irqs(host, 0, irqs);
110 }
111
112 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
113 {
114 sdhci_clear_set_irqs(host, irqs, 0);
115 }
116
117 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
118 {
119 u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
120
121 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
122 return;
123
124 if (enable)
125 sdhci_unmask_irqs(host, irqs);
126 else
127 sdhci_mask_irqs(host, irqs);
128 }
129
130 static void sdhci_enable_card_detection(struct sdhci_host *host)
131 {
132 sdhci_set_card_detection(host, true);
133 }
134
135 static void sdhci_disable_card_detection(struct sdhci_host *host)
136 {
137 sdhci_set_card_detection(host, false);
138 }
139
140 static void sdhci_reset(struct sdhci_host *host, u8 mask)
141 {
142 unsigned long timeout;
143 u32 uninitialized_var(ier);
144
145 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
146 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
147 SDHCI_CARD_PRESENT))
148 return;
149 }
150
151 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
152 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
153
154 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
155
156 if (mask & SDHCI_RESET_ALL)
157 host->clock = 0;
158
159 /* Wait max 100 ms */
160 timeout = 100;
161
162 /* hw clears the bit when it's done */
163 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
164 if (timeout == 0) {
165 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
166 mmc_hostname(host->mmc), (int)mask);
167 sdhci_dumpregs(host);
168 return;
169 }
170 timeout--;
171 mdelay(1);
172 }
173
174 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
175 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
176 }
177
178 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
179
180 static void sdhci_init(struct sdhci_host *host, int soft)
181 {
182 if (soft)
183 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
184 else
185 sdhci_reset(host, SDHCI_RESET_ALL);
186
187 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
188 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
189 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
190 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
191 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
192
193 if (soft) {
194 /* force clock reconfiguration */
195 host->clock = 0;
196 sdhci_set_ios(host->mmc, &host->mmc->ios);
197 }
198 }
199
200 static void sdhci_reinit(struct sdhci_host *host)
201 {
202 sdhci_init(host, 0);
203 sdhci_enable_card_detection(host);
204 }
205
206 static void sdhci_activate_led(struct sdhci_host *host)
207 {
208 u8 ctrl;
209
210 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
211 ctrl |= SDHCI_CTRL_LED;
212 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
213 }
214
215 static void sdhci_deactivate_led(struct sdhci_host *host)
216 {
217 u8 ctrl;
218
219 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
220 ctrl &= ~SDHCI_CTRL_LED;
221 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
222 }
223
224 #ifdef SDHCI_USE_LEDS_CLASS
225 static void sdhci_led_control(struct led_classdev *led,
226 enum led_brightness brightness)
227 {
228 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
229 unsigned long flags;
230
231 spin_lock_irqsave(&host->lock, flags);
232
233 if (brightness == LED_OFF)
234 sdhci_deactivate_led(host);
235 else
236 sdhci_activate_led(host);
237
238 spin_unlock_irqrestore(&host->lock, flags);
239 }
240 #endif
241
242 /*****************************************************************************\
243 * *
244 * Core functions *
245 * *
246 \*****************************************************************************/
247
248 static void sdhci_read_block_pio(struct sdhci_host *host)
249 {
250 unsigned long flags;
251 size_t blksize, len, chunk;
252 u32 uninitialized_var(scratch);
253 u8 *buf;
254
255 DBG("PIO reading\n");
256
257 blksize = host->data->blksz;
258 chunk = 0;
259
260 local_irq_save(flags);
261
262 while (blksize) {
263 if (!sg_miter_next(&host->sg_miter))
264 BUG();
265
266 len = min(host->sg_miter.length, blksize);
267
268 blksize -= len;
269 host->sg_miter.consumed = len;
270
271 buf = host->sg_miter.addr;
272
273 while (len) {
274 if (chunk == 0) {
275 scratch = sdhci_readl(host, SDHCI_BUFFER);
276 chunk = 4;
277 }
278
279 *buf = scratch & 0xFF;
280
281 buf++;
282 scratch >>= 8;
283 chunk--;
284 len--;
285 }
286 }
287
288 sg_miter_stop(&host->sg_miter);
289
290 local_irq_restore(flags);
291 }
292
293 static void sdhci_write_block_pio(struct sdhci_host *host)
294 {
295 unsigned long flags;
296 size_t blksize, len, chunk;
297 u32 scratch;
298 u8 *buf;
299
300 DBG("PIO writing\n");
301
302 blksize = host->data->blksz;
303 chunk = 0;
304 scratch = 0;
305
306 local_irq_save(flags);
307
308 while (blksize) {
309 if (!sg_miter_next(&host->sg_miter))
310 BUG();
311
312 len = min(host->sg_miter.length, blksize);
313
314 blksize -= len;
315 host->sg_miter.consumed = len;
316
317 buf = host->sg_miter.addr;
318
319 while (len) {
320 scratch |= (u32)*buf << (chunk * 8);
321
322 buf++;
323 chunk++;
324 len--;
325
326 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
327 sdhci_writel(host, scratch, SDHCI_BUFFER);
328 chunk = 0;
329 scratch = 0;
330 }
331 }
332 }
333
334 sg_miter_stop(&host->sg_miter);
335
336 local_irq_restore(flags);
337 }
338
339 static void sdhci_transfer_pio(struct sdhci_host *host)
340 {
341 u32 mask;
342
343 BUG_ON(!host->data);
344
345 if (host->blocks == 0)
346 return;
347
348 if (host->data->flags & MMC_DATA_READ)
349 mask = SDHCI_DATA_AVAILABLE;
350 else
351 mask = SDHCI_SPACE_AVAILABLE;
352
353 /*
354 * Some controllers (JMicron JMB38x) mess up the buffer bits
355 * for transfers < 4 bytes. As long as it is just one block,
356 * we can ignore the bits.
357 */
358 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
359 (host->data->blocks == 1))
360 mask = ~0;
361
362 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
363 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
364 udelay(100);
365
366 if (host->data->flags & MMC_DATA_READ)
367 sdhci_read_block_pio(host);
368 else
369 sdhci_write_block_pio(host);
370
371 host->blocks--;
372 if (host->blocks == 0)
373 break;
374 }
375
376 DBG("PIO transfer complete.\n");
377 }
378
379 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
380 {
381 local_irq_save(*flags);
382 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
383 }
384
385 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
386 {
387 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
388 local_irq_restore(*flags);
389 }
390
391 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
392 {
393 __le32 *dataddr = (__le32 __force *)(desc + 4);
394 __le16 *cmdlen = (__le16 __force *)desc;
395
396 /* SDHCI specification says ADMA descriptors should be 4 byte
397 * aligned, so using 16 or 32bit operations should be safe. */
398
399 cmdlen[0] = cpu_to_le16(cmd);
400 cmdlen[1] = cpu_to_le16(len);
401
402 dataddr[0] = cpu_to_le32(addr);
403 }
404
405 static int sdhci_adma_table_pre(struct sdhci_host *host,
406 struct mmc_data *data)
407 {
408 int direction;
409
410 u8 *desc;
411 u8 *align;
412 dma_addr_t addr;
413 dma_addr_t align_addr;
414 int len, offset;
415
416 struct scatterlist *sg;
417 int i;
418 char *buffer;
419 unsigned long flags;
420
421 /*
422 * The spec does not specify endianness of descriptor table.
423 * We currently guess that it is LE.
424 */
425
426 if (data->flags & MMC_DATA_READ)
427 direction = DMA_FROM_DEVICE;
428 else
429 direction = DMA_TO_DEVICE;
430
431 /*
432 * The ADMA descriptor table is mapped further down as we
433 * need to fill it with data first.
434 */
435
436 host->align_addr = dma_map_single(mmc_dev(host->mmc),
437 host->align_buffer, 128 * 4, direction);
438 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
439 goto fail;
440 BUG_ON(host->align_addr & 0x3);
441
442 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
443 data->sg, data->sg_len, direction);
444 if (host->sg_count == 0)
445 goto unmap_align;
446
447 desc = host->adma_desc;
448 align = host->align_buffer;
449
450 align_addr = host->align_addr;
451
452 for_each_sg(data->sg, sg, host->sg_count, i) {
453 addr = sg_dma_address(sg);
454 len = sg_dma_len(sg);
455
456 /*
457 * The SDHCI specification states that ADMA
458 * addresses must be 32-bit aligned. If they
459 * aren't, then we use a bounce buffer for
460 * the (up to three) bytes that screw up the
461 * alignment.
462 */
463 offset = (4 - (addr & 0x3)) & 0x3;
464 if (offset) {
465 if (data->flags & MMC_DATA_WRITE) {
466 buffer = sdhci_kmap_atomic(sg, &flags);
467 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
468 memcpy(align, buffer, offset);
469 sdhci_kunmap_atomic(buffer, &flags);
470 }
471
472 /* tran, valid */
473 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
474
475 BUG_ON(offset > 65536);
476
477 align += 4;
478 align_addr += 4;
479
480 desc += 8;
481
482 addr += offset;
483 len -= offset;
484 }
485
486 BUG_ON(len > 65536);
487
488 /* tran, valid */
489 sdhci_set_adma_desc(desc, addr, len, 0x21);
490 desc += 8;
491
492 /*
493 * If this triggers then we have a calculation bug
494 * somewhere. :/
495 */
496 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
497 }
498
499 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
500 /*
501 * Mark the last descriptor as the terminating descriptor
502 */
503 if (desc != host->adma_desc) {
504 desc -= 8;
505 desc[0] |= 0x2; /* end */
506 }
507 } else {
508 /*
509 * Add a terminating entry.
510 */
511
512 /* nop, end, valid */
513 sdhci_set_adma_desc(desc, 0, 0, 0x3);
514 }
515
516 /*
517 * Resync align buffer as we might have changed it.
518 */
519 if (data->flags & MMC_DATA_WRITE) {
520 dma_sync_single_for_device(mmc_dev(host->mmc),
521 host->align_addr, 128 * 4, direction);
522 }
523
524 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
525 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
526 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
527 goto unmap_entries;
528 BUG_ON(host->adma_addr & 0x3);
529
530 return 0;
531
532 unmap_entries:
533 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
534 data->sg_len, direction);
535 unmap_align:
536 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
537 128 * 4, direction);
538 fail:
539 return -EINVAL;
540 }
541
542 static void sdhci_adma_table_post(struct sdhci_host *host,
543 struct mmc_data *data)
544 {
545 int direction;
546
547 struct scatterlist *sg;
548 int i, size;
549 u8 *align;
550 char *buffer;
551 unsigned long flags;
552
553 if (data->flags & MMC_DATA_READ)
554 direction = DMA_FROM_DEVICE;
555 else
556 direction = DMA_TO_DEVICE;
557
558 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
559 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
560
561 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
562 128 * 4, direction);
563
564 if (data->flags & MMC_DATA_READ) {
565 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
566 data->sg_len, direction);
567
568 align = host->align_buffer;
569
570 for_each_sg(data->sg, sg, host->sg_count, i) {
571 if (sg_dma_address(sg) & 0x3) {
572 size = 4 - (sg_dma_address(sg) & 0x3);
573
574 buffer = sdhci_kmap_atomic(sg, &flags);
575 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
576 memcpy(buffer, align, size);
577 sdhci_kunmap_atomic(buffer, &flags);
578
579 align += 4;
580 }
581 }
582 }
583
584 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
585 data->sg_len, direction);
586 }
587
588 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
589 {
590 u8 count;
591 unsigned target_timeout, current_timeout;
592
593 /*
594 * If the host controller provides us with an incorrect timeout
595 * value, just skip the check and use 0xE. The hardware may take
596 * longer to time out, but that's much better than having a too-short
597 * timeout value.
598 */
599 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
600 return 0xE;
601
602 /* timeout in us */
603 target_timeout = data->timeout_ns / 1000 +
604 data->timeout_clks / host->clock;
605
606 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
607 host->timeout_clk = host->clock / 1000;
608
609 /*
610 * Figure out needed cycles.
611 * We do this in steps in order to fit inside a 32 bit int.
612 * The first step is the minimum timeout, which will have a
613 * minimum resolution of 6 bits:
614 * (1) 2^13*1000 > 2^22,
615 * (2) host->timeout_clk < 2^16
616 * =>
617 * (1) / (2) > 2^6
618 */
619 count = 0;
620 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
621 while (current_timeout < target_timeout) {
622 count++;
623 current_timeout <<= 1;
624 if (count >= 0xF)
625 break;
626 }
627
628 if (count >= 0xF) {
629 printk(KERN_WARNING "%s: Too large timeout requested!\n",
630 mmc_hostname(host->mmc));
631 count = 0xE;
632 }
633
634 return count;
635 }
636
637 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
638 {
639 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
640 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
641
642 if (host->flags & SDHCI_REQ_USE_DMA)
643 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
644 else
645 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
646 }
647
648 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
649 {
650 u8 count;
651 u8 ctrl;
652 int ret;
653
654 WARN_ON(host->data);
655
656 if (data == NULL)
657 return;
658
659 /* Sanity checks */
660 BUG_ON(data->blksz * data->blocks > 524288);
661 BUG_ON(data->blksz > host->mmc->max_blk_size);
662 BUG_ON(data->blocks > 65535);
663
664 host->data = data;
665 host->data_early = 0;
666
667 count = sdhci_calc_timeout(host, data);
668 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
669
670 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
671 host->flags |= SDHCI_REQ_USE_DMA;
672
673 /*
674 * FIXME: This doesn't account for merging when mapping the
675 * scatterlist.
676 */
677 if (host->flags & SDHCI_REQ_USE_DMA) {
678 int broken, i;
679 struct scatterlist *sg;
680
681 broken = 0;
682 if (host->flags & SDHCI_USE_ADMA) {
683 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
684 broken = 1;
685 } else {
686 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
687 broken = 1;
688 }
689
690 if (unlikely(broken)) {
691 for_each_sg(data->sg, sg, data->sg_len, i) {
692 if (sg->length & 0x3) {
693 DBG("Reverting to PIO because of "
694 "transfer size (%d)\n",
695 sg->length);
696 host->flags &= ~SDHCI_REQ_USE_DMA;
697 break;
698 }
699 }
700 }
701 }
702
703 /*
704 * The assumption here being that alignment is the same after
705 * translation to device address space.
706 */
707 if (host->flags & SDHCI_REQ_USE_DMA) {
708 int broken, i;
709 struct scatterlist *sg;
710
711 broken = 0;
712 if (host->flags & SDHCI_USE_ADMA) {
713 /*
714 * As we use 3 byte chunks to work around
715 * alignment problems, we need to check this
716 * quirk.
717 */
718 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
719 broken = 1;
720 } else {
721 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
722 broken = 1;
723 }
724
725 if (unlikely(broken)) {
726 for_each_sg(data->sg, sg, data->sg_len, i) {
727 if (sg->offset & 0x3) {
728 DBG("Reverting to PIO because of "
729 "bad alignment\n");
730 host->flags &= ~SDHCI_REQ_USE_DMA;
731 break;
732 }
733 }
734 }
735 }
736
737 if (host->flags & SDHCI_REQ_USE_DMA) {
738 if (host->flags & SDHCI_USE_ADMA) {
739 ret = sdhci_adma_table_pre(host, data);
740 if (ret) {
741 /*
742 * This only happens when someone fed
743 * us an invalid request.
744 */
745 WARN_ON(1);
746 host->flags &= ~SDHCI_REQ_USE_DMA;
747 } else {
748 sdhci_writel(host, host->adma_addr,
749 SDHCI_ADMA_ADDRESS);
750 }
751 } else {
752 int sg_cnt;
753
754 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
755 data->sg, data->sg_len,
756 (data->flags & MMC_DATA_READ) ?
757 DMA_FROM_DEVICE :
758 DMA_TO_DEVICE);
759 if (sg_cnt == 0) {
760 /*
761 * This only happens when someone fed
762 * us an invalid request.
763 */
764 WARN_ON(1);
765 host->flags &= ~SDHCI_REQ_USE_DMA;
766 } else {
767 WARN_ON(sg_cnt != 1);
768 sdhci_writel(host, sg_dma_address(data->sg),
769 SDHCI_DMA_ADDRESS);
770 }
771 }
772 }
773
774 /*
775 * Always adjust the DMA selection as some controllers
776 * (e.g. JMicron) can't do PIO properly when the selection
777 * is ADMA.
778 */
779 if (host->version >= SDHCI_SPEC_200) {
780 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
781 ctrl &= ~SDHCI_CTRL_DMA_MASK;
782 if ((host->flags & SDHCI_REQ_USE_DMA) &&
783 (host->flags & SDHCI_USE_ADMA))
784 ctrl |= SDHCI_CTRL_ADMA32;
785 else
786 ctrl |= SDHCI_CTRL_SDMA;
787 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
788 }
789
790 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
791 int flags;
792
793 flags = SG_MITER_ATOMIC;
794 if (host->data->flags & MMC_DATA_READ)
795 flags |= SG_MITER_TO_SG;
796 else
797 flags |= SG_MITER_FROM_SG;
798 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
799 host->blocks = data->blocks;
800 }
801
802 sdhci_set_transfer_irqs(host);
803
804 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
805 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE);
806 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
807 }
808
809 static void sdhci_set_transfer_mode(struct sdhci_host *host,
810 struct mmc_data *data)
811 {
812 u16 mode;
813
814 if (data == NULL)
815 return;
816
817 WARN_ON(!host->data);
818
819 mode = SDHCI_TRNS_BLK_CNT_EN;
820 if (data->blocks > 1)
821 mode |= SDHCI_TRNS_MULTI;
822 if (data->flags & MMC_DATA_READ)
823 mode |= SDHCI_TRNS_READ;
824 if (host->flags & SDHCI_REQ_USE_DMA)
825 mode |= SDHCI_TRNS_DMA;
826
827 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
828 }
829
830 static void sdhci_finish_data(struct sdhci_host *host)
831 {
832 struct mmc_data *data;
833
834 BUG_ON(!host->data);
835
836 data = host->data;
837 host->data = NULL;
838
839 if (host->flags & SDHCI_REQ_USE_DMA) {
840 if (host->flags & SDHCI_USE_ADMA)
841 sdhci_adma_table_post(host, data);
842 else {
843 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
844 data->sg_len, (data->flags & MMC_DATA_READ) ?
845 DMA_FROM_DEVICE : DMA_TO_DEVICE);
846 }
847 }
848
849 /*
850 * The specification states that the block count register must
851 * be updated, but it does not specify at what point in the
852 * data flow. That makes the register entirely useless to read
853 * back so we have to assume that nothing made it to the card
854 * in the event of an error.
855 */
856 if (data->error)
857 data->bytes_xfered = 0;
858 else
859 data->bytes_xfered = data->blksz * data->blocks;
860
861 if (data->stop) {
862 /*
863 * The controller needs a reset of internal state machines
864 * upon error conditions.
865 */
866 if (data->error) {
867 sdhci_reset(host, SDHCI_RESET_CMD);
868 sdhci_reset(host, SDHCI_RESET_DATA);
869 }
870
871 sdhci_send_command(host, data->stop);
872 } else
873 tasklet_schedule(&host->finish_tasklet);
874 }
875
876 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
877 {
878 int flags;
879 u32 mask;
880 unsigned long timeout;
881
882 WARN_ON(host->cmd);
883
884 /* Wait max 10 ms */
885 timeout = 10;
886
887 mask = SDHCI_CMD_INHIBIT;
888 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
889 mask |= SDHCI_DATA_INHIBIT;
890
891 /* We shouldn't wait for data inihibit for stop commands, even
892 though they might use busy signaling */
893 if (host->mrq->data && (cmd == host->mrq->data->stop))
894 mask &= ~SDHCI_DATA_INHIBIT;
895
896 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
897 if (timeout == 0) {
898 printk(KERN_ERR "%s: Controller never released "
899 "inhibit bit(s).\n", mmc_hostname(host->mmc));
900 sdhci_dumpregs(host);
901 cmd->error = -EIO;
902 tasklet_schedule(&host->finish_tasklet);
903 return;
904 }
905 timeout--;
906 mdelay(1);
907 }
908
909 mod_timer(&host->timer, jiffies + 10 * HZ);
910
911 host->cmd = cmd;
912
913 sdhci_prepare_data(host, cmd->data);
914
915 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
916
917 sdhci_set_transfer_mode(host, cmd->data);
918
919 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
920 printk(KERN_ERR "%s: Unsupported response type!\n",
921 mmc_hostname(host->mmc));
922 cmd->error = -EINVAL;
923 tasklet_schedule(&host->finish_tasklet);
924 return;
925 }
926
927 if (!(cmd->flags & MMC_RSP_PRESENT))
928 flags = SDHCI_CMD_RESP_NONE;
929 else if (cmd->flags & MMC_RSP_136)
930 flags = SDHCI_CMD_RESP_LONG;
931 else if (cmd->flags & MMC_RSP_BUSY)
932 flags = SDHCI_CMD_RESP_SHORT_BUSY;
933 else
934 flags = SDHCI_CMD_RESP_SHORT;
935
936 if (cmd->flags & MMC_RSP_CRC)
937 flags |= SDHCI_CMD_CRC;
938 if (cmd->flags & MMC_RSP_OPCODE)
939 flags |= SDHCI_CMD_INDEX;
940 if (cmd->data)
941 flags |= SDHCI_CMD_DATA;
942
943 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
944 }
945
946 static void sdhci_finish_command(struct sdhci_host *host)
947 {
948 int i;
949
950 BUG_ON(host->cmd == NULL);
951
952 if (host->cmd->flags & MMC_RSP_PRESENT) {
953 if (host->cmd->flags & MMC_RSP_136) {
954 /* CRC is stripped so we need to do some shifting. */
955 for (i = 0;i < 4;i++) {
956 host->cmd->resp[i] = sdhci_readl(host,
957 SDHCI_RESPONSE + (3-i)*4) << 8;
958 if (i != 3)
959 host->cmd->resp[i] |=
960 sdhci_readb(host,
961 SDHCI_RESPONSE + (3-i)*4-1);
962 }
963 } else {
964 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
965 }
966 }
967
968 host->cmd->error = 0;
969
970 if (host->data && host->data_early)
971 sdhci_finish_data(host);
972
973 if (!host->cmd->data)
974 tasklet_schedule(&host->finish_tasklet);
975
976 host->cmd = NULL;
977 }
978
979 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
980 {
981 int div;
982 u16 clk;
983 unsigned long timeout;
984
985 if (clock == host->clock)
986 return;
987
988 if (host->ops->set_clock) {
989 host->ops->set_clock(host, clock);
990 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
991 return;
992 }
993
994 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
995
996 if (clock == 0)
997 goto out;
998
999 for (div = 1;div < 256;div *= 2) {
1000 if ((host->max_clk / div) <= clock)
1001 break;
1002 }
1003 div >>= 1;
1004
1005 clk = div << SDHCI_DIVIDER_SHIFT;
1006 clk |= SDHCI_CLOCK_INT_EN;
1007 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1008
1009 /* Wait max 20 ms */
1010 timeout = 20;
1011 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1012 & SDHCI_CLOCK_INT_STABLE)) {
1013 if (timeout == 0) {
1014 printk(KERN_ERR "%s: Internal clock never "
1015 "stabilised.\n", mmc_hostname(host->mmc));
1016 sdhci_dumpregs(host);
1017 return;
1018 }
1019 timeout--;
1020 mdelay(1);
1021 }
1022
1023 clk |= SDHCI_CLOCK_CARD_EN;
1024 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1025
1026 out:
1027 host->clock = clock;
1028 }
1029
1030 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1031 {
1032 u8 pwr;
1033
1034 if (power == (unsigned short)-1)
1035 pwr = 0;
1036 else {
1037 switch (1 << power) {
1038 case MMC_VDD_165_195:
1039 pwr = SDHCI_POWER_180;
1040 break;
1041 case MMC_VDD_29_30:
1042 case MMC_VDD_30_31:
1043 pwr = SDHCI_POWER_300;
1044 break;
1045 case MMC_VDD_32_33:
1046 case MMC_VDD_33_34:
1047 pwr = SDHCI_POWER_330;
1048 break;
1049 default:
1050 BUG();
1051 }
1052 }
1053
1054 if (host->pwr == pwr)
1055 return;
1056
1057 host->pwr = pwr;
1058
1059 if (pwr == 0) {
1060 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1061 return;
1062 }
1063
1064 /*
1065 * Spec says that we should clear the power reg before setting
1066 * a new value. Some controllers don't seem to like this though.
1067 */
1068 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1069 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1070
1071 /*
1072 * At least the Marvell CaFe chip gets confused if we set the voltage
1073 * and set turn on power at the same time, so set the voltage first.
1074 */
1075 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1076 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1077
1078 pwr |= SDHCI_POWER_ON;
1079
1080 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1081
1082 /*
1083 * Some controllers need an extra 10ms delay of 10ms before they
1084 * can apply clock after applying power
1085 */
1086 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1087 mdelay(10);
1088 }
1089
1090 /*****************************************************************************\
1091 * *
1092 * MMC callbacks *
1093 * *
1094 \*****************************************************************************/
1095
1096 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1097 {
1098 struct sdhci_host *host;
1099 bool present;
1100 unsigned long flags;
1101
1102 host = mmc_priv(mmc);
1103
1104 spin_lock_irqsave(&host->lock, flags);
1105
1106 WARN_ON(host->mrq != NULL);
1107
1108 #ifndef SDHCI_USE_LEDS_CLASS
1109 sdhci_activate_led(host);
1110 #endif
1111
1112 host->mrq = mrq;
1113
1114 /* If polling, assume that the card is always present. */
1115 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1116 present = true;
1117 else
1118 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1119 SDHCI_CARD_PRESENT;
1120
1121 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1122 host->mrq->cmd->error = -ENOMEDIUM;
1123 tasklet_schedule(&host->finish_tasklet);
1124 } else
1125 sdhci_send_command(host, mrq->cmd);
1126
1127 mmiowb();
1128 spin_unlock_irqrestore(&host->lock, flags);
1129 }
1130
1131 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1132 {
1133 struct sdhci_host *host;
1134 unsigned long flags;
1135 u8 ctrl;
1136
1137 host = mmc_priv(mmc);
1138
1139 spin_lock_irqsave(&host->lock, flags);
1140
1141 if (host->flags & SDHCI_DEVICE_DEAD)
1142 goto out;
1143
1144 /*
1145 * Reset the chip on each power off.
1146 * Should clear out any weird states.
1147 */
1148 if (ios->power_mode == MMC_POWER_OFF) {
1149 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1150 sdhci_reinit(host);
1151 }
1152
1153 sdhci_set_clock(host, ios->clock);
1154
1155 if (ios->power_mode == MMC_POWER_OFF)
1156 sdhci_set_power(host, -1);
1157 else
1158 sdhci_set_power(host, ios->vdd);
1159
1160 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1161
1162 if (ios->bus_width == MMC_BUS_WIDTH_4)
1163 ctrl |= SDHCI_CTRL_4BITBUS;
1164 else
1165 ctrl &= ~SDHCI_CTRL_4BITBUS;
1166
1167 if (ios->timing == MMC_TIMING_SD_HS)
1168 ctrl |= SDHCI_CTRL_HISPD;
1169 else
1170 ctrl &= ~SDHCI_CTRL_HISPD;
1171
1172 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1173
1174 /*
1175 * Some (ENE) controllers go apeshit on some ios operation,
1176 * signalling timeout and CRC errors even on CMD0. Resetting
1177 * it on each ios seems to solve the problem.
1178 */
1179 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1180 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1181
1182 out:
1183 mmiowb();
1184 spin_unlock_irqrestore(&host->lock, flags);
1185 }
1186
1187 static int sdhci_get_ro(struct mmc_host *mmc)
1188 {
1189 struct sdhci_host *host;
1190 unsigned long flags;
1191 int present;
1192
1193 host = mmc_priv(mmc);
1194
1195 spin_lock_irqsave(&host->lock, flags);
1196
1197 if (host->flags & SDHCI_DEVICE_DEAD)
1198 present = 0;
1199 else
1200 present = sdhci_readl(host, SDHCI_PRESENT_STATE);
1201
1202 spin_unlock_irqrestore(&host->lock, flags);
1203
1204 if (host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT)
1205 return !!(present & SDHCI_WRITE_PROTECT);
1206 return !(present & SDHCI_WRITE_PROTECT);
1207 }
1208
1209 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1210 {
1211 struct sdhci_host *host;
1212 unsigned long flags;
1213
1214 host = mmc_priv(mmc);
1215
1216 spin_lock_irqsave(&host->lock, flags);
1217
1218 if (host->flags & SDHCI_DEVICE_DEAD)
1219 goto out;
1220
1221 if (enable)
1222 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1223 else
1224 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1225 out:
1226 mmiowb();
1227
1228 spin_unlock_irqrestore(&host->lock, flags);
1229 }
1230
1231 static const struct mmc_host_ops sdhci_ops = {
1232 .request = sdhci_request,
1233 .set_ios = sdhci_set_ios,
1234 .get_ro = sdhci_get_ro,
1235 .enable_sdio_irq = sdhci_enable_sdio_irq,
1236 };
1237
1238 /*****************************************************************************\
1239 * *
1240 * Tasklets *
1241 * *
1242 \*****************************************************************************/
1243
1244 static void sdhci_tasklet_card(unsigned long param)
1245 {
1246 struct sdhci_host *host;
1247 unsigned long flags;
1248
1249 host = (struct sdhci_host*)param;
1250
1251 spin_lock_irqsave(&host->lock, flags);
1252
1253 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1254 if (host->mrq) {
1255 printk(KERN_ERR "%s: Card removed during transfer!\n",
1256 mmc_hostname(host->mmc));
1257 printk(KERN_ERR "%s: Resetting controller.\n",
1258 mmc_hostname(host->mmc));
1259
1260 sdhci_reset(host, SDHCI_RESET_CMD);
1261 sdhci_reset(host, SDHCI_RESET_DATA);
1262
1263 host->mrq->cmd->error = -ENOMEDIUM;
1264 tasklet_schedule(&host->finish_tasklet);
1265 }
1266 }
1267
1268 spin_unlock_irqrestore(&host->lock, flags);
1269
1270 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1271 }
1272
1273 static void sdhci_tasklet_finish(unsigned long param)
1274 {
1275 struct sdhci_host *host;
1276 unsigned long flags;
1277 struct mmc_request *mrq;
1278
1279 host = (struct sdhci_host*)param;
1280
1281 spin_lock_irqsave(&host->lock, flags);
1282
1283 del_timer(&host->timer);
1284
1285 mrq = host->mrq;
1286
1287 /*
1288 * The controller needs a reset of internal state machines
1289 * upon error conditions.
1290 */
1291 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1292 (mrq->cmd->error ||
1293 (mrq->data && (mrq->data->error ||
1294 (mrq->data->stop && mrq->data->stop->error))) ||
1295 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1296
1297 /* Some controllers need this kick or reset won't work here */
1298 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1299 unsigned int clock;
1300
1301 /* This is to force an update */
1302 clock = host->clock;
1303 host->clock = 0;
1304 sdhci_set_clock(host, clock);
1305 }
1306
1307 /* Spec says we should do both at the same time, but Ricoh
1308 controllers do not like that. */
1309 sdhci_reset(host, SDHCI_RESET_CMD);
1310 sdhci_reset(host, SDHCI_RESET_DATA);
1311 }
1312
1313 host->mrq = NULL;
1314 host->cmd = NULL;
1315 host->data = NULL;
1316
1317 #ifndef SDHCI_USE_LEDS_CLASS
1318 sdhci_deactivate_led(host);
1319 #endif
1320
1321 mmiowb();
1322 spin_unlock_irqrestore(&host->lock, flags);
1323
1324 mmc_request_done(host->mmc, mrq);
1325 }
1326
1327 static void sdhci_timeout_timer(unsigned long data)
1328 {
1329 struct sdhci_host *host;
1330 unsigned long flags;
1331
1332 host = (struct sdhci_host*)data;
1333
1334 spin_lock_irqsave(&host->lock, flags);
1335
1336 if (host->mrq) {
1337 printk(KERN_ERR "%s: Timeout waiting for hardware "
1338 "interrupt.\n", mmc_hostname(host->mmc));
1339 sdhci_dumpregs(host);
1340
1341 if (host->data) {
1342 host->data->error = -ETIMEDOUT;
1343 sdhci_finish_data(host);
1344 } else {
1345 if (host->cmd)
1346 host->cmd->error = -ETIMEDOUT;
1347 else
1348 host->mrq->cmd->error = -ETIMEDOUT;
1349
1350 tasklet_schedule(&host->finish_tasklet);
1351 }
1352 }
1353
1354 mmiowb();
1355 spin_unlock_irqrestore(&host->lock, flags);
1356 }
1357
1358 /*****************************************************************************\
1359 * *
1360 * Interrupt handling *
1361 * *
1362 \*****************************************************************************/
1363
1364 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1365 {
1366 BUG_ON(intmask == 0);
1367
1368 if (!host->cmd) {
1369 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1370 "though no command operation was in progress.\n",
1371 mmc_hostname(host->mmc), (unsigned)intmask);
1372 sdhci_dumpregs(host);
1373 return;
1374 }
1375
1376 if (intmask & SDHCI_INT_TIMEOUT)
1377 host->cmd->error = -ETIMEDOUT;
1378 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1379 SDHCI_INT_INDEX))
1380 host->cmd->error = -EILSEQ;
1381
1382 if (host->cmd->error) {
1383 tasklet_schedule(&host->finish_tasklet);
1384 return;
1385 }
1386
1387 /*
1388 * The host can send and interrupt when the busy state has
1389 * ended, allowing us to wait without wasting CPU cycles.
1390 * Unfortunately this is overloaded on the "data complete"
1391 * interrupt, so we need to take some care when handling
1392 * it.
1393 *
1394 * Note: The 1.0 specification is a bit ambiguous about this
1395 * feature so there might be some problems with older
1396 * controllers.
1397 */
1398 if (host->cmd->flags & MMC_RSP_BUSY) {
1399 if (host->cmd->data)
1400 DBG("Cannot wait for busy signal when also "
1401 "doing a data transfer");
1402 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
1403 return;
1404
1405 /* The controller does not support the end-of-busy IRQ,
1406 * fall through and take the SDHCI_INT_RESPONSE */
1407 }
1408
1409 if (intmask & SDHCI_INT_RESPONSE)
1410 sdhci_finish_command(host);
1411 }
1412
1413 #ifdef DEBUG
1414 static void sdhci_show_adma_error(struct sdhci_host *host)
1415 {
1416 const char *name = mmc_hostname(host->mmc);
1417 u8 *desc = host->adma_desc;
1418 __le32 *dma;
1419 __le16 *len;
1420 u8 attr;
1421
1422 sdhci_dumpregs(host);
1423
1424 while (true) {
1425 dma = (__le32 *)(desc + 4);
1426 len = (__le16 *)(desc + 2);
1427 attr = *desc;
1428
1429 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
1430 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
1431
1432 desc += 8;
1433
1434 if (attr & 2)
1435 break;
1436 }
1437 }
1438 #else
1439 static void sdhci_show_adma_error(struct sdhci_host *host) { }
1440 #endif
1441
1442 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1443 {
1444 BUG_ON(intmask == 0);
1445
1446 if (!host->data) {
1447 /*
1448 * The "data complete" interrupt is also used to
1449 * indicate that a busy state has ended. See comment
1450 * above in sdhci_cmd_irq().
1451 */
1452 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1453 if (intmask & SDHCI_INT_DATA_END) {
1454 sdhci_finish_command(host);
1455 return;
1456 }
1457 }
1458
1459 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1460 "though no data operation was in progress.\n",
1461 mmc_hostname(host->mmc), (unsigned)intmask);
1462 sdhci_dumpregs(host);
1463
1464 return;
1465 }
1466
1467 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1468 host->data->error = -ETIMEDOUT;
1469 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1470 host->data->error = -EILSEQ;
1471 else if (intmask & SDHCI_INT_ADMA_ERROR) {
1472 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
1473 sdhci_show_adma_error(host);
1474 host->data->error = -EIO;
1475 }
1476
1477 if (host->data->error)
1478 sdhci_finish_data(host);
1479 else {
1480 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1481 sdhci_transfer_pio(host);
1482
1483 /*
1484 * We currently don't do anything fancy with DMA
1485 * boundaries, but as we can't disable the feature
1486 * we need to at least restart the transfer.
1487 */
1488 if (intmask & SDHCI_INT_DMA_END)
1489 sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS),
1490 SDHCI_DMA_ADDRESS);
1491
1492 if (intmask & SDHCI_INT_DATA_END) {
1493 if (host->cmd) {
1494 /*
1495 * Data managed to finish before the
1496 * command completed. Make sure we do
1497 * things in the proper order.
1498 */
1499 host->data_early = 1;
1500 } else {
1501 sdhci_finish_data(host);
1502 }
1503 }
1504 }
1505 }
1506
1507 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1508 {
1509 irqreturn_t result;
1510 struct sdhci_host* host = dev_id;
1511 u32 intmask;
1512 int cardint = 0;
1513
1514 spin_lock(&host->lock);
1515
1516 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
1517
1518 if (!intmask || intmask == 0xffffffff) {
1519 result = IRQ_NONE;
1520 goto out;
1521 }
1522
1523 DBG("*** %s got interrupt: 0x%08x\n",
1524 mmc_hostname(host->mmc), intmask);
1525
1526 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1527 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
1528 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
1529 tasklet_schedule(&host->card_tasklet);
1530 }
1531
1532 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1533
1534 if (intmask & SDHCI_INT_CMD_MASK) {
1535 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
1536 SDHCI_INT_STATUS);
1537 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1538 }
1539
1540 if (intmask & SDHCI_INT_DATA_MASK) {
1541 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
1542 SDHCI_INT_STATUS);
1543 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1544 }
1545
1546 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1547
1548 intmask &= ~SDHCI_INT_ERROR;
1549
1550 if (intmask & SDHCI_INT_BUS_POWER) {
1551 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1552 mmc_hostname(host->mmc));
1553 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
1554 }
1555
1556 intmask &= ~SDHCI_INT_BUS_POWER;
1557
1558 if (intmask & SDHCI_INT_CARD_INT)
1559 cardint = 1;
1560
1561 intmask &= ~SDHCI_INT_CARD_INT;
1562
1563 if (intmask) {
1564 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1565 mmc_hostname(host->mmc), intmask);
1566 sdhci_dumpregs(host);
1567
1568 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
1569 }
1570
1571 result = IRQ_HANDLED;
1572
1573 mmiowb();
1574 out:
1575 spin_unlock(&host->lock);
1576
1577 /*
1578 * We have to delay this as it calls back into the driver.
1579 */
1580 if (cardint)
1581 mmc_signal_sdio_irq(host->mmc);
1582
1583 return result;
1584 }
1585
1586 /*****************************************************************************\
1587 * *
1588 * Suspend/resume *
1589 * *
1590 \*****************************************************************************/
1591
1592 #ifdef CONFIG_PM
1593
1594 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
1595 {
1596 int ret;
1597
1598 sdhci_disable_card_detection(host);
1599
1600 ret = mmc_suspend_host(host->mmc);
1601 if (ret)
1602 return ret;
1603
1604 free_irq(host->irq, host);
1605
1606 return 0;
1607 }
1608
1609 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
1610
1611 int sdhci_resume_host(struct sdhci_host *host)
1612 {
1613 int ret;
1614
1615 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1616 if (host->ops->enable_dma)
1617 host->ops->enable_dma(host);
1618 }
1619
1620 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1621 mmc_hostname(host->mmc), host);
1622 if (ret)
1623 return ret;
1624
1625 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
1626 mmiowb();
1627
1628 ret = mmc_resume_host(host->mmc);
1629 sdhci_enable_card_detection(host);
1630
1631 return ret;
1632 }
1633
1634 EXPORT_SYMBOL_GPL(sdhci_resume_host);
1635
1636 #endif /* CONFIG_PM */
1637
1638 /*****************************************************************************\
1639 * *
1640 * Device allocation/registration *
1641 * *
1642 \*****************************************************************************/
1643
1644 struct sdhci_host *sdhci_alloc_host(struct device *dev,
1645 size_t priv_size)
1646 {
1647 struct mmc_host *mmc;
1648 struct sdhci_host *host;
1649
1650 WARN_ON(dev == NULL);
1651
1652 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
1653 if (!mmc)
1654 return ERR_PTR(-ENOMEM);
1655
1656 host = mmc_priv(mmc);
1657 host->mmc = mmc;
1658
1659 return host;
1660 }
1661
1662 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
1663
1664 int sdhci_add_host(struct sdhci_host *host)
1665 {
1666 struct mmc_host *mmc;
1667 unsigned int caps;
1668 int ret;
1669
1670 WARN_ON(host == NULL);
1671 if (host == NULL)
1672 return -EINVAL;
1673
1674 mmc = host->mmc;
1675
1676 if (debug_quirks)
1677 host->quirks = debug_quirks;
1678
1679 sdhci_reset(host, SDHCI_RESET_ALL);
1680
1681 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
1682 host->version = (host->version & SDHCI_SPEC_VER_MASK)
1683 >> SDHCI_SPEC_VER_SHIFT;
1684 if (host->version > SDHCI_SPEC_200) {
1685 printk(KERN_ERR "%s: Unknown controller version (%d). "
1686 "You may experience problems.\n", mmc_hostname(mmc),
1687 host->version);
1688 }
1689
1690 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
1691
1692 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
1693 host->flags |= SDHCI_USE_SDMA;
1694 else if (!(caps & SDHCI_CAN_DO_SDMA))
1695 DBG("Controller doesn't have SDMA capability\n");
1696 else
1697 host->flags |= SDHCI_USE_SDMA;
1698
1699 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1700 (host->flags & SDHCI_USE_SDMA)) {
1701 DBG("Disabling DMA as it is marked broken\n");
1702 host->flags &= ~SDHCI_USE_SDMA;
1703 }
1704
1705 if ((host->version >= SDHCI_SPEC_200) && (caps & SDHCI_CAN_DO_ADMA2))
1706 host->flags |= SDHCI_USE_ADMA;
1707
1708 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1709 (host->flags & SDHCI_USE_ADMA)) {
1710 DBG("Disabling ADMA as it is marked broken\n");
1711 host->flags &= ~SDHCI_USE_ADMA;
1712 }
1713
1714 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1715 if (host->ops->enable_dma) {
1716 if (host->ops->enable_dma(host)) {
1717 printk(KERN_WARNING "%s: No suitable DMA "
1718 "available. Falling back to PIO.\n",
1719 mmc_hostname(mmc));
1720 host->flags &=
1721 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
1722 }
1723 }
1724 }
1725
1726 if (host->flags & SDHCI_USE_ADMA) {
1727 /*
1728 * We need to allocate descriptors for all sg entries
1729 * (128) and potentially one alignment transfer for
1730 * each of those entries.
1731 */
1732 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1733 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1734 if (!host->adma_desc || !host->align_buffer) {
1735 kfree(host->adma_desc);
1736 kfree(host->align_buffer);
1737 printk(KERN_WARNING "%s: Unable to allocate ADMA "
1738 "buffers. Falling back to standard DMA.\n",
1739 mmc_hostname(mmc));
1740 host->flags &= ~SDHCI_USE_ADMA;
1741 }
1742 }
1743
1744 /*
1745 * If we use DMA, then it's up to the caller to set the DMA
1746 * mask, but PIO does not need the hw shim so we set a new
1747 * mask here in that case.
1748 */
1749 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
1750 host->dma_mask = DMA_BIT_MASK(64);
1751 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
1752 }
1753
1754 host->max_clk =
1755 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1756 host->max_clk *= 1000000;
1757 if (host->max_clk == 0 || host->quirks &
1758 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
1759 if (!host->ops->get_max_clock) {
1760 printk(KERN_ERR
1761 "%s: Hardware doesn't specify base clock "
1762 "frequency.\n", mmc_hostname(mmc));
1763 return -ENODEV;
1764 }
1765 host->max_clk = host->ops->get_max_clock(host);
1766 }
1767
1768 host->timeout_clk =
1769 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1770 if (host->timeout_clk == 0) {
1771 if (host->ops->get_timeout_clock) {
1772 host->timeout_clk = host->ops->get_timeout_clock(host);
1773 } else if (!(host->quirks &
1774 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
1775 printk(KERN_ERR
1776 "%s: Hardware doesn't specify timeout clock "
1777 "frequency.\n", mmc_hostname(mmc));
1778 return -ENODEV;
1779 }
1780 }
1781 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1782 host->timeout_clk *= 1000;
1783
1784 /*
1785 * Set host parameters.
1786 */
1787 mmc->ops = &sdhci_ops;
1788 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK &&
1789 host->ops->set_clock && host->ops->get_min_clock)
1790 mmc->f_min = host->ops->get_min_clock(host);
1791 else
1792 mmc->f_min = host->max_clk / 256;
1793 mmc->f_max = host->max_clk;
1794 mmc->caps = MMC_CAP_SDIO_IRQ;
1795
1796 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
1797 mmc->caps |= MMC_CAP_4_BIT_DATA;
1798
1799 if (caps & SDHCI_CAN_DO_HISPD)
1800 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1801
1802 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1803 mmc->caps |= MMC_CAP_NEEDS_POLL;
1804
1805 mmc->ocr_avail = 0;
1806 if (caps & SDHCI_CAN_VDD_330)
1807 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1808 if (caps & SDHCI_CAN_VDD_300)
1809 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1810 if (caps & SDHCI_CAN_VDD_180)
1811 mmc->ocr_avail |= MMC_VDD_165_195;
1812
1813 if (mmc->ocr_avail == 0) {
1814 printk(KERN_ERR "%s: Hardware doesn't report any "
1815 "support voltages.\n", mmc_hostname(mmc));
1816 return -ENODEV;
1817 }
1818
1819 spin_lock_init(&host->lock);
1820
1821 /*
1822 * Maximum number of segments. Depends on if the hardware
1823 * can do scatter/gather or not.
1824 */
1825 if (host->flags & SDHCI_USE_ADMA)
1826 mmc->max_hw_segs = 128;
1827 else if (host->flags & SDHCI_USE_SDMA)
1828 mmc->max_hw_segs = 1;
1829 else /* PIO */
1830 mmc->max_hw_segs = 128;
1831 mmc->max_phys_segs = 128;
1832
1833 /*
1834 * Maximum number of sectors in one transfer. Limited by DMA boundary
1835 * size (512KiB).
1836 */
1837 mmc->max_req_size = 524288;
1838
1839 /*
1840 * Maximum segment size. Could be one segment with the maximum number
1841 * of bytes. When doing hardware scatter/gather, each entry cannot
1842 * be larger than 64 KiB though.
1843 */
1844 if (host->flags & SDHCI_USE_ADMA)
1845 mmc->max_seg_size = 65536;
1846 else
1847 mmc->max_seg_size = mmc->max_req_size;
1848
1849 /*
1850 * Maximum block size. This varies from controller to controller and
1851 * is specified in the capabilities register.
1852 */
1853 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
1854 mmc->max_blk_size = 2;
1855 } else {
1856 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >>
1857 SDHCI_MAX_BLOCK_SHIFT;
1858 if (mmc->max_blk_size >= 3) {
1859 printk(KERN_WARNING "%s: Invalid maximum block size, "
1860 "assuming 512 bytes\n", mmc_hostname(mmc));
1861 mmc->max_blk_size = 0;
1862 }
1863 }
1864
1865 mmc->max_blk_size = 512 << mmc->max_blk_size;
1866
1867 /*
1868 * Maximum block count.
1869 */
1870 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
1871
1872 /*
1873 * Init tasklets.
1874 */
1875 tasklet_init(&host->card_tasklet,
1876 sdhci_tasklet_card, (unsigned long)host);
1877 tasklet_init(&host->finish_tasklet,
1878 sdhci_tasklet_finish, (unsigned long)host);
1879
1880 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1881
1882 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1883 mmc_hostname(mmc), host);
1884 if (ret)
1885 goto untasklet;
1886
1887 sdhci_init(host, 0);
1888
1889 #ifdef CONFIG_MMC_DEBUG
1890 sdhci_dumpregs(host);
1891 #endif
1892
1893 #ifdef SDHCI_USE_LEDS_CLASS
1894 snprintf(host->led_name, sizeof(host->led_name),
1895 "%s::", mmc_hostname(mmc));
1896 host->led.name = host->led_name;
1897 host->led.brightness = LED_OFF;
1898 host->led.default_trigger = mmc_hostname(mmc);
1899 host->led.brightness_set = sdhci_led_control;
1900
1901 ret = led_classdev_register(mmc_dev(mmc), &host->led);
1902 if (ret)
1903 goto reset;
1904 #endif
1905
1906 mmiowb();
1907
1908 mmc_add_host(mmc);
1909
1910 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
1911 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
1912 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
1913 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
1914
1915 sdhci_enable_card_detection(host);
1916
1917 return 0;
1918
1919 #ifdef SDHCI_USE_LEDS_CLASS
1920 reset:
1921 sdhci_reset(host, SDHCI_RESET_ALL);
1922 free_irq(host->irq, host);
1923 #endif
1924 untasklet:
1925 tasklet_kill(&host->card_tasklet);
1926 tasklet_kill(&host->finish_tasklet);
1927
1928 return ret;
1929 }
1930
1931 EXPORT_SYMBOL_GPL(sdhci_add_host);
1932
1933 void sdhci_remove_host(struct sdhci_host *host, int dead)
1934 {
1935 unsigned long flags;
1936
1937 if (dead) {
1938 spin_lock_irqsave(&host->lock, flags);
1939
1940 host->flags |= SDHCI_DEVICE_DEAD;
1941
1942 if (host->mrq) {
1943 printk(KERN_ERR "%s: Controller removed during "
1944 " transfer!\n", mmc_hostname(host->mmc));
1945
1946 host->mrq->cmd->error = -ENOMEDIUM;
1947 tasklet_schedule(&host->finish_tasklet);
1948 }
1949
1950 spin_unlock_irqrestore(&host->lock, flags);
1951 }
1952
1953 sdhci_disable_card_detection(host);
1954
1955 mmc_remove_host(host->mmc);
1956
1957 #ifdef SDHCI_USE_LEDS_CLASS
1958 led_classdev_unregister(&host->led);
1959 #endif
1960
1961 if (!dead)
1962 sdhci_reset(host, SDHCI_RESET_ALL);
1963
1964 free_irq(host->irq, host);
1965
1966 del_timer_sync(&host->timer);
1967
1968 tasklet_kill(&host->card_tasklet);
1969 tasklet_kill(&host->finish_tasklet);
1970
1971 kfree(host->adma_desc);
1972 kfree(host->align_buffer);
1973
1974 host->adma_desc = NULL;
1975 host->align_buffer = NULL;
1976 }
1977
1978 EXPORT_SYMBOL_GPL(sdhci_remove_host);
1979
1980 void sdhci_free_host(struct sdhci_host *host)
1981 {
1982 mmc_free_host(host->mmc);
1983 }
1984
1985 EXPORT_SYMBOL_GPL(sdhci_free_host);
1986
1987 /*****************************************************************************\
1988 * *
1989 * Driver init/exit *
1990 * *
1991 \*****************************************************************************/
1992
1993 static int __init sdhci_drv_init(void)
1994 {
1995 printk(KERN_INFO DRIVER_NAME
1996 ": Secure Digital Host Controller Interface driver\n");
1997 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1998
1999 return 0;
2000 }
2001
2002 static void __exit sdhci_drv_exit(void)
2003 {
2004 }
2005
2006 module_init(sdhci_drv_init);
2007 module_exit(sdhci_drv_exit);
2008
2009 module_param(debug_quirks, uint, 0444);
2010
2011 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2012 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
2013 MODULE_LICENSE("GPL");
2014
2015 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");