| blob | 1d7a05f3021e058bd59eabb6fd049446accf7073 |
1 /*
2 * P2020 RDB Device Tree Source
3 *
4 * Copyright 2009-2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 /include/ "p2020si.dtsi"
14 / {
15 model = "fsl,P2020RDB";
16 compatible = "fsl,P2020RDB";
18 aliases {
19 ethernet0 = &enet0;
20 ethernet1 = &enet1;
21 ethernet2 = &enet2;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 };
28 memory {
29 device_type = "memory";
30 };
32 localbus@ffe05000 {
34 /* NOR and NAND Flashes */
35 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
36 0x1 0x0 0x0 0xffa00000 0x00040000
37 0x2 0x0 0x0 0xffb00000 0x00020000>;
39 nor@0,0 {
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "cfi-flash";
43 reg = <0x0 0x0 0x1000000>;
44 bank-width = <2>;
45 device-width = <1>;
47 partition@0 {
48 /* This location must not be altered */
49 /* 256KB for Vitesse 7385 Switch firmware */
50 reg = <0x0 0x00040000>;
51 label = "NOR (RO) Vitesse-7385 Firmware";
52 read-only;
53 };
55 partition@40000 {
56 /* 256KB for DTB Image */
57 reg = <0x00040000 0x00040000>;
58 label = "NOR (RO) DTB Image";
59 read-only;
60 };
62 partition@80000 {
63 /* 3.5 MB for Linux Kernel Image */
64 reg = <0x00080000 0x00380000>;
65 label = "NOR (RO) Linux Kernel Image";
66 read-only;
67 };
69 partition@400000 {
70 /* 11MB for JFFS2 based Root file System */
71 reg = <0x00400000 0x00b00000>;
72 label = "NOR (RW) JFFS2 Root File System";
73 };
75 partition@f00000 {
76 /* This location must not be altered */
77 /* 512KB for u-boot Bootloader Image */
78 /* 512KB for u-boot Environment Variables */
79 reg = <0x00f00000 0x00100000>;
80 label = "NOR (RO) U-Boot Image";
81 read-only;
82 };
83 };
85 nand@1,0 {
86 #address-cells = <1>;
87 #size-cells = <1>;
88 compatible = "fsl,p2020-fcm-nand",
89 "fsl,elbc-fcm-nand";
90 reg = <0x1 0x0 0x40000>;
92 partition@0 {
93 /* This location must not be altered */
94 /* 1MB for u-boot Bootloader Image */
95 reg = <0x0 0x00100000>;
96 label = "NAND (RO) U-Boot Image";
97 read-only;
98 };
100 partition@100000 {
101 /* 1MB for DTB Image */
102 reg = <0x00100000 0x00100000>;
103 label = "NAND (RO) DTB Image";
104 read-only;
105 };
107 partition@200000 {
108 /* 4MB for Linux Kernel Image */
109 reg = <0x00200000 0x00400000>;
110 label = "NAND (RO) Linux Kernel Image";
111 read-only;
112 };
114 partition@600000 {
115 /* 4MB for Compressed Root file System Image */
116 reg = <0x00600000 0x00400000>;
117 label = "NAND (RO) Compressed RFS Image";
118 read-only;
119 };
121 partition@a00000 {
122 /* 7MB for JFFS2 based Root file System */
123 reg = <0x00a00000 0x00700000>;
124 label = "NAND (RW) JFFS2 Root File System";
125 };
127 partition@1100000 {
128 /* 15MB for JFFS2 based Root file System */
129 reg = <0x01100000 0x00f00000>;
130 label = "NAND (RW) Writable User area";
131 };
132 };
134 L2switch@2,0 {
135 #address-cells = <1>;
136 #size-cells = <1>;
137 compatible = "vitesse-7385";
138 reg = <0x2 0x0 0x20000>;
139 };
141 };
143 soc@ffe00000 {
144 i2c@3000 {
145 rtc@68 {
146 compatible = "dallas,ds1339";
147 reg = <0x68>;
148 };
149 };
151 spi@7000 {
153 fsl_m25p80@0 {
154 #address-cells = <1>;
155 #size-cells = <1>;
156 compatible = "fsl,espi-flash";
157 reg = <0>;
158 linux,modalias = "fsl_m25p80";
159 modal = "s25sl128b";
160 spi-max-frequency = <50000000>;
161 mode = <0>;
163 partition@0 {
164 /* 512KB for u-boot Bootloader Image */
165 reg = <0x0 0x00080000>;
166 label = "SPI (RO) U-Boot Image";
167 read-only;
168 };
170 partition@80000 {
171 /* 512KB for DTB Image */
172 reg = <0x00080000 0x00080000>;
173 label = "SPI (RO) DTB Image";
174 read-only;
175 };
177 partition@100000 {
178 /* 4MB for Linux Kernel Image */
179 reg = <0x00100000 0x00400000>;
180 label = "SPI (RO) Linux Kernel Image";
181 read-only;
182 };
184 partition@500000 {
185 /* 4MB for Compressed RFS Image */
186 reg = <0x00500000 0x00400000>;
187 label = "SPI (RO) Compressed RFS Image";
188 read-only;
189 };
191 partition@900000 {
192 /* 7MB for JFFS2 based RFS */
193 reg = <0x00900000 0x00700000>;
194 label = "SPI (RW) JFFS2 RFS";
195 };
196 };
197 };
199 usb@22000 {
200 phy_type = "ulpi";
201 };
203 mdio@24520 {
204 phy0: ethernet-phy@0 {
205 interrupt-parent = <&mpic>;
206 interrupts = <3 1>;
207 reg = <0x0>;
208 };
209 phy1: ethernet-phy@1 {
210 interrupt-parent = <&mpic>;
211 interrupts = <3 1>;
212 reg = <0x1>;
213 };
214 };
216 mdio@25520 {
217 tbi0: tbi-phy@11 {
218 reg = <0x11>;
219 device_type = "tbi-phy";
220 };
221 };
223 mdio@26520 {
224 status = "disabled";
225 };
227 ptp_clock@24E00 {
228 compatible = "fsl,etsec-ptp";
229 reg = <0x24E00 0xB0>;
230 interrupts = <68 2 69 2 70 2>;
231 interrupt-parent = < &mpic >;
232 fsl,tclk-period = <5>;
233 fsl,tmr-prsc = <200>;
234 fsl,tmr-add = <0xCCCCCCCD>;
235 fsl,tmr-fiper1 = <0x3B9AC9FB>;
236 fsl,tmr-fiper2 = <0x0001869B>;
237 fsl,max-adj = <249999999>;
238 };
240 enet0: ethernet@24000 {
241 fixed-link = <1 1 1000 0 0>;
242 phy-connection-type = "rgmii-id";
243 };
245 enet1: ethernet@25000 {
246 tbi-handle = <&tbi0>;
247 phy-handle = <&phy0>;
248 phy-connection-type = "sgmii";
249 };
251 enet2: ethernet@26000 {
252 phy-handle = <&phy1>;
253 phy-connection-type = "rgmii-id";
254 };
256 };
258 pci0: pcie@ffe08000 {
259 status = "disabled";
260 };
262 pci1: pcie@ffe09000 {
263 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
264 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
265 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
266 interrupt-map = <
267 /* IDSEL 0x0 */
268 0000 0x0 0x0 0x1 &mpic 0x4 0x1
269 0000 0x0 0x0 0x2 &mpic 0x5 0x1
270 0000 0x0 0x0 0x3 &mpic 0x6 0x1
271 0000 0x0 0x0 0x4 &mpic 0x7 0x1
272 >;
273 pcie@0 {
274 reg = <0x0 0x0 0x0 0x0 0x0>;
275 #size-cells = <2>;
276 #address-cells = <3>;
277 device_type = "pci";
278 ranges = <0x2000000 0x0 0xa0000000
279 0x2000000 0x0 0xa0000000
280 0x0 0x20000000
282 0x1000000 0x0 0x0
283 0x1000000 0x0 0x0
284 0x0 0x100000>;
285 };
286 };
288 pci2: pcie@ffe0a000 {
289 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
290 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
291 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
292 interrupt-map = <
293 /* IDSEL 0x0 */
294 0000 0x0 0x0 0x1 &mpic 0x0 0x1
295 0000 0x0 0x0 0x2 &mpic 0x1 0x1
296 0000 0x0 0x0 0x3 &mpic 0x2 0x1
297 0000 0x0 0x0 0x4 &mpic 0x3 0x1
298 >;
299 pcie@0 {
300 reg = <0x0 0x0 0x0 0x0 0x0>;
301 #size-cells = <2>;
302 #address-cells = <3>;
303 device_type = "pci";
304 ranges = <0x2000000 0x0 0x80000000
305 0x2000000 0x0 0x80000000
306 0x0 0x20000000
308 0x1000000 0x0 0x0
309 0x1000000 0x0 0x0
310 0x0 0x100000>;
311 };
312 };
313 };