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staging:iio:Documentation gyro -> anglvel updates in attribute names
[zen-stable.git] / arch / powerpc / sysdev / mpic.c
blobd5d3ff3d757e6085d146ce1fb020e254fe331db1
1 /*
2 * arch/powerpc/kernel/mpic.c
3 *
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
7 *
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9 * Copyright 2010-2011 Freescale Semiconductor, Inc.
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file COPYING in the main directory of this archive
13 * for more details.
14 */
15
16 #undef DEBUG
17 #undef DEBUG_IPI
18 #undef DEBUG_IRQ
19 #undef DEBUG_LOW
20
21 #include <linux/types.h>
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/irq.h>
25 #include <linux/smp.h>
26 #include <linux/interrupt.h>
27 #include <linux/bootmem.h>
28 #include <linux/spinlock.h>
29 #include <linux/pci.h>
30 #include <linux/slab.h>
31 #include <linux/syscore_ops.h>
32 #include <linux/ratelimit.h>
33
34 #include <asm/ptrace.h>
35 #include <asm/signal.h>
36 #include <asm/io.h>
37 #include <asm/pgtable.h>
38 #include <asm/irq.h>
39 #include <asm/machdep.h>
40 #include <asm/mpic.h>
41 #include <asm/smp.h>
42
43 #include "mpic.h"
44
45 #ifdef DEBUG
46 #define DBG(fmt...) printk(fmt)
47 #else
48 #define DBG(fmt...)
49 #endif
50
51 static struct mpic *mpics;
52 static struct mpic *mpic_primary;
53 static DEFINE_RAW_SPINLOCK(mpic_lock);
54
55 #ifdef CONFIG_PPC32 /* XXX for now */
56 #ifdef CONFIG_IRQ_ALL_CPUS
57 #define distribute_irqs (1)
58 #else
59 #define distribute_irqs (0)
60 #endif
61 #endif
62
63 #ifdef CONFIG_MPIC_WEIRD
64 static u32 mpic_infos[][MPIC_IDX_END] = {
65 [0] = { /* Original OpenPIC compatible MPIC */
66 MPIC_GREG_BASE,
67 MPIC_GREG_FEATURE_0,
68 MPIC_GREG_GLOBAL_CONF_0,
69 MPIC_GREG_VENDOR_ID,
70 MPIC_GREG_IPI_VECTOR_PRI_0,
71 MPIC_GREG_IPI_STRIDE,
72 MPIC_GREG_SPURIOUS,
73 MPIC_GREG_TIMER_FREQ,
74
75 MPIC_TIMER_BASE,
76 MPIC_TIMER_STRIDE,
77 MPIC_TIMER_CURRENT_CNT,
78 MPIC_TIMER_BASE_CNT,
79 MPIC_TIMER_VECTOR_PRI,
80 MPIC_TIMER_DESTINATION,
81
82 MPIC_CPU_BASE,
83 MPIC_CPU_STRIDE,
84 MPIC_CPU_IPI_DISPATCH_0,
85 MPIC_CPU_IPI_DISPATCH_STRIDE,
86 MPIC_CPU_CURRENT_TASK_PRI,
87 MPIC_CPU_WHOAMI,
88 MPIC_CPU_INTACK,
89 MPIC_CPU_EOI,
90 MPIC_CPU_MCACK,
91
92 MPIC_IRQ_BASE,
93 MPIC_IRQ_STRIDE,
94 MPIC_IRQ_VECTOR_PRI,
95 MPIC_VECPRI_VECTOR_MASK,
96 MPIC_VECPRI_POLARITY_POSITIVE,
97 MPIC_VECPRI_POLARITY_NEGATIVE,
98 MPIC_VECPRI_SENSE_LEVEL,
99 MPIC_VECPRI_SENSE_EDGE,
100 MPIC_VECPRI_POLARITY_MASK,
101 MPIC_VECPRI_SENSE_MASK,
102 MPIC_IRQ_DESTINATION
103 },
104 [1] = { /* Tsi108/109 PIC */
105 TSI108_GREG_BASE,
106 TSI108_GREG_FEATURE_0,
107 TSI108_GREG_GLOBAL_CONF_0,
108 TSI108_GREG_VENDOR_ID,
109 TSI108_GREG_IPI_VECTOR_PRI_0,
110 TSI108_GREG_IPI_STRIDE,
111 TSI108_GREG_SPURIOUS,
112 TSI108_GREG_TIMER_FREQ,
113
114 TSI108_TIMER_BASE,
115 TSI108_TIMER_STRIDE,
116 TSI108_TIMER_CURRENT_CNT,
117 TSI108_TIMER_BASE_CNT,
118 TSI108_TIMER_VECTOR_PRI,
119 TSI108_TIMER_DESTINATION,
120
121 TSI108_CPU_BASE,
122 TSI108_CPU_STRIDE,
123 TSI108_CPU_IPI_DISPATCH_0,
124 TSI108_CPU_IPI_DISPATCH_STRIDE,
125 TSI108_CPU_CURRENT_TASK_PRI,
126 TSI108_CPU_WHOAMI,
127 TSI108_CPU_INTACK,
128 TSI108_CPU_EOI,
129 TSI108_CPU_MCACK,
130
131 TSI108_IRQ_BASE,
132 TSI108_IRQ_STRIDE,
133 TSI108_IRQ_VECTOR_PRI,
134 TSI108_VECPRI_VECTOR_MASK,
135 TSI108_VECPRI_POLARITY_POSITIVE,
136 TSI108_VECPRI_POLARITY_NEGATIVE,
137 TSI108_VECPRI_SENSE_LEVEL,
138 TSI108_VECPRI_SENSE_EDGE,
139 TSI108_VECPRI_POLARITY_MASK,
140 TSI108_VECPRI_SENSE_MASK,
141 TSI108_IRQ_DESTINATION
142 },
143 };
144
145 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
146
147 #else /* CONFIG_MPIC_WEIRD */
148
149 #define MPIC_INFO(name) MPIC_##name
150
151 #endif /* CONFIG_MPIC_WEIRD */
152
153 static inline unsigned int mpic_processor_id(struct mpic *mpic)
154 {
155 unsigned int cpu = 0;
156
157 if (mpic->flags & MPIC_PRIMARY)
158 cpu = hard_smp_processor_id();
159
160 return cpu;
161 }
162
163 /*
164 * Register accessor functions
165 */
166
167
168 static inline u32 _mpic_read(enum mpic_reg_type type,
169 struct mpic_reg_bank *rb,
170 unsigned int reg)
171 {
172 switch(type) {
173 #ifdef CONFIG_PPC_DCR
174 case mpic_access_dcr:
175 return dcr_read(rb->dhost, reg);
176 #endif
177 case mpic_access_mmio_be:
178 return in_be32(rb->base + (reg >> 2));
179 case mpic_access_mmio_le:
180 default:
181 return in_le32(rb->base + (reg >> 2));
182 }
183 }
184
185 static inline void _mpic_write(enum mpic_reg_type type,
186 struct mpic_reg_bank *rb,
187 unsigned int reg, u32 value)
188 {
189 switch(type) {
190 #ifdef CONFIG_PPC_DCR
191 case mpic_access_dcr:
192 dcr_write(rb->dhost, reg, value);
193 break;
194 #endif
195 case mpic_access_mmio_be:
196 out_be32(rb->base + (reg >> 2), value);
197 break;
198 case mpic_access_mmio_le:
199 default:
200 out_le32(rb->base + (reg >> 2), value);
201 break;
202 }
203 }
204
205 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
206 {
207 enum mpic_reg_type type = mpic->reg_type;
208 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
209 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
210
211 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
212 type = mpic_access_mmio_be;
213 return _mpic_read(type, &mpic->gregs, offset);
214 }
215
216 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
217 {
218 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
219 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
220
221 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
222 }
223
224 static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
225 {
226 unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
227 ((tm & 3) * MPIC_INFO(TIMER_STRIDE));
228
229 if (tm >= 4)
230 offset += 0x1000 / 4;
231
232 return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
233 }
234
235 static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
236 {
237 unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
238 ((tm & 3) * MPIC_INFO(TIMER_STRIDE));
239
240 if (tm >= 4)
241 offset += 0x1000 / 4;
242
243 _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
244 }
245
246 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
247 {
248 unsigned int cpu = mpic_processor_id(mpic);
249
250 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
251 }
252
253 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
254 {
255 unsigned int cpu = mpic_processor_id(mpic);
256
257 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
258 }
259
260 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
261 {
262 unsigned int isu = src_no >> mpic->isu_shift;
263 unsigned int idx = src_no & mpic->isu_mask;
264 unsigned int val;
265
266 val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
267 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
268 #ifdef CONFIG_MPIC_BROKEN_REGREAD
269 if (reg == 0)
270 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
271 mpic->isu_reg0_shadow[src_no];
272 #endif
273 return val;
274 }
275
276 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
277 unsigned int reg, u32 value)
278 {
279 unsigned int isu = src_no >> mpic->isu_shift;
280 unsigned int idx = src_no & mpic->isu_mask;
281
282 _mpic_write(mpic->reg_type, &mpic->isus[isu],
283 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
284
285 #ifdef CONFIG_MPIC_BROKEN_REGREAD
286 if (reg == 0)
287 mpic->isu_reg0_shadow[src_no] =
288 value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
289 #endif
290 }
291
292 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
293 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
294 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
295 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
296 #define mpic_tm_read(i) _mpic_tm_read(mpic,(i))
297 #define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v))
298 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
299 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
300 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
301 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
302
303
304 /*
305 * Low level utility functions
306 */
307
308
309 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
310 struct mpic_reg_bank *rb, unsigned int offset,
311 unsigned int size)
312 {
313 rb->base = ioremap(phys_addr + offset, size);
314 BUG_ON(rb->base == NULL);
315 }
316
317 #ifdef CONFIG_PPC_DCR
318 static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node,
319 struct mpic_reg_bank *rb,
320 unsigned int offset, unsigned int size)
321 {
322 const u32 *dbasep;
323
324 dbasep = of_get_property(node, "dcr-reg", NULL);
325
326 rb->dhost = dcr_map(node, *dbasep + offset, size);
327 BUG_ON(!DCR_MAP_OK(rb->dhost));
328 }
329
330 static inline void mpic_map(struct mpic *mpic, struct device_node *node,
331 phys_addr_t phys_addr, struct mpic_reg_bank *rb,
332 unsigned int offset, unsigned int size)
333 {
334 if (mpic->flags & MPIC_USES_DCR)
335 _mpic_map_dcr(mpic, node, rb, offset, size);
336 else
337 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
338 }
339 #else /* CONFIG_PPC_DCR */
340 #define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
341 #endif /* !CONFIG_PPC_DCR */
342
343
344
345 /* Check if we have one of those nice broken MPICs with a flipped endian on
346 * reads from IPI registers
347 */
348 static void __init mpic_test_broken_ipi(struct mpic *mpic)
349 {
350 u32 r;
351
352 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
353 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
354
355 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
356 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
357 mpic->flags |= MPIC_BROKEN_IPI;
358 }
359 }
360
361 #ifdef CONFIG_MPIC_U3_HT_IRQS
362
363 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
364 * to force the edge setting on the MPIC and do the ack workaround.
365 */
366 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
367 {
368 if (source >= 128 || !mpic->fixups)
369 return 0;
370 return mpic->fixups[source].base != NULL;
371 }
372
373
374 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
375 {
376 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
377
378 if (fixup->applebase) {
379 unsigned int soff = (fixup->index >> 3) & ~3;
380 unsigned int mask = 1U << (fixup->index & 0x1f);
381 writel(mask, fixup->applebase + soff);
382 } else {
383 raw_spin_lock(&mpic->fixup_lock);
384 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
385 writel(fixup->data, fixup->base + 4);
386 raw_spin_unlock(&mpic->fixup_lock);
387 }
388 }
389
390 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
391 bool level)
392 {
393 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
394 unsigned long flags;
395 u32 tmp;
396
397 if (fixup->base == NULL)
398 return;
399
400 DBG("startup_ht_interrupt(0x%x) index: %d\n",
401 source, fixup->index);
402 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
403 /* Enable and configure */
404 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
405 tmp = readl(fixup->base + 4);
406 tmp &= ~(0x23U);
407 if (level)
408 tmp |= 0x22;
409 writel(tmp, fixup->base + 4);
410 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
411
412 #ifdef CONFIG_PM
413 /* use the lowest bit inverted to the actual HW,
414 * set if this fixup was enabled, clear otherwise */
415 mpic->save_data[source].fixup_data = tmp | 1;
416 #endif
417 }
418
419 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
420 {
421 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
422 unsigned long flags;
423 u32 tmp;
424
425 if (fixup->base == NULL)
426 return;
427
428 DBG("shutdown_ht_interrupt(0x%x)\n", source);
429
430 /* Disable */
431 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
432 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
433 tmp = readl(fixup->base + 4);
434 tmp |= 1;
435 writel(tmp, fixup->base + 4);
436 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
437
438 #ifdef CONFIG_PM
439 /* use the lowest bit inverted to the actual HW,
440 * set if this fixup was enabled, clear otherwise */
441 mpic->save_data[source].fixup_data = tmp & ~1;
442 #endif
443 }
444
445 #ifdef CONFIG_PCI_MSI
446 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
447 unsigned int devfn)
448 {
449 u8 __iomem *base;
450 u8 pos, flags;
451 u64 addr = 0;
452
453 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
454 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
455 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
456 if (id == PCI_CAP_ID_HT) {
457 id = readb(devbase + pos + 3);
458 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
459 break;
460 }
461 }
462
463 if (pos == 0)
464 return;
465
466 base = devbase + pos;
467
468 flags = readb(base + HT_MSI_FLAGS);
469 if (!(flags & HT_MSI_FLAGS_FIXED)) {
470 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
471 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
472 }
473
474 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
475 PCI_SLOT(devfn), PCI_FUNC(devfn),
476 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
477
478 if (!(flags & HT_MSI_FLAGS_ENABLE))
479 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
480 }
481 #else
482 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
483 unsigned int devfn)
484 {
485 return;
486 }
487 #endif
488
489 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
490 unsigned int devfn, u32 vdid)
491 {
492 int i, irq, n;
493 u8 __iomem *base;
494 u32 tmp;
495 u8 pos;
496
497 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
498 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
499 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
500 if (id == PCI_CAP_ID_HT) {
501 id = readb(devbase + pos + 3);
502 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
503 break;
504 }
505 }
506 if (pos == 0)
507 return;
508
509 base = devbase + pos;
510 writeb(0x01, base + 2);
511 n = (readl(base + 4) >> 16) & 0xff;
512
513 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
514 " has %d irqs\n",
515 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
516
517 for (i = 0; i <= n; i++) {
518 writeb(0x10 + 2 * i, base + 2);
519 tmp = readl(base + 4);
520 irq = (tmp >> 16) & 0xff;
521 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
522 /* mask it , will be unmasked later */
523 tmp |= 0x1;
524 writel(tmp, base + 4);
525 mpic->fixups[irq].index = i;
526 mpic->fixups[irq].base = base;
527 /* Apple HT PIC has a non-standard way of doing EOIs */
528 if ((vdid & 0xffff) == 0x106b)
529 mpic->fixups[irq].applebase = devbase + 0x60;
530 else
531 mpic->fixups[irq].applebase = NULL;
532 writeb(0x11 + 2 * i, base + 2);
533 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
534 }
535 }
536
537
538 static void __init mpic_scan_ht_pics(struct mpic *mpic)
539 {
540 unsigned int devfn;
541 u8 __iomem *cfgspace;
542
543 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
544
545 /* Allocate fixups array */
546 mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
547 BUG_ON(mpic->fixups == NULL);
548
549 /* Init spinlock */
550 raw_spin_lock_init(&mpic->fixup_lock);
551
552 /* Map U3 config space. We assume all IO-APICs are on the primary bus
553 * so we only need to map 64kB.
554 */
555 cfgspace = ioremap(0xf2000000, 0x10000);
556 BUG_ON(cfgspace == NULL);
557
558 /* Now we scan all slots. We do a very quick scan, we read the header
559 * type, vendor ID and device ID only, that's plenty enough
560 */
561 for (devfn = 0; devfn < 0x100; devfn++) {
562 u8 __iomem *devbase = cfgspace + (devfn << 8);
563 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
564 u32 l = readl(devbase + PCI_VENDOR_ID);
565 u16 s;
566
567 DBG("devfn %x, l: %x\n", devfn, l);
568
569 /* If no device, skip */
570 if (l == 0xffffffff || l == 0x00000000 ||
571 l == 0x0000ffff || l == 0xffff0000)
572 goto next;
573 /* Check if is supports capability lists */
574 s = readw(devbase + PCI_STATUS);
575 if (!(s & PCI_STATUS_CAP_LIST))
576 goto next;
577
578 mpic_scan_ht_pic(mpic, devbase, devfn, l);
579 mpic_scan_ht_msi(mpic, devbase, devfn);
580
581 next:
582 /* next device, if function 0 */
583 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
584 devfn += 7;
585 }
586 }
587
588 #else /* CONFIG_MPIC_U3_HT_IRQS */
589
590 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
591 {
592 return 0;
593 }
594
595 static void __init mpic_scan_ht_pics(struct mpic *mpic)
596 {
597 }
598
599 #endif /* CONFIG_MPIC_U3_HT_IRQS */
600
601 /* Find an mpic associated with a given linux interrupt */
602 static struct mpic *mpic_find(unsigned int irq)
603 {
604 if (irq < NUM_ISA_INTERRUPTS)
605 return NULL;
606
607 return irq_get_chip_data(irq);
608 }
609
610 /* Determine if the linux irq is an IPI */
611 static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
612 {
613 unsigned int src = virq_to_hw(irq);
614
615 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
616 }
617
618 /* Determine if the linux irq is a timer */
619 static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq)
620 {
621 unsigned int src = virq_to_hw(irq);
622
623 return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
624 }
625
626 /* Convert a cpu mask from logical to physical cpu numbers. */
627 static inline u32 mpic_physmask(u32 cpumask)
628 {
629 int i;
630 u32 mask = 0;
631
632 for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1)
633 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
634 return mask;
635 }
636
637 #ifdef CONFIG_SMP
638 /* Get the mpic structure from the IPI number */
639 static inline struct mpic * mpic_from_ipi(struct irq_data *d)
640 {
641 return irq_data_get_irq_chip_data(d);
642 }
643 #endif
644
645 /* Get the mpic structure from the irq number */
646 static inline struct mpic * mpic_from_irq(unsigned int irq)
647 {
648 return irq_get_chip_data(irq);
649 }
650
651 /* Get the mpic structure from the irq data */
652 static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
653 {
654 return irq_data_get_irq_chip_data(d);
655 }
656
657 /* Send an EOI */
658 static inline void mpic_eoi(struct mpic *mpic)
659 {
660 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
661 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
662 }
663
664 /*
665 * Linux descriptor level callbacks
666 */
667
668
669 void mpic_unmask_irq(struct irq_data *d)
670 {
671 unsigned int loops = 100000;
672 struct mpic *mpic = mpic_from_irq_data(d);
673 unsigned int src = irqd_to_hwirq(d);
674
675 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
676
677 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
678 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
679 ~MPIC_VECPRI_MASK);
680 /* make sure mask gets to controller before we return to user */
681 do {
682 if (!loops--) {
683 printk(KERN_ERR "%s: timeout on hwirq %u\n",
684 __func__, src);
685 break;
686 }
687 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
688 }
689
690 void mpic_mask_irq(struct irq_data *d)
691 {
692 unsigned int loops = 100000;
693 struct mpic *mpic = mpic_from_irq_data(d);
694 unsigned int src = irqd_to_hwirq(d);
695
696 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
697
698 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
699 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
700 MPIC_VECPRI_MASK);
701
702 /* make sure mask gets to controller before we return to user */
703 do {
704 if (!loops--) {
705 printk(KERN_ERR "%s: timeout on hwirq %u\n",
706 __func__, src);
707 break;
708 }
709 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
710 }
711
712 void mpic_end_irq(struct irq_data *d)
713 {
714 struct mpic *mpic = mpic_from_irq_data(d);
715
716 #ifdef DEBUG_IRQ
717 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
718 #endif
719 /* We always EOI on end_irq() even for edge interrupts since that
720 * should only lower the priority, the MPIC should have properly
721 * latched another edge interrupt coming in anyway
722 */
723
724 mpic_eoi(mpic);
725 }
726
727 #ifdef CONFIG_MPIC_U3_HT_IRQS
728
729 static void mpic_unmask_ht_irq(struct irq_data *d)
730 {
731 struct mpic *mpic = mpic_from_irq_data(d);
732 unsigned int src = irqd_to_hwirq(d);
733
734 mpic_unmask_irq(d);
735
736 if (irqd_is_level_type(d))
737 mpic_ht_end_irq(mpic, src);
738 }
739
740 static unsigned int mpic_startup_ht_irq(struct irq_data *d)
741 {
742 struct mpic *mpic = mpic_from_irq_data(d);
743 unsigned int src = irqd_to_hwirq(d);
744
745 mpic_unmask_irq(d);
746 mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
747
748 return 0;
749 }
750
751 static void mpic_shutdown_ht_irq(struct irq_data *d)
752 {
753 struct mpic *mpic = mpic_from_irq_data(d);
754 unsigned int src = irqd_to_hwirq(d);
755
756 mpic_shutdown_ht_interrupt(mpic, src);
757 mpic_mask_irq(d);
758 }
759
760 static void mpic_end_ht_irq(struct irq_data *d)
761 {
762 struct mpic *mpic = mpic_from_irq_data(d);
763 unsigned int src = irqd_to_hwirq(d);
764
765 #ifdef DEBUG_IRQ
766 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
767 #endif
768 /* We always EOI on end_irq() even for edge interrupts since that
769 * should only lower the priority, the MPIC should have properly
770 * latched another edge interrupt coming in anyway
771 */
772
773 if (irqd_is_level_type(d))
774 mpic_ht_end_irq(mpic, src);
775 mpic_eoi(mpic);
776 }
777 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
778
779 #ifdef CONFIG_SMP
780
781 static void mpic_unmask_ipi(struct irq_data *d)
782 {
783 struct mpic *mpic = mpic_from_ipi(d);
784 unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
785
786 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
787 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
788 }
789
790 static void mpic_mask_ipi(struct irq_data *d)
791 {
792 /* NEVER disable an IPI... that's just plain wrong! */
793 }
794
795 static void mpic_end_ipi(struct irq_data *d)
796 {
797 struct mpic *mpic = mpic_from_ipi(d);
798
799 /*
800 * IPIs are marked IRQ_PER_CPU. This has the side effect of
801 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
802 * applying to them. We EOI them late to avoid re-entering.
803 * We mark IPI's with IRQF_DISABLED as they must run with
804 * irqs disabled.
805 */
806 mpic_eoi(mpic);
807 }
808
809 #endif /* CONFIG_SMP */
810
811 static void mpic_unmask_tm(struct irq_data *d)
812 {
813 struct mpic *mpic = mpic_from_irq_data(d);
814 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
815
816 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src);
817 mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
818 mpic_tm_read(src);
819 }
820
821 static void mpic_mask_tm(struct irq_data *d)
822 {
823 struct mpic *mpic = mpic_from_irq_data(d);
824 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
825
826 mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK);
827 mpic_tm_read(src);
828 }
829
830 int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
831 bool force)
832 {
833 struct mpic *mpic = mpic_from_irq_data(d);
834 unsigned int src = irqd_to_hwirq(d);
835
836 if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
837 int cpuid = irq_choose_cpu(cpumask);
838
839 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
840 } else {
841 u32 mask = cpumask_bits(cpumask)[0];
842
843 mask &= cpumask_bits(cpu_online_mask)[0];
844
845 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
846 mpic_physmask(mask));
847 }
848
849 return 0;
850 }
851
852 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
853 {
854 /* Now convert sense value */
855 switch(type & IRQ_TYPE_SENSE_MASK) {
856 case IRQ_TYPE_EDGE_RISING:
857 return MPIC_INFO(VECPRI_SENSE_EDGE) |
858 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
859 case IRQ_TYPE_EDGE_FALLING:
860 case IRQ_TYPE_EDGE_BOTH:
861 return MPIC_INFO(VECPRI_SENSE_EDGE) |
862 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
863 case IRQ_TYPE_LEVEL_HIGH:
864 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
865 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
866 case IRQ_TYPE_LEVEL_LOW:
867 default:
868 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
869 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
870 }
871 }
872
873 int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
874 {
875 struct mpic *mpic = mpic_from_irq_data(d);
876 unsigned int src = irqd_to_hwirq(d);
877 unsigned int vecpri, vold, vnew;
878
879 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
880 mpic, d->irq, src, flow_type);
881
882 if (src >= mpic->irq_count)
883 return -EINVAL;
884
885 if (flow_type == IRQ_TYPE_NONE)
886 if (mpic->senses && src < mpic->senses_count)
887 flow_type = mpic->senses[src];
888 if (flow_type == IRQ_TYPE_NONE)
889 flow_type = IRQ_TYPE_LEVEL_LOW;
890
891 irqd_set_trigger_type(d, flow_type);
892
893 if (mpic_is_ht_interrupt(mpic, src))
894 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
895 MPIC_VECPRI_SENSE_EDGE;
896 else
897 vecpri = mpic_type_to_vecpri(mpic, flow_type);
898
899 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
900 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
901 MPIC_INFO(VECPRI_SENSE_MASK));
902 vnew |= vecpri;
903 if (vold != vnew)
904 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
905
906 return IRQ_SET_MASK_OK_NOCOPY;;
907 }
908
909 void mpic_set_vector(unsigned int virq, unsigned int vector)
910 {
911 struct mpic *mpic = mpic_from_irq(virq);
912 unsigned int src = virq_to_hw(virq);
913 unsigned int vecpri;
914
915 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
916 mpic, virq, src, vector);
917
918 if (src >= mpic->irq_count)
919 return;
920
921 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
922 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
923 vecpri |= vector;
924 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
925 }
926
927 void mpic_set_destination(unsigned int virq, unsigned int cpuid)
928 {
929 struct mpic *mpic = mpic_from_irq(virq);
930 unsigned int src = virq_to_hw(virq);
931
932 DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
933 mpic, virq, src, cpuid);
934
935 if (src >= mpic->irq_count)
936 return;
937
938 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
939 }
940
941 static struct irq_chip mpic_irq_chip = {
942 .irq_mask = mpic_mask_irq,
943 .irq_unmask = mpic_unmask_irq,
944 .irq_eoi = mpic_end_irq,
945 .irq_set_type = mpic_set_irq_type,
946 };
947
948 #ifdef CONFIG_SMP
949 static struct irq_chip mpic_ipi_chip = {
950 .irq_mask = mpic_mask_ipi,
951 .irq_unmask = mpic_unmask_ipi,
952 .irq_eoi = mpic_end_ipi,
953 };
954 #endif /* CONFIG_SMP */
955
956 static struct irq_chip mpic_tm_chip = {
957 .irq_mask = mpic_mask_tm,
958 .irq_unmask = mpic_unmask_tm,
959 .irq_eoi = mpic_end_irq,
960 };
961
962 #ifdef CONFIG_MPIC_U3_HT_IRQS
963 static struct irq_chip mpic_irq_ht_chip = {
964 .irq_startup = mpic_startup_ht_irq,
965 .irq_shutdown = mpic_shutdown_ht_irq,
966 .irq_mask = mpic_mask_irq,
967 .irq_unmask = mpic_unmask_ht_irq,
968 .irq_eoi = mpic_end_ht_irq,
969 .irq_set_type = mpic_set_irq_type,
970 };
971 #endif /* CONFIG_MPIC_U3_HT_IRQS */
972
973
974 static int mpic_host_match(struct irq_host *h, struct device_node *node)
975 {
976 /* Exact match, unless mpic node is NULL */
977 return h->of_node == NULL || h->of_node == node;
978 }
979
980 static int mpic_host_map(struct irq_host *h, unsigned int virq,
981 irq_hw_number_t hw)
982 {
983 struct mpic *mpic = h->host_data;
984 struct irq_chip *chip;
985
986 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
987
988 if (hw == mpic->spurious_vec)
989 return -EINVAL;
990 if (mpic->protected && test_bit(hw, mpic->protected))
991 return -EINVAL;
992
993 #ifdef CONFIG_SMP
994 else if (hw >= mpic->ipi_vecs[0]) {
995 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
996
997 DBG("mpic: mapping as IPI\n");
998 irq_set_chip_data(virq, mpic);
999 irq_set_chip_and_handler(virq, &mpic->hc_ipi,
1000 handle_percpu_irq);
1001 return 0;
1002 }
1003 #endif /* CONFIG_SMP */
1004
1005 if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
1006 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
1007
1008 DBG("mpic: mapping as timer\n");
1009 irq_set_chip_data(virq, mpic);
1010 irq_set_chip_and_handler(virq, &mpic->hc_tm,
1011 handle_fasteoi_irq);
1012 return 0;
1013 }
1014
1015 if (hw >= mpic->irq_count)
1016 return -EINVAL;
1017
1018 mpic_msi_reserve_hwirq(mpic, hw);
1019
1020 /* Default chip */
1021 chip = &mpic->hc_irq;
1022
1023 #ifdef CONFIG_MPIC_U3_HT_IRQS
1024 /* Check for HT interrupts, override vecpri */
1025 if (mpic_is_ht_interrupt(mpic, hw))
1026 chip = &mpic->hc_ht_irq;
1027 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1028
1029 DBG("mpic: mapping to irq chip @%p\n", chip);
1030
1031 irq_set_chip_data(virq, mpic);
1032 irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
1033
1034 /* Set default irq type */
1035 irq_set_irq_type(virq, IRQ_TYPE_NONE);
1036
1037 /* If the MPIC was reset, then all vectors have already been
1038 * initialized. Otherwise, a per source lazy initialization
1039 * is done here.
1040 */
1041 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1042 mpic_set_vector(virq, hw);
1043 mpic_set_destination(virq, mpic_processor_id(mpic));
1044 mpic_irq_set_priority(virq, 8);
1045 }
1046
1047 return 0;
1048 }
1049
1050 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
1051 const u32 *intspec, unsigned int intsize,
1052 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1053
1054 {
1055 struct mpic *mpic = h->host_data;
1056 static unsigned char map_mpic_senses[4] = {
1057 IRQ_TYPE_EDGE_RISING,
1058 IRQ_TYPE_LEVEL_LOW,
1059 IRQ_TYPE_LEVEL_HIGH,
1060 IRQ_TYPE_EDGE_FALLING,
1061 };
1062
1063 *out_hwirq = intspec[0];
1064 if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
1065 /*
1066 * Freescale MPIC with extended intspec:
1067 * First two cells are as usual. Third specifies
1068 * an "interrupt type". Fourth is type-specific data.
1069 *
1070 * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
1071 */
1072 switch (intspec[2]) {
1073 case 0:
1074 case 1: /* no EISR/EIMR support for now, treat as shared IRQ */
1075 break;
1076 case 2:
1077 if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
1078 return -EINVAL;
1079
1080 *out_hwirq = mpic->ipi_vecs[intspec[0]];
1081 break;
1082 case 3:
1083 if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
1084 return -EINVAL;
1085
1086 *out_hwirq = mpic->timer_vecs[intspec[0]];
1087 break;
1088 default:
1089 pr_debug("%s: unknown irq type %u\n",
1090 __func__, intspec[2]);
1091 return -EINVAL;
1092 }
1093
1094 *out_flags = map_mpic_senses[intspec[1] & 3];
1095 } else if (intsize > 1) {
1096 u32 mask = 0x3;
1097
1098 /* Apple invented a new race of encoding on machines with
1099 * an HT APIC. They encode, among others, the index within
1100 * the HT APIC. We don't care about it here since thankfully,
1101 * it appears that they have the APIC already properly
1102 * configured, and thus our current fixup code that reads the
1103 * APIC config works fine. However, we still need to mask out
1104 * bits in the specifier to make sure we only get bit 0 which
1105 * is the level/edge bit (the only sense bit exposed by Apple),
1106 * as their bit 1 means something else.
1107 */
1108 if (machine_is(powermac))
1109 mask = 0x1;
1110 *out_flags = map_mpic_senses[intspec[1] & mask];
1111 } else
1112 *out_flags = IRQ_TYPE_NONE;
1113
1114 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1115 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1116
1117 return 0;
1118 }
1119
1120 static struct irq_host_ops mpic_host_ops = {
1121 .match = mpic_host_match,
1122 .map = mpic_host_map,
1123 .xlate = mpic_host_xlate,
1124 };
1125
1126 static int mpic_reset_prohibited(struct device_node *node)
1127 {
1128 return node && of_get_property(node, "pic-no-reset", NULL);
1129 }
1130
1131 /*
1132 * Exported functions
1133 */
1134
1135 struct mpic * __init mpic_alloc(struct device_node *node,
1136 phys_addr_t phys_addr,
1137 unsigned int flags,
1138 unsigned int isu_size,
1139 unsigned int irq_count,
1140 const char *name)
1141 {
1142 struct mpic *mpic;
1143 u32 greg_feature;
1144 const char *vers;
1145 int i;
1146 int intvec_top;
1147 u64 paddr = phys_addr;
1148
1149 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1150 if (mpic == NULL)
1151 return NULL;
1152
1153 mpic->name = name;
1154
1155 mpic->hc_irq = mpic_irq_chip;
1156 mpic->hc_irq.name = name;
1157 if (flags & MPIC_PRIMARY)
1158 mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1159 #ifdef CONFIG_MPIC_U3_HT_IRQS
1160 mpic->hc_ht_irq = mpic_irq_ht_chip;
1161 mpic->hc_ht_irq.name = name;
1162 if (flags & MPIC_PRIMARY)
1163 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1164 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1165
1166 #ifdef CONFIG_SMP
1167 mpic->hc_ipi = mpic_ipi_chip;
1168 mpic->hc_ipi.name = name;
1169 #endif /* CONFIG_SMP */
1170
1171 mpic->hc_tm = mpic_tm_chip;
1172 mpic->hc_tm.name = name;
1173
1174 mpic->flags = flags;
1175 mpic->isu_size = isu_size;
1176 mpic->irq_count = irq_count;
1177 mpic->num_sources = 0; /* so far */
1178
1179 if (flags & MPIC_LARGE_VECTORS)
1180 intvec_top = 2047;
1181 else
1182 intvec_top = 255;
1183
1184 mpic->timer_vecs[0] = intvec_top - 12;
1185 mpic->timer_vecs[1] = intvec_top - 11;
1186 mpic->timer_vecs[2] = intvec_top - 10;
1187 mpic->timer_vecs[3] = intvec_top - 9;
1188 mpic->timer_vecs[4] = intvec_top - 8;
1189 mpic->timer_vecs[5] = intvec_top - 7;
1190 mpic->timer_vecs[6] = intvec_top - 6;
1191 mpic->timer_vecs[7] = intvec_top - 5;
1192 mpic->ipi_vecs[0] = intvec_top - 4;
1193 mpic->ipi_vecs[1] = intvec_top - 3;
1194 mpic->ipi_vecs[2] = intvec_top - 2;
1195 mpic->ipi_vecs[3] = intvec_top - 1;
1196 mpic->spurious_vec = intvec_top;
1197
1198 /* Check for "big-endian" in device-tree */
1199 if (node && of_get_property(node, "big-endian", NULL) != NULL)
1200 mpic->flags |= MPIC_BIG_ENDIAN;
1201 if (node && of_device_is_compatible(node, "fsl,mpic"))
1202 mpic->flags |= MPIC_FSL;
1203
1204 /* Look for protected sources */
1205 if (node) {
1206 int psize;
1207 unsigned int bits, mapsize;
1208 const u32 *psrc =
1209 of_get_property(node, "protected-sources", &psize);
1210 if (psrc) {
1211 psize /= 4;
1212 bits = intvec_top + 1;
1213 mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);
1214 mpic->protected = kzalloc(mapsize, GFP_KERNEL);
1215 BUG_ON(mpic->protected == NULL);
1216 for (i = 0; i < psize; i++) {
1217 if (psrc[i] > intvec_top)
1218 continue;
1219 __set_bit(psrc[i], mpic->protected);
1220 }
1221 }
1222 }
1223
1224 #ifdef CONFIG_MPIC_WEIRD
1225 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
1226 #endif
1227
1228 /* default register type */
1229 mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
1230 mpic_access_mmio_be : mpic_access_mmio_le;
1231
1232 /* If no physical address is passed in, a device-node is mandatory */
1233 BUG_ON(paddr == 0 && node == NULL);
1234
1235 /* If no physical address passed in, check if it's dcr based */
1236 if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {
1237 #ifdef CONFIG_PPC_DCR
1238 mpic->flags |= MPIC_USES_DCR;
1239 mpic->reg_type = mpic_access_dcr;
1240 #else
1241 BUG();
1242 #endif /* CONFIG_PPC_DCR */
1243 }
1244
1245 /* If the MPIC is not DCR based, and no physical address was passed
1246 * in, try to obtain one
1247 */
1248 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1249 const u32 *reg = of_get_property(node, "reg", NULL);
1250 BUG_ON(reg == NULL);
1251 paddr = of_translate_address(node, reg);
1252 BUG_ON(paddr == OF_BAD_ADDR);
1253 }
1254
1255 /* Map the global registers */
1256 mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1257 mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1258
1259 /* Reset */
1260
1261 /* When using a device-node, reset requests are only honored if the MPIC
1262 * is allowed to reset.
1263 */
1264 if (mpic_reset_prohibited(node))
1265 mpic->flags |= MPIC_NO_RESET;
1266
1267 if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) {
1268 printk(KERN_DEBUG "mpic: Resetting\n");
1269 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1270 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1271 | MPIC_GREG_GCONF_RESET);
1272 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1273 & MPIC_GREG_GCONF_RESET)
1274 mb();
1275 }
1276
1277 /* CoreInt */
1278 if (flags & MPIC_ENABLE_COREINT)
1279 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1280 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1281 | MPIC_GREG_GCONF_COREINT);
1282
1283 if (flags & MPIC_ENABLE_MCK)
1284 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1285 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1286 | MPIC_GREG_GCONF_MCK);
1287
1288 /* Read feature register, calculate num CPUs and, for non-ISU
1289 * MPICs, num sources as well. On ISU MPICs, sources are counted
1290 * as ISUs are added
1291 */
1292 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1293 mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK)
1294 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
1295 if (isu_size == 0) {
1296 if (flags & MPIC_BROKEN_FRR_NIRQS)
1297 mpic->num_sources = mpic->irq_count;
1298 else
1299 mpic->num_sources =
1300 ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1301 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1302 }
1303
1304 /* Map the per-CPU registers */
1305 for (i = 0; i < mpic->num_cpus; i++) {
1306 mpic_map(mpic, node, paddr, &mpic->cpuregs[i],
1307 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
1308 0x1000);
1309 }
1310
1311 /* Initialize main ISU if none provided */
1312 if (mpic->isu_size == 0) {
1313 mpic->isu_size = mpic->num_sources;
1314 mpic_map(mpic, node, paddr, &mpic->isus[0],
1315 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1316 }
1317 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1318 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1319
1320 mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
1321 isu_size ? isu_size : mpic->num_sources,
1322 &mpic_host_ops,
1323 flags & MPIC_LARGE_VECTORS ? 2048 : 256);
1324 if (mpic->irqhost == NULL)
1325 return NULL;
1326
1327 mpic->irqhost->host_data = mpic;
1328
1329 /* Display version */
1330 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1331 case 1:
1332 vers = "1.0";
1333 break;
1334 case 2:
1335 vers = "1.2";
1336 break;
1337 case 3:
1338 vers = "1.3";
1339 break;
1340 default:
1341 vers = "<unknown>";
1342 break;
1343 }
1344 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1345 " max %d CPUs\n",
1346 name, vers, (unsigned long long)paddr, mpic->num_cpus);
1347 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1348 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1349
1350 mpic->next = mpics;
1351 mpics = mpic;
1352
1353 if (flags & MPIC_PRIMARY) {
1354 mpic_primary = mpic;
1355 irq_set_default_host(mpic->irqhost);
1356 }
1357
1358 return mpic;
1359 }
1360
1361 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1362 phys_addr_t paddr)
1363 {
1364 unsigned int isu_first = isu_num * mpic->isu_size;
1365
1366 BUG_ON(isu_num >= MPIC_MAX_ISU);
1367
1368 mpic_map(mpic, mpic->irqhost->of_node,
1369 paddr, &mpic->isus[isu_num], 0,
1370 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1371
1372 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1373 mpic->num_sources = isu_first + mpic->isu_size;
1374 }
1375
1376 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
1377 {
1378 mpic->senses = senses;
1379 mpic->senses_count = count;
1380 }
1381
1382 void __init mpic_init(struct mpic *mpic)
1383 {
1384 int i;
1385 int cpu;
1386
1387 BUG_ON(mpic->num_sources == 0);
1388
1389 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1390
1391 /* Set current processor priority to max */
1392 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1393
1394 /* Initialize timers to our reserved vectors and mask them for now */
1395 for (i = 0; i < 4; i++) {
1396 mpic_write(mpic->tmregs,
1397 i * MPIC_INFO(TIMER_STRIDE) +
1398 MPIC_INFO(TIMER_DESTINATION),
1399 1 << hard_smp_processor_id());
1400 mpic_write(mpic->tmregs,
1401 i * MPIC_INFO(TIMER_STRIDE) +
1402 MPIC_INFO(TIMER_VECTOR_PRI),
1403 MPIC_VECPRI_MASK |
1404 (9 << MPIC_VECPRI_PRIORITY_SHIFT) |
1405 (mpic->timer_vecs[0] + i));
1406 }
1407
1408 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1409 mpic_test_broken_ipi(mpic);
1410 for (i = 0; i < 4; i++) {
1411 mpic_ipi_write(i,
1412 MPIC_VECPRI_MASK |
1413 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1414 (mpic->ipi_vecs[0] + i));
1415 }
1416
1417 /* Initialize interrupt sources */
1418 if (mpic->irq_count == 0)
1419 mpic->irq_count = mpic->num_sources;
1420
1421 /* Do the HT PIC fixups on U3 broken mpic */
1422 DBG("MPIC flags: %x\n", mpic->flags);
1423 if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
1424 mpic_scan_ht_pics(mpic);
1425 mpic_u3msi_init(mpic);
1426 }
1427
1428 mpic_pasemi_msi_init(mpic);
1429
1430 cpu = mpic_processor_id(mpic);
1431
1432 if (!(mpic->flags & MPIC_NO_RESET)) {
1433 for (i = 0; i < mpic->num_sources; i++) {
1434 /* start with vector = source number, and masked */
1435 u32 vecpri = MPIC_VECPRI_MASK | i |
1436 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1437
1438 /* check if protected */
1439 if (mpic->protected && test_bit(i, mpic->protected))
1440 continue;
1441 /* init hw */
1442 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1443 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1444 }
1445 }
1446
1447 /* Init spurious vector */
1448 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1449
1450 /* Disable 8259 passthrough, if supported */
1451 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1452 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1453 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1454 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1455
1456 if (mpic->flags & MPIC_NO_BIAS)
1457 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1458 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1459 | MPIC_GREG_GCONF_NO_BIAS);
1460
1461 /* Set current processor priority to 0 */
1462 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1463
1464 #ifdef CONFIG_PM
1465 /* allocate memory to save mpic state */
1466 mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
1467 GFP_KERNEL);
1468 BUG_ON(mpic->save_data == NULL);
1469 #endif
1470 }
1471
1472 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1473 {
1474 u32 v;
1475
1476 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1477 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1478 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1479 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1480 }
1481
1482 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1483 {
1484 unsigned long flags;
1485 u32 v;
1486
1487 raw_spin_lock_irqsave(&mpic_lock, flags);
1488 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1489 if (enable)
1490 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1491 else
1492 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1493 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1494 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1495 }
1496
1497 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1498 {
1499 struct mpic *mpic = mpic_find(irq);
1500 unsigned int src = virq_to_hw(irq);
1501 unsigned long flags;
1502 u32 reg;
1503
1504 if (!mpic)
1505 return;
1506
1507 raw_spin_lock_irqsave(&mpic_lock, flags);
1508 if (mpic_is_ipi(mpic, irq)) {
1509 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1510 ~MPIC_VECPRI_PRIORITY_MASK;
1511 mpic_ipi_write(src - mpic->ipi_vecs[0],
1512 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1513 } else if (mpic_is_tm(mpic, irq)) {
1514 reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
1515 ~MPIC_VECPRI_PRIORITY_MASK;
1516 mpic_tm_write(src - mpic->timer_vecs[0],
1517 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1518 } else {
1519 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1520 & ~MPIC_VECPRI_PRIORITY_MASK;
1521 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1522 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1523 }
1524 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1525 }
1526
1527 void mpic_setup_this_cpu(void)
1528 {
1529 #ifdef CONFIG_SMP
1530 struct mpic *mpic = mpic_primary;
1531 unsigned long flags;
1532 u32 msk = 1 << hard_smp_processor_id();
1533 unsigned int i;
1534
1535 BUG_ON(mpic == NULL);
1536
1537 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1538
1539 raw_spin_lock_irqsave(&mpic_lock, flags);
1540
1541 /* let the mpic know we want intrs. default affinity is 0xffffffff
1542 * until changed via /proc. That's how it's done on x86. If we want
1543 * it differently, then we should make sure we also change the default
1544 * values of irq_desc[].affinity in irq.c.
1545 */
1546 if (distribute_irqs) {
1547 for (i = 0; i < mpic->num_sources ; i++)
1548 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1549 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1550 }
1551
1552 /* Set current processor priority to 0 */
1553 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1554
1555 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1556 #endif /* CONFIG_SMP */
1557 }
1558
1559 int mpic_cpu_get_priority(void)
1560 {
1561 struct mpic *mpic = mpic_primary;
1562
1563 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1564 }
1565
1566 void mpic_cpu_set_priority(int prio)
1567 {
1568 struct mpic *mpic = mpic_primary;
1569
1570 prio &= MPIC_CPU_TASKPRI_MASK;
1571 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1572 }
1573
1574 void mpic_teardown_this_cpu(int secondary)
1575 {
1576 struct mpic *mpic = mpic_primary;
1577 unsigned long flags;
1578 u32 msk = 1 << hard_smp_processor_id();
1579 unsigned int i;
1580
1581 BUG_ON(mpic == NULL);
1582
1583 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1584 raw_spin_lock_irqsave(&mpic_lock, flags);
1585
1586 /* let the mpic know we don't want intrs. */
1587 for (i = 0; i < mpic->num_sources ; i++)
1588 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1589 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1590
1591 /* Set current processor priority to max */
1592 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1593 /* We need to EOI the IPI since not all platforms reset the MPIC
1594 * on boot and new interrupts wouldn't get delivered otherwise.
1595 */
1596 mpic_eoi(mpic);
1597
1598 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1599 }
1600
1601
1602 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1603 {
1604 u32 src;
1605
1606 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1607 #ifdef DEBUG_LOW
1608 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1609 #endif
1610 if (unlikely(src == mpic->spurious_vec)) {
1611 if (mpic->flags & MPIC_SPV_EOI)
1612 mpic_eoi(mpic);
1613 return NO_IRQ;
1614 }
1615 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1616 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1617 mpic->name, (int)src);
1618 mpic_eoi(mpic);
1619 return NO_IRQ;
1620 }
1621
1622 return irq_linear_revmap(mpic->irqhost, src);
1623 }
1624
1625 unsigned int mpic_get_one_irq(struct mpic *mpic)
1626 {
1627 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1628 }
1629
1630 unsigned int mpic_get_irq(void)
1631 {
1632 struct mpic *mpic = mpic_primary;
1633
1634 BUG_ON(mpic == NULL);
1635
1636 return mpic_get_one_irq(mpic);
1637 }
1638
1639 unsigned int mpic_get_coreint_irq(void)
1640 {
1641 #ifdef CONFIG_BOOKE
1642 struct mpic *mpic = mpic_primary;
1643 u32 src;
1644
1645 BUG_ON(mpic == NULL);
1646
1647 src = mfspr(SPRN_EPR);
1648
1649 if (unlikely(src == mpic->spurious_vec)) {
1650 if (mpic->flags & MPIC_SPV_EOI)
1651 mpic_eoi(mpic);
1652 return NO_IRQ;
1653 }
1654 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1655 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1656 mpic->name, (int)src);
1657 return NO_IRQ;
1658 }
1659
1660 return irq_linear_revmap(mpic->irqhost, src);
1661 #else
1662 return NO_IRQ;
1663 #endif
1664 }
1665
1666 unsigned int mpic_get_mcirq(void)
1667 {
1668 struct mpic *mpic = mpic_primary;
1669
1670 BUG_ON(mpic == NULL);
1671
1672 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1673 }
1674
1675 #ifdef CONFIG_SMP
1676 void mpic_request_ipis(void)
1677 {
1678 struct mpic *mpic = mpic_primary;
1679 int i;
1680 BUG_ON(mpic == NULL);
1681
1682 printk(KERN_INFO "mpic: requesting IPIs...\n");
1683
1684 for (i = 0; i < 4; i++) {
1685 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1686 mpic->ipi_vecs[0] + i);
1687 if (vipi == NO_IRQ) {
1688 printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1689 continue;
1690 }
1691 smp_request_message_ipi(vipi, i);
1692 }
1693 }
1694
1695 void smp_mpic_message_pass(int cpu, int msg)
1696 {
1697 struct mpic *mpic = mpic_primary;
1698 u32 physmask;
1699
1700 BUG_ON(mpic == NULL);
1701
1702 /* make sure we're sending something that translates to an IPI */
1703 if ((unsigned int)msg > 3) {
1704 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1705 smp_processor_id(), msg);
1706 return;
1707 }
1708
1709 #ifdef DEBUG_IPI
1710 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg);
1711 #endif
1712
1713 physmask = 1 << get_hard_smp_processor_id(cpu);
1714
1715 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1716 msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask);
1717 }
1718
1719 int __init smp_mpic_probe(void)
1720 {
1721 int nr_cpus;
1722
1723 DBG("smp_mpic_probe()...\n");
1724
1725 nr_cpus = cpumask_weight(cpu_possible_mask);
1726
1727 DBG("nr_cpus: %d\n", nr_cpus);
1728
1729 if (nr_cpus > 1)
1730 mpic_request_ipis();
1731
1732 return nr_cpus;
1733 }
1734
1735 void __devinit smp_mpic_setup_cpu(int cpu)
1736 {
1737 mpic_setup_this_cpu();
1738 }
1739
1740 void mpic_reset_core(int cpu)
1741 {
1742 struct mpic *mpic = mpic_primary;
1743 u32 pir;
1744 int cpuid = get_hard_smp_processor_id(cpu);
1745
1746 /* Set target bit for core reset */
1747 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1748 pir |= (1 << cpuid);
1749 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1750 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1751
1752 /* Restore target bit after reset complete */
1753 pir &= ~(1 << cpuid);
1754 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1755 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1756 }
1757 #endif /* CONFIG_SMP */
1758
1759 #ifdef CONFIG_PM
1760 static void mpic_suspend_one(struct mpic *mpic)
1761 {
1762 int i;
1763
1764 for (i = 0; i < mpic->num_sources; i++) {
1765 mpic->save_data[i].vecprio =
1766 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1767 mpic->save_data[i].dest =
1768 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1769 }
1770 }
1771
1772 static int mpic_suspend(void)
1773 {
1774 struct mpic *mpic = mpics;
1775
1776 while (mpic) {
1777 mpic_suspend_one(mpic);
1778 mpic = mpic->next;
1779 }
1780
1781 return 0;
1782 }
1783
1784 static void mpic_resume_one(struct mpic *mpic)
1785 {
1786 int i;
1787
1788 for (i = 0; i < mpic->num_sources; i++) {
1789 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1790 mpic->save_data[i].vecprio);
1791 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1792 mpic->save_data[i].dest);
1793
1794 #ifdef CONFIG_MPIC_U3_HT_IRQS
1795 if (mpic->fixups) {
1796 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1797
1798 if (fixup->base) {
1799 /* we use the lowest bit in an inverted meaning */
1800 if ((mpic->save_data[i].fixup_data & 1) == 0)
1801 continue;
1802
1803 /* Enable and configure */
1804 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1805
1806 writel(mpic->save_data[i].fixup_data & ~1,
1807 fixup->base + 4);
1808 }
1809 }
1810 #endif
1811 } /* end for loop */
1812 }
1813
1814 static void mpic_resume(void)
1815 {
1816 struct mpic *mpic = mpics;
1817
1818 while (mpic) {
1819 mpic_resume_one(mpic);
1820 mpic = mpic->next;
1821 }
1822 }
1823
1824 static struct syscore_ops mpic_syscore_ops = {
1825 .resume = mpic_resume,
1826 .suspend = mpic_suspend,
1827 };
1828
1829 static int mpic_init_sys(void)
1830 {
1831 register_syscore_ops(&mpic_syscore_ops);
1832 return 0;
1833 }
1834
1835 device_initcall(mpic_init_sys);
1836 #endif