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spi/pxa2xx: Add CE4100 support
[zen-stable.git] / sound / arm / aaci.c
blob91acc9a243ec47dec8aabb6a67bcdd9b4f4aa671
1 /*
2 * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
3 *
4 * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Documentation: ARM DDI 0173B
11 */
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/ioport.h>
16 #include <linux/device.h>
17 #include <linux/spinlock.h>
18 #include <linux/interrupt.h>
19 #include <linux/err.h>
20 #include <linux/amba/bus.h>
21 #include <linux/io.h>
22
23 #include <sound/core.h>
24 #include <sound/initval.h>
25 #include <sound/ac97_codec.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28
29 #include "aaci.h"
30
31 #define DRIVER_NAME "aaci-pl041"
32
33 /*
34 * PM support is not complete. Turn it off.
35 */
36 #undef CONFIG_PM
37
38 static void aaci_ac97_select_codec(struct aaci *aaci, struct snd_ac97 *ac97)
39 {
40 u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num);
41
42 /*
43 * Ensure that the slot 1/2 RX registers are empty.
44 */
45 v = readl(aaci->base + AACI_SLFR);
46 if (v & SLFR_2RXV)
47 readl(aaci->base + AACI_SL2RX);
48 if (v & SLFR_1RXV)
49 readl(aaci->base + AACI_SL1RX);
50
51 writel(maincr, aaci->base + AACI_MAINCR);
52 }
53
54 /*
55 * P29:
56 * The recommended use of programming the external codec through slot 1
57 * and slot 2 data is to use the channels during setup routines and the
58 * slot register at any other time. The data written into slot 1, slot 2
59 * and slot 12 registers is transmitted only when their corresponding
60 * SI1TxEn, SI2TxEn and SI12TxEn bits are set in the AACI_MAINCR
61 * register.
62 */
63 static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
64 unsigned short val)
65 {
66 struct aaci *aaci = ac97->private_data;
67 u32 v;
68 int timeout = 5000;
69
70 if (ac97->num >= 4)
71 return;
72
73 mutex_lock(&aaci->ac97_sem);
74
75 aaci_ac97_select_codec(aaci, ac97);
76
77 /*
78 * P54: You must ensure that AACI_SL2TX is always written
79 * to, if required, before data is written to AACI_SL1TX.
80 */
81 writel(val << 4, aaci->base + AACI_SL2TX);
82 writel(reg << 12, aaci->base + AACI_SL1TX);
83
84 /*
85 * Wait for the transmission of both slots to complete.
86 */
87 do {
88 v = readl(aaci->base + AACI_SLFR);
89 } while ((v & (SLFR_1TXB|SLFR_2TXB)) && --timeout);
90
91 if (!timeout)
92 dev_err(&aaci->dev->dev,
93 "timeout waiting for write to complete\n");
94
95 mutex_unlock(&aaci->ac97_sem);
96 }
97
98 /*
99 * Read an AC'97 register.
100 */
101 static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
102 {
103 struct aaci *aaci = ac97->private_data;
104 u32 v;
105 int timeout = 5000;
106 int retries = 10;
107
108 if (ac97->num >= 4)
109 return ~0;
110
111 mutex_lock(&aaci->ac97_sem);
112
113 aaci_ac97_select_codec(aaci, ac97);
114
115 /*
116 * Write the register address to slot 1.
117 */
118 writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX);
119
120 /*
121 * Wait for the transmission to complete.
122 */
123 do {
124 v = readl(aaci->base + AACI_SLFR);
125 } while ((v & SLFR_1TXB) && --timeout);
126
127 if (!timeout) {
128 dev_err(&aaci->dev->dev, "timeout on slot 1 TX busy\n");
129 v = ~0;
130 goto out;
131 }
132
133 /*
134 * Give the AC'97 codec more than enough time
135 * to respond. (42us = ~2 frames at 48kHz.)
136 */
137 udelay(42);
138
139 /*
140 * Wait for slot 2 to indicate data.
141 */
142 timeout = 5000;
143 do {
144 cond_resched();
145 v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV);
146 } while ((v != (SLFR_1RXV|SLFR_2RXV)) && --timeout);
147
148 if (!timeout) {
149 dev_err(&aaci->dev->dev, "timeout on RX valid\n");
150 v = ~0;
151 goto out;
152 }
153
154 do {
155 v = readl(aaci->base + AACI_SL1RX) >> 12;
156 if (v == reg) {
157 v = readl(aaci->base + AACI_SL2RX) >> 4;
158 break;
159 } else if (--retries) {
160 dev_warn(&aaci->dev->dev,
161 "ac97 read back fail. retry\n");
162 continue;
163 } else {
164 dev_warn(&aaci->dev->dev,
165 "wrong ac97 register read back (%x != %x)\n",
166 v, reg);
167 v = ~0;
168 }
169 } while (retries);
170 out:
171 mutex_unlock(&aaci->ac97_sem);
172 return v;
173 }
174
175 static inline void
176 aaci_chan_wait_ready(struct aaci_runtime *aacirun, unsigned long mask)
177 {
178 u32 val;
179 int timeout = 5000;
180
181 do {
182 val = readl(aacirun->base + AACI_SR);
183 } while (val & mask && timeout--);
184 }
185
186
187
188 /*
189 * Interrupt support.
190 */
191 static void aaci_fifo_irq(struct aaci *aaci, int channel, u32 mask)
192 {
193 if (mask & ISR_ORINTR) {
194 dev_warn(&aaci->dev->dev, "RX overrun on chan %d\n", channel);
195 writel(ICLR_RXOEC1 << channel, aaci->base + AACI_INTCLR);
196 }
197
198 if (mask & ISR_RXTOINTR) {
199 dev_warn(&aaci->dev->dev, "RX timeout on chan %d\n", channel);
200 writel(ICLR_RXTOFEC1 << channel, aaci->base + AACI_INTCLR);
201 }
202
203 if (mask & ISR_RXINTR) {
204 struct aaci_runtime *aacirun = &aaci->capture;
205 void *ptr;
206
207 if (!aacirun->substream || !aacirun->start) {
208 dev_warn(&aaci->dev->dev, "RX interrupt???\n");
209 writel(0, aacirun->base + AACI_IE);
210 return;
211 }
212
213 spin_lock(&aacirun->lock);
214
215 ptr = aacirun->ptr;
216 do {
217 unsigned int len = aacirun->fifosz;
218 u32 val;
219
220 if (aacirun->bytes <= 0) {
221 aacirun->bytes += aacirun->period;
222 aacirun->ptr = ptr;
223 spin_unlock(&aacirun->lock);
224 snd_pcm_period_elapsed(aacirun->substream);
225 spin_lock(&aacirun->lock);
226 }
227 if (!(aacirun->cr & CR_EN))
228 break;
229
230 val = readl(aacirun->base + AACI_SR);
231 if (!(val & SR_RXHF))
232 break;
233 if (!(val & SR_RXFF))
234 len >>= 1;
235
236 aacirun->bytes -= len;
237
238 /* reading 16 bytes at a time */
239 for( ; len > 0; len -= 16) {
240 asm(
241 "ldmia %1, {r0, r1, r2, r3}\n\t"
242 "stmia %0!, {r0, r1, r2, r3}"
243 : "+r" (ptr)
244 : "r" (aacirun->fifo)
245 : "r0", "r1", "r2", "r3", "cc");
246
247 if (ptr >= aacirun->end)
248 ptr = aacirun->start;
249 }
250 } while(1);
251
252 aacirun->ptr = ptr;
253
254 spin_unlock(&aacirun->lock);
255 }
256
257 if (mask & ISR_URINTR) {
258 dev_dbg(&aaci->dev->dev, "TX underrun on chan %d\n", channel);
259 writel(ICLR_TXUEC1 << channel, aaci->base + AACI_INTCLR);
260 }
261
262 if (mask & ISR_TXINTR) {
263 struct aaci_runtime *aacirun = &aaci->playback;
264 void *ptr;
265
266 if (!aacirun->substream || !aacirun->start) {
267 dev_warn(&aaci->dev->dev, "TX interrupt???\n");
268 writel(0, aacirun->base + AACI_IE);
269 return;
270 }
271
272 spin_lock(&aacirun->lock);
273
274 ptr = aacirun->ptr;
275 do {
276 unsigned int len = aacirun->fifosz;
277 u32 val;
278
279 if (aacirun->bytes <= 0) {
280 aacirun->bytes += aacirun->period;
281 aacirun->ptr = ptr;
282 spin_unlock(&aacirun->lock);
283 snd_pcm_period_elapsed(aacirun->substream);
284 spin_lock(&aacirun->lock);
285 }
286 if (!(aacirun->cr & CR_EN))
287 break;
288
289 val = readl(aacirun->base + AACI_SR);
290 if (!(val & SR_TXHE))
291 break;
292 if (!(val & SR_TXFE))
293 len >>= 1;
294
295 aacirun->bytes -= len;
296
297 /* writing 16 bytes at a time */
298 for ( ; len > 0; len -= 16) {
299 asm(
300 "ldmia %0!, {r0, r1, r2, r3}\n\t"
301 "stmia %1, {r0, r1, r2, r3}"
302 : "+r" (ptr)
303 : "r" (aacirun->fifo)
304 : "r0", "r1", "r2", "r3", "cc");
305
306 if (ptr >= aacirun->end)
307 ptr = aacirun->start;
308 }
309 } while (1);
310
311 aacirun->ptr = ptr;
312
313 spin_unlock(&aacirun->lock);
314 }
315 }
316
317 static irqreturn_t aaci_irq(int irq, void *devid)
318 {
319 struct aaci *aaci = devid;
320 u32 mask;
321 int i;
322
323 mask = readl(aaci->base + AACI_ALLINTS);
324 if (mask) {
325 u32 m = mask;
326 for (i = 0; i < 4; i++, m >>= 7) {
327 if (m & 0x7f) {
328 aaci_fifo_irq(aaci, i, m);
329 }
330 }
331 }
332
333 return mask ? IRQ_HANDLED : IRQ_NONE;
334 }
335
336
337
338 /*
339 * ALSA support.
340 */
341 static struct snd_pcm_hardware aaci_hw_info = {
342 .info = SNDRV_PCM_INFO_MMAP |
343 SNDRV_PCM_INFO_MMAP_VALID |
344 SNDRV_PCM_INFO_INTERLEAVED |
345 SNDRV_PCM_INFO_BLOCK_TRANSFER |
346 SNDRV_PCM_INFO_RESUME,
347
348 /*
349 * ALSA doesn't support 18-bit or 20-bit packed into 32-bit
350 * words. It also doesn't support 12-bit at all.
351 */
352 .formats = SNDRV_PCM_FMTBIT_S16_LE,
353
354 /* rates are setup from the AC'97 codec */
355 .channels_min = 2,
356 .channels_max = 6,
357 .buffer_bytes_max = 64 * 1024,
358 .period_bytes_min = 256,
359 .period_bytes_max = PAGE_SIZE,
360 .periods_min = 4,
361 .periods_max = PAGE_SIZE / 16,
362 };
363
364 static int __aaci_pcm_open(struct aaci *aaci,
365 struct snd_pcm_substream *substream,
366 struct aaci_runtime *aacirun)
367 {
368 struct snd_pcm_runtime *runtime = substream->runtime;
369 int ret;
370
371 aacirun->substream = substream;
372 runtime->private_data = aacirun;
373 runtime->hw = aaci_hw_info;
374 runtime->hw.rates = aacirun->pcm->rates;
375 snd_pcm_limit_hw_rates(runtime);
376
377 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
378 aacirun->pcm->r[1].slots)
379 snd_ac97_pcm_double_rate_rules(runtime);
380
381 /*
382 * FIXME: ALSA specifies fifo_size in bytes. If we're in normal
383 * mode, each 32-bit word contains one sample. If we're in
384 * compact mode, each 32-bit word contains two samples, effectively
385 * halving the FIFO size. However, we don't know for sure which
386 * we'll be using at this point. We set this to the lower limit.
387 */
388 runtime->hw.fifo_size = aaci->fifosize * 2;
389
390 ret = request_irq(aaci->dev->irq[0], aaci_irq, IRQF_SHARED|IRQF_DISABLED,
391 DRIVER_NAME, aaci);
392 if (ret)
393 goto out;
394
395 return 0;
396
397 out:
398 return ret;
399 }
400
401
402 /*
403 * Common ALSA stuff
404 */
405 static int aaci_pcm_close(struct snd_pcm_substream *substream)
406 {
407 struct aaci *aaci = substream->private_data;
408 struct aaci_runtime *aacirun = substream->runtime->private_data;
409
410 WARN_ON(aacirun->cr & CR_EN);
411
412 aacirun->substream = NULL;
413 free_irq(aaci->dev->irq[0], aaci);
414
415 return 0;
416 }
417
418 static int aaci_pcm_hw_free(struct snd_pcm_substream *substream)
419 {
420 struct aaci_runtime *aacirun = substream->runtime->private_data;
421
422 /*
423 * This must not be called with the device enabled.
424 */
425 WARN_ON(aacirun->cr & CR_EN);
426
427 if (aacirun->pcm_open)
428 snd_ac97_pcm_close(aacirun->pcm);
429 aacirun->pcm_open = 0;
430
431 /*
432 * Clear out the DMA and any allocated buffers.
433 */
434 snd_pcm_lib_free_pages(substream);
435
436 return 0;
437 }
438
439 static int aaci_pcm_hw_params(struct snd_pcm_substream *substream,
440 struct aaci_runtime *aacirun,
441 struct snd_pcm_hw_params *params)
442 {
443 int err;
444 struct aaci *aaci = substream->private_data;
445
446 aaci_pcm_hw_free(substream);
447 if (aacirun->pcm_open) {
448 snd_ac97_pcm_close(aacirun->pcm);
449 aacirun->pcm_open = 0;
450 }
451
452 err = snd_pcm_lib_malloc_pages(substream,
453 params_buffer_bytes(params));
454 if (err >= 0) {
455 unsigned int rate = params_rate(params);
456 int dbl = rate > 48000;
457
458 err = snd_ac97_pcm_open(aacirun->pcm, rate,
459 params_channels(params),
460 aacirun->pcm->r[dbl].slots);
461
462 aacirun->pcm_open = err == 0;
463 aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16;
464 aacirun->fifosz = aaci->fifosize * 4;
465
466 if (aacirun->cr & CR_COMPACT)
467 aacirun->fifosz >>= 1;
468 }
469
470 return err;
471 }
472
473 static int aaci_pcm_prepare(struct snd_pcm_substream *substream)
474 {
475 struct snd_pcm_runtime *runtime = substream->runtime;
476 struct aaci_runtime *aacirun = runtime->private_data;
477
478 aacirun->start = runtime->dma_area;
479 aacirun->end = aacirun->start + snd_pcm_lib_buffer_bytes(substream);
480 aacirun->ptr = aacirun->start;
481 aacirun->period =
482 aacirun->bytes = frames_to_bytes(runtime, runtime->period_size);
483
484 return 0;
485 }
486
487 static snd_pcm_uframes_t aaci_pcm_pointer(struct snd_pcm_substream *substream)
488 {
489 struct snd_pcm_runtime *runtime = substream->runtime;
490 struct aaci_runtime *aacirun = runtime->private_data;
491 ssize_t bytes = aacirun->ptr - aacirun->start;
492
493 return bytes_to_frames(runtime, bytes);
494 }
495
496
497 /*
498 * Playback specific ALSA stuff
499 */
500 static const u32 channels_to_txmask[] = {
501 [2] = CR_SL3 | CR_SL4,
502 [4] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8,
503 [6] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8 | CR_SL6 | CR_SL9,
504 };
505
506 /*
507 * We can support two and four channel audio. Unfortunately
508 * six channel audio requires a non-standard channel ordering:
509 * 2 -> FL(3), FR(4)
510 * 4 -> FL(3), FR(4), SL(7), SR(8)
511 * 6 -> FL(3), FR(4), SL(7), SR(8), C(6), LFE(9) (required)
512 * FL(3), FR(4), C(6), SL(7), SR(8), LFE(9) (actual)
513 * This requires an ALSA configuration file to correct.
514 */
515 static unsigned int channel_list[] = { 2, 4, 6 };
516
517 static int
518 aaci_rule_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule)
519 {
520 struct aaci *aaci = rule->private;
521 unsigned int chan_mask = 1 << 0, slots;
522
523 /*
524 * pcms[0] is the our 5.1 PCM instance.
525 */
526 slots = aaci->ac97_bus->pcms[0].r[0].slots;
527 if (slots & (1 << AC97_SLOT_PCM_SLEFT)) {
528 chan_mask |= 1 << 1;
529 if (slots & (1 << AC97_SLOT_LFE))
530 chan_mask |= 1 << 2;
531 }
532
533 return snd_interval_list(hw_param_interval(p, rule->var),
534 ARRAY_SIZE(channel_list), channel_list,
535 chan_mask);
536 }
537
538 static int aaci_pcm_open(struct snd_pcm_substream *substream)
539 {
540 struct aaci *aaci = substream->private_data;
541 int ret;
542
543 /*
544 * Add rule describing channel dependency.
545 */
546 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
547 SNDRV_PCM_HW_PARAM_CHANNELS,
548 aaci_rule_channels, aaci,
549 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
550 if (ret)
551 return ret;
552
553 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
554 ret = __aaci_pcm_open(aaci, substream, &aaci->playback);
555 } else {
556 ret = __aaci_pcm_open(aaci, substream, &aaci->capture);
557 }
558 return ret;
559 }
560
561 static int aaci_pcm_playback_hw_params(struct snd_pcm_substream *substream,
562 struct snd_pcm_hw_params *params)
563 {
564 struct aaci_runtime *aacirun = substream->runtime->private_data;
565 unsigned int channels = params_channels(params);
566 int ret;
567
568 WARN_ON(channels >= ARRAY_SIZE(channels_to_txmask) ||
569 !channels_to_txmask[channels]);
570
571 ret = aaci_pcm_hw_params(substream, aacirun, params);
572
573 /*
574 * Enable FIFO, compact mode, 16 bits per sample.
575 * FIXME: double rate slots?
576 */
577 if (ret >= 0)
578 aacirun->cr |= channels_to_txmask[channels];
579
580 return ret;
581 }
582
583 static void aaci_pcm_playback_stop(struct aaci_runtime *aacirun)
584 {
585 u32 ie;
586
587 ie = readl(aacirun->base + AACI_IE);
588 ie &= ~(IE_URIE|IE_TXIE);
589 writel(ie, aacirun->base + AACI_IE);
590 aacirun->cr &= ~CR_EN;
591 aaci_chan_wait_ready(aacirun, SR_TXB);
592 writel(aacirun->cr, aacirun->base + AACI_TXCR);
593 }
594
595 static void aaci_pcm_playback_start(struct aaci_runtime *aacirun)
596 {
597 u32 ie;
598
599 aaci_chan_wait_ready(aacirun, SR_TXB);
600 aacirun->cr |= CR_EN;
601
602 ie = readl(aacirun->base + AACI_IE);
603 ie |= IE_URIE | IE_TXIE;
604 writel(ie, aacirun->base + AACI_IE);
605 writel(aacirun->cr, aacirun->base + AACI_TXCR);
606 }
607
608 static int aaci_pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd)
609 {
610 struct aaci_runtime *aacirun = substream->runtime->private_data;
611 unsigned long flags;
612 int ret = 0;
613
614 spin_lock_irqsave(&aacirun->lock, flags);
615
616 switch (cmd) {
617 case SNDRV_PCM_TRIGGER_START:
618 aaci_pcm_playback_start(aacirun);
619 break;
620
621 case SNDRV_PCM_TRIGGER_RESUME:
622 aaci_pcm_playback_start(aacirun);
623 break;
624
625 case SNDRV_PCM_TRIGGER_STOP:
626 aaci_pcm_playback_stop(aacirun);
627 break;
628
629 case SNDRV_PCM_TRIGGER_SUSPEND:
630 aaci_pcm_playback_stop(aacirun);
631 break;
632
633 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
634 break;
635
636 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
637 break;
638
639 default:
640 ret = -EINVAL;
641 }
642
643 spin_unlock_irqrestore(&aacirun->lock, flags);
644
645 return ret;
646 }
647
648 static struct snd_pcm_ops aaci_playback_ops = {
649 .open = aaci_pcm_open,
650 .close = aaci_pcm_close,
651 .ioctl = snd_pcm_lib_ioctl,
652 .hw_params = aaci_pcm_playback_hw_params,
653 .hw_free = aaci_pcm_hw_free,
654 .prepare = aaci_pcm_prepare,
655 .trigger = aaci_pcm_playback_trigger,
656 .pointer = aaci_pcm_pointer,
657 };
658
659 static int aaci_pcm_capture_hw_params(struct snd_pcm_substream *substream,
660 struct snd_pcm_hw_params *params)
661 {
662 struct aaci_runtime *aacirun = substream->runtime->private_data;
663 int ret;
664
665 ret = aaci_pcm_hw_params(substream, aacirun, params);
666 if (ret >= 0)
667 /* Line in record: slot 3 and 4 */
668 aacirun->cr |= CR_SL3 | CR_SL4;
669
670 return ret;
671 }
672
673 static void aaci_pcm_capture_stop(struct aaci_runtime *aacirun)
674 {
675 u32 ie;
676
677 aaci_chan_wait_ready(aacirun, SR_RXB);
678
679 ie = readl(aacirun->base + AACI_IE);
680 ie &= ~(IE_ORIE | IE_RXIE);
681 writel(ie, aacirun->base+AACI_IE);
682
683 aacirun->cr &= ~CR_EN;
684
685 writel(aacirun->cr, aacirun->base + AACI_RXCR);
686 }
687
688 static void aaci_pcm_capture_start(struct aaci_runtime *aacirun)
689 {
690 u32 ie;
691
692 aaci_chan_wait_ready(aacirun, SR_RXB);
693
694 #ifdef DEBUG
695 /* RX Timeout value: bits 28:17 in RXCR */
696 aacirun->cr |= 0xf << 17;
697 #endif
698
699 aacirun->cr |= CR_EN;
700 writel(aacirun->cr, aacirun->base + AACI_RXCR);
701
702 ie = readl(aacirun->base + AACI_IE);
703 ie |= IE_ORIE |IE_RXIE; // overrun and rx interrupt -- half full
704 writel(ie, aacirun->base + AACI_IE);
705 }
706
707 static int aaci_pcm_capture_trigger(struct snd_pcm_substream *substream, int cmd)
708 {
709 struct aaci_runtime *aacirun = substream->runtime->private_data;
710 unsigned long flags;
711 int ret = 0;
712
713 spin_lock_irqsave(&aacirun->lock, flags);
714
715 switch (cmd) {
716 case SNDRV_PCM_TRIGGER_START:
717 aaci_pcm_capture_start(aacirun);
718 break;
719
720 case SNDRV_PCM_TRIGGER_RESUME:
721 aaci_pcm_capture_start(aacirun);
722 break;
723
724 case SNDRV_PCM_TRIGGER_STOP:
725 aaci_pcm_capture_stop(aacirun);
726 break;
727
728 case SNDRV_PCM_TRIGGER_SUSPEND:
729 aaci_pcm_capture_stop(aacirun);
730 break;
731
732 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
733 break;
734
735 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
736 break;
737
738 default:
739 ret = -EINVAL;
740 }
741
742 spin_unlock_irqrestore(&aacirun->lock, flags);
743
744 return ret;
745 }
746
747 static int aaci_pcm_capture_prepare(struct snd_pcm_substream *substream)
748 {
749 struct snd_pcm_runtime *runtime = substream->runtime;
750 struct aaci *aaci = substream->private_data;
751
752 aaci_pcm_prepare(substream);
753
754 /* allow changing of sample rate */
755 aaci_ac97_write(aaci->ac97, AC97_EXTENDED_STATUS, 0x0001); /* VRA */
756 aaci_ac97_write(aaci->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
757 aaci_ac97_write(aaci->ac97, AC97_PCM_MIC_ADC_RATE, runtime->rate);
758
759 /* Record select: Mic: 0, Aux: 3, Line: 4 */
760 aaci_ac97_write(aaci->ac97, AC97_REC_SEL, 0x0404);
761
762 return 0;
763 }
764
765 static struct snd_pcm_ops aaci_capture_ops = {
766 .open = aaci_pcm_open,
767 .close = aaci_pcm_close,
768 .ioctl = snd_pcm_lib_ioctl,
769 .hw_params = aaci_pcm_capture_hw_params,
770 .hw_free = aaci_pcm_hw_free,
771 .prepare = aaci_pcm_capture_prepare,
772 .trigger = aaci_pcm_capture_trigger,
773 .pointer = aaci_pcm_pointer,
774 };
775
776 /*
777 * Power Management.
778 */
779 #ifdef CONFIG_PM
780 static int aaci_do_suspend(struct snd_card *card, unsigned int state)
781 {
782 struct aaci *aaci = card->private_data;
783 snd_power_change_state(card, SNDRV_CTL_POWER_D3cold);
784 snd_pcm_suspend_all(aaci->pcm);
785 return 0;
786 }
787
788 static int aaci_do_resume(struct snd_card *card, unsigned int state)
789 {
790 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
791 return 0;
792 }
793
794 static int aaci_suspend(struct amba_device *dev, pm_message_t state)
795 {
796 struct snd_card *card = amba_get_drvdata(dev);
797 return card ? aaci_do_suspend(card) : 0;
798 }
799
800 static int aaci_resume(struct amba_device *dev)
801 {
802 struct snd_card *card = amba_get_drvdata(dev);
803 return card ? aaci_do_resume(card) : 0;
804 }
805 #else
806 #define aaci_do_suspend NULL
807 #define aaci_do_resume NULL
808 #define aaci_suspend NULL
809 #define aaci_resume NULL
810 #endif
811
812
813 static struct ac97_pcm ac97_defs[] __devinitdata = {
814 [0] = { /* Front PCM */
815 .exclusive = 1,
816 .r = {
817 [0] = {
818 .slots = (1 << AC97_SLOT_PCM_LEFT) |
819 (1 << AC97_SLOT_PCM_RIGHT) |
820 (1 << AC97_SLOT_PCM_CENTER) |
821 (1 << AC97_SLOT_PCM_SLEFT) |
822 (1 << AC97_SLOT_PCM_SRIGHT) |
823 (1 << AC97_SLOT_LFE),
824 },
825 [1] = {
826 .slots = (1 << AC97_SLOT_PCM_LEFT) |
827 (1 << AC97_SLOT_PCM_RIGHT) |
828 (1 << AC97_SLOT_PCM_LEFT_0) |
829 (1 << AC97_SLOT_PCM_RIGHT_0),
830 },
831 },
832 },
833 [1] = { /* PCM in */
834 .stream = 1,
835 .exclusive = 1,
836 .r = {
837 [0] = {
838 .slots = (1 << AC97_SLOT_PCM_LEFT) |
839 (1 << AC97_SLOT_PCM_RIGHT),
840 },
841 },
842 },
843 [2] = { /* Mic in */
844 .stream = 1,
845 .exclusive = 1,
846 .r = {
847 [0] = {
848 .slots = (1 << AC97_SLOT_MIC),
849 },
850 },
851 }
852 };
853
854 static struct snd_ac97_bus_ops aaci_bus_ops = {
855 .write = aaci_ac97_write,
856 .read = aaci_ac97_read,
857 };
858
859 static int __devinit aaci_probe_ac97(struct aaci *aaci)
860 {
861 struct snd_ac97_template ac97_template;
862 struct snd_ac97_bus *ac97_bus;
863 struct snd_ac97 *ac97;
864 int ret;
865
866 /*
867 * Assert AACIRESET for 2us
868 */
869 writel(0, aaci->base + AACI_RESET);
870 udelay(2);
871 writel(RESET_NRST, aaci->base + AACI_RESET);
872
873 /*
874 * Give the AC'97 codec more than enough time
875 * to wake up. (42us = ~2 frames at 48kHz.)
876 */
877 udelay(42);
878
879 ret = snd_ac97_bus(aaci->card, 0, &aaci_bus_ops, aaci, &ac97_bus);
880 if (ret)
881 goto out;
882
883 ac97_bus->clock = 48000;
884 aaci->ac97_bus = ac97_bus;
885
886 memset(&ac97_template, 0, sizeof(struct snd_ac97_template));
887 ac97_template.private_data = aaci;
888 ac97_template.num = 0;
889 ac97_template.scaps = AC97_SCAP_SKIP_MODEM;
890
891 ret = snd_ac97_mixer(ac97_bus, &ac97_template, &ac97);
892 if (ret)
893 goto out;
894 aaci->ac97 = ac97;
895
896 /*
897 * Disable AC97 PC Beep input on audio codecs.
898 */
899 if (ac97_is_audio(ac97))
900 snd_ac97_write_cache(ac97, AC97_PC_BEEP, 0x801e);
901
902 ret = snd_ac97_pcm_assign(ac97_bus, ARRAY_SIZE(ac97_defs), ac97_defs);
903 if (ret)
904 goto out;
905
906 aaci->playback.pcm = &ac97_bus->pcms[0];
907 aaci->capture.pcm = &ac97_bus->pcms[1];
908
909 out:
910 return ret;
911 }
912
913 static void aaci_free_card(struct snd_card *card)
914 {
915 struct aaci *aaci = card->private_data;
916 if (aaci->base)
917 iounmap(aaci->base);
918 }
919
920 static struct aaci * __devinit aaci_init_card(struct amba_device *dev)
921 {
922 struct aaci *aaci;
923 struct snd_card *card;
924 int err;
925
926 err = snd_card_create(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
927 THIS_MODULE, sizeof(struct aaci), &card);
928 if (err < 0)
929 return NULL;
930
931 card->private_free = aaci_free_card;
932
933 strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver));
934 strlcpy(card->shortname, "ARM AC'97 Interface", sizeof(card->shortname));
935 snprintf(card->longname, sizeof(card->longname),
936 "%s at 0x%016llx, irq %d",
937 card->shortname, (unsigned long long)dev->res.start,
938 dev->irq[0]);
939
940 aaci = card->private_data;
941 mutex_init(&aaci->ac97_sem);
942 aaci->card = card;
943 aaci->dev = dev;
944
945 /* Set MAINCR to allow slot 1 and 2 data IO */
946 aaci->maincr = MAINCR_IE | MAINCR_SL1RXEN | MAINCR_SL1TXEN |
947 MAINCR_SL2RXEN | MAINCR_SL2TXEN;
948
949 return aaci;
950 }
951
952 static int __devinit aaci_init_pcm(struct aaci *aaci)
953 {
954 struct snd_pcm *pcm;
955 int ret;
956
957 ret = snd_pcm_new(aaci->card, "AACI AC'97", 0, 1, 1, &pcm);
958 if (ret == 0) {
959 aaci->pcm = pcm;
960 pcm->private_data = aaci;
961 pcm->info_flags = 0;
962
963 strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name));
964
965 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &aaci_playback_ops);
966 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &aaci_capture_ops);
967 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
968 NULL, 0, 64 * 1024);
969 }
970
971 return ret;
972 }
973
974 static unsigned int __devinit aaci_size_fifo(struct aaci *aaci)
975 {
976 struct aaci_runtime *aacirun = &aaci->playback;
977 int i;
978
979 writel(CR_FEN | CR_SZ16 | CR_EN, aacirun->base + AACI_TXCR);
980
981 for (i = 0; !(readl(aacirun->base + AACI_SR) & SR_TXFF) && i < 4096; i++)
982 writel(0, aacirun->fifo);
983
984 writel(0, aacirun->base + AACI_TXCR);
985
986 /*
987 * Re-initialise the AACI after the FIFO depth test, to
988 * ensure that the FIFOs are empty. Unfortunately, merely
989 * disabling the channel doesn't clear the FIFO.
990 */
991 writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR);
992 writel(aaci->maincr, aaci->base + AACI_MAINCR);
993
994 /*
995 * If we hit 4096, we failed. Go back to the specified
996 * fifo depth.
997 */
998 if (i == 4096)
999 i = 8;
1000
1001 return i;
1002 }
1003
1004 static int __devinit aaci_probe(struct amba_device *dev, struct amba_id *id)
1005 {
1006 struct aaci *aaci;
1007 int ret, i;
1008
1009 ret = amba_request_regions(dev, NULL);
1010 if (ret)
1011 return ret;
1012
1013 aaci = aaci_init_card(dev);
1014 if (!aaci) {
1015 ret = -ENOMEM;
1016 goto out;
1017 }
1018
1019 aaci->base = ioremap(dev->res.start, resource_size(&dev->res));
1020 if (!aaci->base) {
1021 ret = -ENOMEM;
1022 goto out;
1023 }
1024
1025 /*
1026 * Playback uses AACI channel 0
1027 */
1028 spin_lock_init(&aaci->playback.lock);
1029 aaci->playback.base = aaci->base + AACI_CSCH1;
1030 aaci->playback.fifo = aaci->base + AACI_DR1;
1031
1032 /*
1033 * Capture uses AACI channel 0
1034 */
1035 spin_lock_init(&aaci->capture.lock);
1036 aaci->capture.base = aaci->base + AACI_CSCH1;
1037 aaci->capture.fifo = aaci->base + AACI_DR1;
1038
1039 for (i = 0; i < 4; i++) {
1040 void __iomem *base = aaci->base + i * 0x14;
1041
1042 writel(0, base + AACI_IE);
1043 writel(0, base + AACI_TXCR);
1044 writel(0, base + AACI_RXCR);
1045 }
1046
1047 writel(0x1fff, aaci->base + AACI_INTCLR);
1048 writel(aaci->maincr, aaci->base + AACI_MAINCR);
1049 /*
1050 * Fix: ac97 read back fail errors by reading
1051 * from any arbitrary aaci register.
1052 */
1053 readl(aaci->base + AACI_CSCH1);
1054 ret = aaci_probe_ac97(aaci);
1055 if (ret)
1056 goto out;
1057
1058 /*
1059 * Size the FIFOs (must be multiple of 16).
1060 */
1061 aaci->fifosize = aaci_size_fifo(aaci);
1062 if (aaci->fifosize & 15) {
1063 printk(KERN_WARNING "AACI: fifosize = %d not supported\n",
1064 aaci->fifosize);
1065 ret = -ENODEV;
1066 goto out;
1067 }
1068
1069 ret = aaci_init_pcm(aaci);
1070 if (ret)
1071 goto out;
1072
1073 snd_card_set_dev(aaci->card, &dev->dev);
1074
1075 ret = snd_card_register(aaci->card);
1076 if (ret == 0) {
1077 dev_info(&dev->dev, "%s, fifo %d\n", aaci->card->longname,
1078 aaci->fifosize);
1079 amba_set_drvdata(dev, aaci->card);
1080 return ret;
1081 }
1082
1083 out:
1084 if (aaci)
1085 snd_card_free(aaci->card);
1086 amba_release_regions(dev);
1087 return ret;
1088 }
1089
1090 static int __devexit aaci_remove(struct amba_device *dev)
1091 {
1092 struct snd_card *card = amba_get_drvdata(dev);
1093
1094 amba_set_drvdata(dev, NULL);
1095
1096 if (card) {
1097 struct aaci *aaci = card->private_data;
1098 writel(0, aaci->base + AACI_MAINCR);
1099
1100 snd_card_free(card);
1101 amba_release_regions(dev);
1102 }
1103
1104 return 0;
1105 }
1106
1107 static struct amba_id aaci_ids[] = {
1108 {
1109 .id = 0x00041041,
1110 .mask = 0x000fffff,
1111 },
1112 { 0, 0 },
1113 };
1114
1115 static struct amba_driver aaci_driver = {
1116 .drv = {
1117 .name = DRIVER_NAME,
1118 },
1119 .probe = aaci_probe,
1120 .remove = __devexit_p(aaci_remove),
1121 .suspend = aaci_suspend,
1122 .resume = aaci_resume,
1123 .id_table = aaci_ids,
1124 };
1125
1126 static int __init aaci_init(void)
1127 {
1128 return amba_driver_register(&aaci_driver);
1129 }
1130
1131 static void __exit aaci_exit(void)
1132 {
1133 amba_driver_unregister(&aaci_driver);
1134 }
1135
1136 module_init(aaci_init);
1137 module_exit(aaci_exit);
1138
1139 MODULE_LICENSE("GPL");
1140 MODULE_DESCRIPTION("ARM PrimeCell PL041 Advanced Audio CODEC Interface driver");