drivers/staging/brcm80211/brcmsmac/dma.h

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef _BRCM_DMA_H_
  18 #define _BRCM_DMA_H_
  19
  20 #include <linux/delay.h>
  21 #include "types.h"              /* forward structure declarations */
  22
  23 /* map/unmap direction */
  24 #define DMA_TX  1               /* TX direction for DMA */
  25 #define DMA_RX  2               /* RX direction for DMA */
  26
  27 /* DMA structure:
  28  *  support two DMA engines: 32 bits address or 64 bit addressing
  29  *  basic DMA register set is per channel(transmit or receive)
  30  *  a pair of channels is defined for convenience
  31  */
  32
  33 /* 32 bits addressing */
  34
  35 struct dma32diag {      /* diag access */
  36         u32 fifoaddr;   /* diag address */
  37         u32 fifodatalow;        /* low 32bits of data */
  38         u32 fifodatahigh;       /* high 32bits of data */
  39         u32 pad;                /* reserved */
  40 };
  41
  42 /* 64 bits addressing */
  43
  44 /* dma registers per channel(xmt or rcv) */
  45 struct dma64regs {
  46         u32 control;    /* enable, et al */
  47         u32 ptr;        /* last descriptor posted to chip */
  48         u32 addrlow;    /* desc ring base address low 32-bits (8K aligned) */
  49         u32 addrhigh;   /* desc ring base address bits 63:32 (8K aligned) */
  50         u32 status0;    /* current descriptor, xmt state */
  51         u32 status1;    /* active descriptor, xmt error */
  52 };
  53
  54 /* range param for dma_getnexttxp() and dma_txreclaim */
  55 enum txd_range {
  56         DMA_RANGE_ALL = 1,
  57         DMA_RANGE_TRANSMITTED,
  58         DMA_RANGE_TRANSFERED
  59 };
  60
  61 /*
  62  * Exported data structure (read-only)
  63  */
  64 /* export structure */
  65 struct dma_pub {
  66         uint txavail;           /* # free tx descriptors */
  67         uint dmactrlflags;      /* dma control flags */
  68
  69         /* rx error counters */
  70         uint rxgiants;          /* rx giant frames */
  71         uint rxnobuf;           /* rx out of dma descriptors */
  72         /* tx error counters */
  73         uint txnobuf;           /* tx out of dma descriptors */
  74 };
  75
  76 extern struct dma_pub *dma_attach(char *name, struct si_pub *sih,
  77                             void __iomem *dmaregstx, void __iomem *dmaregsrx,
  78                             uint ntxd, uint nrxd,
  79                             uint rxbufsize, int rxextheadroom,
  80                             uint nrxpost, uint rxoffset, uint *msg_level);
  81
  82 void dma_rxinit(struct dma_pub *pub);
  83 struct sk_buff *dma_rx(struct dma_pub *pub);
  84 bool dma_rxfill(struct dma_pub *pub);
  85 bool dma_rxreset(struct dma_pub *pub);
  86 bool dma_txreset(struct dma_pub *pub);
  87 void dma_txinit(struct dma_pub *pub);
  88 int dma_txfast(struct dma_pub *pub, struct sk_buff *p0, bool commit);
  89 void dma_txsuspend(struct dma_pub *pub);
  90 bool dma_txsuspended(struct dma_pub *pub);
  91 void dma_txresume(struct dma_pub *pub);
  92 void dma_txreclaim(struct dma_pub *pub, enum txd_range range);
  93 void dma_rxreclaim(struct dma_pub *pub);
  94 void dma_detach(struct dma_pub *pub);
  95 unsigned long dma_getvar(struct dma_pub *pub, const char *name);
  96 struct sk_buff *dma_getnexttxp(struct dma_pub *pub, enum txd_range range);
  97 void dma_counterreset(struct dma_pub *pub);
  98
  99 void dma_walk_packets(struct dma_pub *dmah, void (*callback_fnc)
 100                       (void *pkt, void *arg_a), void *arg_a);
 101
 102 /*
 103  * DMA(Bug) on bcm47xx chips seems to declare that the packet is ready, but
 104  * the packet length is not updated yet (by DMA) on the expected time.
 105  * Workaround is to hold processor till DMA updates the length, and stay off
 106  * the bus to allow DMA update the length in buffer
 107  */
 108 static inline void dma_spin_for_len(uint len, struct sk_buff *head)
 109 {
 110 #if defined(CONFIG_BCM47XX)
 111         if (!len) {
 112                 while (!(len = *(u16 *) KSEG1ADDR(head->data)))
 113                         udelay(1);
 114
 115                 *(u16 *) (head->data) = cpu_to_le16((u16) len);
 116         }
 117 #endif                          /* defined(CONFIG_BCM47XX) */
 118 }
 119
 120 #endif                          /* _BRCM_DMA_H_ */