drivers/staging/et131x/et131x_isr.c

   1 /*
   2  * Agere Systems Inc.
   3  * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
   4  *
   5  * Copyright © 2005 Agere Systems Inc.
   6  * All rights reserved.
   7  *   http://www.agere.com
   8  *
   9  * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
  10  *
  11  *------------------------------------------------------------------------------
  12  *
  13  * et131x_isr.c - File which contains the ISR, ISR handler, and related routines
  14  *                for processing interrupts from the device.
  15  *
  16  *------------------------------------------------------------------------------
  17  *
  18  * SOFTWARE LICENSE
  19  *
  20  * This software is provided subject to the following terms and conditions,
  21  * which you should read carefully before using the software.  Using this
  22  * software indicates your acceptance of these terms and conditions.  If you do
  23  * not agree with these terms and conditions, do not use the software.
  24  *
  25  * Copyright © 2005 Agere Systems Inc.
  26  * All rights reserved.
  27  *
  28  * Redistribution and use in source or binary forms, with or without
  29  * modifications, are permitted provided that the following conditions are met:
  30  *
  31  * . Redistributions of source code must retain the above copyright notice, this
  32  *    list of conditions and the following Disclaimer as comments in the code as
  33  *    well as in the documentation and/or other materials provided with the
  34  *    distribution.
  35  *
  36  * . Redistributions in binary form must reproduce the above copyright notice,
  37  *    this list of conditions and the following Disclaimer in the documentation
  38  *    and/or other materials provided with the distribution.
  39  *
  40  * . Neither the name of Agere Systems Inc. nor the names of the contributors
  41  *    may be used to endorse or promote products derived from this software
  42  *    without specific prior written permission.
  43  *
  44  * Disclaimer
  45  *
  46  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
  47  * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
  48  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
  49  * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
  50  * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
  51  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  52  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  53  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  54  * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
  55  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  56  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  57  * DAMAGE.
  58  *
  59  */
  60
  61 #include "et131x_version.h"
  62 #include "et131x_defs.h"
  63
  64 #include <linux/init.h>
  65 #include <linux/module.h>
  66 #include <linux/types.h>
  67 #include <linux/kernel.h>
  68
  69 #include <linux/sched.h>
  70 #include <linux/ptrace.h>
  71 #include <linux/ctype.h>
  72 #include <linux/string.h>
  73 #include <linux/timer.h>
  74 #include <linux/interrupt.h>
  75 #include <linux/in.h>
  76 #include <linux/delay.h>
  77 #include <linux/io.h>
  78 #include <linux/bitops.h>
  79 #include <linux/pci.h>
  80 #include <asm/system.h>
  81
  82 #include <linux/netdevice.h>
  83 #include <linux/etherdevice.h>
  84 #include <linux/skbuff.h>
  85 #include <linux/if_arp.h>
  86 #include <linux/ioport.h>
  87
  88 #include "et1310_phy.h"
  89 #include "et131x_adapter.h"
  90 #include "et131x.h"
  91
  92 /*
  93  * For interrupts, normal running is:
  94  *       rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
  95  *       watchdog_interrupt & txdma_xfer_done
  96  *
  97  * In both cases, when flow control is enabled for either Tx or bi-direction,
  98  * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
  99  * buffer rings are running low.
 100  */
 101 #define INT_MASK_DISABLE            0xffffffff
 102
 103 /* NOTE: Masking out MAC_STAT Interrupt for now...
 104  * #define INT_MASK_ENABLE             0xfff6bf17
 105  * #define INT_MASK_ENABLE_NO_FLOW     0xfff6bfd7
 106  */
 107 #define INT_MASK_ENABLE             0xfffebf17
 108 #define INT_MASK_ENABLE_NO_FLOW     0xfffebfd7
 109
 110
 111 /**
 112  *      et131x_enable_interrupts        -       enable interrupt
 113  *      @adapter: et131x device
 114  *
 115  *      Enable the appropriate interrupts on the ET131x according to our
 116  *      configuration
 117  */
 118
 119 void et131x_enable_interrupts(struct et131x_adapter *adapter)
 120 {
 121         u32 mask;
 122
 123         /* Enable all global interrupts */
 124         if (adapter->flowcontrol == FLOW_TXONLY ||
 125                             adapter->flowcontrol == FLOW_BOTH)
 126                 mask = INT_MASK_ENABLE;
 127         else
 128                 mask = INT_MASK_ENABLE_NO_FLOW;
 129
 130         writel(mask, &adapter->regs->global.int_mask);
 131 }
 132
 133 /**
 134  *      et131x_disable_interrupts       -       interrupt disable
 135  *      @adapter: et131x device
 136  *
 137  *      Block all interrupts from the et131x device at the device itself
 138  */
 139
 140 void et131x_disable_interrupts(struct et131x_adapter *adapter)
 141 {
 142         /* Disable all global interrupts */
 143         writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask);
 144 }
 145
 146
 147 /**
 148  * et131x_isr - The Interrupt Service Routine for the driver.
 149  * @irq: the IRQ on which the interrupt was received.
 150  * @dev_id: device-specific info (here a pointer to a net_device struct)
 151  *
 152  * Returns a value indicating if the interrupt was handled.
 153  */
 154
 155 irqreturn_t et131x_isr(int irq, void *dev_id)
 156 {
 157         bool handled = true;
 158         struct net_device *netdev = (struct net_device *)dev_id;
 159         struct et131x_adapter *adapter = NULL;
 160         u32 status;
 161
 162         if (!netif_device_present(netdev)) {
 163                 handled = false;
 164                 goto out;
 165         }
 166
 167         adapter = netdev_priv(netdev);
 168
 169         /* If the adapter is in low power state, then it should not
 170          * recognize any interrupt
 171          */
 172
 173         /* Disable Device Interrupts */
 174         et131x_disable_interrupts(adapter);
 175
 176         /* Get a copy of the value in the interrupt status register
 177          * so we can process the interrupting section
 178          */
 179         status = readl(&adapter->regs->global.int_status);
 180
 181         if (adapter->flowcontrol == FLOW_TXONLY ||
 182             adapter->flowcontrol == FLOW_BOTH) {
 183                 status &= ~INT_MASK_ENABLE;
 184         } else {
 185                 status &= ~INT_MASK_ENABLE_NO_FLOW;
 186         }
 187
 188         /* Make sure this is our interrupt */
 189         if (!status) {
 190                 handled = false;
 191                 et131x_enable_interrupts(adapter);
 192                 goto out;
 193         }
 194
 195         /* This is our interrupt, so process accordingly */
 196
 197         if (status & ET_INTR_WATCHDOG) {
 198                 struct tcb *tcb = adapter->tx_ring.send_head;
 199
 200                 if (tcb)
 201                         if (++tcb->stale > 1)
 202                                 status |= ET_INTR_TXDMA_ISR;
 203
 204                 if (adapter->rx_ring.unfinished_receives)
 205                         status |= ET_INTR_RXDMA_XFR_DONE;
 206                 else if (tcb == NULL)
 207                         writel(0, &adapter->regs->global.watchdog_timer);
 208
 209                 status &= ~ET_INTR_WATCHDOG;
 210         }
 211
 212         if (status == 0) {
 213                 /* This interrupt has in some way been "handled" by
 214                  * the ISR. Either it was a spurious Rx interrupt, or
 215                  * it was a Tx interrupt that has been filtered by
 216                  * the ISR.
 217                  */
 218                 et131x_enable_interrupts(adapter);
 219                 goto out;
 220         }
 221
 222         /* We need to save the interrupt status value for use in our
 223          * DPC. We will clear the software copy of that in that
 224          * routine.
 225          */
 226         adapter->stats.interrupt_status = status;
 227
 228         /* Schedule the ISR handler as a bottom-half task in the
 229          * kernel's tq_immediate queue, and mark the queue for
 230          * execution
 231          */
 232         schedule_work(&adapter->task);
 233 out:
 234         return IRQ_RETVAL(handled);
 235 }
 236
 237 /**
 238  * et131x_isr_handler - The ISR handler
 239  * @p_adapter, a pointer to the device's private adapter structure
 240  *
 241  * scheduled to run in a deferred context by the ISR. This is where the ISR's
 242  * work actually gets done.
 243  */
 244 void et131x_isr_handler(struct work_struct *work)
 245 {
 246         struct et131x_adapter *adapter =
 247                 container_of(work, struct et131x_adapter, task);
 248         u32 status = adapter->stats.interrupt_status;
 249         struct address_map __iomem *iomem = adapter->regs;
 250
 251         /*
 252          * These first two are by far the most common.  Once handled, we clear
 253          * their two bits in the status word.  If the word is now zero, we
 254          * exit.
 255          */
 256         /* Handle all the completed Transmit interrupts */
 257         if (status & ET_INTR_TXDMA_ISR)
 258                 et131x_handle_send_interrupt(adapter);
 259
 260         /* Handle all the completed Receives interrupts */
 261         if (status & ET_INTR_RXDMA_XFR_DONE)
 262                 et131x_handle_recv_interrupt(adapter);
 263
 264         status &= 0xffffffd7;
 265
 266         if (status) {
 267                 /* Handle the TXDMA Error interrupt */
 268                 if (status & ET_INTR_TXDMA_ERR) {
 269                         u32 txdma_err;
 270
 271                         /* Following read also clears the register (COR) */
 272                         txdma_err = readl(&iomem->txdma.tx_dma_error);
 273
 274                         dev_warn(&adapter->pdev->dev,
 275                                     "TXDMA_ERR interrupt, error = %d\n",
 276                                     txdma_err);
 277                 }
 278
 279                 /* Handle Free Buffer Ring 0 and 1 Low interrupt */
 280                 if (status &
 281                     (ET_INTR_RXDMA_FB_R0_LOW | ET_INTR_RXDMA_FB_R1_LOW)) {
 282                         /*
 283                          * This indicates the number of unused buffers in
 284                          * RXDMA free buffer ring 0 is <= the limit you
 285                          * programmed. Free buffer resources need to be
 286                          * returned.  Free buffers are consumed as packets
 287                          * are passed from the network to the host. The host
 288                          * becomes aware of the packets from the contents of
 289                          * the packet status ring. This ring is queried when
 290                          * the packet done interrupt occurs. Packets are then
 291                          * passed to the OS. When the OS is done with the
 292                          * packets the resources can be returned to the
 293                          * ET1310 for re-use. This interrupt is one method of
 294                          * returning resources.
 295                          */
 296
 297                         /* If the user has flow control on, then we will
 298                          * send a pause packet, otherwise just exit
 299                          */
 300                         if (adapter->flowcontrol == FLOW_TXONLY ||
 301                             adapter->flowcontrol == FLOW_BOTH) {
 302                                 u32 pm_csr;
 303
 304                                 /* Tell the device to send a pause packet via
 305                                  * the back pressure register (bp req  and
 306                                  * bp xon/xoff)
 307                                  */
 308                                 pm_csr = readl(&iomem->global.pm_csr);
 309                                 if (!et1310_in_phy_coma(adapter))
 310                                         writel(3, &iomem->txmac.bp_ctrl);
 311                         }
 312                 }
 313
 314                 /* Handle Packet Status Ring Low Interrupt */
 315                 if (status & ET_INTR_RXDMA_STAT_LOW) {
 316
 317                         /*
 318                          * Same idea as with the two Free Buffer Rings.
 319                          * Packets going from the network to the host each
 320                          * consume a free buffer resource and a packet status
 321                          * resource.  These resoures are passed to the OS.
 322                          * When the OS is done with the resources, they need
 323                          * to be returned to the ET1310. This is one method
 324                          * of returning the resources.
 325                          */
 326                 }
 327
 328                 /* Handle RXDMA Error Interrupt */
 329                 if (status & ET_INTR_RXDMA_ERR) {
 330                         /*
 331                          * The rxdma_error interrupt is sent when a time-out
 332                          * on a request issued by the JAGCore has occurred or
 333                          * a completion is returned with an un-successful
 334                          * status.  In both cases the request is considered
 335                          * complete. The JAGCore will automatically re-try the
 336                          * request in question. Normally information on events
 337                          * like these are sent to the host using the "Advanced
 338                          * Error Reporting" capability. This interrupt is
 339                          * another way of getting similar information. The
 340                          * only thing required is to clear the interrupt by
 341                          * reading the ISR in the global resources. The
 342                          * JAGCore will do a re-try on the request.  Normally
 343                          * you should never see this interrupt. If you start
 344                          * to see this interrupt occurring frequently then
 345                          * something bad has occurred. A reset might be the
 346                          * thing to do.
 347                          */
 348                         /* TRAP();*/
 349
 350                         dev_warn(&adapter->pdev->dev,
 351                                     "RxDMA_ERR interrupt, error %x\n",
 352                                     readl(&iomem->txmac.tx_test));
 353                 }
 354
 355                 /* Handle the Wake on LAN Event */
 356                 if (status & ET_INTR_WOL) {
 357                         /*
 358                          * This is a secondary interrupt for wake on LAN.
 359                          * The driver should never see this, if it does,
 360                          * something serious is wrong. We will TRAP the
 361                          * message when we are in DBG mode, otherwise we
 362                          * will ignore it.
 363                          */
 364                         dev_err(&adapter->pdev->dev, "WAKE_ON_LAN interrupt\n");
 365                 }
 366
 367                 /* Let's move on to the TxMac */
 368                 if (status & ET_INTR_TXMAC) {
 369                         u32 err = readl(&iomem->txmac.err);
 370
 371                         /*
 372                          * When any of the errors occur and TXMAC generates
 373                          * an interrupt to report these errors, it usually
 374                          * means that TXMAC has detected an error in the data
 375                          * stream retrieved from the on-chip Tx Q. All of
 376                          * these errors are catastrophic and TXMAC won't be
 377                          * able to recover data when these errors occur.  In
 378                          * a nutshell, the whole Tx path will have to be reset
 379                          * and re-configured afterwards.
 380                          */
 381                         dev_warn(&adapter->pdev->dev,
 382                                     "TXMAC interrupt, error 0x%08x\n",
 383                                     err);
 384
 385                         /* If we are debugging, we want to see this error,
 386                          * otherwise we just want the device to be reset and
 387                          * continue
 388                          */
 389                 }
 390
 391                 /* Handle RXMAC Interrupt */
 392                 if (status & ET_INTR_RXMAC) {
 393                         /*
 394                          * These interrupts are catastrophic to the device,
 395                          * what we need to do is disable the interrupts and
 396                          * set the flag to cause us to reset so we can solve
 397                          * this issue.
 398                          */
 399                         /* MP_SET_FLAG( adapter,
 400                                                 fMP_ADAPTER_HARDWARE_ERROR); */
 401
 402                         dev_warn(&adapter->pdev->dev,
 403                           "RXMAC interrupt, error 0x%08x.  Requesting reset\n",
 404                                     readl(&iomem->rxmac.err_reg));
 405
 406                         dev_warn(&adapter->pdev->dev,
 407                                     "Enable 0x%08x, Diag 0x%08x\n",
 408                                     readl(&iomem->rxmac.ctrl),
 409                                     readl(&iomem->rxmac.rxq_diag));
 410
 411                         /*
 412                          * If we are debugging, we want to see this error,
 413                          * otherwise we just want the device to be reset and
 414                          * continue
 415                          */
 416                 }
 417
 418                 /* Handle MAC_STAT Interrupt */
 419                 if (status & ET_INTR_MAC_STAT) {
 420                         /*
 421                          * This means at least one of the un-masked counters
 422                          * in the MAC_STAT block has rolled over.  Use this
 423                          * to maintain the top, software managed bits of the
 424                          * counter(s).
 425                          */
 426                         et1310_handle_macstat_interrupt(adapter);
 427                 }
 428
 429                 /* Handle SLV Timeout Interrupt */
 430                 if (status & ET_INTR_SLV_TIMEOUT) {
 431                         /*
 432                          * This means a timeout has occurred on a read or
 433                          * write request to one of the JAGCore registers. The
 434                          * Global Resources block has terminated the request
 435                          * and on a read request, returned a "fake" value.
 436                          * The most likely reasons are: Bad Address or the
 437                          * addressed module is in a power-down state and
 438                          * can't respond.
 439                          */
 440                 }
 441         }
 442         et131x_enable_interrupts(adapter);
 443 }