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sky2: version 1.30
[zen-stable.git] / drivers / net / ethernet / marvell / sky2.c
blob539de09cffc956b50d8039d07a03959db5298918
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/slab.h>
38 #include <net/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/in.h>
41 #include <linux/delay.h>
42 #include <linux/workqueue.h>
43 #include <linux/if_vlan.h>
44 #include <linux/prefetch.h>
45 #include <linux/debugfs.h>
46 #include <linux/mii.h>
47
48 #include <asm/irq.h>
49
50 #include "sky2.h"
51
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.30"
54
55 /*
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
58 * similar to Tigon3.
59 */
60
61 #define RX_LE_SIZE 1024
62 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
63 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
64 #define RX_DEF_PENDING RX_MAX_PENDING
65
66 /* This is the worst case number of transmit list elements for a single skb:
67 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
68 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
69 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
70 #define TX_MAX_PENDING 1024
71 #define TX_DEF_PENDING 63
72
73 #define TX_WATCHDOG (5 * HZ)
74 #define NAPI_WEIGHT 64
75 #define PHY_RETRIES 1000
76
77 #define SKY2_EEPROM_MAGIC 0x9955aabb
78
79 #define RING_NEXT(x, s) (((x)+1) & ((s)-1))
80
81 static const u32 default_msg =
82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
85
86 static int debug = -1; /* defaults above */
87 module_param(debug, int, 0);
88 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
89
90 static int copybreak __read_mostly = 128;
91 module_param(copybreak, int, 0);
92 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
93
94 static int disable_msi = 0;
95 module_param(disable_msi, int, 0);
96 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97
98 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
99 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
100 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
102 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
140 { 0 }
141 };
142
143 MODULE_DEVICE_TABLE(pci, sky2_id_table);
144
145 /* Avoid conditionals by using array */
146 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
148 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
149
150 static void sky2_set_multicast(struct net_device *dev);
151 static irqreturn_t sky2_intr(int irq, void *dev_id);
152
153 /* Access to PHY via serial interconnect */
154 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
155 {
156 int i;
157
158 gma_write16(hw, port, GM_SMI_DATA, val);
159 gma_write16(hw, port, GM_SMI_CTRL,
160 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
161
162 for (i = 0; i < PHY_RETRIES; i++) {
163 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
164 if (ctrl == 0xffff)
165 goto io_error;
166
167 if (!(ctrl & GM_SMI_CT_BUSY))
168 return 0;
169
170 udelay(10);
171 }
172
173 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name);
174 return -ETIMEDOUT;
175
176 io_error:
177 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
178 return -EIO;
179 }
180
181 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
182 {
183 int i;
184
185 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
186 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
187
188 for (i = 0; i < PHY_RETRIES; i++) {
189 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
190 if (ctrl == 0xffff)
191 goto io_error;
192
193 if (ctrl & GM_SMI_CT_RD_VAL) {
194 *val = gma_read16(hw, port, GM_SMI_DATA);
195 return 0;
196 }
197
198 udelay(10);
199 }
200
201 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
202 return -ETIMEDOUT;
203 io_error:
204 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
205 return -EIO;
206 }
207
208 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
209 {
210 u16 v;
211 __gm_phy_read(hw, port, reg, &v);
212 return v;
213 }
214
215
216 static void sky2_power_on(struct sky2_hw *hw)
217 {
218 /* switch power to VCC (WA for VAUX problem) */
219 sky2_write8(hw, B0_POWER_CTRL,
220 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
221
222 /* disable Core Clock Division, */
223 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
224
225 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
226 /* enable bits are inverted */
227 sky2_write8(hw, B2_Y2_CLK_GATE,
228 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
229 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
230 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
231 else
232 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
233
234 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
235 u32 reg;
236
237 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
238
239 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
240 /* set all bits to 0 except bits 15..12 and 8 */
241 reg &= P_ASPM_CONTROL_MSK;
242 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
243
244 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
245 /* set all bits to 0 except bits 28 & 27 */
246 reg &= P_CTL_TIM_VMAIN_AV_MSK;
247 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
248
249 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
250
251 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
252
253 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
254 reg = sky2_read32(hw, B2_GP_IO);
255 reg |= GLB_GPIO_STAT_RACE_DIS;
256 sky2_write32(hw, B2_GP_IO, reg);
257
258 sky2_read32(hw, B2_GP_IO);
259 }
260
261 /* Turn on "driver loaded" LED */
262 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
263 }
264
265 static void sky2_power_aux(struct sky2_hw *hw)
266 {
267 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
268 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
269 else
270 /* enable bits are inverted */
271 sky2_write8(hw, B2_Y2_CLK_GATE,
272 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
273 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
274 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
275
276 /* switch power to VAUX if supported and PME from D3cold */
277 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
278 pci_pme_capable(hw->pdev, PCI_D3cold))
279 sky2_write8(hw, B0_POWER_CTRL,
280 (PC_VAUX_ENA | PC_VCC_ENA |
281 PC_VAUX_ON | PC_VCC_OFF));
282
283 /* turn off "driver loaded LED" */
284 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
285 }
286
287 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
288 {
289 u16 reg;
290
291 /* disable all GMAC IRQ's */
292 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
293
294 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
295 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
297 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
298
299 reg = gma_read16(hw, port, GM_RX_CTRL);
300 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
301 gma_write16(hw, port, GM_RX_CTRL, reg);
302 }
303
304 /* flow control to advertise bits */
305 static const u16 copper_fc_adv[] = {
306 [FC_NONE] = 0,
307 [FC_TX] = PHY_M_AN_ASP,
308 [FC_RX] = PHY_M_AN_PC,
309 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
310 };
311
312 /* flow control to advertise bits when using 1000BaseX */
313 static const u16 fiber_fc_adv[] = {
314 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
315 [FC_TX] = PHY_M_P_ASYM_MD_X,
316 [FC_RX] = PHY_M_P_SYM_MD_X,
317 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
318 };
319
320 /* flow control to GMA disable bits */
321 static const u16 gm_fc_disable[] = {
322 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
323 [FC_TX] = GM_GPCR_FC_RX_DIS,
324 [FC_RX] = GM_GPCR_FC_TX_DIS,
325 [FC_BOTH] = 0,
326 };
327
328
329 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
330 {
331 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
332 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
333
334 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
335 !(hw->flags & SKY2_HW_NEWER_PHY)) {
336 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
337
338 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
339 PHY_M_EC_MAC_S_MSK);
340 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
341
342 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
343 if (hw->chip_id == CHIP_ID_YUKON_EC)
344 /* set downshift counter to 3x and enable downshift */
345 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
346 else
347 /* set master & slave downshift counter to 1x */
348 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
349
350 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
351 }
352
353 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
354 if (sky2_is_copper(hw)) {
355 if (!(hw->flags & SKY2_HW_GIGABIT)) {
356 /* enable automatic crossover */
357 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
358
359 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
360 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
361 u16 spec;
362
363 /* Enable Class A driver for FE+ A0 */
364 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
365 spec |= PHY_M_FESC_SEL_CL_A;
366 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
367 }
368 } else {
369 /* disable energy detect */
370 ctrl &= ~PHY_M_PC_EN_DET_MSK;
371
372 /* enable automatic crossover */
373 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
374
375 /* downshift on PHY 88E1112 and 88E1149 is changed */
376 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
377 (hw->flags & SKY2_HW_NEWER_PHY)) {
378 /* set downshift counter to 3x and enable downshift */
379 ctrl &= ~PHY_M_PC_DSC_MSK;
380 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
381 }
382 }
383 } else {
384 /* workaround for deviation #4.88 (CRC errors) */
385 /* disable Automatic Crossover */
386
387 ctrl &= ~PHY_M_PC_MDIX_MSK;
388 }
389
390 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
391
392 /* special setup for PHY 88E1112 Fiber */
393 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
394 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
395
396 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
397 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl &= ~PHY_M_MAC_MD_MSK;
400 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
401 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
402
403 if (hw->pmd_type == 'P') {
404 /* select page 1 to access Fiber registers */
405 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
406
407 /* for SFP-module set SIGDET polarity to low */
408 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
409 ctrl |= PHY_M_FIB_SIGD_POL;
410 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
411 }
412
413 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
414 }
415
416 ctrl = PHY_CT_RESET;
417 ct1000 = 0;
418 adv = PHY_AN_CSMA;
419 reg = 0;
420
421 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
422 if (sky2_is_copper(hw)) {
423 if (sky2->advertising & ADVERTISED_1000baseT_Full)
424 ct1000 |= PHY_M_1000C_AFD;
425 if (sky2->advertising & ADVERTISED_1000baseT_Half)
426 ct1000 |= PHY_M_1000C_AHD;
427 if (sky2->advertising & ADVERTISED_100baseT_Full)
428 adv |= PHY_M_AN_100_FD;
429 if (sky2->advertising & ADVERTISED_100baseT_Half)
430 adv |= PHY_M_AN_100_HD;
431 if (sky2->advertising & ADVERTISED_10baseT_Full)
432 adv |= PHY_M_AN_10_FD;
433 if (sky2->advertising & ADVERTISED_10baseT_Half)
434 adv |= PHY_M_AN_10_HD;
435
436 } else { /* special defines for FIBER (88E1040S only) */
437 if (sky2->advertising & ADVERTISED_1000baseT_Full)
438 adv |= PHY_M_AN_1000X_AFD;
439 if (sky2->advertising & ADVERTISED_1000baseT_Half)
440 adv |= PHY_M_AN_1000X_AHD;
441 }
442
443 /* Restart Auto-negotiation */
444 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
445 } else {
446 /* forced speed/duplex settings */
447 ct1000 = PHY_M_1000C_MSE;
448
449 /* Disable auto update for duplex flow control and duplex */
450 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
451
452 switch (sky2->speed) {
453 case SPEED_1000:
454 ctrl |= PHY_CT_SP1000;
455 reg |= GM_GPCR_SPEED_1000;
456 break;
457 case SPEED_100:
458 ctrl |= PHY_CT_SP100;
459 reg |= GM_GPCR_SPEED_100;
460 break;
461 }
462
463 if (sky2->duplex == DUPLEX_FULL) {
464 reg |= GM_GPCR_DUP_FULL;
465 ctrl |= PHY_CT_DUP_MD;
466 } else if (sky2->speed < SPEED_1000)
467 sky2->flow_mode = FC_NONE;
468 }
469
470 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
471 if (sky2_is_copper(hw))
472 adv |= copper_fc_adv[sky2->flow_mode];
473 else
474 adv |= fiber_fc_adv[sky2->flow_mode];
475 } else {
476 reg |= GM_GPCR_AU_FCT_DIS;
477 reg |= gm_fc_disable[sky2->flow_mode];
478
479 /* Forward pause packets to GMAC? */
480 if (sky2->flow_mode & FC_RX)
481 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
482 else
483 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
484 }
485
486 gma_write16(hw, port, GM_GP_CTRL, reg);
487
488 if (hw->flags & SKY2_HW_GIGABIT)
489 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
490
491 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
492 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
493
494 /* Setup Phy LED's */
495 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
496 ledover = 0;
497
498 switch (hw->chip_id) {
499 case CHIP_ID_YUKON_FE:
500 /* on 88E3082 these bits are at 11..9 (shifted left) */
501 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
502
503 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
504
505 /* delete ACT LED control bits */
506 ctrl &= ~PHY_M_FELP_LED1_MSK;
507 /* change ACT LED control to blink mode */
508 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
509 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
510 break;
511
512 case CHIP_ID_YUKON_FE_P:
513 /* Enable Link Partner Next Page */
514 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
515 ctrl |= PHY_M_PC_ENA_LIP_NP;
516
517 /* disable Energy Detect and enable scrambler */
518 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
519 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
520
521 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
522 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
523 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
524 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
525
526 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
527 break;
528
529 case CHIP_ID_YUKON_XL:
530 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
531
532 /* select page 3 to access LED control register */
533 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
534
535 /* set LED Function Control register */
536 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
537 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
538 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
539 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
540 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
541
542 /* set Polarity Control register */
543 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
544 (PHY_M_POLC_LS1_P_MIX(4) |
545 PHY_M_POLC_IS0_P_MIX(4) |
546 PHY_M_POLC_LOS_CTRL(2) |
547 PHY_M_POLC_INIT_CTRL(2) |
548 PHY_M_POLC_STA1_CTRL(2) |
549 PHY_M_POLC_STA0_CTRL(2)));
550
551 /* restore page register */
552 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
553 break;
554
555 case CHIP_ID_YUKON_EC_U:
556 case CHIP_ID_YUKON_EX:
557 case CHIP_ID_YUKON_SUPR:
558 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
559
560 /* select page 3 to access LED control register */
561 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
562
563 /* set LED Function Control register */
564 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
565 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
566 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
567 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
568 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
569
570 /* set Blink Rate in LED Timer Control Register */
571 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
572 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
573 /* restore page register */
574 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
575 break;
576
577 default:
578 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
579 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
580
581 /* turn off the Rx LED (LED_RX) */
582 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
583 }
584
585 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
586 /* apply fixes in PHY AFE */
587 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
588
589 /* increase differential signal amplitude in 10BASE-T */
590 gm_phy_write(hw, port, 0x18, 0xaa99);
591 gm_phy_write(hw, port, 0x17, 0x2011);
592
593 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
594 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
595 gm_phy_write(hw, port, 0x18, 0xa204);
596 gm_phy_write(hw, port, 0x17, 0x2002);
597 }
598
599 /* set page register to 0 */
600 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
601 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
602 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
603 /* apply workaround for integrated resistors calibration */
604 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
605 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
606 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
607 /* apply fixes in PHY AFE */
608 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
609
610 /* apply RDAC termination workaround */
611 gm_phy_write(hw, port, 24, 0x2800);
612 gm_phy_write(hw, port, 23, 0x2001);
613
614 /* set page register back to 0 */
615 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
616 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
617 hw->chip_id < CHIP_ID_YUKON_SUPR) {
618 /* no effect on Yukon-XL */
619 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
620
621 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
622 sky2->speed == SPEED_100) {
623 /* turn on 100 Mbps LED (LED_LINK100) */
624 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
625 }
626
627 if (ledover)
628 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
629
630 } else if (hw->chip_id == CHIP_ID_YUKON_PRM &&
631 (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) {
632 int i;
633 /* This a phy register setup workaround copied from vendor driver. */
634 static const struct {
635 u16 reg, val;
636 } eee_afe[] = {
637 { 0x156, 0x58ce },
638 { 0x153, 0x99eb },
639 { 0x141, 0x8064 },
640 /* { 0x155, 0x130b },*/
641 { 0x000, 0x0000 },
642 { 0x151, 0x8433 },
643 { 0x14b, 0x8c44 },
644 { 0x14c, 0x0f90 },
645 { 0x14f, 0x39aa },
646 /* { 0x154, 0x2f39 },*/
647 { 0x14d, 0xba33 },
648 { 0x144, 0x0048 },
649 { 0x152, 0x2010 },
650 /* { 0x158, 0x1223 },*/
651 { 0x140, 0x4444 },
652 { 0x154, 0x2f3b },
653 { 0x158, 0xb203 },
654 { 0x157, 0x2029 },
655 };
656
657 /* Start Workaround for OptimaEEE Rev.Z0 */
658 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb);
659
660 gm_phy_write(hw, port, 1, 0x4099);
661 gm_phy_write(hw, port, 3, 0x1120);
662 gm_phy_write(hw, port, 11, 0x113c);
663 gm_phy_write(hw, port, 14, 0x8100);
664 gm_phy_write(hw, port, 15, 0x112a);
665 gm_phy_write(hw, port, 17, 0x1008);
666
667 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc);
668 gm_phy_write(hw, port, 1, 0x20b0);
669
670 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
671
672 for (i = 0; i < ARRAY_SIZE(eee_afe); i++) {
673 /* apply AFE settings */
674 gm_phy_write(hw, port, 17, eee_afe[i].val);
675 gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13);
676 }
677
678 /* End Workaround for OptimaEEE */
679 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
680
681 /* Enable 10Base-Te (EEE) */
682 if (hw->chip_id >= CHIP_ID_YUKON_PRM) {
683 reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
684 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL,
685 reg | PHY_M_10B_TE_ENABLE);
686 }
687 }
688
689 /* Enable phy interrupt on auto-negotiation complete (or link up) */
690 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
691 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
692 else
693 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
694 }
695
696 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
697 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
698
699 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
700 {
701 u32 reg1;
702
703 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
704 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
705 reg1 &= ~phy_power[port];
706
707 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
708 reg1 |= coma_mode[port];
709
710 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
711 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
712 sky2_pci_read32(hw, PCI_DEV_REG1);
713
714 if (hw->chip_id == CHIP_ID_YUKON_FE)
715 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
716 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
717 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
718 }
719
720 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
721 {
722 u32 reg1;
723 u16 ctrl;
724
725 /* release GPHY Control reset */
726 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
727
728 /* release GMAC reset */
729 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
730
731 if (hw->flags & SKY2_HW_NEWER_PHY) {
732 /* select page 2 to access MAC control register */
733 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
734
735 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
736 /* allow GMII Power Down */
737 ctrl &= ~PHY_M_MAC_GMIF_PUP;
738 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
739
740 /* set page register back to 0 */
741 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
742 }
743
744 /* setup General Purpose Control Register */
745 gma_write16(hw, port, GM_GP_CTRL,
746 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
747 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
748 GM_GPCR_AU_SPD_DIS);
749
750 if (hw->chip_id != CHIP_ID_YUKON_EC) {
751 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
752 /* select page 2 to access MAC control register */
753 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
754
755 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
756 /* enable Power Down */
757 ctrl |= PHY_M_PC_POW_D_ENA;
758 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
759
760 /* set page register back to 0 */
761 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
762 }
763
764 /* set IEEE compatible Power Down Mode (dev. #4.99) */
765 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
766 }
767
768 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
769 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
770 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
771 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
772 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
773 }
774
775 /* configure IPG according to used link speed */
776 static void sky2_set_ipg(struct sky2_port *sky2)
777 {
778 u16 reg;
779
780 reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE);
781 reg &= ~GM_SMOD_IPG_MSK;
782 if (sky2->speed > SPEED_100)
783 reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
784 else
785 reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
786 gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg);
787 }
788
789 /* Enable Rx/Tx */
790 static void sky2_enable_rx_tx(struct sky2_port *sky2)
791 {
792 struct sky2_hw *hw = sky2->hw;
793 unsigned port = sky2->port;
794 u16 reg;
795
796 reg = gma_read16(hw, port, GM_GP_CTRL);
797 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
798 gma_write16(hw, port, GM_GP_CTRL, reg);
799 }
800
801 /* Force a renegotiation */
802 static void sky2_phy_reinit(struct sky2_port *sky2)
803 {
804 spin_lock_bh(&sky2->phy_lock);
805 sky2_phy_init(sky2->hw, sky2->port);
806 sky2_enable_rx_tx(sky2);
807 spin_unlock_bh(&sky2->phy_lock);
808 }
809
810 /* Put device in state to listen for Wake On Lan */
811 static void sky2_wol_init(struct sky2_port *sky2)
812 {
813 struct sky2_hw *hw = sky2->hw;
814 unsigned port = sky2->port;
815 enum flow_control save_mode;
816 u16 ctrl;
817
818 /* Bring hardware out of reset */
819 sky2_write16(hw, B0_CTST, CS_RST_CLR);
820 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
821
822 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
823 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
824
825 /* Force to 10/100
826 * sky2_reset will re-enable on resume
827 */
828 save_mode = sky2->flow_mode;
829 ctrl = sky2->advertising;
830
831 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
832 sky2->flow_mode = FC_NONE;
833
834 spin_lock_bh(&sky2->phy_lock);
835 sky2_phy_power_up(hw, port);
836 sky2_phy_init(hw, port);
837 spin_unlock_bh(&sky2->phy_lock);
838
839 sky2->flow_mode = save_mode;
840 sky2->advertising = ctrl;
841
842 /* Set GMAC to no flow control and auto update for speed/duplex */
843 gma_write16(hw, port, GM_GP_CTRL,
844 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
845 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
846
847 /* Set WOL address */
848 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
849 sky2->netdev->dev_addr, ETH_ALEN);
850
851 /* Turn on appropriate WOL control bits */
852 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
853 ctrl = 0;
854 if (sky2->wol & WAKE_PHY)
855 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
856 else
857 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
858
859 if (sky2->wol & WAKE_MAGIC)
860 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
861 else
862 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
863
864 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
865 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
866
867 /* Disable PiG firmware */
868 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
869
870 /* block receiver */
871 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
872 sky2_read32(hw, B0_CTST);
873 }
874
875 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
876 {
877 struct net_device *dev = hw->dev[port];
878
879 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
880 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
881 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
882 /* Yukon-Extreme B0 and further Extreme devices */
883 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
884 } else if (dev->mtu > ETH_DATA_LEN) {
885 /* set Tx GMAC FIFO Almost Empty Threshold */
886 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
887 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
888
889 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
890 } else
891 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
892 }
893
894 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
895 {
896 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
897 u16 reg;
898 u32 rx_reg;
899 int i;
900 const u8 *addr = hw->dev[port]->dev_addr;
901
902 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
903 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
904
905 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
906
907 if (hw->chip_id == CHIP_ID_YUKON_XL &&
908 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
909 port == 1) {
910 /* WA DEV_472 -- looks like crossed wires on port 2 */
911 /* clear GMAC 1 Control reset */
912 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
913 do {
914 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
915 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
916 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
917 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
918 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
919 }
920
921 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
922
923 /* Enable Transmit FIFO Underrun */
924 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
925
926 spin_lock_bh(&sky2->phy_lock);
927 sky2_phy_power_up(hw, port);
928 sky2_phy_init(hw, port);
929 spin_unlock_bh(&sky2->phy_lock);
930
931 /* MIB clear */
932 reg = gma_read16(hw, port, GM_PHY_ADDR);
933 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
934
935 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
936 gma_read16(hw, port, i);
937 gma_write16(hw, port, GM_PHY_ADDR, reg);
938
939 /* transmit control */
940 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
941
942 /* receive control reg: unicast + multicast + no FCS */
943 gma_write16(hw, port, GM_RX_CTRL,
944 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
945
946 /* transmit flow control */
947 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
948
949 /* transmit parameter */
950 gma_write16(hw, port, GM_TX_PARAM,
951 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
952 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
953 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
954 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
955
956 /* serial mode register */
957 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
958 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000);
959
960 if (hw->dev[port]->mtu > ETH_DATA_LEN)
961 reg |= GM_SMOD_JUMBO_ENA;
962
963 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
964 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
965 reg |= GM_NEW_FLOW_CTRL;
966
967 gma_write16(hw, port, GM_SERIAL_MODE, reg);
968
969 /* virtual address for data */
970 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
971
972 /* physical address: used for pause frames */
973 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
974
975 /* ignore counter overflows */
976 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
977 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
978 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
979
980 /* Configure Rx MAC FIFO */
981 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
982 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
983 if (hw->chip_id == CHIP_ID_YUKON_EX ||
984 hw->chip_id == CHIP_ID_YUKON_FE_P)
985 rx_reg |= GMF_RX_OVER_ON;
986
987 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
988
989 if (hw->chip_id == CHIP_ID_YUKON_XL) {
990 /* Hardware errata - clear flush mask */
991 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
992 } else {
993 /* Flush Rx MAC FIFO on any flow control or error */
994 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
995 }
996
997 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
998 reg = RX_GMF_FL_THR_DEF + 1;
999 /* Another magic mystery workaround from sk98lin */
1000 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1001 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1002 reg = 0x178;
1003 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
1004
1005 /* Configure Tx MAC FIFO */
1006 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1007 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1008
1009 /* On chips without ram buffer, pause is controlled by MAC level */
1010 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
1011 /* Pause threshold is scaled by 8 in bytes */
1012 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1013 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1014 reg = 1568 / 8;
1015 else
1016 reg = 1024 / 8;
1017 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
1018 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
1019
1020 sky2_set_tx_stfwd(hw, port);
1021 }
1022
1023 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1024 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
1025 /* disable dynamic watermark */
1026 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
1027 reg &= ~TX_DYN_WM_ENA;
1028 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
1029 }
1030 }
1031
1032 /* Assign Ram Buffer allocation to queue */
1033 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
1034 {
1035 u32 end;
1036
1037 /* convert from K bytes to qwords used for hw register */
1038 start *= 1024/8;
1039 space *= 1024/8;
1040 end = start + space - 1;
1041
1042 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1043 sky2_write32(hw, RB_ADDR(q, RB_START), start);
1044 sky2_write32(hw, RB_ADDR(q, RB_END), end);
1045 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
1046 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
1047
1048 if (q == Q_R1 || q == Q_R2) {
1049 u32 tp = space - space/4;
1050
1051 /* On receive queue's set the thresholds
1052 * give receiver priority when > 3/4 full
1053 * send pause when down to 2K
1054 */
1055 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
1056 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
1057
1058 tp = space - 2048/8;
1059 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
1060 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
1061 } else {
1062 /* Enable store & forward on Tx queue's because
1063 * Tx FIFO is only 1K on Yukon
1064 */
1065 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1066 }
1067
1068 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
1069 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
1070 }
1071
1072 /* Setup Bus Memory Interface */
1073 static void sky2_qset(struct sky2_hw *hw, u16 q)
1074 {
1075 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1076 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1077 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1078 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1079 }
1080
1081 /* Setup prefetch unit registers. This is the interface between
1082 * hardware and driver list elements
1083 */
1084 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1085 dma_addr_t addr, u32 last)
1086 {
1087 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1088 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1089 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1090 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1091 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1092 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1093
1094 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1095 }
1096
1097 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1098 {
1099 struct sky2_tx_le *le = sky2->tx_le + *slot;
1100
1101 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1102 le->ctrl = 0;
1103 return le;
1104 }
1105
1106 static void tx_init(struct sky2_port *sky2)
1107 {
1108 struct sky2_tx_le *le;
1109
1110 sky2->tx_prod = sky2->tx_cons = 0;
1111 sky2->tx_tcpsum = 0;
1112 sky2->tx_last_mss = 0;
1113
1114 le = get_tx_le(sky2, &sky2->tx_prod);
1115 le->addr = 0;
1116 le->opcode = OP_ADDR64 | HW_OWNER;
1117 sky2->tx_last_upper = 0;
1118 }
1119
1120 /* Update chip's next pointer */
1121 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1122 {
1123 /* Make sure write' to descriptors are complete before we tell hardware */
1124 wmb();
1125 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1126
1127 /* Synchronize I/O on since next processor may write to tail */
1128 mmiowb();
1129 }
1130
1131
1132 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1133 {
1134 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1135 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1136 le->ctrl = 0;
1137 return le;
1138 }
1139
1140 static unsigned sky2_get_rx_threshold(struct sky2_port *sky2)
1141 {
1142 unsigned size;
1143
1144 /* Space needed for frame data + headers rounded up */
1145 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1146
1147 /* Stopping point for hardware truncation */
1148 return (size - 8) / sizeof(u32);
1149 }
1150
1151 static unsigned sky2_get_rx_data_size(struct sky2_port *sky2)
1152 {
1153 struct rx_ring_info *re;
1154 unsigned size;
1155
1156 /* Space needed for frame data + headers rounded up */
1157 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1158
1159 sky2->rx_nfrags = size >> PAGE_SHIFT;
1160 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1161
1162 /* Compute residue after pages */
1163 size -= sky2->rx_nfrags << PAGE_SHIFT;
1164
1165 /* Optimize to handle small packets and headers */
1166 if (size < copybreak)
1167 size = copybreak;
1168 if (size < ETH_HLEN)
1169 size = ETH_HLEN;
1170
1171 return size;
1172 }
1173
1174 /* Build description to hardware for one receive segment */
1175 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1176 dma_addr_t map, unsigned len)
1177 {
1178 struct sky2_rx_le *le;
1179
1180 if (sizeof(dma_addr_t) > sizeof(u32)) {
1181 le = sky2_next_rx(sky2);
1182 le->addr = cpu_to_le32(upper_32_bits(map));
1183 le->opcode = OP_ADDR64 | HW_OWNER;
1184 }
1185
1186 le = sky2_next_rx(sky2);
1187 le->addr = cpu_to_le32(lower_32_bits(map));
1188 le->length = cpu_to_le16(len);
1189 le->opcode = op | HW_OWNER;
1190 }
1191
1192 /* Build description to hardware for one possibly fragmented skb */
1193 static void sky2_rx_submit(struct sky2_port *sky2,
1194 const struct rx_ring_info *re)
1195 {
1196 int i;
1197
1198 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1199
1200 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1201 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1202 }
1203
1204
1205 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1206 unsigned size)
1207 {
1208 struct sk_buff *skb = re->skb;
1209 int i;
1210
1211 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1212 if (pci_dma_mapping_error(pdev, re->data_addr))
1213 goto mapping_error;
1214
1215 dma_unmap_len_set(re, data_size, size);
1216
1217 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1218 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1219
1220 re->frag_addr[i] = skb_frag_dma_map(&pdev->dev, frag, 0,
1221 skb_frag_size(frag),
1222 DMA_FROM_DEVICE);
1223
1224 if (dma_mapping_error(&pdev->dev, re->frag_addr[i]))
1225 goto map_page_error;
1226 }
1227 return 0;
1228
1229 map_page_error:
1230 while (--i >= 0) {
1231 pci_unmap_page(pdev, re->frag_addr[i],
1232 skb_frag_size(&skb_shinfo(skb)->frags[i]),
1233 PCI_DMA_FROMDEVICE);
1234 }
1235
1236 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1237 PCI_DMA_FROMDEVICE);
1238
1239 mapping_error:
1240 if (net_ratelimit())
1241 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1242 skb->dev->name);
1243 return -EIO;
1244 }
1245
1246 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1247 {
1248 struct sk_buff *skb = re->skb;
1249 int i;
1250
1251 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1252 PCI_DMA_FROMDEVICE);
1253
1254 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1255 pci_unmap_page(pdev, re->frag_addr[i],
1256 skb_frag_size(&skb_shinfo(skb)->frags[i]),
1257 PCI_DMA_FROMDEVICE);
1258 }
1259
1260 /* Tell chip where to start receive checksum.
1261 * Actually has two checksums, but set both same to avoid possible byte
1262 * order problems.
1263 */
1264 static void rx_set_checksum(struct sky2_port *sky2)
1265 {
1266 struct sky2_rx_le *le = sky2_next_rx(sky2);
1267
1268 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1269 le->ctrl = 0;
1270 le->opcode = OP_TCPSTART | HW_OWNER;
1271
1272 sky2_write32(sky2->hw,
1273 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1274 (sky2->netdev->features & NETIF_F_RXCSUM)
1275 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1276 }
1277
1278 /*
1279 * Fixed initial key as seed to RSS.
1280 */
1281 static const uint32_t rss_init_key[10] = {
1282 0x7c3351da, 0x51c5cf4e, 0x44adbdd1, 0xe8d38d18, 0x48897c43,
1283 0xb1d60e7e, 0x6a3dd760, 0x01a2e453, 0x16f46f13, 0x1a0e7b30
1284 };
1285
1286 /* Enable/disable receive hash calculation (RSS) */
1287 static void rx_set_rss(struct net_device *dev, u32 features)
1288 {
1289 struct sky2_port *sky2 = netdev_priv(dev);
1290 struct sky2_hw *hw = sky2->hw;
1291 int i, nkeys = 4;
1292
1293 /* Supports IPv6 and other modes */
1294 if (hw->flags & SKY2_HW_NEW_LE) {
1295 nkeys = 10;
1296 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1297 }
1298
1299 /* Program RSS initial values */
1300 if (features & NETIF_F_RXHASH) {
1301 for (i = 0; i < nkeys; i++)
1302 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1303 rss_init_key[i]);
1304
1305 /* Need to turn on (undocumented) flag to make hashing work */
1306 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1307 RX_STFW_ENA);
1308
1309 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1310 BMU_ENA_RX_RSS_HASH);
1311 } else
1312 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1313 BMU_DIS_RX_RSS_HASH);
1314 }
1315
1316 /*
1317 * The RX Stop command will not work for Yukon-2 if the BMU does not
1318 * reach the end of packet and since we can't make sure that we have
1319 * incoming data, we must reset the BMU while it is not doing a DMA
1320 * transfer. Since it is possible that the RX path is still active,
1321 * the RX RAM buffer will be stopped first, so any possible incoming
1322 * data will not trigger a DMA. After the RAM buffer is stopped, the
1323 * BMU is polled until any DMA in progress is ended and only then it
1324 * will be reset.
1325 */
1326 static void sky2_rx_stop(struct sky2_port *sky2)
1327 {
1328 struct sky2_hw *hw = sky2->hw;
1329 unsigned rxq = rxqaddr[sky2->port];
1330 int i;
1331
1332 /* disable the RAM Buffer receive queue */
1333 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1334
1335 for (i = 0; i < 0xffff; i++)
1336 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1337 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1338 goto stopped;
1339
1340 netdev_warn(sky2->netdev, "receiver stop failed\n");
1341 stopped:
1342 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1343
1344 /* reset the Rx prefetch unit */
1345 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1346 mmiowb();
1347 }
1348
1349 /* Clean out receive buffer area, assumes receiver hardware stopped */
1350 static void sky2_rx_clean(struct sky2_port *sky2)
1351 {
1352 unsigned i;
1353
1354 memset(sky2->rx_le, 0, RX_LE_BYTES);
1355 for (i = 0; i < sky2->rx_pending; i++) {
1356 struct rx_ring_info *re = sky2->rx_ring + i;
1357
1358 if (re->skb) {
1359 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1360 kfree_skb(re->skb);
1361 re->skb = NULL;
1362 }
1363 }
1364 }
1365
1366 /* Basic MII support */
1367 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1368 {
1369 struct mii_ioctl_data *data = if_mii(ifr);
1370 struct sky2_port *sky2 = netdev_priv(dev);
1371 struct sky2_hw *hw = sky2->hw;
1372 int err = -EOPNOTSUPP;
1373
1374 if (!netif_running(dev))
1375 return -ENODEV; /* Phy still in reset */
1376
1377 switch (cmd) {
1378 case SIOCGMIIPHY:
1379 data->phy_id = PHY_ADDR_MARV;
1380
1381 /* fallthru */
1382 case SIOCGMIIREG: {
1383 u16 val = 0;
1384
1385 spin_lock_bh(&sky2->phy_lock);
1386 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1387 spin_unlock_bh(&sky2->phy_lock);
1388
1389 data->val_out = val;
1390 break;
1391 }
1392
1393 case SIOCSMIIREG:
1394 spin_lock_bh(&sky2->phy_lock);
1395 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1396 data->val_in);
1397 spin_unlock_bh(&sky2->phy_lock);
1398 break;
1399 }
1400 return err;
1401 }
1402
1403 #define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO)
1404
1405 static void sky2_vlan_mode(struct net_device *dev, u32 features)
1406 {
1407 struct sky2_port *sky2 = netdev_priv(dev);
1408 struct sky2_hw *hw = sky2->hw;
1409 u16 port = sky2->port;
1410
1411 if (features & NETIF_F_HW_VLAN_RX)
1412 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1413 RX_VLAN_STRIP_ON);
1414 else
1415 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1416 RX_VLAN_STRIP_OFF);
1417
1418 if (features & NETIF_F_HW_VLAN_TX) {
1419 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1420 TX_VLAN_TAG_ON);
1421
1422 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
1423 } else {
1424 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1425 TX_VLAN_TAG_OFF);
1426
1427 /* Can't do transmit offload of vlan without hw vlan */
1428 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS;
1429 }
1430 }
1431
1432 /* Amount of required worst case padding in rx buffer */
1433 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1434 {
1435 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1436 }
1437
1438 /*
1439 * Allocate an skb for receiving. If the MTU is large enough
1440 * make the skb non-linear with a fragment list of pages.
1441 */
1442 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp)
1443 {
1444 struct sk_buff *skb;
1445 int i;
1446
1447 skb = __netdev_alloc_skb(sky2->netdev,
1448 sky2->rx_data_size + sky2_rx_pad(sky2->hw),
1449 gfp);
1450 if (!skb)
1451 goto nomem;
1452
1453 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1454 unsigned char *start;
1455 /*
1456 * Workaround for a bug in FIFO that cause hang
1457 * if the FIFO if the receive buffer is not 64 byte aligned.
1458 * The buffer returned from netdev_alloc_skb is
1459 * aligned except if slab debugging is enabled.
1460 */
1461 start = PTR_ALIGN(skb->data, 8);
1462 skb_reserve(skb, start - skb->data);
1463 } else
1464 skb_reserve(skb, NET_IP_ALIGN);
1465
1466 for (i = 0; i < sky2->rx_nfrags; i++) {
1467 struct page *page = alloc_page(gfp);
1468
1469 if (!page)
1470 goto free_partial;
1471 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1472 }
1473
1474 return skb;
1475 free_partial:
1476 kfree_skb(skb);
1477 nomem:
1478 return NULL;
1479 }
1480
1481 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1482 {
1483 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1484 }
1485
1486 static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1487 {
1488 struct sky2_hw *hw = sky2->hw;
1489 unsigned i;
1490
1491 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1492
1493 /* Fill Rx ring */
1494 for (i = 0; i < sky2->rx_pending; i++) {
1495 struct rx_ring_info *re = sky2->rx_ring + i;
1496
1497 re->skb = sky2_rx_alloc(sky2, GFP_KERNEL);
1498 if (!re->skb)
1499 return -ENOMEM;
1500
1501 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1502 dev_kfree_skb(re->skb);
1503 re->skb = NULL;
1504 return -ENOMEM;
1505 }
1506 }
1507 return 0;
1508 }
1509
1510 /*
1511 * Setup receiver buffer pool.
1512 * Normal case this ends up creating one list element for skb
1513 * in the receive ring. Worst case if using large MTU and each
1514 * allocation falls on a different 64 bit region, that results
1515 * in 6 list elements per ring entry.
1516 * One element is used for checksum enable/disable, and one
1517 * extra to avoid wrap.
1518 */
1519 static void sky2_rx_start(struct sky2_port *sky2)
1520 {
1521 struct sky2_hw *hw = sky2->hw;
1522 struct rx_ring_info *re;
1523 unsigned rxq = rxqaddr[sky2->port];
1524 unsigned i, thresh;
1525
1526 sky2->rx_put = sky2->rx_next = 0;
1527 sky2_qset(hw, rxq);
1528
1529 /* On PCI express lowering the watermark gives better performance */
1530 if (pci_is_pcie(hw->pdev))
1531 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1532
1533 /* These chips have no ram buffer?
1534 * MAC Rx RAM Read is controlled by hardware */
1535 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1536 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
1537 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1538
1539 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1540
1541 if (!(hw->flags & SKY2_HW_NEW_LE))
1542 rx_set_checksum(sky2);
1543
1544 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
1545 rx_set_rss(sky2->netdev, sky2->netdev->features);
1546
1547 /* submit Rx ring */
1548 for (i = 0; i < sky2->rx_pending; i++) {
1549 re = sky2->rx_ring + i;
1550 sky2_rx_submit(sky2, re);
1551 }
1552
1553 /*
1554 * The receiver hangs if it receives frames larger than the
1555 * packet buffer. As a workaround, truncate oversize frames, but
1556 * the register is limited to 9 bits, so if you do frames > 2052
1557 * you better get the MTU right!
1558 */
1559 thresh = sky2_get_rx_threshold(sky2);
1560 if (thresh > 0x1ff)
1561 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1562 else {
1563 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1564 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1565 }
1566
1567 /* Tell chip about available buffers */
1568 sky2_rx_update(sky2, rxq);
1569
1570 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1571 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1572 /*
1573 * Disable flushing of non ASF packets;
1574 * must be done after initializing the BMUs;
1575 * drivers without ASF support should do this too, otherwise
1576 * it may happen that they cannot run on ASF devices;
1577 * remember that the MAC FIFO isn't reset during initialization.
1578 */
1579 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1580 }
1581
1582 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1583 /* Enable RX Home Address & Routing Header checksum fix */
1584 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1585 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1586
1587 /* Enable TX Home Address & Routing Header checksum fix */
1588 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1589 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1590 }
1591 }
1592
1593 static int sky2_alloc_buffers(struct sky2_port *sky2)
1594 {
1595 struct sky2_hw *hw = sky2->hw;
1596
1597 /* must be power of 2 */
1598 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1599 sky2->tx_ring_size *
1600 sizeof(struct sky2_tx_le),
1601 &sky2->tx_le_map);
1602 if (!sky2->tx_le)
1603 goto nomem;
1604
1605 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1606 GFP_KERNEL);
1607 if (!sky2->tx_ring)
1608 goto nomem;
1609
1610 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1611 &sky2->rx_le_map);
1612 if (!sky2->rx_le)
1613 goto nomem;
1614 memset(sky2->rx_le, 0, RX_LE_BYTES);
1615
1616 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1617 GFP_KERNEL);
1618 if (!sky2->rx_ring)
1619 goto nomem;
1620
1621 return sky2_alloc_rx_skbs(sky2);
1622 nomem:
1623 return -ENOMEM;
1624 }
1625
1626 static void sky2_free_buffers(struct sky2_port *sky2)
1627 {
1628 struct sky2_hw *hw = sky2->hw;
1629
1630 sky2_rx_clean(sky2);
1631
1632 if (sky2->rx_le) {
1633 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1634 sky2->rx_le, sky2->rx_le_map);
1635 sky2->rx_le = NULL;
1636 }
1637 if (sky2->tx_le) {
1638 pci_free_consistent(hw->pdev,
1639 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1640 sky2->tx_le, sky2->tx_le_map);
1641 sky2->tx_le = NULL;
1642 }
1643 kfree(sky2->tx_ring);
1644 kfree(sky2->rx_ring);
1645
1646 sky2->tx_ring = NULL;
1647 sky2->rx_ring = NULL;
1648 }
1649
1650 static void sky2_hw_up(struct sky2_port *sky2)
1651 {
1652 struct sky2_hw *hw = sky2->hw;
1653 unsigned port = sky2->port;
1654 u32 ramsize;
1655 int cap;
1656 struct net_device *otherdev = hw->dev[sky2->port^1];
1657
1658 tx_init(sky2);
1659
1660 /*
1661 * On dual port PCI-X card, there is an problem where status
1662 * can be received out of order due to split transactions
1663 */
1664 if (otherdev && netif_running(otherdev) &&
1665 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1666 u16 cmd;
1667
1668 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1669 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1670 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1671 }
1672
1673 sky2_mac_init(hw, port);
1674
1675 /* Register is number of 4K blocks on internal RAM buffer. */
1676 ramsize = sky2_read8(hw, B2_E_0) * 4;
1677 if (ramsize > 0) {
1678 u32 rxspace;
1679
1680 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
1681 if (ramsize < 16)
1682 rxspace = ramsize / 2;
1683 else
1684 rxspace = 8 + (2*(ramsize - 16))/3;
1685
1686 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1687 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1688
1689 /* Make sure SyncQ is disabled */
1690 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1691 RB_RST_SET);
1692 }
1693
1694 sky2_qset(hw, txqaddr[port]);
1695
1696 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1697 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1698 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1699
1700 /* Set almost empty threshold */
1701 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1702 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1703 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1704
1705 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1706 sky2->tx_ring_size - 1);
1707
1708 sky2_vlan_mode(sky2->netdev, sky2->netdev->features);
1709 netdev_update_features(sky2->netdev);
1710
1711 sky2_rx_start(sky2);
1712 }
1713
1714 /* Setup device IRQ and enable napi to process */
1715 static int sky2_setup_irq(struct sky2_hw *hw, const char *name)
1716 {
1717 struct pci_dev *pdev = hw->pdev;
1718 int err;
1719
1720 err = request_irq(pdev->irq, sky2_intr,
1721 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
1722 name, hw);
1723 if (err)
1724 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
1725 else {
1726 napi_enable(&hw->napi);
1727 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
1728 sky2_read32(hw, B0_IMSK);
1729 }
1730
1731 return err;
1732 }
1733
1734
1735 /* Bring up network interface. */
1736 static int sky2_open(struct net_device *dev)
1737 {
1738 struct sky2_port *sky2 = netdev_priv(dev);
1739 struct sky2_hw *hw = sky2->hw;
1740 unsigned port = sky2->port;
1741 u32 imask;
1742 int err;
1743
1744 netif_carrier_off(dev);
1745
1746 err = sky2_alloc_buffers(sky2);
1747 if (err)
1748 goto err_out;
1749
1750 /* With single port, IRQ is setup when device is brought up */
1751 if (hw->ports == 1 && (err = sky2_setup_irq(hw, dev->name)))
1752 goto err_out;
1753
1754 sky2_hw_up(sky2);
1755
1756 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
1757 hw->chip_id == CHIP_ID_YUKON_PRM ||
1758 hw->chip_id == CHIP_ID_YUKON_OP_2)
1759 imask |= Y2_IS_PHY_QLNK; /* enable PHY Quick Link */
1760
1761 /* Enable interrupts from phy/mac for port */
1762 imask = sky2_read32(hw, B0_IMSK);
1763 imask |= portirq_msk[port];
1764 sky2_write32(hw, B0_IMSK, imask);
1765 sky2_read32(hw, B0_IMSK);
1766
1767 netif_info(sky2, ifup, dev, "enabling interface\n");
1768
1769 return 0;
1770
1771 err_out:
1772 sky2_free_buffers(sky2);
1773 return err;
1774 }
1775
1776 /* Modular subtraction in ring */
1777 static inline int tx_inuse(const struct sky2_port *sky2)
1778 {
1779 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1780 }
1781
1782 /* Number of list elements available for next tx */
1783 static inline int tx_avail(const struct sky2_port *sky2)
1784 {
1785 return sky2->tx_pending - tx_inuse(sky2);
1786 }
1787
1788 /* Estimate of number of transmit list elements required */
1789 static unsigned tx_le_req(const struct sk_buff *skb)
1790 {
1791 unsigned count;
1792
1793 count = (skb_shinfo(skb)->nr_frags + 1)
1794 * (sizeof(dma_addr_t) / sizeof(u32));
1795
1796 if (skb_is_gso(skb))
1797 ++count;
1798 else if (sizeof(dma_addr_t) == sizeof(u32))
1799 ++count; /* possible vlan */
1800
1801 if (skb->ip_summed == CHECKSUM_PARTIAL)
1802 ++count;
1803
1804 return count;
1805 }
1806
1807 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
1808 {
1809 if (re->flags & TX_MAP_SINGLE)
1810 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr),
1811 dma_unmap_len(re, maplen),
1812 PCI_DMA_TODEVICE);
1813 else if (re->flags & TX_MAP_PAGE)
1814 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr),
1815 dma_unmap_len(re, maplen),
1816 PCI_DMA_TODEVICE);
1817 re->flags = 0;
1818 }
1819
1820 /*
1821 * Put one packet in ring for transmit.
1822 * A single packet can generate multiple list elements, and
1823 * the number of ring elements will probably be less than the number
1824 * of list elements used.
1825 */
1826 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1827 struct net_device *dev)
1828 {
1829 struct sky2_port *sky2 = netdev_priv(dev);
1830 struct sky2_hw *hw = sky2->hw;
1831 struct sky2_tx_le *le = NULL;
1832 struct tx_ring_info *re;
1833 unsigned i, len;
1834 dma_addr_t mapping;
1835 u32 upper;
1836 u16 slot;
1837 u16 mss;
1838 u8 ctrl;
1839
1840 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1841 return NETDEV_TX_BUSY;
1842
1843 len = skb_headlen(skb);
1844 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1845
1846 if (pci_dma_mapping_error(hw->pdev, mapping))
1847 goto mapping_error;
1848
1849 slot = sky2->tx_prod;
1850 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1851 "tx queued, slot %u, len %d\n", slot, skb->len);
1852
1853 /* Send high bits if needed */
1854 upper = upper_32_bits(mapping);
1855 if (upper != sky2->tx_last_upper) {
1856 le = get_tx_le(sky2, &slot);
1857 le->addr = cpu_to_le32(upper);
1858 sky2->tx_last_upper = upper;
1859 le->opcode = OP_ADDR64 | HW_OWNER;
1860 }
1861
1862 /* Check for TCP Segmentation Offload */
1863 mss = skb_shinfo(skb)->gso_size;
1864 if (mss != 0) {
1865
1866 if (!(hw->flags & SKY2_HW_NEW_LE))
1867 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1868
1869 if (mss != sky2->tx_last_mss) {
1870 le = get_tx_le(sky2, &slot);
1871 le->addr = cpu_to_le32(mss);
1872
1873 if (hw->flags & SKY2_HW_NEW_LE)
1874 le->opcode = OP_MSS | HW_OWNER;
1875 else
1876 le->opcode = OP_LRGLEN | HW_OWNER;
1877 sky2->tx_last_mss = mss;
1878 }
1879 }
1880
1881 ctrl = 0;
1882
1883 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1884 if (vlan_tx_tag_present(skb)) {
1885 if (!le) {
1886 le = get_tx_le(sky2, &slot);
1887 le->addr = 0;
1888 le->opcode = OP_VLAN|HW_OWNER;
1889 } else
1890 le->opcode |= OP_VLAN;
1891 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1892 ctrl |= INS_VLAN;
1893 }
1894
1895 /* Handle TCP checksum offload */
1896 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1897 /* On Yukon EX (some versions) encoding change. */
1898 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1899 ctrl |= CALSUM; /* auto checksum */
1900 else {
1901 const unsigned offset = skb_transport_offset(skb);
1902 u32 tcpsum;
1903
1904 tcpsum = offset << 16; /* sum start */
1905 tcpsum |= offset + skb->csum_offset; /* sum write */
1906
1907 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1908 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1909 ctrl |= UDPTCP;
1910
1911 if (tcpsum != sky2->tx_tcpsum) {
1912 sky2->tx_tcpsum = tcpsum;
1913
1914 le = get_tx_le(sky2, &slot);
1915 le->addr = cpu_to_le32(tcpsum);
1916 le->length = 0; /* initial checksum value */
1917 le->ctrl = 1; /* one packet */
1918 le->opcode = OP_TCPLISW | HW_OWNER;
1919 }
1920 }
1921 }
1922
1923 re = sky2->tx_ring + slot;
1924 re->flags = TX_MAP_SINGLE;
1925 dma_unmap_addr_set(re, mapaddr, mapping);
1926 dma_unmap_len_set(re, maplen, len);
1927
1928 le = get_tx_le(sky2, &slot);
1929 le->addr = cpu_to_le32(lower_32_bits(mapping));
1930 le->length = cpu_to_le16(len);
1931 le->ctrl = ctrl;
1932 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1933
1934
1935 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1936 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1937
1938 mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
1939 skb_frag_size(frag), DMA_TO_DEVICE);
1940
1941 if (dma_mapping_error(&hw->pdev->dev, mapping))
1942 goto mapping_unwind;
1943
1944 upper = upper_32_bits(mapping);
1945 if (upper != sky2->tx_last_upper) {
1946 le = get_tx_le(sky2, &slot);
1947 le->addr = cpu_to_le32(upper);
1948 sky2->tx_last_upper = upper;
1949 le->opcode = OP_ADDR64 | HW_OWNER;
1950 }
1951
1952 re = sky2->tx_ring + slot;
1953 re->flags = TX_MAP_PAGE;
1954 dma_unmap_addr_set(re, mapaddr, mapping);
1955 dma_unmap_len_set(re, maplen, skb_frag_size(frag));
1956
1957 le = get_tx_le(sky2, &slot);
1958 le->addr = cpu_to_le32(lower_32_bits(mapping));
1959 le->length = cpu_to_le16(skb_frag_size(frag));
1960 le->ctrl = ctrl;
1961 le->opcode = OP_BUFFER | HW_OWNER;
1962 }
1963
1964 re->skb = skb;
1965 le->ctrl |= EOP;
1966
1967 sky2->tx_prod = slot;
1968
1969 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1970 netif_stop_queue(dev);
1971
1972 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1973
1974 return NETDEV_TX_OK;
1975
1976 mapping_unwind:
1977 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1978 re = sky2->tx_ring + i;
1979
1980 sky2_tx_unmap(hw->pdev, re);
1981 }
1982
1983 mapping_error:
1984 if (net_ratelimit())
1985 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1986 dev_kfree_skb(skb);
1987 return NETDEV_TX_OK;
1988 }
1989
1990 /*
1991 * Free ring elements from starting at tx_cons until "done"
1992 *
1993 * NB:
1994 * 1. The hardware will tell us about partial completion of multi-part
1995 * buffers so make sure not to free skb to early.
1996 * 2. This may run in parallel start_xmit because the it only
1997 * looks at the tail of the queue of FIFO (tx_cons), not
1998 * the head (tx_prod)
1999 */
2000 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
2001 {
2002 struct net_device *dev = sky2->netdev;
2003 unsigned idx;
2004
2005 BUG_ON(done >= sky2->tx_ring_size);
2006
2007 for (idx = sky2->tx_cons; idx != done;
2008 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
2009 struct tx_ring_info *re = sky2->tx_ring + idx;
2010 struct sk_buff *skb = re->skb;
2011
2012 sky2_tx_unmap(sky2->hw->pdev, re);
2013
2014 if (skb) {
2015 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
2016 "tx done %u\n", idx);
2017
2018 u64_stats_update_begin(&sky2->tx_stats.syncp);
2019 ++sky2->tx_stats.packets;
2020 sky2->tx_stats.bytes += skb->len;
2021 u64_stats_update_end(&sky2->tx_stats.syncp);
2022
2023 re->skb = NULL;
2024 dev_kfree_skb_any(skb);
2025
2026 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
2027 }
2028 }
2029
2030 sky2->tx_cons = idx;
2031 smp_mb();
2032 }
2033
2034 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
2035 {
2036 /* Disable Force Sync bit and Enable Alloc bit */
2037 sky2_write8(hw, SK_REG(port, TXA_CTRL),
2038 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2039
2040 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2041 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2042 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2043
2044 /* Reset the PCI FIFO of the async Tx queue */
2045 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
2046 BMU_RST_SET | BMU_FIFO_RST);
2047
2048 /* Reset the Tx prefetch units */
2049 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
2050 PREF_UNIT_RST_SET);
2051
2052 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2053 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2054
2055 sky2_read32(hw, B0_CTST);
2056 }
2057
2058 static void sky2_hw_down(struct sky2_port *sky2)
2059 {
2060 struct sky2_hw *hw = sky2->hw;
2061 unsigned port = sky2->port;
2062 u16 ctrl;
2063
2064 /* Force flow control off */
2065 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2066
2067 /* Stop transmitter */
2068 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
2069 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
2070
2071 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2072 RB_RST_SET | RB_DIS_OP_MD);
2073
2074 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2075 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
2076 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2077
2078 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2079
2080 /* Workaround shared GMAC reset */
2081 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
2082 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
2083 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2084
2085 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2086
2087 /* Force any delayed status interrupt and NAPI */
2088 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
2089 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
2090 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
2091 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
2092
2093 sky2_rx_stop(sky2);
2094
2095 spin_lock_bh(&sky2->phy_lock);
2096 sky2_phy_power_down(hw, port);
2097 spin_unlock_bh(&sky2->phy_lock);
2098
2099 sky2_tx_reset(hw, port);
2100
2101 /* Free any pending frames stuck in HW queue */
2102 sky2_tx_complete(sky2, sky2->tx_prod);
2103 }
2104
2105 /* Network shutdown */
2106 static int sky2_close(struct net_device *dev)
2107 {
2108 struct sky2_port *sky2 = netdev_priv(dev);
2109 struct sky2_hw *hw = sky2->hw;
2110
2111 /* Never really got started! */
2112 if (!sky2->tx_le)
2113 return 0;
2114
2115 netif_info(sky2, ifdown, dev, "disabling interface\n");
2116
2117 if (hw->ports == 1) {
2118 sky2_write32(hw, B0_IMSK, 0);
2119 sky2_read32(hw, B0_IMSK);
2120
2121 napi_disable(&hw->napi);
2122 free_irq(hw->pdev->irq, hw);
2123 } else {
2124 u32 imask;
2125
2126 /* Disable port IRQ */
2127 imask = sky2_read32(hw, B0_IMSK);
2128 imask &= ~portirq_msk[sky2->port];
2129 sky2_write32(hw, B0_IMSK, imask);
2130 sky2_read32(hw, B0_IMSK);
2131
2132 synchronize_irq(hw->pdev->irq);
2133 napi_synchronize(&hw->napi);
2134 }
2135
2136 sky2_hw_down(sky2);
2137
2138 sky2_free_buffers(sky2);
2139
2140 return 0;
2141 }
2142
2143 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2144 {
2145 if (hw->flags & SKY2_HW_FIBRE_PHY)
2146 return SPEED_1000;
2147
2148 if (!(hw->flags & SKY2_HW_GIGABIT)) {
2149 if (aux & PHY_M_PS_SPEED_100)
2150 return SPEED_100;
2151 else
2152 return SPEED_10;
2153 }
2154
2155 switch (aux & PHY_M_PS_SPEED_MSK) {
2156 case PHY_M_PS_SPEED_1000:
2157 return SPEED_1000;
2158 case PHY_M_PS_SPEED_100:
2159 return SPEED_100;
2160 default:
2161 return SPEED_10;
2162 }
2163 }
2164
2165 static void sky2_link_up(struct sky2_port *sky2)
2166 {
2167 struct sky2_hw *hw = sky2->hw;
2168 unsigned port = sky2->port;
2169 static const char *fc_name[] = {
2170 [FC_NONE] = "none",
2171 [FC_TX] = "tx",
2172 [FC_RX] = "rx",
2173 [FC_BOTH] = "both",
2174 };
2175
2176 sky2_set_ipg(sky2);
2177
2178 sky2_enable_rx_tx(sky2);
2179
2180 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2181
2182 netif_carrier_on(sky2->netdev);
2183
2184 mod_timer(&hw->watchdog_timer, jiffies + 1);
2185
2186 /* Turn on link LED */
2187 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
2188 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2189
2190 netif_info(sky2, link, sky2->netdev,
2191 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2192 sky2->speed,
2193 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2194 fc_name[sky2->flow_status]);
2195 }
2196
2197 static void sky2_link_down(struct sky2_port *sky2)
2198 {
2199 struct sky2_hw *hw = sky2->hw;
2200 unsigned port = sky2->port;
2201 u16 reg;
2202
2203 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2204
2205 reg = gma_read16(hw, port, GM_GP_CTRL);
2206 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2207 gma_write16(hw, port, GM_GP_CTRL, reg);
2208
2209 netif_carrier_off(sky2->netdev);
2210
2211 /* Turn off link LED */
2212 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2213
2214 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2215
2216 sky2_phy_init(hw, port);
2217 }
2218
2219 static enum flow_control sky2_flow(int rx, int tx)
2220 {
2221 if (rx)
2222 return tx ? FC_BOTH : FC_RX;
2223 else
2224 return tx ? FC_TX : FC_NONE;
2225 }
2226
2227 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2228 {
2229 struct sky2_hw *hw = sky2->hw;
2230 unsigned port = sky2->port;
2231 u16 advert, lpa;
2232
2233 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2234 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2235 if (lpa & PHY_M_AN_RF) {
2236 netdev_err(sky2->netdev, "remote fault\n");
2237 return -1;
2238 }
2239
2240 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2241 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
2242 return -1;
2243 }
2244
2245 sky2->speed = sky2_phy_speed(hw, aux);
2246 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2247
2248 /* Since the pause result bits seem to in different positions on
2249 * different chips. look at registers.
2250 */
2251 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2252 /* Shift for bits in fiber PHY */
2253 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2254 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2255
2256 if (advert & ADVERTISE_1000XPAUSE)
2257 advert |= ADVERTISE_PAUSE_CAP;
2258 if (advert & ADVERTISE_1000XPSE_ASYM)
2259 advert |= ADVERTISE_PAUSE_ASYM;
2260 if (lpa & LPA_1000XPAUSE)
2261 lpa |= LPA_PAUSE_CAP;
2262 if (lpa & LPA_1000XPAUSE_ASYM)
2263 lpa |= LPA_PAUSE_ASYM;
2264 }
2265
2266 sky2->flow_status = FC_NONE;
2267 if (advert & ADVERTISE_PAUSE_CAP) {
2268 if (lpa & LPA_PAUSE_CAP)
2269 sky2->flow_status = FC_BOTH;
2270 else if (advert & ADVERTISE_PAUSE_ASYM)
2271 sky2->flow_status = FC_RX;
2272 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2273 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2274 sky2->flow_status = FC_TX;
2275 }
2276
2277 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2278 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2279 sky2->flow_status = FC_NONE;
2280
2281 if (sky2->flow_status & FC_TX)
2282 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2283 else
2284 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2285
2286 return 0;
2287 }
2288
2289 /* Interrupt from PHY */
2290 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2291 {
2292 struct net_device *dev = hw->dev[port];
2293 struct sky2_port *sky2 = netdev_priv(dev);
2294 u16 istatus, phystat;
2295
2296 if (!netif_running(dev))
2297 return;
2298
2299 spin_lock(&sky2->phy_lock);
2300 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2301 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2302
2303 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2304 istatus, phystat);
2305
2306 if (istatus & PHY_M_IS_AN_COMPL) {
2307 if (sky2_autoneg_done(sky2, phystat) == 0 &&
2308 !netif_carrier_ok(dev))
2309 sky2_link_up(sky2);
2310 goto out;
2311 }
2312
2313 if (istatus & PHY_M_IS_LSP_CHANGE)
2314 sky2->speed = sky2_phy_speed(hw, phystat);
2315
2316 if (istatus & PHY_M_IS_DUP_CHANGE)
2317 sky2->duplex =
2318 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2319
2320 if (istatus & PHY_M_IS_LST_CHANGE) {
2321 if (phystat & PHY_M_PS_LINK_UP)
2322 sky2_link_up(sky2);
2323 else
2324 sky2_link_down(sky2);
2325 }
2326 out:
2327 spin_unlock(&sky2->phy_lock);
2328 }
2329
2330 /* Special quick link interrupt (Yukon-2 Optima only) */
2331 static void sky2_qlink_intr(struct sky2_hw *hw)
2332 {
2333 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2334 u32 imask;
2335 u16 phy;
2336
2337 /* disable irq */
2338 imask = sky2_read32(hw, B0_IMSK);
2339 imask &= ~Y2_IS_PHY_QLNK;
2340 sky2_write32(hw, B0_IMSK, imask);
2341
2342 /* reset PHY Link Detect */
2343 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2344 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2345 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2346 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2347
2348 sky2_link_up(sky2);
2349 }
2350
2351 /* Transmit timeout is only called if we are running, carrier is up
2352 * and tx queue is full (stopped).
2353 */
2354 static void sky2_tx_timeout(struct net_device *dev)
2355 {
2356 struct sky2_port *sky2 = netdev_priv(dev);
2357 struct sky2_hw *hw = sky2->hw;
2358
2359 netif_err(sky2, timer, dev, "tx timeout\n");
2360
2361 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2362 sky2->tx_cons, sky2->tx_prod,
2363 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2364 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2365
2366 /* can't restart safely under softirq */
2367 schedule_work(&hw->restart_work);
2368 }
2369
2370 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2371 {
2372 struct sky2_port *sky2 = netdev_priv(dev);
2373 struct sky2_hw *hw = sky2->hw;
2374 unsigned port = sky2->port;
2375 int err;
2376 u16 ctl, mode;
2377 u32 imask;
2378
2379 /* MTU size outside the spec */
2380 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2381 return -EINVAL;
2382
2383 /* MTU > 1500 on yukon FE and FE+ not allowed */
2384 if (new_mtu > ETH_DATA_LEN &&
2385 (hw->chip_id == CHIP_ID_YUKON_FE ||
2386 hw->chip_id == CHIP_ID_YUKON_FE_P))
2387 return -EINVAL;
2388
2389 if (!netif_running(dev)) {
2390 dev->mtu = new_mtu;
2391 netdev_update_features(dev);
2392 return 0;
2393 }
2394
2395 imask = sky2_read32(hw, B0_IMSK);
2396 sky2_write32(hw, B0_IMSK, 0);
2397
2398 dev->trans_start = jiffies; /* prevent tx timeout */
2399 napi_disable(&hw->napi);
2400 netif_tx_disable(dev);
2401
2402 synchronize_irq(hw->pdev->irq);
2403
2404 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2405 sky2_set_tx_stfwd(hw, port);
2406
2407 ctl = gma_read16(hw, port, GM_GP_CTRL);
2408 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2409 sky2_rx_stop(sky2);
2410 sky2_rx_clean(sky2);
2411
2412 dev->mtu = new_mtu;
2413 netdev_update_features(dev);
2414
2415 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA;
2416 if (sky2->speed > SPEED_100)
2417 mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
2418 else
2419 mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
2420
2421 if (dev->mtu > ETH_DATA_LEN)
2422 mode |= GM_SMOD_JUMBO_ENA;
2423
2424 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2425
2426 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2427
2428 err = sky2_alloc_rx_skbs(sky2);
2429 if (!err)
2430 sky2_rx_start(sky2);
2431 else
2432 sky2_rx_clean(sky2);
2433 sky2_write32(hw, B0_IMSK, imask);
2434
2435 sky2_read32(hw, B0_Y2_SP_LISR);
2436 napi_enable(&hw->napi);
2437
2438 if (err)
2439 dev_close(dev);
2440 else {
2441 gma_write16(hw, port, GM_GP_CTRL, ctl);
2442
2443 netif_wake_queue(dev);
2444 }
2445
2446 return err;
2447 }
2448
2449 /* For small just reuse existing skb for next receive */
2450 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2451 const struct rx_ring_info *re,
2452 unsigned length)
2453 {
2454 struct sk_buff *skb;
2455
2456 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2457 if (likely(skb)) {
2458 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2459 length, PCI_DMA_FROMDEVICE);
2460 skb_copy_from_linear_data(re->skb, skb->data, length);
2461 skb->ip_summed = re->skb->ip_summed;
2462 skb->csum = re->skb->csum;
2463 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2464 length, PCI_DMA_FROMDEVICE);
2465 re->skb->ip_summed = CHECKSUM_NONE;
2466 skb_put(skb, length);
2467 }
2468 return skb;
2469 }
2470
2471 /* Adjust length of skb with fragments to match received data */
2472 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2473 unsigned int length)
2474 {
2475 int i, num_frags;
2476 unsigned int size;
2477
2478 /* put header into skb */
2479 size = min(length, hdr_space);
2480 skb->tail += size;
2481 skb->len += size;
2482 length -= size;
2483
2484 num_frags = skb_shinfo(skb)->nr_frags;
2485 for (i = 0; i < num_frags; i++) {
2486 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2487
2488 if (length == 0) {
2489 /* don't need this page */
2490 __skb_frag_unref(frag);
2491 --skb_shinfo(skb)->nr_frags;
2492 } else {
2493 size = min(length, (unsigned) PAGE_SIZE);
2494
2495 skb_frag_size_set(frag, size);
2496 skb->data_len += size;
2497 skb->truesize += PAGE_SIZE;
2498 skb->len += size;
2499 length -= size;
2500 }
2501 }
2502 }
2503
2504 /* Normal packet - take skb from ring element and put in a new one */
2505 static struct sk_buff *receive_new(struct sky2_port *sky2,
2506 struct rx_ring_info *re,
2507 unsigned int length)
2508 {
2509 struct sk_buff *skb;
2510 struct rx_ring_info nre;
2511 unsigned hdr_space = sky2->rx_data_size;
2512
2513 nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC);
2514 if (unlikely(!nre.skb))
2515 goto nobuf;
2516
2517 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2518 goto nomap;
2519
2520 skb = re->skb;
2521 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2522 prefetch(skb->data);
2523 *re = nre;
2524
2525 if (skb_shinfo(skb)->nr_frags)
2526 skb_put_frags(skb, hdr_space, length);
2527 else
2528 skb_put(skb, length);
2529 return skb;
2530
2531 nomap:
2532 dev_kfree_skb(nre.skb);
2533 nobuf:
2534 return NULL;
2535 }
2536
2537 /*
2538 * Receive one packet.
2539 * For larger packets, get new buffer.
2540 */
2541 static struct sk_buff *sky2_receive(struct net_device *dev,
2542 u16 length, u32 status)
2543 {
2544 struct sky2_port *sky2 = netdev_priv(dev);
2545 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2546 struct sk_buff *skb = NULL;
2547 u16 count = (status & GMR_FS_LEN) >> 16;
2548
2549 if (status & GMR_FS_VLAN)
2550 count -= VLAN_HLEN; /* Account for vlan tag */
2551
2552 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2553 "rx slot %u status 0x%x len %d\n",
2554 sky2->rx_next, status, length);
2555
2556 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2557 prefetch(sky2->rx_ring + sky2->rx_next);
2558
2559 /* This chip has hardware problems that generates bogus status.
2560 * So do only marginal checking and expect higher level protocols
2561 * to handle crap frames.
2562 */
2563 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2564 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2565 length != count)
2566 goto okay;
2567
2568 if (status & GMR_FS_ANY_ERR)
2569 goto error;
2570
2571 if (!(status & GMR_FS_RX_OK))
2572 goto resubmit;
2573
2574 /* if length reported by DMA does not match PHY, packet was truncated */
2575 if (length != count)
2576 goto error;
2577
2578 okay:
2579 if (length < copybreak)
2580 skb = receive_copy(sky2, re, length);
2581 else
2582 skb = receive_new(sky2, re, length);
2583
2584 dev->stats.rx_dropped += (skb == NULL);
2585
2586 resubmit:
2587 sky2_rx_submit(sky2, re);
2588
2589 return skb;
2590
2591 error:
2592 ++dev->stats.rx_errors;
2593
2594 if (net_ratelimit())
2595 netif_info(sky2, rx_err, dev,
2596 "rx error, status 0x%x length %d\n", status, length);
2597
2598 goto resubmit;
2599 }
2600
2601 /* Transmit complete */
2602 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2603 {
2604 struct sky2_port *sky2 = netdev_priv(dev);
2605
2606 if (netif_running(dev)) {
2607 sky2_tx_complete(sky2, last);
2608
2609 /* Wake unless it's detached, and called e.g. from sky2_close() */
2610 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2611 netif_wake_queue(dev);
2612 }
2613 }
2614
2615 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2616 u32 status, struct sk_buff *skb)
2617 {
2618 if (status & GMR_FS_VLAN)
2619 __vlan_hwaccel_put_tag(skb, be16_to_cpu(sky2->rx_tag));
2620
2621 if (skb->ip_summed == CHECKSUM_NONE)
2622 netif_receive_skb(skb);
2623 else
2624 napi_gro_receive(&sky2->hw->napi, skb);
2625 }
2626
2627 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2628 unsigned packets, unsigned bytes)
2629 {
2630 struct net_device *dev = hw->dev[port];
2631 struct sky2_port *sky2 = netdev_priv(dev);
2632
2633 if (packets == 0)
2634 return;
2635
2636 u64_stats_update_begin(&sky2->rx_stats.syncp);
2637 sky2->rx_stats.packets += packets;
2638 sky2->rx_stats.bytes += bytes;
2639 u64_stats_update_end(&sky2->rx_stats.syncp);
2640
2641 dev->last_rx = jiffies;
2642 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2643 }
2644
2645 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2646 {
2647 /* If this happens then driver assuming wrong format for chip type */
2648 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2649
2650 /* Both checksum counters are programmed to start at
2651 * the same offset, so unless there is a problem they
2652 * should match. This failure is an early indication that
2653 * hardware receive checksumming won't work.
2654 */
2655 if (likely((u16)(status >> 16) == (u16)status)) {
2656 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2657 skb->ip_summed = CHECKSUM_COMPLETE;
2658 skb->csum = le16_to_cpu(status);
2659 } else {
2660 dev_notice(&sky2->hw->pdev->dev,
2661 "%s: receive checksum problem (status = %#x)\n",
2662 sky2->netdev->name, status);
2663
2664 /* Disable checksum offload
2665 * It will be reenabled on next ndo_set_features, but if it's
2666 * really broken, will get disabled again
2667 */
2668 sky2->netdev->features &= ~NETIF_F_RXCSUM;
2669 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2670 BMU_DIS_RX_CHKSUM);
2671 }
2672 }
2673
2674 static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
2675 {
2676 struct sk_buff *skb;
2677
2678 skb = sky2->rx_ring[sky2->rx_next].skb;
2679 skb->rxhash = le32_to_cpu(status);
2680 }
2681
2682 /* Process status response ring */
2683 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2684 {
2685 int work_done = 0;
2686 unsigned int total_bytes[2] = { 0 };
2687 unsigned int total_packets[2] = { 0 };
2688
2689 rmb();
2690 do {
2691 struct sky2_port *sky2;
2692 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2693 unsigned port;
2694 struct net_device *dev;
2695 struct sk_buff *skb;
2696 u32 status;
2697 u16 length;
2698 u8 opcode = le->opcode;
2699
2700 if (!(opcode & HW_OWNER))
2701 break;
2702
2703 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
2704
2705 port = le->css & CSS_LINK_BIT;
2706 dev = hw->dev[port];
2707 sky2 = netdev_priv(dev);
2708 length = le16_to_cpu(le->length);
2709 status = le32_to_cpu(le->status);
2710
2711 le->opcode = 0;
2712 switch (opcode & ~HW_OWNER) {
2713 case OP_RXSTAT:
2714 total_packets[port]++;
2715 total_bytes[port] += length;
2716
2717 skb = sky2_receive(dev, length, status);
2718 if (!skb)
2719 break;
2720
2721 /* This chip reports checksum status differently */
2722 if (hw->flags & SKY2_HW_NEW_LE) {
2723 if ((dev->features & NETIF_F_RXCSUM) &&
2724 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2725 (le->css & CSS_TCPUDPCSOK))
2726 skb->ip_summed = CHECKSUM_UNNECESSARY;
2727 else
2728 skb->ip_summed = CHECKSUM_NONE;
2729 }
2730
2731 skb->protocol = eth_type_trans(skb, dev);
2732
2733 sky2_skb_rx(sky2, status, skb);
2734
2735 /* Stop after net poll weight */
2736 if (++work_done >= to_do)
2737 goto exit_loop;
2738 break;
2739
2740 case OP_RXVLAN:
2741 sky2->rx_tag = length;
2742 break;
2743
2744 case OP_RXCHKSVLAN:
2745 sky2->rx_tag = length;
2746 /* fall through */
2747 case OP_RXCHKS:
2748 if (likely(dev->features & NETIF_F_RXCSUM))
2749 sky2_rx_checksum(sky2, status);
2750 break;
2751
2752 case OP_RSS_HASH:
2753 sky2_rx_hash(sky2, status);
2754 break;
2755
2756 case OP_TXINDEXLE:
2757 /* TX index reports status for both ports */
2758 sky2_tx_done(hw->dev[0], status & 0xfff);
2759 if (hw->dev[1])
2760 sky2_tx_done(hw->dev[1],
2761 ((status >> 24) & 0xff)
2762 | (u16)(length & 0xf) << 8);
2763 break;
2764
2765 default:
2766 if (net_ratelimit())
2767 pr_warning("unknown status opcode 0x%x\n", opcode);
2768 }
2769 } while (hw->st_idx != idx);
2770
2771 /* Fully processed status ring so clear irq */
2772 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2773
2774 exit_loop:
2775 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2776 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2777
2778 return work_done;
2779 }
2780
2781 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2782 {
2783 struct net_device *dev = hw->dev[port];
2784
2785 if (net_ratelimit())
2786 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
2787
2788 if (status & Y2_IS_PAR_RD1) {
2789 if (net_ratelimit())
2790 netdev_err(dev, "ram data read parity error\n");
2791 /* Clear IRQ */
2792 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2793 }
2794
2795 if (status & Y2_IS_PAR_WR1) {
2796 if (net_ratelimit())
2797 netdev_err(dev, "ram data write parity error\n");
2798
2799 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2800 }
2801
2802 if (status & Y2_IS_PAR_MAC1) {
2803 if (net_ratelimit())
2804 netdev_err(dev, "MAC parity error\n");
2805 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2806 }
2807
2808 if (status & Y2_IS_PAR_RX1) {
2809 if (net_ratelimit())
2810 netdev_err(dev, "RX parity error\n");
2811 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2812 }
2813
2814 if (status & Y2_IS_TCP_TXA1) {
2815 if (net_ratelimit())
2816 netdev_err(dev, "TCP segmentation error\n");
2817 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2818 }
2819 }
2820
2821 static void sky2_hw_intr(struct sky2_hw *hw)
2822 {
2823 struct pci_dev *pdev = hw->pdev;
2824 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2825 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2826
2827 status &= hwmsk;
2828
2829 if (status & Y2_IS_TIST_OV)
2830 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2831
2832 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2833 u16 pci_err;
2834
2835 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2836 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2837 if (net_ratelimit())
2838 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2839 pci_err);
2840
2841 sky2_pci_write16(hw, PCI_STATUS,
2842 pci_err | PCI_STATUS_ERROR_BITS);
2843 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2844 }
2845
2846 if (status & Y2_IS_PCI_EXP) {
2847 /* PCI-Express uncorrectable Error occurred */
2848 u32 err;
2849
2850 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2851 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2852 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2853 0xfffffffful);
2854 if (net_ratelimit())
2855 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2856
2857 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2858 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2859 }
2860
2861 if (status & Y2_HWE_L1_MASK)
2862 sky2_hw_error(hw, 0, status);
2863 status >>= 8;
2864 if (status & Y2_HWE_L1_MASK)
2865 sky2_hw_error(hw, 1, status);
2866 }
2867
2868 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2869 {
2870 struct net_device *dev = hw->dev[port];
2871 struct sky2_port *sky2 = netdev_priv(dev);
2872 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2873
2874 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
2875
2876 if (status & GM_IS_RX_CO_OV)
2877 gma_read16(hw, port, GM_RX_IRQ_SRC);
2878
2879 if (status & GM_IS_TX_CO_OV)
2880 gma_read16(hw, port, GM_TX_IRQ_SRC);
2881
2882 if (status & GM_IS_RX_FF_OR) {
2883 ++dev->stats.rx_fifo_errors;
2884 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2885 }
2886
2887 if (status & GM_IS_TX_FF_UR) {
2888 ++dev->stats.tx_fifo_errors;
2889 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2890 }
2891 }
2892
2893 /* This should never happen it is a bug. */
2894 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2895 {
2896 struct net_device *dev = hw->dev[port];
2897 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2898
2899 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
2900 dev->name, (unsigned) q, (unsigned) idx,
2901 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2902
2903 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2904 }
2905
2906 static int sky2_rx_hung(struct net_device *dev)
2907 {
2908 struct sky2_port *sky2 = netdev_priv(dev);
2909 struct sky2_hw *hw = sky2->hw;
2910 unsigned port = sky2->port;
2911 unsigned rxq = rxqaddr[port];
2912 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2913 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2914 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2915 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2916
2917 /* If idle and MAC or PCI is stuck */
2918 if (sky2->check.last == dev->last_rx &&
2919 ((mac_rp == sky2->check.mac_rp &&
2920 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2921 /* Check if the PCI RX hang */
2922 (fifo_rp == sky2->check.fifo_rp &&
2923 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2924 netdev_printk(KERN_DEBUG, dev,
2925 "hung mac %d:%d fifo %d (%d:%d)\n",
2926 mac_lev, mac_rp, fifo_lev,
2927 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2928 return 1;
2929 } else {
2930 sky2->check.last = dev->last_rx;
2931 sky2->check.mac_rp = mac_rp;
2932 sky2->check.mac_lev = mac_lev;
2933 sky2->check.fifo_rp = fifo_rp;
2934 sky2->check.fifo_lev = fifo_lev;
2935 return 0;
2936 }
2937 }
2938
2939 static void sky2_watchdog(unsigned long arg)
2940 {
2941 struct sky2_hw *hw = (struct sky2_hw *) arg;
2942
2943 /* Check for lost IRQ once a second */
2944 if (sky2_read32(hw, B0_ISRC)) {
2945 napi_schedule(&hw->napi);
2946 } else {
2947 int i, active = 0;
2948
2949 for (i = 0; i < hw->ports; i++) {
2950 struct net_device *dev = hw->dev[i];
2951 if (!netif_running(dev))
2952 continue;
2953 ++active;
2954
2955 /* For chips with Rx FIFO, check if stuck */
2956 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2957 sky2_rx_hung(dev)) {
2958 netdev_info(dev, "receiver hang detected\n");
2959 schedule_work(&hw->restart_work);
2960 return;
2961 }
2962 }
2963
2964 if (active == 0)
2965 return;
2966 }
2967
2968 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2969 }
2970
2971 /* Hardware/software error handling */
2972 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2973 {
2974 if (net_ratelimit())
2975 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2976
2977 if (status & Y2_IS_HW_ERR)
2978 sky2_hw_intr(hw);
2979
2980 if (status & Y2_IS_IRQ_MAC1)
2981 sky2_mac_intr(hw, 0);
2982
2983 if (status & Y2_IS_IRQ_MAC2)
2984 sky2_mac_intr(hw, 1);
2985
2986 if (status & Y2_IS_CHK_RX1)
2987 sky2_le_error(hw, 0, Q_R1);
2988
2989 if (status & Y2_IS_CHK_RX2)
2990 sky2_le_error(hw, 1, Q_R2);
2991
2992 if (status & Y2_IS_CHK_TXA1)
2993 sky2_le_error(hw, 0, Q_XA1);
2994
2995 if (status & Y2_IS_CHK_TXA2)
2996 sky2_le_error(hw, 1, Q_XA2);
2997 }
2998
2999 static int sky2_poll(struct napi_struct *napi, int work_limit)
3000 {
3001 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
3002 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
3003 int work_done = 0;
3004 u16 idx;
3005
3006 if (unlikely(status & Y2_IS_ERROR))
3007 sky2_err_intr(hw, status);
3008
3009 if (status & Y2_IS_IRQ_PHY1)
3010 sky2_phy_intr(hw, 0);
3011
3012 if (status & Y2_IS_IRQ_PHY2)
3013 sky2_phy_intr(hw, 1);
3014
3015 if (status & Y2_IS_PHY_QLNK)
3016 sky2_qlink_intr(hw);
3017
3018 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
3019 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
3020
3021 if (work_done >= work_limit)
3022 goto done;
3023 }
3024
3025 napi_complete(napi);
3026 sky2_read32(hw, B0_Y2_SP_LISR);
3027 done:
3028
3029 return work_done;
3030 }
3031
3032 static irqreturn_t sky2_intr(int irq, void *dev_id)
3033 {
3034 struct sky2_hw *hw = dev_id;
3035 u32 status;
3036
3037 /* Reading this mask interrupts as side effect */
3038 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3039 if (status == 0 || status == ~0)
3040 return IRQ_NONE;
3041
3042 prefetch(&hw->st_le[hw->st_idx]);
3043
3044 napi_schedule(&hw->napi);
3045
3046 return IRQ_HANDLED;
3047 }
3048
3049 #ifdef CONFIG_NET_POLL_CONTROLLER
3050 static void sky2_netpoll(struct net_device *dev)
3051 {
3052 struct sky2_port *sky2 = netdev_priv(dev);
3053
3054 napi_schedule(&sky2->hw->napi);
3055 }
3056 #endif
3057
3058 /* Chip internal frequency for clock calculations */
3059 static u32 sky2_mhz(const struct sky2_hw *hw)
3060 {
3061 switch (hw->chip_id) {
3062 case CHIP_ID_YUKON_EC:
3063 case CHIP_ID_YUKON_EC_U:
3064 case CHIP_ID_YUKON_EX:
3065 case CHIP_ID_YUKON_SUPR:
3066 case CHIP_ID_YUKON_UL_2:
3067 case CHIP_ID_YUKON_OPT:
3068 case CHIP_ID_YUKON_PRM:
3069 case CHIP_ID_YUKON_OP_2:
3070 return 125;
3071
3072 case CHIP_ID_YUKON_FE:
3073 return 100;
3074
3075 case CHIP_ID_YUKON_FE_P:
3076 return 50;
3077
3078 case CHIP_ID_YUKON_XL:
3079 return 156;
3080
3081 default:
3082 BUG();
3083 }
3084 }
3085
3086 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
3087 {
3088 return sky2_mhz(hw) * us;
3089 }
3090
3091 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
3092 {
3093 return clk / sky2_mhz(hw);
3094 }
3095
3096
3097 static int __devinit sky2_init(struct sky2_hw *hw)
3098 {
3099 u8 t8;
3100
3101 /* Enable all clocks and check for bad PCI access */
3102 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3103
3104 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3105
3106 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
3107 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
3108
3109 switch (hw->chip_id) {
3110 case CHIP_ID_YUKON_XL:
3111 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
3112 if (hw->chip_rev < CHIP_REV_YU_XL_A2)
3113 hw->flags |= SKY2_HW_RSS_BROKEN;
3114 break;
3115
3116 case CHIP_ID_YUKON_EC_U:
3117 hw->flags = SKY2_HW_GIGABIT
3118 | SKY2_HW_NEWER_PHY
3119 | SKY2_HW_ADV_POWER_CTL;
3120 break;
3121
3122 case CHIP_ID_YUKON_EX:
3123 hw->flags = SKY2_HW_GIGABIT
3124 | SKY2_HW_NEWER_PHY
3125 | SKY2_HW_NEW_LE
3126 | SKY2_HW_ADV_POWER_CTL
3127 | SKY2_HW_RSS_CHKSUM;
3128
3129 /* New transmit checksum */
3130 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
3131 hw->flags |= SKY2_HW_AUTO_TX_SUM;
3132 break;
3133
3134 case CHIP_ID_YUKON_EC:
3135 /* This rev is really old, and requires untested workarounds */
3136 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3137 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3138 return -EOPNOTSUPP;
3139 }
3140 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
3141 break;
3142
3143 case CHIP_ID_YUKON_FE:
3144 hw->flags = SKY2_HW_RSS_BROKEN;
3145 break;
3146
3147 case CHIP_ID_YUKON_FE_P:
3148 hw->flags = SKY2_HW_NEWER_PHY
3149 | SKY2_HW_NEW_LE
3150 | SKY2_HW_AUTO_TX_SUM
3151 | SKY2_HW_ADV_POWER_CTL;
3152
3153 /* The workaround for status conflicts VLAN tag detection. */
3154 if (hw->chip_rev == CHIP_REV_YU_FE2_A0)
3155 hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM;
3156 break;
3157
3158 case CHIP_ID_YUKON_SUPR:
3159 hw->flags = SKY2_HW_GIGABIT
3160 | SKY2_HW_NEWER_PHY
3161 | SKY2_HW_NEW_LE
3162 | SKY2_HW_AUTO_TX_SUM
3163 | SKY2_HW_ADV_POWER_CTL;
3164
3165 if (hw->chip_rev == CHIP_REV_YU_SU_A0)
3166 hw->flags |= SKY2_HW_RSS_CHKSUM;
3167 break;
3168
3169 case CHIP_ID_YUKON_UL_2:
3170 hw->flags = SKY2_HW_GIGABIT
3171 | SKY2_HW_ADV_POWER_CTL;
3172 break;
3173
3174 case CHIP_ID_YUKON_OPT:
3175 case CHIP_ID_YUKON_PRM:
3176 case CHIP_ID_YUKON_OP_2:
3177 hw->flags = SKY2_HW_GIGABIT
3178 | SKY2_HW_NEW_LE
3179 | SKY2_HW_ADV_POWER_CTL;
3180 break;
3181
3182 default:
3183 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3184 hw->chip_id);
3185 return -EOPNOTSUPP;
3186 }
3187
3188 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3189 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3190 hw->flags |= SKY2_HW_FIBRE_PHY;
3191
3192 hw->ports = 1;
3193 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3194 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3195 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3196 ++hw->ports;
3197 }
3198
3199 if (sky2_read8(hw, B2_E_0))
3200 hw->flags |= SKY2_HW_RAM_BUFFER;
3201
3202 return 0;
3203 }
3204
3205 static void sky2_reset(struct sky2_hw *hw)
3206 {
3207 struct pci_dev *pdev = hw->pdev;
3208 u16 status;
3209 int i;
3210 u32 hwe_mask = Y2_HWE_ALL_MASK;
3211
3212 /* disable ASF */
3213 if (hw->chip_id == CHIP_ID_YUKON_EX
3214 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3215 sky2_write32(hw, CPU_WDOG, 0);
3216 status = sky2_read16(hw, HCU_CCSR);
3217 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3218 HCU_CCSR_UC_STATE_MSK);
3219 /*
3220 * CPU clock divider shouldn't be used because
3221 * - ASF firmware may malfunction
3222 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3223 */
3224 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
3225 sky2_write16(hw, HCU_CCSR, status);
3226 sky2_write32(hw, CPU_WDOG, 0);
3227 } else
3228 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3229 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3230
3231 /* do a SW reset */
3232 sky2_write8(hw, B0_CTST, CS_RST_SET);
3233 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3234
3235 /* allow writes to PCI config */
3236 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3237
3238 /* clear PCI errors, if any */
3239 status = sky2_pci_read16(hw, PCI_STATUS);
3240 status |= PCI_STATUS_ERROR_BITS;
3241 sky2_pci_write16(hw, PCI_STATUS, status);
3242
3243 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3244
3245 if (pci_is_pcie(pdev)) {
3246 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3247 0xfffffffful);
3248
3249 /* If error bit is stuck on ignore it */
3250 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3251 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3252 else
3253 hwe_mask |= Y2_IS_PCI_EXP;
3254 }
3255
3256 sky2_power_on(hw);
3257 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3258
3259 for (i = 0; i < hw->ports; i++) {
3260 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3261 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3262
3263 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3264 hw->chip_id == CHIP_ID_YUKON_SUPR)
3265 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3266 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3267 | GMC_BYP_RETR_ON);
3268
3269 }
3270
3271 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3272 /* enable MACSec clock gating */
3273 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3274 }
3275
3276 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
3277 hw->chip_id == CHIP_ID_YUKON_PRM ||
3278 hw->chip_id == CHIP_ID_YUKON_OP_2) {
3279 u16 reg;
3280
3281 if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
3282 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3283 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3284
3285 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3286 reg = 10;
3287
3288 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3289 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3290 } else {
3291 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3292 reg = 3;
3293 }
3294
3295 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3296 reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT;
3297
3298 /* reset PHY Link Detect */
3299 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3300 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3301
3302 /* check if PSMv2 was running before */
3303 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3304 if (reg & PCI_EXP_LNKCTL_ASPMC)
3305 /* restore the PCIe Link Control register */
3306 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL,
3307 reg);
3308
3309 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3310
3311 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3312 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3313 }
3314
3315 /* Clear I2C IRQ noise */
3316 sky2_write32(hw, B2_I2C_IRQ, 1);
3317
3318 /* turn off hardware timer (unused) */
3319 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3320 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3321
3322 /* Turn off descriptor polling */
3323 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3324
3325 /* Turn off receive timestamp */
3326 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3327 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3328
3329 /* enable the Tx Arbiters */
3330 for (i = 0; i < hw->ports; i++)
3331 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3332
3333 /* Initialize ram interface */
3334 for (i = 0; i < hw->ports; i++) {
3335 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3336
3337 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3338 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3339 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3340 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3341 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3342 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3343 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3344 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3345 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3346 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3347 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3348 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3349 }
3350
3351 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3352
3353 for (i = 0; i < hw->ports; i++)
3354 sky2_gmac_reset(hw, i);
3355
3356 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
3357 hw->st_idx = 0;
3358
3359 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3360 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3361
3362 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3363 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3364
3365 /* Set the list last index */
3366 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
3367
3368 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3369 sky2_write8(hw, STAT_FIFO_WM, 16);
3370
3371 /* set Status-FIFO ISR watermark */
3372 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3373 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3374 else
3375 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3376
3377 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3378 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3379 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3380
3381 /* enable status unit */
3382 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3383
3384 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3385 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3386 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3387 }
3388
3389 /* Take device down (offline).
3390 * Equivalent to doing dev_stop() but this does not
3391 * inform upper layers of the transition.
3392 */
3393 static void sky2_detach(struct net_device *dev)
3394 {
3395 if (netif_running(dev)) {
3396 netif_tx_lock(dev);
3397 netif_device_detach(dev); /* stop txq */
3398 netif_tx_unlock(dev);
3399 sky2_close(dev);
3400 }
3401 }
3402
3403 /* Bring device back after doing sky2_detach */
3404 static int sky2_reattach(struct net_device *dev)
3405 {
3406 int err = 0;
3407
3408 if (netif_running(dev)) {
3409 err = sky2_open(dev);
3410 if (err) {
3411 netdev_info(dev, "could not restart %d\n", err);
3412 dev_close(dev);
3413 } else {
3414 netif_device_attach(dev);
3415 sky2_set_multicast(dev);
3416 }
3417 }
3418
3419 return err;
3420 }
3421
3422 static void sky2_all_down(struct sky2_hw *hw)
3423 {
3424 int i;
3425
3426 sky2_read32(hw, B0_IMSK);
3427 sky2_write32(hw, B0_IMSK, 0);
3428
3429 if (hw->ports > 1 || netif_running(hw->dev[0]))
3430 synchronize_irq(hw->pdev->irq);
3431 napi_disable(&hw->napi);
3432
3433 for (i = 0; i < hw->ports; i++) {
3434 struct net_device *dev = hw->dev[i];
3435 struct sky2_port *sky2 = netdev_priv(dev);
3436
3437 if (!netif_running(dev))
3438 continue;
3439
3440 netif_carrier_off(dev);
3441 netif_tx_disable(dev);
3442 sky2_hw_down(sky2);
3443 }
3444 }
3445
3446 static void sky2_all_up(struct sky2_hw *hw)
3447 {
3448 u32 imask = 0;
3449 int i;
3450
3451 for (i = 0; i < hw->ports; i++) {
3452 struct net_device *dev = hw->dev[i];
3453 struct sky2_port *sky2 = netdev_priv(dev);
3454
3455 if (!netif_running(dev))
3456 continue;
3457
3458 sky2_hw_up(sky2);
3459 sky2_set_multicast(dev);
3460 imask |= portirq_msk[i];
3461 netif_wake_queue(dev);
3462 }
3463
3464 if (imask || hw->ports > 1) {
3465 imask |= Y2_IS_BASE;
3466 sky2_write32(hw, B0_IMSK, imask);
3467 sky2_read32(hw, B0_IMSK);
3468 sky2_read32(hw, B0_Y2_SP_LISR);
3469 napi_enable(&hw->napi);
3470 }
3471 }
3472
3473 static void sky2_restart(struct work_struct *work)
3474 {
3475 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3476
3477 rtnl_lock();
3478
3479 sky2_all_down(hw);
3480 sky2_reset(hw);
3481 sky2_all_up(hw);
3482
3483 rtnl_unlock();
3484 }
3485
3486 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3487 {
3488 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3489 }
3490
3491 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3492 {
3493 const struct sky2_port *sky2 = netdev_priv(dev);
3494
3495 wol->supported = sky2_wol_supported(sky2->hw);
3496 wol->wolopts = sky2->wol;
3497 }
3498
3499 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3500 {
3501 struct sky2_port *sky2 = netdev_priv(dev);
3502 struct sky2_hw *hw = sky2->hw;
3503 bool enable_wakeup = false;
3504 int i;
3505
3506 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3507 !device_can_wakeup(&hw->pdev->dev))
3508 return -EOPNOTSUPP;
3509
3510 sky2->wol = wol->wolopts;
3511
3512 for (i = 0; i < hw->ports; i++) {
3513 struct net_device *dev = hw->dev[i];
3514 struct sky2_port *sky2 = netdev_priv(dev);
3515
3516 if (sky2->wol)
3517 enable_wakeup = true;
3518 }
3519 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup);
3520
3521 return 0;
3522 }
3523
3524 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3525 {
3526 if (sky2_is_copper(hw)) {
3527 u32 modes = SUPPORTED_10baseT_Half
3528 | SUPPORTED_10baseT_Full
3529 | SUPPORTED_100baseT_Half
3530 | SUPPORTED_100baseT_Full;
3531
3532 if (hw->flags & SKY2_HW_GIGABIT)
3533 modes |= SUPPORTED_1000baseT_Half
3534 | SUPPORTED_1000baseT_Full;
3535 return modes;
3536 } else
3537 return SUPPORTED_1000baseT_Half
3538 | SUPPORTED_1000baseT_Full;
3539 }
3540
3541 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3542 {
3543 struct sky2_port *sky2 = netdev_priv(dev);
3544 struct sky2_hw *hw = sky2->hw;
3545
3546 ecmd->transceiver = XCVR_INTERNAL;
3547 ecmd->supported = sky2_supported_modes(hw);
3548 ecmd->phy_address = PHY_ADDR_MARV;
3549 if (sky2_is_copper(hw)) {
3550 ecmd->port = PORT_TP;
3551 ethtool_cmd_speed_set(ecmd, sky2->speed);
3552 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_TP;
3553 } else {
3554 ethtool_cmd_speed_set(ecmd, SPEED_1000);
3555 ecmd->port = PORT_FIBRE;
3556 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE;
3557 }
3558
3559 ecmd->advertising = sky2->advertising;
3560 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3561 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3562 ecmd->duplex = sky2->duplex;
3563 return 0;
3564 }
3565
3566 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3567 {
3568 struct sky2_port *sky2 = netdev_priv(dev);
3569 const struct sky2_hw *hw = sky2->hw;
3570 u32 supported = sky2_supported_modes(hw);
3571
3572 if (ecmd->autoneg == AUTONEG_ENABLE) {
3573 if (ecmd->advertising & ~supported)
3574 return -EINVAL;
3575
3576 if (sky2_is_copper(hw))
3577 sky2->advertising = ecmd->advertising |
3578 ADVERTISED_TP |
3579 ADVERTISED_Autoneg;
3580 else
3581 sky2->advertising = ecmd->advertising |
3582 ADVERTISED_FIBRE |
3583 ADVERTISED_Autoneg;
3584
3585 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3586 sky2->duplex = -1;
3587 sky2->speed = -1;
3588 } else {
3589 u32 setting;
3590 u32 speed = ethtool_cmd_speed(ecmd);
3591
3592 switch (speed) {
3593 case SPEED_1000:
3594 if (ecmd->duplex == DUPLEX_FULL)
3595 setting = SUPPORTED_1000baseT_Full;
3596 else if (ecmd->duplex == DUPLEX_HALF)
3597 setting = SUPPORTED_1000baseT_Half;
3598 else
3599 return -EINVAL;
3600 break;
3601 case SPEED_100:
3602 if (ecmd->duplex == DUPLEX_FULL)
3603 setting = SUPPORTED_100baseT_Full;
3604 else if (ecmd->duplex == DUPLEX_HALF)
3605 setting = SUPPORTED_100baseT_Half;
3606 else
3607 return -EINVAL;
3608 break;
3609
3610 case SPEED_10:
3611 if (ecmd->duplex == DUPLEX_FULL)
3612 setting = SUPPORTED_10baseT_Full;
3613 else if (ecmd->duplex == DUPLEX_HALF)
3614 setting = SUPPORTED_10baseT_Half;
3615 else
3616 return -EINVAL;
3617 break;
3618 default:
3619 return -EINVAL;
3620 }
3621
3622 if ((setting & supported) == 0)
3623 return -EINVAL;
3624
3625 sky2->speed = speed;
3626 sky2->duplex = ecmd->duplex;
3627 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3628 }
3629
3630 if (netif_running(dev)) {
3631 sky2_phy_reinit(sky2);
3632 sky2_set_multicast(dev);
3633 }
3634
3635 return 0;
3636 }
3637
3638 static void sky2_get_drvinfo(struct net_device *dev,
3639 struct ethtool_drvinfo *info)
3640 {
3641 struct sky2_port *sky2 = netdev_priv(dev);
3642
3643 strcpy(info->driver, DRV_NAME);
3644 strcpy(info->version, DRV_VERSION);
3645 strcpy(info->fw_version, "N/A");
3646 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3647 }
3648
3649 static const struct sky2_stat {
3650 char name[ETH_GSTRING_LEN];
3651 u16 offset;
3652 } sky2_stats[] = {
3653 { "tx_bytes", GM_TXO_OK_HI },
3654 { "rx_bytes", GM_RXO_OK_HI },
3655 { "tx_broadcast", GM_TXF_BC_OK },
3656 { "rx_broadcast", GM_RXF_BC_OK },
3657 { "tx_multicast", GM_TXF_MC_OK },
3658 { "rx_multicast", GM_RXF_MC_OK },
3659 { "tx_unicast", GM_TXF_UC_OK },
3660 { "rx_unicast", GM_RXF_UC_OK },
3661 { "tx_mac_pause", GM_TXF_MPAUSE },
3662 { "rx_mac_pause", GM_RXF_MPAUSE },
3663 { "collisions", GM_TXF_COL },
3664 { "late_collision",GM_TXF_LAT_COL },
3665 { "aborted", GM_TXF_ABO_COL },
3666 { "single_collisions", GM_TXF_SNG_COL },
3667 { "multi_collisions", GM_TXF_MUL_COL },
3668
3669 { "rx_short", GM_RXF_SHT },
3670 { "rx_runt", GM_RXE_FRAG },
3671 { "rx_64_byte_packets", GM_RXF_64B },
3672 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3673 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3674 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3675 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3676 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3677 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3678 { "rx_too_long", GM_RXF_LNG_ERR },
3679 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3680 { "rx_jabber", GM_RXF_JAB_PKT },
3681 { "rx_fcs_error", GM_RXF_FCS_ERR },
3682
3683 { "tx_64_byte_packets", GM_TXF_64B },
3684 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3685 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3686 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3687 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3688 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3689 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3690 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3691 };
3692
3693 static u32 sky2_get_msglevel(struct net_device *netdev)
3694 {
3695 struct sky2_port *sky2 = netdev_priv(netdev);
3696 return sky2->msg_enable;
3697 }
3698
3699 static int sky2_nway_reset(struct net_device *dev)
3700 {
3701 struct sky2_port *sky2 = netdev_priv(dev);
3702
3703 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3704 return -EINVAL;
3705
3706 sky2_phy_reinit(sky2);
3707 sky2_set_multicast(dev);
3708
3709 return 0;
3710 }
3711
3712 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3713 {
3714 struct sky2_hw *hw = sky2->hw;
3715 unsigned port = sky2->port;
3716 int i;
3717
3718 data[0] = get_stats64(hw, port, GM_TXO_OK_LO);
3719 data[1] = get_stats64(hw, port, GM_RXO_OK_LO);
3720
3721 for (i = 2; i < count; i++)
3722 data[i] = get_stats32(hw, port, sky2_stats[i].offset);
3723 }
3724
3725 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3726 {
3727 struct sky2_port *sky2 = netdev_priv(netdev);
3728 sky2->msg_enable = value;
3729 }
3730
3731 static int sky2_get_sset_count(struct net_device *dev, int sset)
3732 {
3733 switch (sset) {
3734 case ETH_SS_STATS:
3735 return ARRAY_SIZE(sky2_stats);
3736 default:
3737 return -EOPNOTSUPP;
3738 }
3739 }
3740
3741 static void sky2_get_ethtool_stats(struct net_device *dev,
3742 struct ethtool_stats *stats, u64 * data)
3743 {
3744 struct sky2_port *sky2 = netdev_priv(dev);
3745
3746 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3747 }
3748
3749 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3750 {
3751 int i;
3752
3753 switch (stringset) {
3754 case ETH_SS_STATS:
3755 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3756 memcpy(data + i * ETH_GSTRING_LEN,
3757 sky2_stats[i].name, ETH_GSTRING_LEN);
3758 break;
3759 }
3760 }
3761
3762 static int sky2_set_mac_address(struct net_device *dev, void *p)
3763 {
3764 struct sky2_port *sky2 = netdev_priv(dev);
3765 struct sky2_hw *hw = sky2->hw;
3766 unsigned port = sky2->port;
3767 const struct sockaddr *addr = p;
3768
3769 if (!is_valid_ether_addr(addr->sa_data))
3770 return -EADDRNOTAVAIL;
3771
3772 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3773 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3774 dev->dev_addr, ETH_ALEN);
3775 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3776 dev->dev_addr, ETH_ALEN);
3777
3778 /* virtual address for data */
3779 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3780
3781 /* physical address: used for pause frames */
3782 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3783
3784 return 0;
3785 }
3786
3787 static inline void sky2_add_filter(u8 filter[8], const u8 *addr)
3788 {
3789 u32 bit;
3790
3791 bit = ether_crc(ETH_ALEN, addr) & 63;
3792 filter[bit >> 3] |= 1 << (bit & 7);
3793 }
3794
3795 static void sky2_set_multicast(struct net_device *dev)
3796 {
3797 struct sky2_port *sky2 = netdev_priv(dev);
3798 struct sky2_hw *hw = sky2->hw;
3799 unsigned port = sky2->port;
3800 struct netdev_hw_addr *ha;
3801 u16 reg;
3802 u8 filter[8];
3803 int rx_pause;
3804 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3805
3806 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3807 memset(filter, 0, sizeof(filter));
3808
3809 reg = gma_read16(hw, port, GM_RX_CTRL);
3810 reg |= GM_RXCR_UCF_ENA;
3811
3812 if (dev->flags & IFF_PROMISC) /* promiscuous */
3813 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3814 else if (dev->flags & IFF_ALLMULTI)
3815 memset(filter, 0xff, sizeof(filter));
3816 else if (netdev_mc_empty(dev) && !rx_pause)
3817 reg &= ~GM_RXCR_MCF_ENA;
3818 else {
3819 reg |= GM_RXCR_MCF_ENA;
3820
3821 if (rx_pause)
3822 sky2_add_filter(filter, pause_mc_addr);
3823
3824 netdev_for_each_mc_addr(ha, dev)
3825 sky2_add_filter(filter, ha->addr);
3826 }
3827
3828 gma_write16(hw, port, GM_MC_ADDR_H1,
3829 (u16) filter[0] | ((u16) filter[1] << 8));
3830 gma_write16(hw, port, GM_MC_ADDR_H2,
3831 (u16) filter[2] | ((u16) filter[3] << 8));
3832 gma_write16(hw, port, GM_MC_ADDR_H3,
3833 (u16) filter[4] | ((u16) filter[5] << 8));
3834 gma_write16(hw, port, GM_MC_ADDR_H4,
3835 (u16) filter[6] | ((u16) filter[7] << 8));
3836
3837 gma_write16(hw, port, GM_RX_CTRL, reg);
3838 }
3839
3840 static struct rtnl_link_stats64 *sky2_get_stats(struct net_device *dev,
3841 struct rtnl_link_stats64 *stats)
3842 {
3843 struct sky2_port *sky2 = netdev_priv(dev);
3844 struct sky2_hw *hw = sky2->hw;
3845 unsigned port = sky2->port;
3846 unsigned int start;
3847 u64 _bytes, _packets;
3848
3849 do {
3850 start = u64_stats_fetch_begin_bh(&sky2->rx_stats.syncp);
3851 _bytes = sky2->rx_stats.bytes;
3852 _packets = sky2->rx_stats.packets;
3853 } while (u64_stats_fetch_retry_bh(&sky2->rx_stats.syncp, start));
3854
3855 stats->rx_packets = _packets;
3856 stats->rx_bytes = _bytes;
3857
3858 do {
3859 start = u64_stats_fetch_begin_bh(&sky2->tx_stats.syncp);
3860 _bytes = sky2->tx_stats.bytes;
3861 _packets = sky2->tx_stats.packets;
3862 } while (u64_stats_fetch_retry_bh(&sky2->tx_stats.syncp, start));
3863
3864 stats->tx_packets = _packets;
3865 stats->tx_bytes = _bytes;
3866
3867 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK)
3868 + get_stats32(hw, port, GM_RXF_BC_OK);
3869
3870 stats->collisions = get_stats32(hw, port, GM_TXF_COL);
3871
3872 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR);
3873 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR);
3874 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT)
3875 + get_stats32(hw, port, GM_RXE_FRAG);
3876 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV);
3877
3878 stats->rx_dropped = dev->stats.rx_dropped;
3879 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
3880 stats->tx_fifo_errors = dev->stats.tx_fifo_errors;
3881
3882 return stats;
3883 }
3884
3885 /* Can have one global because blinking is controlled by
3886 * ethtool and that is always under RTNL mutex
3887 */
3888 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3889 {
3890 struct sky2_hw *hw = sky2->hw;
3891 unsigned port = sky2->port;
3892
3893 spin_lock_bh(&sky2->phy_lock);
3894 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3895 hw->chip_id == CHIP_ID_YUKON_EX ||
3896 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3897 u16 pg;
3898 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3899 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3900
3901 switch (mode) {
3902 case MO_LED_OFF:
3903 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3904 PHY_M_LEDC_LOS_CTRL(8) |
3905 PHY_M_LEDC_INIT_CTRL(8) |
3906 PHY_M_LEDC_STA1_CTRL(8) |
3907 PHY_M_LEDC_STA0_CTRL(8));
3908 break;
3909 case MO_LED_ON:
3910 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3911 PHY_M_LEDC_LOS_CTRL(9) |
3912 PHY_M_LEDC_INIT_CTRL(9) |
3913 PHY_M_LEDC_STA1_CTRL(9) |
3914 PHY_M_LEDC_STA0_CTRL(9));
3915 break;
3916 case MO_LED_BLINK:
3917 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3918 PHY_M_LEDC_LOS_CTRL(0xa) |
3919 PHY_M_LEDC_INIT_CTRL(0xa) |
3920 PHY_M_LEDC_STA1_CTRL(0xa) |
3921 PHY_M_LEDC_STA0_CTRL(0xa));
3922 break;
3923 case MO_LED_NORM:
3924 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3925 PHY_M_LEDC_LOS_CTRL(1) |
3926 PHY_M_LEDC_INIT_CTRL(8) |
3927 PHY_M_LEDC_STA1_CTRL(7) |
3928 PHY_M_LEDC_STA0_CTRL(7));
3929 }
3930
3931 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3932 } else
3933 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3934 PHY_M_LED_MO_DUP(mode) |
3935 PHY_M_LED_MO_10(mode) |
3936 PHY_M_LED_MO_100(mode) |
3937 PHY_M_LED_MO_1000(mode) |
3938 PHY_M_LED_MO_RX(mode) |
3939 PHY_M_LED_MO_TX(mode));
3940
3941 spin_unlock_bh(&sky2->phy_lock);
3942 }
3943
3944 /* blink LED's for finding board */
3945 static int sky2_set_phys_id(struct net_device *dev,
3946 enum ethtool_phys_id_state state)
3947 {
3948 struct sky2_port *sky2 = netdev_priv(dev);
3949
3950 switch (state) {
3951 case ETHTOOL_ID_ACTIVE:
3952 return 1; /* cycle on/off once per second */
3953 case ETHTOOL_ID_INACTIVE:
3954 sky2_led(sky2, MO_LED_NORM);
3955 break;
3956 case ETHTOOL_ID_ON:
3957 sky2_led(sky2, MO_LED_ON);
3958 break;
3959 case ETHTOOL_ID_OFF:
3960 sky2_led(sky2, MO_LED_OFF);
3961 break;
3962 }
3963
3964 return 0;
3965 }
3966
3967 static void sky2_get_pauseparam(struct net_device *dev,
3968 struct ethtool_pauseparam *ecmd)
3969 {
3970 struct sky2_port *sky2 = netdev_priv(dev);
3971
3972 switch (sky2->flow_mode) {
3973 case FC_NONE:
3974 ecmd->tx_pause = ecmd->rx_pause = 0;
3975 break;
3976 case FC_TX:
3977 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3978 break;
3979 case FC_RX:
3980 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3981 break;
3982 case FC_BOTH:
3983 ecmd->tx_pause = ecmd->rx_pause = 1;
3984 }
3985
3986 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3987 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3988 }
3989
3990 static int sky2_set_pauseparam(struct net_device *dev,
3991 struct ethtool_pauseparam *ecmd)
3992 {
3993 struct sky2_port *sky2 = netdev_priv(dev);
3994
3995 if (ecmd->autoneg == AUTONEG_ENABLE)
3996 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3997 else
3998 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3999
4000 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
4001
4002 if (netif_running(dev))
4003 sky2_phy_reinit(sky2);
4004
4005 return 0;
4006 }
4007
4008 static int sky2_get_coalesce(struct net_device *dev,
4009 struct ethtool_coalesce *ecmd)
4010 {
4011 struct sky2_port *sky2 = netdev_priv(dev);
4012 struct sky2_hw *hw = sky2->hw;
4013
4014 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
4015 ecmd->tx_coalesce_usecs = 0;
4016 else {
4017 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
4018 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
4019 }
4020 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
4021
4022 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
4023 ecmd->rx_coalesce_usecs = 0;
4024 else {
4025 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
4026 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
4027 }
4028 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
4029
4030 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
4031 ecmd->rx_coalesce_usecs_irq = 0;
4032 else {
4033 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
4034 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
4035 }
4036
4037 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
4038
4039 return 0;
4040 }
4041
4042 /* Note: this affect both ports */
4043 static int sky2_set_coalesce(struct net_device *dev,
4044 struct ethtool_coalesce *ecmd)
4045 {
4046 struct sky2_port *sky2 = netdev_priv(dev);
4047 struct sky2_hw *hw = sky2->hw;
4048 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
4049
4050 if (ecmd->tx_coalesce_usecs > tmax ||
4051 ecmd->rx_coalesce_usecs > tmax ||
4052 ecmd->rx_coalesce_usecs_irq > tmax)
4053 return -EINVAL;
4054
4055 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
4056 return -EINVAL;
4057 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
4058 return -EINVAL;
4059 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING)
4060 return -EINVAL;
4061
4062 if (ecmd->tx_coalesce_usecs == 0)
4063 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
4064 else {
4065 sky2_write32(hw, STAT_TX_TIMER_INI,
4066 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
4067 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
4068 }
4069 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
4070
4071 if (ecmd->rx_coalesce_usecs == 0)
4072 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
4073 else {
4074 sky2_write32(hw, STAT_LEV_TIMER_INI,
4075 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
4076 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
4077 }
4078 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
4079
4080 if (ecmd->rx_coalesce_usecs_irq == 0)
4081 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
4082 else {
4083 sky2_write32(hw, STAT_ISR_TIMER_INI,
4084 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
4085 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
4086 }
4087 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
4088 return 0;
4089 }
4090
4091 static void sky2_get_ringparam(struct net_device *dev,
4092 struct ethtool_ringparam *ering)
4093 {
4094 struct sky2_port *sky2 = netdev_priv(dev);
4095
4096 ering->rx_max_pending = RX_MAX_PENDING;
4097 ering->tx_max_pending = TX_MAX_PENDING;
4098
4099 ering->rx_pending = sky2->rx_pending;
4100 ering->tx_pending = sky2->tx_pending;
4101 }
4102
4103 static int sky2_set_ringparam(struct net_device *dev,
4104 struct ethtool_ringparam *ering)
4105 {
4106 struct sky2_port *sky2 = netdev_priv(dev);
4107
4108 if (ering->rx_pending > RX_MAX_PENDING ||
4109 ering->rx_pending < 8 ||
4110 ering->tx_pending < TX_MIN_PENDING ||
4111 ering->tx_pending > TX_MAX_PENDING)
4112 return -EINVAL;
4113
4114 sky2_detach(dev);
4115
4116 sky2->rx_pending = ering->rx_pending;
4117 sky2->tx_pending = ering->tx_pending;
4118 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
4119
4120 return sky2_reattach(dev);
4121 }
4122
4123 static int sky2_get_regs_len(struct net_device *dev)
4124 {
4125 return 0x4000;
4126 }
4127
4128 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
4129 {
4130 /* This complicated switch statement is to make sure and
4131 * only access regions that are unreserved.
4132 * Some blocks are only valid on dual port cards.
4133 */
4134 switch (b) {
4135 /* second port */
4136 case 5: /* Tx Arbiter 2 */
4137 case 9: /* RX2 */
4138 case 14 ... 15: /* TX2 */
4139 case 17: case 19: /* Ram Buffer 2 */
4140 case 22 ... 23: /* Tx Ram Buffer 2 */
4141 case 25: /* Rx MAC Fifo 1 */
4142 case 27: /* Tx MAC Fifo 2 */
4143 case 31: /* GPHY 2 */
4144 case 40 ... 47: /* Pattern Ram 2 */
4145 case 52: case 54: /* TCP Segmentation 2 */
4146 case 112 ... 116: /* GMAC 2 */
4147 return hw->ports > 1;
4148
4149 case 0: /* Control */
4150 case 2: /* Mac address */
4151 case 4: /* Tx Arbiter 1 */
4152 case 7: /* PCI express reg */
4153 case 8: /* RX1 */
4154 case 12 ... 13: /* TX1 */
4155 case 16: case 18:/* Rx Ram Buffer 1 */
4156 case 20 ... 21: /* Tx Ram Buffer 1 */
4157 case 24: /* Rx MAC Fifo 1 */
4158 case 26: /* Tx MAC Fifo 1 */
4159 case 28 ... 29: /* Descriptor and status unit */
4160 case 30: /* GPHY 1*/
4161 case 32 ... 39: /* Pattern Ram 1 */
4162 case 48: case 50: /* TCP Segmentation 1 */
4163 case 56 ... 60: /* PCI space */
4164 case 80 ... 84: /* GMAC 1 */
4165 return 1;
4166
4167 default:
4168 return 0;
4169 }
4170 }
4171
4172 /*
4173 * Returns copy of control register region
4174 * Note: ethtool_get_regs always provides full size (16k) buffer
4175 */
4176 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4177 void *p)
4178 {
4179 const struct sky2_port *sky2 = netdev_priv(dev);
4180 const void __iomem *io = sky2->hw->regs;
4181 unsigned int b;
4182
4183 regs->version = 1;
4184
4185 for (b = 0; b < 128; b++) {
4186 /* skip poisonous diagnostic ram region in block 3 */
4187 if (b == 3)
4188 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
4189 else if (sky2_reg_access_ok(sky2->hw, b))
4190 memcpy_fromio(p, io, 128);
4191 else
4192 memset(p, 0, 128);
4193
4194 p += 128;
4195 io += 128;
4196 }
4197 }
4198
4199 static int sky2_get_eeprom_len(struct net_device *dev)
4200 {
4201 struct sky2_port *sky2 = netdev_priv(dev);
4202 struct sky2_hw *hw = sky2->hw;
4203 u16 reg2;
4204
4205 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4206 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4207 }
4208
4209 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
4210 {
4211 unsigned long start = jiffies;
4212
4213 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4214 /* Can take up to 10.6 ms for write */
4215 if (time_after(jiffies, start + HZ/4)) {
4216 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
4217 return -ETIMEDOUT;
4218 }
4219 mdelay(1);
4220 }
4221
4222 return 0;
4223 }
4224
4225 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4226 u16 offset, size_t length)
4227 {
4228 int rc = 0;
4229
4230 while (length > 0) {
4231 u32 val;
4232
4233 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4234 rc = sky2_vpd_wait(hw, cap, 0);
4235 if (rc)
4236 break;
4237
4238 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4239
4240 memcpy(data, &val, min(sizeof(val), length));
4241 offset += sizeof(u32);
4242 data += sizeof(u32);
4243 length -= sizeof(u32);
4244 }
4245
4246 return rc;
4247 }
4248
4249 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4250 u16 offset, unsigned int length)
4251 {
4252 unsigned int i;
4253 int rc = 0;
4254
4255 for (i = 0; i < length; i += sizeof(u32)) {
4256 u32 val = *(u32 *)(data + i);
4257
4258 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4259 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4260
4261 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4262 if (rc)
4263 break;
4264 }
4265 return rc;
4266 }
4267
4268 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4269 u8 *data)
4270 {
4271 struct sky2_port *sky2 = netdev_priv(dev);
4272 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4273
4274 if (!cap)
4275 return -EINVAL;
4276
4277 eeprom->magic = SKY2_EEPROM_MAGIC;
4278
4279 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4280 }
4281
4282 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4283 u8 *data)
4284 {
4285 struct sky2_port *sky2 = netdev_priv(dev);
4286 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4287
4288 if (!cap)
4289 return -EINVAL;
4290
4291 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4292 return -EINVAL;
4293
4294 /* Partial writes not supported */
4295 if ((eeprom->offset & 3) || (eeprom->len & 3))
4296 return -EINVAL;
4297
4298 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4299 }
4300
4301 static u32 sky2_fix_features(struct net_device *dev, u32 features)
4302 {
4303 const struct sky2_port *sky2 = netdev_priv(dev);
4304 const struct sky2_hw *hw = sky2->hw;
4305
4306 /* In order to do Jumbo packets on these chips, need to turn off the
4307 * transmit store/forward. Therefore checksum offload won't work.
4308 */
4309 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) {
4310 netdev_info(dev, "checksum offload not possible with jumbo frames\n");
4311 features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
4312 }
4313
4314 /* Some hardware requires receive checksum for RSS to work. */
4315 if ( (features & NETIF_F_RXHASH) &&
4316 !(features & NETIF_F_RXCSUM) &&
4317 (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) {
4318 netdev_info(dev, "receive hashing forces receive checksum\n");
4319 features |= NETIF_F_RXCSUM;
4320 }
4321
4322 return features;
4323 }
4324
4325 static int sky2_set_features(struct net_device *dev, u32 features)
4326 {
4327 struct sky2_port *sky2 = netdev_priv(dev);
4328 u32 changed = dev->features ^ features;
4329
4330 if (changed & NETIF_F_RXCSUM) {
4331 u32 on = features & NETIF_F_RXCSUM;
4332 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
4333 on ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
4334 }
4335
4336 if (changed & NETIF_F_RXHASH)
4337 rx_set_rss(dev, features);
4338
4339 if (changed & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
4340 sky2_vlan_mode(dev, features);
4341
4342 return 0;
4343 }
4344
4345 static const struct ethtool_ops sky2_ethtool_ops = {
4346 .get_settings = sky2_get_settings,
4347 .set_settings = sky2_set_settings,
4348 .get_drvinfo = sky2_get_drvinfo,
4349 .get_wol = sky2_get_wol,
4350 .set_wol = sky2_set_wol,
4351 .get_msglevel = sky2_get_msglevel,
4352 .set_msglevel = sky2_set_msglevel,
4353 .nway_reset = sky2_nway_reset,
4354 .get_regs_len = sky2_get_regs_len,
4355 .get_regs = sky2_get_regs,
4356 .get_link = ethtool_op_get_link,
4357 .get_eeprom_len = sky2_get_eeprom_len,
4358 .get_eeprom = sky2_get_eeprom,
4359 .set_eeprom = sky2_set_eeprom,
4360 .get_strings = sky2_get_strings,
4361 .get_coalesce = sky2_get_coalesce,
4362 .set_coalesce = sky2_set_coalesce,
4363 .get_ringparam = sky2_get_ringparam,
4364 .set_ringparam = sky2_set_ringparam,
4365 .get_pauseparam = sky2_get_pauseparam,
4366 .set_pauseparam = sky2_set_pauseparam,
4367 .set_phys_id = sky2_set_phys_id,
4368 .get_sset_count = sky2_get_sset_count,
4369 .get_ethtool_stats = sky2_get_ethtool_stats,
4370 };
4371
4372 #ifdef CONFIG_SKY2_DEBUG
4373
4374 static struct dentry *sky2_debug;
4375
4376
4377 /*
4378 * Read and parse the first part of Vital Product Data
4379 */
4380 #define VPD_SIZE 128
4381 #define VPD_MAGIC 0x82
4382
4383 static const struct vpd_tag {
4384 char tag[2];
4385 char *label;
4386 } vpd_tags[] = {
4387 { "PN", "Part Number" },
4388 { "EC", "Engineering Level" },
4389 { "MN", "Manufacturer" },
4390 { "SN", "Serial Number" },
4391 { "YA", "Asset Tag" },
4392 { "VL", "First Error Log Message" },
4393 { "VF", "Second Error Log Message" },
4394 { "VB", "Boot Agent ROM Configuration" },
4395 { "VE", "EFI UNDI Configuration" },
4396 };
4397
4398 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4399 {
4400 size_t vpd_size;
4401 loff_t offs;
4402 u8 len;
4403 unsigned char *buf;
4404 u16 reg2;
4405
4406 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4407 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4408
4409 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4410 buf = kmalloc(vpd_size, GFP_KERNEL);
4411 if (!buf) {
4412 seq_puts(seq, "no memory!\n");
4413 return;
4414 }
4415
4416 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4417 seq_puts(seq, "VPD read failed\n");
4418 goto out;
4419 }
4420
4421 if (buf[0] != VPD_MAGIC) {
4422 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4423 goto out;
4424 }
4425 len = buf[1];
4426 if (len == 0 || len > vpd_size - 4) {
4427 seq_printf(seq, "Invalid id length: %d\n", len);
4428 goto out;
4429 }
4430
4431 seq_printf(seq, "%.*s\n", len, buf + 3);
4432 offs = len + 3;
4433
4434 while (offs < vpd_size - 4) {
4435 int i;
4436
4437 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4438 break;
4439 len = buf[offs + 2];
4440 if (offs + len + 3 >= vpd_size)
4441 break;
4442
4443 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4444 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4445 seq_printf(seq, " %s: %.*s\n",
4446 vpd_tags[i].label, len, buf + offs + 3);
4447 break;
4448 }
4449 }
4450 offs += len + 3;
4451 }
4452 out:
4453 kfree(buf);
4454 }
4455
4456 static int sky2_debug_show(struct seq_file *seq, void *v)
4457 {
4458 struct net_device *dev = seq->private;
4459 const struct sky2_port *sky2 = netdev_priv(dev);
4460 struct sky2_hw *hw = sky2->hw;
4461 unsigned port = sky2->port;
4462 unsigned idx, last;
4463 int sop;
4464
4465 sky2_show_vpd(seq, hw);
4466
4467 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4468 sky2_read32(hw, B0_ISRC),
4469 sky2_read32(hw, B0_IMSK),
4470 sky2_read32(hw, B0_Y2_SP_ICR));
4471
4472 if (!netif_running(dev)) {
4473 seq_printf(seq, "network not running\n");
4474 return 0;
4475 }
4476
4477 napi_disable(&hw->napi);
4478 last = sky2_read16(hw, STAT_PUT_IDX);
4479
4480 seq_printf(seq, "Status ring %u\n", hw->st_size);
4481 if (hw->st_idx == last)
4482 seq_puts(seq, "Status ring (empty)\n");
4483 else {
4484 seq_puts(seq, "Status ring\n");
4485 for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4486 idx = RING_NEXT(idx, hw->st_size)) {
4487 const struct sky2_status_le *le = hw->st_le + idx;
4488 seq_printf(seq, "[%d] %#x %d %#x\n",
4489 idx, le->opcode, le->length, le->status);
4490 }
4491 seq_puts(seq, "\n");
4492 }
4493
4494 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4495 sky2->tx_cons, sky2->tx_prod,
4496 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4497 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4498
4499 /* Dump contents of tx ring */
4500 sop = 1;
4501 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4502 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4503 const struct sky2_tx_le *le = sky2->tx_le + idx;
4504 u32 a = le32_to_cpu(le->addr);
4505
4506 if (sop)
4507 seq_printf(seq, "%u:", idx);
4508 sop = 0;
4509
4510 switch (le->opcode & ~HW_OWNER) {
4511 case OP_ADDR64:
4512 seq_printf(seq, " %#x:", a);
4513 break;
4514 case OP_LRGLEN:
4515 seq_printf(seq, " mtu=%d", a);
4516 break;
4517 case OP_VLAN:
4518 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4519 break;
4520 case OP_TCPLISW:
4521 seq_printf(seq, " csum=%#x", a);
4522 break;
4523 case OP_LARGESEND:
4524 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4525 break;
4526 case OP_PACKET:
4527 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4528 break;
4529 case OP_BUFFER:
4530 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4531 break;
4532 default:
4533 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4534 a, le16_to_cpu(le->length));
4535 }
4536
4537 if (le->ctrl & EOP) {
4538 seq_putc(seq, '\n');
4539 sop = 1;
4540 }
4541 }
4542
4543 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4544 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4545 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4546 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4547
4548 sky2_read32(hw, B0_Y2_SP_LISR);
4549 napi_enable(&hw->napi);
4550 return 0;
4551 }
4552
4553 static int sky2_debug_open(struct inode *inode, struct file *file)
4554 {
4555 return single_open(file, sky2_debug_show, inode->i_private);
4556 }
4557
4558 static const struct file_operations sky2_debug_fops = {
4559 .owner = THIS_MODULE,
4560 .open = sky2_debug_open,
4561 .read = seq_read,
4562 .llseek = seq_lseek,
4563 .release = single_release,
4564 };
4565
4566 /*
4567 * Use network device events to create/remove/rename
4568 * debugfs file entries
4569 */
4570 static int sky2_device_event(struct notifier_block *unused,
4571 unsigned long event, void *ptr)
4572 {
4573 struct net_device *dev = ptr;
4574 struct sky2_port *sky2 = netdev_priv(dev);
4575
4576 if (dev->netdev_ops->ndo_open != sky2_open || !sky2_debug)
4577 return NOTIFY_DONE;
4578
4579 switch (event) {
4580 case NETDEV_CHANGENAME:
4581 if (sky2->debugfs) {
4582 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4583 sky2_debug, dev->name);
4584 }
4585 break;
4586
4587 case NETDEV_GOING_DOWN:
4588 if (sky2->debugfs) {
4589 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
4590 debugfs_remove(sky2->debugfs);
4591 sky2->debugfs = NULL;
4592 }
4593 break;
4594
4595 case NETDEV_UP:
4596 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4597 sky2_debug, dev,
4598 &sky2_debug_fops);
4599 if (IS_ERR(sky2->debugfs))
4600 sky2->debugfs = NULL;
4601 }
4602
4603 return NOTIFY_DONE;
4604 }
4605
4606 static struct notifier_block sky2_notifier = {
4607 .notifier_call = sky2_device_event,
4608 };
4609
4610
4611 static __init void sky2_debug_init(void)
4612 {
4613 struct dentry *ent;
4614
4615 ent = debugfs_create_dir("sky2", NULL);
4616 if (!ent || IS_ERR(ent))
4617 return;
4618
4619 sky2_debug = ent;
4620 register_netdevice_notifier(&sky2_notifier);
4621 }
4622
4623 static __exit void sky2_debug_cleanup(void)
4624 {
4625 if (sky2_debug) {
4626 unregister_netdevice_notifier(&sky2_notifier);
4627 debugfs_remove(sky2_debug);
4628 sky2_debug = NULL;
4629 }
4630 }
4631
4632 #else
4633 #define sky2_debug_init()
4634 #define sky2_debug_cleanup()
4635 #endif
4636
4637 /* Two copies of network device operations to handle special case of
4638 not allowing netpoll on second port */
4639 static const struct net_device_ops sky2_netdev_ops[2] = {
4640 {
4641 .ndo_open = sky2_open,
4642 .ndo_stop = sky2_close,
4643 .ndo_start_xmit = sky2_xmit_frame,
4644 .ndo_do_ioctl = sky2_ioctl,
4645 .ndo_validate_addr = eth_validate_addr,
4646 .ndo_set_mac_address = sky2_set_mac_address,
4647 .ndo_set_rx_mode = sky2_set_multicast,
4648 .ndo_change_mtu = sky2_change_mtu,
4649 .ndo_fix_features = sky2_fix_features,
4650 .ndo_set_features = sky2_set_features,
4651 .ndo_tx_timeout = sky2_tx_timeout,
4652 .ndo_get_stats64 = sky2_get_stats,
4653 #ifdef CONFIG_NET_POLL_CONTROLLER
4654 .ndo_poll_controller = sky2_netpoll,
4655 #endif
4656 },
4657 {
4658 .ndo_open = sky2_open,
4659 .ndo_stop = sky2_close,
4660 .ndo_start_xmit = sky2_xmit_frame,
4661 .ndo_do_ioctl = sky2_ioctl,
4662 .ndo_validate_addr = eth_validate_addr,
4663 .ndo_set_mac_address = sky2_set_mac_address,
4664 .ndo_set_rx_mode = sky2_set_multicast,
4665 .ndo_change_mtu = sky2_change_mtu,
4666 .ndo_fix_features = sky2_fix_features,
4667 .ndo_set_features = sky2_set_features,
4668 .ndo_tx_timeout = sky2_tx_timeout,
4669 .ndo_get_stats64 = sky2_get_stats,
4670 },
4671 };
4672
4673 /* Initialize network device */
4674 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4675 unsigned port,
4676 int highmem, int wol)
4677 {
4678 struct sky2_port *sky2;
4679 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4680
4681 if (!dev) {
4682 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4683 return NULL;
4684 }
4685
4686 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4687 dev->irq = hw->pdev->irq;
4688 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4689 dev->watchdog_timeo = TX_WATCHDOG;
4690 dev->netdev_ops = &sky2_netdev_ops[port];
4691
4692 sky2 = netdev_priv(dev);
4693 sky2->netdev = dev;
4694 sky2->hw = hw;
4695 sky2->msg_enable = netif_msg_init(debug, default_msg);
4696
4697 /* Auto speed and flow control */
4698 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4699 if (hw->chip_id != CHIP_ID_YUKON_XL)
4700 dev->hw_features |= NETIF_F_RXCSUM;
4701
4702 sky2->flow_mode = FC_BOTH;
4703
4704 sky2->duplex = -1;
4705 sky2->speed = -1;
4706 sky2->advertising = sky2_supported_modes(hw);
4707 sky2->wol = wol;
4708
4709 spin_lock_init(&sky2->phy_lock);
4710
4711 sky2->tx_pending = TX_DEF_PENDING;
4712 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
4713 sky2->rx_pending = RX_DEF_PENDING;
4714
4715 hw->dev[port] = dev;
4716
4717 sky2->port = port;
4718
4719 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO;
4720
4721 if (highmem)
4722 dev->features |= NETIF_F_HIGHDMA;
4723
4724 /* Enable receive hashing unless hardware is known broken */
4725 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
4726 dev->hw_features |= NETIF_F_RXHASH;
4727
4728 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) {
4729 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4730 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
4731 }
4732
4733 dev->features |= dev->hw_features;
4734
4735 /* read the mac address */
4736 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4737 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4738
4739 return dev;
4740 }
4741
4742 static void __devinit sky2_show_addr(struct net_device *dev)
4743 {
4744 const struct sky2_port *sky2 = netdev_priv(dev);
4745
4746 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
4747 }
4748
4749 /* Handle software interrupt used during MSI test */
4750 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4751 {
4752 struct sky2_hw *hw = dev_id;
4753 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4754
4755 if (status == 0)
4756 return IRQ_NONE;
4757
4758 if (status & Y2_IS_IRQ_SW) {
4759 hw->flags |= SKY2_HW_USE_MSI;
4760 wake_up(&hw->msi_wait);
4761 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4762 }
4763 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4764
4765 return IRQ_HANDLED;
4766 }
4767
4768 /* Test interrupt path by forcing a a software IRQ */
4769 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4770 {
4771 struct pci_dev *pdev = hw->pdev;
4772 int err;
4773
4774 init_waitqueue_head(&hw->msi_wait);
4775
4776 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4777
4778 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4779 if (err) {
4780 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4781 return err;
4782 }
4783
4784 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4785 sky2_read8(hw, B0_CTST);
4786
4787 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4788
4789 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4790 /* MSI test failed, go back to INTx mode */
4791 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4792 "switching to INTx mode.\n");
4793
4794 err = -EOPNOTSUPP;
4795 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4796 }
4797
4798 sky2_write32(hw, B0_IMSK, 0);
4799 sky2_read32(hw, B0_IMSK);
4800
4801 free_irq(pdev->irq, hw);
4802
4803 return err;
4804 }
4805
4806 /* This driver supports yukon2 chipset only */
4807 static const char *sky2_name(u8 chipid, char *buf, int sz)
4808 {
4809 const char *name[] = {
4810 "XL", /* 0xb3 */
4811 "EC Ultra", /* 0xb4 */
4812 "Extreme", /* 0xb5 */
4813 "EC", /* 0xb6 */
4814 "FE", /* 0xb7 */
4815 "FE+", /* 0xb8 */
4816 "Supreme", /* 0xb9 */
4817 "UL 2", /* 0xba */
4818 "Unknown", /* 0xbb */
4819 "Optima", /* 0xbc */
4820 "Optima Prime", /* 0xbd */
4821 "Optima 2", /* 0xbe */
4822 };
4823
4824 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2)
4825 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4826 else
4827 snprintf(buf, sz, "(chip %#x)", chipid);
4828 return buf;
4829 }
4830
4831 static int __devinit sky2_probe(struct pci_dev *pdev,
4832 const struct pci_device_id *ent)
4833 {
4834 struct net_device *dev, *dev1;
4835 struct sky2_hw *hw;
4836 int err, using_dac = 0, wol_default;
4837 u32 reg;
4838 char buf1[16];
4839
4840 err = pci_enable_device(pdev);
4841 if (err) {
4842 dev_err(&pdev->dev, "cannot enable PCI device\n");
4843 goto err_out;
4844 }
4845
4846 /* Get configuration information
4847 * Note: only regular PCI config access once to test for HW issues
4848 * other PCI access through shared memory for speed and to
4849 * avoid MMCONFIG problems.
4850 */
4851 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4852 if (err) {
4853 dev_err(&pdev->dev, "PCI read config failed\n");
4854 goto err_out;
4855 }
4856
4857 if (~reg == 0) {
4858 dev_err(&pdev->dev, "PCI configuration read error\n");
4859 goto err_out;
4860 }
4861
4862 err = pci_request_regions(pdev, DRV_NAME);
4863 if (err) {
4864 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4865 goto err_out_disable;
4866 }
4867
4868 pci_set_master(pdev);
4869
4870 if (sizeof(dma_addr_t) > sizeof(u32) &&
4871 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4872 using_dac = 1;
4873 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4874 if (err < 0) {
4875 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4876 "for consistent allocations\n");
4877 goto err_out_free_regions;
4878 }
4879 } else {
4880 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4881 if (err) {
4882 dev_err(&pdev->dev, "no usable DMA configuration\n");
4883 goto err_out_free_regions;
4884 }
4885 }
4886
4887
4888 #ifdef __BIG_ENDIAN
4889 /* The sk98lin vendor driver uses hardware byte swapping but
4890 * this driver uses software swapping.
4891 */
4892 reg &= ~PCI_REV_DESC;
4893 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
4894 if (err) {
4895 dev_err(&pdev->dev, "PCI write config failed\n");
4896 goto err_out_free_regions;
4897 }
4898 #endif
4899
4900 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4901
4902 err = -ENOMEM;
4903
4904 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4905 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
4906 if (!hw) {
4907 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4908 goto err_out_free_regions;
4909 }
4910
4911 hw->pdev = pdev;
4912 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
4913
4914 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4915 if (!hw->regs) {
4916 dev_err(&pdev->dev, "cannot map device registers\n");
4917 goto err_out_free_hw;
4918 }
4919
4920 err = sky2_init(hw);
4921 if (err)
4922 goto err_out_iounmap;
4923
4924 /* ring for status responses */
4925 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
4926 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4927 &hw->st_dma);
4928 if (!hw->st_le)
4929 goto err_out_reset;
4930
4931 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4932 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4933
4934 sky2_reset(hw);
4935
4936 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4937 if (!dev) {
4938 err = -ENOMEM;
4939 goto err_out_free_pci;
4940 }
4941
4942 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4943 err = sky2_test_msi(hw);
4944 if (err == -EOPNOTSUPP)
4945 pci_disable_msi(pdev);
4946 else if (err)
4947 goto err_out_free_netdev;
4948 }
4949
4950 err = register_netdev(dev);
4951 if (err) {
4952 dev_err(&pdev->dev, "cannot register net device\n");
4953 goto err_out_free_netdev;
4954 }
4955
4956 netif_carrier_off(dev);
4957
4958 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4959
4960 sky2_show_addr(dev);
4961
4962 if (hw->ports > 1) {
4963 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4964 if (!dev1) {
4965 err = -ENOMEM;
4966 goto err_out_unregister;
4967 }
4968
4969 err = register_netdev(dev1);
4970 if (err) {
4971 dev_err(&pdev->dev, "cannot register second net device\n");
4972 goto err_out_free_dev1;
4973 }
4974
4975 err = sky2_setup_irq(hw, hw->irq_name);
4976 if (err)
4977 goto err_out_unregister_dev1;
4978
4979 sky2_show_addr(dev1);
4980 }
4981
4982 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4983 INIT_WORK(&hw->restart_work, sky2_restart);
4984
4985 pci_set_drvdata(pdev, hw);
4986 pdev->d3_delay = 150;
4987
4988 return 0;
4989
4990 err_out_unregister_dev1:
4991 unregister_netdev(dev1);
4992 err_out_free_dev1:
4993 free_netdev(dev1);
4994 err_out_unregister:
4995 if (hw->flags & SKY2_HW_USE_MSI)
4996 pci_disable_msi(pdev);
4997 unregister_netdev(dev);
4998 err_out_free_netdev:
4999 free_netdev(dev);
5000 err_out_free_pci:
5001 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
5002 hw->st_le, hw->st_dma);
5003 err_out_reset:
5004 sky2_write8(hw, B0_CTST, CS_RST_SET);
5005 err_out_iounmap:
5006 iounmap(hw->regs);
5007 err_out_free_hw:
5008 kfree(hw);
5009 err_out_free_regions:
5010 pci_release_regions(pdev);
5011 err_out_disable:
5012 pci_disable_device(pdev);
5013 err_out:
5014 pci_set_drvdata(pdev, NULL);
5015 return err;
5016 }
5017
5018 static void __devexit sky2_remove(struct pci_dev *pdev)
5019 {
5020 struct sky2_hw *hw = pci_get_drvdata(pdev);
5021 int i;
5022
5023 if (!hw)
5024 return;
5025
5026 del_timer_sync(&hw->watchdog_timer);
5027 cancel_work_sync(&hw->restart_work);
5028
5029 for (i = hw->ports-1; i >= 0; --i)
5030 unregister_netdev(hw->dev[i]);
5031
5032 sky2_write32(hw, B0_IMSK, 0);
5033 sky2_read32(hw, B0_IMSK);
5034
5035 sky2_power_aux(hw);
5036
5037 sky2_write8(hw, B0_CTST, CS_RST_SET);
5038 sky2_read8(hw, B0_CTST);
5039
5040 if (hw->ports > 1) {
5041 napi_disable(&hw->napi);
5042 free_irq(pdev->irq, hw);
5043 }
5044
5045 if (hw->flags & SKY2_HW_USE_MSI)
5046 pci_disable_msi(pdev);
5047 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
5048 hw->st_le, hw->st_dma);
5049 pci_release_regions(pdev);
5050 pci_disable_device(pdev);
5051
5052 for (i = hw->ports-1; i >= 0; --i)
5053 free_netdev(hw->dev[i]);
5054
5055 iounmap(hw->regs);
5056 kfree(hw);
5057
5058 pci_set_drvdata(pdev, NULL);
5059 }
5060
5061 static int sky2_suspend(struct device *dev)
5062 {
5063 struct pci_dev *pdev = to_pci_dev(dev);
5064 struct sky2_hw *hw = pci_get_drvdata(pdev);
5065 int i;
5066
5067 if (!hw)
5068 return 0;
5069
5070 del_timer_sync(&hw->watchdog_timer);
5071 cancel_work_sync(&hw->restart_work);
5072
5073 rtnl_lock();
5074
5075 sky2_all_down(hw);
5076 for (i = 0; i < hw->ports; i++) {
5077 struct net_device *dev = hw->dev[i];
5078 struct sky2_port *sky2 = netdev_priv(dev);
5079
5080 if (sky2->wol)
5081 sky2_wol_init(sky2);
5082 }
5083
5084 sky2_power_aux(hw);
5085 rtnl_unlock();
5086
5087 return 0;
5088 }
5089
5090 #ifdef CONFIG_PM_SLEEP
5091 static int sky2_resume(struct device *dev)
5092 {
5093 struct pci_dev *pdev = to_pci_dev(dev);
5094 struct sky2_hw *hw = pci_get_drvdata(pdev);
5095 int err;
5096
5097 if (!hw)
5098 return 0;
5099
5100 /* Re-enable all clocks */
5101 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
5102 if (err) {
5103 dev_err(&pdev->dev, "PCI write config failed\n");
5104 goto out;
5105 }
5106
5107 rtnl_lock();
5108 sky2_reset(hw);
5109 sky2_all_up(hw);
5110 rtnl_unlock();
5111
5112 return 0;
5113 out:
5114
5115 dev_err(&pdev->dev, "resume failed (%d)\n", err);
5116 pci_disable_device(pdev);
5117 return err;
5118 }
5119
5120 static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume);
5121 #define SKY2_PM_OPS (&sky2_pm_ops)
5122
5123 #else
5124
5125 #define SKY2_PM_OPS NULL
5126 #endif
5127
5128 static void sky2_shutdown(struct pci_dev *pdev)
5129 {
5130 sky2_suspend(&pdev->dev);
5131 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
5132 pci_set_power_state(pdev, PCI_D3hot);
5133 }
5134
5135 static struct pci_driver sky2_driver = {
5136 .name = DRV_NAME,
5137 .id_table = sky2_id_table,
5138 .probe = sky2_probe,
5139 .remove = __devexit_p(sky2_remove),
5140 .shutdown = sky2_shutdown,
5141 .driver.pm = SKY2_PM_OPS,
5142 };
5143
5144 static int __init sky2_init_module(void)
5145 {
5146 pr_info("driver version " DRV_VERSION "\n");
5147
5148 sky2_debug_init();
5149 return pci_register_driver(&sky2_driver);
5150 }
5151
5152 static void __exit sky2_cleanup_module(void)
5153 {
5154 pci_unregister_driver(&sky2_driver);
5155 sky2_debug_cleanup();
5156 }
5157
5158 module_init(sky2_init_module);
5159 module_exit(sky2_cleanup_module);
5160
5161 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
5162 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
5163 MODULE_LICENSE("GPL");
5164 MODULE_VERSION(DRV_VERSION);