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Staging: hv: mousevsc: Cleanup and properly implement reportdesc_callback()
[zen-stable.git] / drivers / net / ixgbe / ixgbe_82599.c
blob34f30ec79c2ebea6af3d5475339d51238a8bc73d
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
35
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
41 #define IXGBE_82599_RX_PB_SIZE 512
42
43 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
44 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
46 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed,
48 bool autoneg,
49 bool autoneg_wait_to_complete);
50 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
51 ixgbe_link_speed speed,
52 bool autoneg,
53 bool autoneg_wait_to_complete);
54 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
55 bool autoneg_wait_to_complete);
56 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
57 ixgbe_link_speed speed,
58 bool autoneg,
59 bool autoneg_wait_to_complete);
60 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
61 ixgbe_link_speed speed,
62 bool autoneg,
63 bool autoneg_wait_to_complete);
64 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
65 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
66
67 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
68 {
69 struct ixgbe_mac_info *mac = &hw->mac;
70
71 /* enable the laser control functions for SFP+ fiber */
72 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
73 mac->ops.disable_tx_laser =
74 &ixgbe_disable_tx_laser_multispeed_fiber;
75 mac->ops.enable_tx_laser =
76 &ixgbe_enable_tx_laser_multispeed_fiber;
77 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
78 } else {
79 mac->ops.disable_tx_laser = NULL;
80 mac->ops.enable_tx_laser = NULL;
81 mac->ops.flap_tx_laser = NULL;
82 }
83
84 if (hw->phy.multispeed_fiber) {
85 /* Set up dual speed SFP+ support */
86 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
87 } else {
88 if ((mac->ops.get_media_type(hw) ==
89 ixgbe_media_type_backplane) &&
90 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
91 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
92 !ixgbe_verify_lesm_fw_enabled_82599(hw))
93 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
94 else
95 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
96 }
97 }
98
99 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
100 {
101 s32 ret_val = 0;
102 u32 reg_anlp1 = 0;
103 u32 i = 0;
104 u16 list_offset, data_offset, data_value;
105
106 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
107 ixgbe_init_mac_link_ops_82599(hw);
108
109 hw->phy.ops.reset = NULL;
110
111 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
112 &data_offset);
113 if (ret_val != 0)
114 goto setup_sfp_out;
115
116 /* PHY config will finish before releasing the semaphore */
117 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
118 IXGBE_GSSR_MAC_CSR_SM);
119 if (ret_val != 0) {
120 ret_val = IXGBE_ERR_SWFW_SYNC;
121 goto setup_sfp_out;
122 }
123
124 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
125 while (data_value != 0xffff) {
126 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
127 IXGBE_WRITE_FLUSH(hw);
128 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
129 }
130
131 /* Release the semaphore */
132 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
133 /*
134 * Delay obtaining semaphore again to allow FW access,
135 * semaphore_delay is in ms usleep_range needs us.
136 */
137 usleep_range(hw->eeprom.semaphore_delay * 1000,
138 hw->eeprom.semaphore_delay * 2000);
139
140 /* Now restart DSP by setting Restart_AN and clearing LMS */
141 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
142 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
143 IXGBE_AUTOC_AN_RESTART));
144
145 /* Wait for AN to leave state 0 */
146 for (i = 0; i < 10; i++) {
147 usleep_range(4000, 8000);
148 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
149 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
150 break;
151 }
152 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
153 hw_dbg(hw, "sfp module setup not complete\n");
154 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
155 goto setup_sfp_out;
156 }
157
158 /* Restart DSP by setting Restart_AN and return to SFI mode */
159 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
160 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
161 IXGBE_AUTOC_AN_RESTART));
162 }
163
164 setup_sfp_out:
165 return ret_val;
166 }
167
168 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
169 {
170 struct ixgbe_mac_info *mac = &hw->mac;
171
172 ixgbe_init_mac_link_ops_82599(hw);
173
174 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
175 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
176 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
177 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
178 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
179 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
180
181 return 0;
182 }
183
184 /**
185 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
186 * @hw: pointer to hardware structure
187 *
188 * Initialize any function pointers that were not able to be
189 * set during get_invariants because the PHY/SFP type was
190 * not known. Perform the SFP init if necessary.
191 *
192 **/
193 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
194 {
195 struct ixgbe_mac_info *mac = &hw->mac;
196 struct ixgbe_phy_info *phy = &hw->phy;
197 s32 ret_val = 0;
198
199 /* Identify the PHY or SFP module */
200 ret_val = phy->ops.identify(hw);
201
202 /* Setup function pointers based on detected SFP module and speeds */
203 ixgbe_init_mac_link_ops_82599(hw);
204
205 /* If copper media, overwrite with copper function pointers */
206 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
207 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
208 mac->ops.get_link_capabilities =
209 &ixgbe_get_copper_link_capabilities_generic;
210 }
211
212 /* Set necessary function pointers based on phy type */
213 switch (hw->phy.type) {
214 case ixgbe_phy_tn:
215 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
216 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
217 phy->ops.get_firmware_version =
218 &ixgbe_get_phy_firmware_version_tnx;
219 break;
220 case ixgbe_phy_aq:
221 phy->ops.get_firmware_version =
222 &ixgbe_get_phy_firmware_version_generic;
223 break;
224 default:
225 break;
226 }
227
228 return ret_val;
229 }
230
231 /**
232 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
233 * @hw: pointer to hardware structure
234 * @speed: pointer to link speed
235 * @negotiation: true when autoneg or autotry is enabled
236 *
237 * Determines the link capabilities by reading the AUTOC register.
238 **/
239 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
240 ixgbe_link_speed *speed,
241 bool *negotiation)
242 {
243 s32 status = 0;
244 u32 autoc = 0;
245
246 /* Determine 1G link capabilities off of SFP+ type */
247 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
248 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) {
249 *speed = IXGBE_LINK_SPEED_1GB_FULL;
250 *negotiation = true;
251 goto out;
252 }
253
254 /*
255 * Determine link capabilities based on the stored value of AUTOC,
256 * which represents EEPROM defaults. If AUTOC value has not been
257 * stored, use the current register value.
258 */
259 if (hw->mac.orig_link_settings_stored)
260 autoc = hw->mac.orig_autoc;
261 else
262 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
263
264 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
265 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
266 *speed = IXGBE_LINK_SPEED_1GB_FULL;
267 *negotiation = false;
268 break;
269
270 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
271 *speed = IXGBE_LINK_SPEED_10GB_FULL;
272 *negotiation = false;
273 break;
274
275 case IXGBE_AUTOC_LMS_1G_AN:
276 *speed = IXGBE_LINK_SPEED_1GB_FULL;
277 *negotiation = true;
278 break;
279
280 case IXGBE_AUTOC_LMS_10G_SERIAL:
281 *speed = IXGBE_LINK_SPEED_10GB_FULL;
282 *negotiation = false;
283 break;
284
285 case IXGBE_AUTOC_LMS_KX4_KX_KR:
286 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
287 *speed = IXGBE_LINK_SPEED_UNKNOWN;
288 if (autoc & IXGBE_AUTOC_KR_SUPP)
289 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
290 if (autoc & IXGBE_AUTOC_KX4_SUPP)
291 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
292 if (autoc & IXGBE_AUTOC_KX_SUPP)
293 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
294 *negotiation = true;
295 break;
296
297 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
298 *speed = IXGBE_LINK_SPEED_100_FULL;
299 if (autoc & IXGBE_AUTOC_KR_SUPP)
300 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
301 if (autoc & IXGBE_AUTOC_KX4_SUPP)
302 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
303 if (autoc & IXGBE_AUTOC_KX_SUPP)
304 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
305 *negotiation = true;
306 break;
307
308 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
309 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
310 *negotiation = false;
311 break;
312
313 default:
314 status = IXGBE_ERR_LINK_SETUP;
315 goto out;
316 break;
317 }
318
319 if (hw->phy.multispeed_fiber) {
320 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
321 IXGBE_LINK_SPEED_1GB_FULL;
322 *negotiation = true;
323 }
324
325 out:
326 return status;
327 }
328
329 /**
330 * ixgbe_get_media_type_82599 - Get media type
331 * @hw: pointer to hardware structure
332 *
333 * Returns the media type (fiber, copper, backplane)
334 **/
335 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
336 {
337 enum ixgbe_media_type media_type;
338
339 /* Detect if there is a copper PHY attached. */
340 switch (hw->phy.type) {
341 case ixgbe_phy_cu_unknown:
342 case ixgbe_phy_tn:
343 case ixgbe_phy_aq:
344 media_type = ixgbe_media_type_copper;
345 goto out;
346 default:
347 break;
348 }
349
350 switch (hw->device_id) {
351 case IXGBE_DEV_ID_82599_KX4:
352 case IXGBE_DEV_ID_82599_KX4_MEZZ:
353 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
354 case IXGBE_DEV_ID_82599_KR:
355 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
356 case IXGBE_DEV_ID_82599_XAUI_LOM:
357 /* Default device ID is mezzanine card KX/KX4 */
358 media_type = ixgbe_media_type_backplane;
359 break;
360 case IXGBE_DEV_ID_82599_SFP:
361 case IXGBE_DEV_ID_82599_SFP_FCOE:
362 case IXGBE_DEV_ID_82599_SFP_EM:
363 case IXGBE_DEV_ID_82599_SFP_SF2:
364 media_type = ixgbe_media_type_fiber;
365 break;
366 case IXGBE_DEV_ID_82599_CX4:
367 media_type = ixgbe_media_type_cx4;
368 break;
369 case IXGBE_DEV_ID_82599_T3_LOM:
370 media_type = ixgbe_media_type_copper;
371 break;
372 case IXGBE_DEV_ID_82599_LS:
373 media_type = ixgbe_media_type_fiber_lco;
374 break;
375 default:
376 media_type = ixgbe_media_type_unknown;
377 break;
378 }
379 out:
380 return media_type;
381 }
382
383 /**
384 * ixgbe_start_mac_link_82599 - Setup MAC link settings
385 * @hw: pointer to hardware structure
386 * @autoneg_wait_to_complete: true when waiting for completion is needed
387 *
388 * Configures link settings based on values in the ixgbe_hw struct.
389 * Restarts the link. Performs autonegotiation if needed.
390 **/
391 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
392 bool autoneg_wait_to_complete)
393 {
394 u32 autoc_reg;
395 u32 links_reg;
396 u32 i;
397 s32 status = 0;
398
399 /* Restart link */
400 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
401 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
402 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
403
404 /* Only poll for autoneg to complete if specified to do so */
405 if (autoneg_wait_to_complete) {
406 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
407 IXGBE_AUTOC_LMS_KX4_KX_KR ||
408 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
409 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
410 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
411 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
412 links_reg = 0; /* Just in case Autoneg time = 0 */
413 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
414 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
415 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
416 break;
417 msleep(100);
418 }
419 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
420 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
421 hw_dbg(hw, "Autoneg did not complete.\n");
422 }
423 }
424 }
425
426 /* Add delay to filter out noises during initial link setup */
427 msleep(50);
428
429 return status;
430 }
431
432 /**
433 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
434 * @hw: pointer to hardware structure
435 *
436 * The base drivers may require better control over SFP+ module
437 * PHY states. This includes selectively shutting down the Tx
438 * laser on the PHY, effectively halting physical link.
439 **/
440 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
441 {
442 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
443
444 /* Disable tx laser; allow 100us to go dark per spec */
445 esdp_reg |= IXGBE_ESDP_SDP3;
446 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
447 IXGBE_WRITE_FLUSH(hw);
448 udelay(100);
449 }
450
451 /**
452 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
453 * @hw: pointer to hardware structure
454 *
455 * The base drivers may require better control over SFP+ module
456 * PHY states. This includes selectively turning on the Tx
457 * laser on the PHY, effectively starting physical link.
458 **/
459 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
460 {
461 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
462
463 /* Enable tx laser; allow 100ms to light up */
464 esdp_reg &= ~IXGBE_ESDP_SDP3;
465 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
466 IXGBE_WRITE_FLUSH(hw);
467 msleep(100);
468 }
469
470 /**
471 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
472 * @hw: pointer to hardware structure
473 *
474 * When the driver changes the link speeds that it can support,
475 * it sets autotry_restart to true to indicate that we need to
476 * initiate a new autotry session with the link partner. To do
477 * so, we set the speed then disable and re-enable the tx laser, to
478 * alert the link partner that it also needs to restart autotry on its
479 * end. This is consistent with true clause 37 autoneg, which also
480 * involves a loss of signal.
481 **/
482 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
483 {
484 if (hw->mac.autotry_restart) {
485 ixgbe_disable_tx_laser_multispeed_fiber(hw);
486 ixgbe_enable_tx_laser_multispeed_fiber(hw);
487 hw->mac.autotry_restart = false;
488 }
489 }
490
491 /**
492 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
493 * @hw: pointer to hardware structure
494 * @speed: new link speed
495 * @autoneg: true if autonegotiation enabled
496 * @autoneg_wait_to_complete: true when waiting for completion is needed
497 *
498 * Set the link speed in the AUTOC register and restarts link.
499 **/
500 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
501 ixgbe_link_speed speed,
502 bool autoneg,
503 bool autoneg_wait_to_complete)
504 {
505 s32 status = 0;
506 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
507 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
508 u32 speedcnt = 0;
509 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
510 u32 i = 0;
511 bool link_up = false;
512 bool negotiation;
513
514 /* Mask off requested but non-supported speeds */
515 status = hw->mac.ops.get_link_capabilities(hw, &link_speed,
516 &negotiation);
517 if (status != 0)
518 return status;
519
520 speed &= link_speed;
521
522 /*
523 * Try each speed one by one, highest priority first. We do this in
524 * software because 10gb fiber doesn't support speed autonegotiation.
525 */
526 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
527 speedcnt++;
528 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
529
530 /* If we already have link at this speed, just jump out */
531 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
532 false);
533 if (status != 0)
534 return status;
535
536 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
537 goto out;
538
539 /* Set the module link speed */
540 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
541 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
542 IXGBE_WRITE_FLUSH(hw);
543
544 /* Allow module to change analog characteristics (1G->10G) */
545 msleep(40);
546
547 status = ixgbe_setup_mac_link_82599(hw,
548 IXGBE_LINK_SPEED_10GB_FULL,
549 autoneg,
550 autoneg_wait_to_complete);
551 if (status != 0)
552 return status;
553
554 /* Flap the tx laser if it has not already been done */
555 hw->mac.ops.flap_tx_laser(hw);
556
557 /*
558 * Wait for the controller to acquire link. Per IEEE 802.3ap,
559 * Section 73.10.2, we may have to wait up to 500ms if KR is
560 * attempted. 82599 uses the same timing for 10g SFI.
561 */
562 for (i = 0; i < 5; i++) {
563 /* Wait for the link partner to also set speed */
564 msleep(100);
565
566 /* If we have link, just jump out */
567 status = hw->mac.ops.check_link(hw, &link_speed,
568 &link_up, false);
569 if (status != 0)
570 return status;
571
572 if (link_up)
573 goto out;
574 }
575 }
576
577 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
578 speedcnt++;
579 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
580 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
581
582 /* If we already have link at this speed, just jump out */
583 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
584 false);
585 if (status != 0)
586 return status;
587
588 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
589 goto out;
590
591 /* Set the module link speed */
592 esdp_reg &= ~IXGBE_ESDP_SDP5;
593 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
594 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
595 IXGBE_WRITE_FLUSH(hw);
596
597 /* Allow module to change analog characteristics (10G->1G) */
598 msleep(40);
599
600 status = ixgbe_setup_mac_link_82599(hw,
601 IXGBE_LINK_SPEED_1GB_FULL,
602 autoneg,
603 autoneg_wait_to_complete);
604 if (status != 0)
605 return status;
606
607 /* Flap the tx laser if it has not already been done */
608 hw->mac.ops.flap_tx_laser(hw);
609
610 /* Wait for the link partner to also set speed */
611 msleep(100);
612
613 /* If we have link, just jump out */
614 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
615 false);
616 if (status != 0)
617 return status;
618
619 if (link_up)
620 goto out;
621 }
622
623 /*
624 * We didn't get link. Configure back to the highest speed we tried,
625 * (if there was more than one). We call ourselves back with just the
626 * single highest speed that the user requested.
627 */
628 if (speedcnt > 1)
629 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
630 highest_link_speed,
631 autoneg,
632 autoneg_wait_to_complete);
633
634 out:
635 /* Set autoneg_advertised value based on input link speed */
636 hw->phy.autoneg_advertised = 0;
637
638 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
639 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
640
641 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
642 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
643
644 return status;
645 }
646
647 /**
648 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
649 * @hw: pointer to hardware structure
650 * @speed: new link speed
651 * @autoneg: true if autonegotiation enabled
652 * @autoneg_wait_to_complete: true when waiting for completion is needed
653 *
654 * Implements the Intel SmartSpeed algorithm.
655 **/
656 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
657 ixgbe_link_speed speed, bool autoneg,
658 bool autoneg_wait_to_complete)
659 {
660 s32 status = 0;
661 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
662 s32 i, j;
663 bool link_up = false;
664 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
665
666 /* Set autoneg_advertised value based on input link speed */
667 hw->phy.autoneg_advertised = 0;
668
669 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
670 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
671
672 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
673 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
674
675 if (speed & IXGBE_LINK_SPEED_100_FULL)
676 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
677
678 /*
679 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
680 * autoneg advertisement if link is unable to be established at the
681 * highest negotiated rate. This can sometimes happen due to integrity
682 * issues with the physical media connection.
683 */
684
685 /* First, try to get link with full advertisement */
686 hw->phy.smart_speed_active = false;
687 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
688 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
689 autoneg_wait_to_complete);
690 if (status != 0)
691 goto out;
692
693 /*
694 * Wait for the controller to acquire link. Per IEEE 802.3ap,
695 * Section 73.10.2, we may have to wait up to 500ms if KR is
696 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
697 * Table 9 in the AN MAS.
698 */
699 for (i = 0; i < 5; i++) {
700 mdelay(100);
701
702 /* If we have link, just jump out */
703 status = hw->mac.ops.check_link(hw, &link_speed,
704 &link_up, false);
705 if (status != 0)
706 goto out;
707
708 if (link_up)
709 goto out;
710 }
711 }
712
713 /*
714 * We didn't get link. If we advertised KR plus one of KX4/KX
715 * (or BX4/BX), then disable KR and try again.
716 */
717 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
718 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
719 goto out;
720
721 /* Turn SmartSpeed on to disable KR support */
722 hw->phy.smart_speed_active = true;
723 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
724 autoneg_wait_to_complete);
725 if (status != 0)
726 goto out;
727
728 /*
729 * Wait for the controller to acquire link. 600ms will allow for
730 * the AN link_fail_inhibit_timer as well for multiple cycles of
731 * parallel detect, both 10g and 1g. This allows for the maximum
732 * connect attempts as defined in the AN MAS table 73-7.
733 */
734 for (i = 0; i < 6; i++) {
735 mdelay(100);
736
737 /* If we have link, just jump out */
738 status = hw->mac.ops.check_link(hw, &link_speed,
739 &link_up, false);
740 if (status != 0)
741 goto out;
742
743 if (link_up)
744 goto out;
745 }
746
747 /* We didn't get link. Turn SmartSpeed back off. */
748 hw->phy.smart_speed_active = false;
749 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
750 autoneg_wait_to_complete);
751
752 out:
753 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
754 hw_dbg(hw, "Smartspeed has downgraded the link speed from "
755 "the maximum advertised\n");
756 return status;
757 }
758
759 /**
760 * ixgbe_setup_mac_link_82599 - Set MAC link speed
761 * @hw: pointer to hardware structure
762 * @speed: new link speed
763 * @autoneg: true if autonegotiation enabled
764 * @autoneg_wait_to_complete: true when waiting for completion is needed
765 *
766 * Set the link speed in the AUTOC register and restarts link.
767 **/
768 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
769 ixgbe_link_speed speed, bool autoneg,
770 bool autoneg_wait_to_complete)
771 {
772 s32 status = 0;
773 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
774 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
775 u32 start_autoc = autoc;
776 u32 orig_autoc = 0;
777 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
778 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
779 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
780 u32 links_reg;
781 u32 i;
782 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
783
784 /* Check to see if speed passed in is supported. */
785 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
786 if (status != 0)
787 goto out;
788
789 speed &= link_capabilities;
790
791 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
792 status = IXGBE_ERR_LINK_SETUP;
793 goto out;
794 }
795
796 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
797 if (hw->mac.orig_link_settings_stored)
798 orig_autoc = hw->mac.orig_autoc;
799 else
800 orig_autoc = autoc;
801
802 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
803 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
804 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
805 /* Set KX4/KX/KR support according to speed requested */
806 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
807 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
808 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
809 autoc |= IXGBE_AUTOC_KX4_SUPP;
810 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
811 (hw->phy.smart_speed_active == false))
812 autoc |= IXGBE_AUTOC_KR_SUPP;
813 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
814 autoc |= IXGBE_AUTOC_KX_SUPP;
815 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
816 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
817 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
818 /* Switch from 1G SFI to 10G SFI if requested */
819 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
820 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
821 autoc &= ~IXGBE_AUTOC_LMS_MASK;
822 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
823 }
824 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
825 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
826 /* Switch from 10G SFI to 1G SFI if requested */
827 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
828 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
829 autoc &= ~IXGBE_AUTOC_LMS_MASK;
830 if (autoneg)
831 autoc |= IXGBE_AUTOC_LMS_1G_AN;
832 else
833 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
834 }
835 }
836
837 if (autoc != start_autoc) {
838 /* Restart link */
839 autoc |= IXGBE_AUTOC_AN_RESTART;
840 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
841
842 /* Only poll for autoneg to complete if specified to do so */
843 if (autoneg_wait_to_complete) {
844 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
845 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
846 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
847 links_reg = 0; /*Just in case Autoneg time=0*/
848 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
849 links_reg =
850 IXGBE_READ_REG(hw, IXGBE_LINKS);
851 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
852 break;
853 msleep(100);
854 }
855 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
856 status =
857 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
858 hw_dbg(hw, "Autoneg did not "
859 "complete.\n");
860 }
861 }
862 }
863
864 /* Add delay to filter out noises during initial link setup */
865 msleep(50);
866 }
867
868 out:
869 return status;
870 }
871
872 /**
873 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
874 * @hw: pointer to hardware structure
875 * @speed: new link speed
876 * @autoneg: true if autonegotiation enabled
877 * @autoneg_wait_to_complete: true if waiting is needed to complete
878 *
879 * Restarts link on PHY and MAC based on settings passed in.
880 **/
881 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
882 ixgbe_link_speed speed,
883 bool autoneg,
884 bool autoneg_wait_to_complete)
885 {
886 s32 status;
887
888 /* Setup the PHY according to input speed */
889 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
890 autoneg_wait_to_complete);
891 /* Set up MAC */
892 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
893
894 return status;
895 }
896
897 /**
898 * ixgbe_reset_hw_82599 - Perform hardware reset
899 * @hw: pointer to hardware structure
900 *
901 * Resets the hardware by resetting the transmit and receive units, masks
902 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
903 * reset.
904 **/
905 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
906 {
907 s32 status = 0;
908 u32 ctrl;
909 u32 i;
910 u32 autoc;
911 u32 autoc2;
912
913 /* Call adapter stop to disable tx/rx and clear interrupts */
914 hw->mac.ops.stop_adapter(hw);
915
916 /* PHY ops must be identified and initialized prior to reset */
917
918 /* Identify PHY and related function pointers */
919 status = hw->phy.ops.init(hw);
920
921 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
922 goto reset_hw_out;
923
924 /* Setup SFP module if there is one present. */
925 if (hw->phy.sfp_setup_needed) {
926 status = hw->mac.ops.setup_sfp(hw);
927 hw->phy.sfp_setup_needed = false;
928 }
929
930 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
931 goto reset_hw_out;
932
933 /* Reset PHY */
934 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
935 hw->phy.ops.reset(hw);
936
937 /*
938 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
939 * access and verify no pending requests before reset
940 */
941 ixgbe_disable_pcie_master(hw);
942
943 mac_reset_top:
944 /*
945 * Issue global reset to the MAC. This needs to be a SW reset.
946 * If link reset is used, it might reset the MAC when mng is using it
947 */
948 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
949 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
950 IXGBE_WRITE_FLUSH(hw);
951
952 /* Poll for reset bit to self-clear indicating reset is complete */
953 for (i = 0; i < 10; i++) {
954 udelay(1);
955 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
956 if (!(ctrl & IXGBE_CTRL_RST))
957 break;
958 }
959 if (ctrl & IXGBE_CTRL_RST) {
960 status = IXGBE_ERR_RESET_FAILED;
961 hw_dbg(hw, "Reset polling failed to complete.\n");
962 }
963
964 /*
965 * Double resets are required for recovery from certain error
966 * conditions. Between resets, it is necessary to stall to allow time
967 * for any pending HW events to complete. We use 1usec since that is
968 * what is needed for ixgbe_disable_pcie_master(). The second reset
969 * then clears out any effects of those events.
970 */
971 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
972 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
973 udelay(1);
974 goto mac_reset_top;
975 }
976
977 msleep(50);
978
979 /*
980 * Store the original AUTOC/AUTOC2 values if they have not been
981 * stored off yet. Otherwise restore the stored original
982 * values since the reset operation sets back to defaults.
983 */
984 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
985 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
986 if (hw->mac.orig_link_settings_stored == false) {
987 hw->mac.orig_autoc = autoc;
988 hw->mac.orig_autoc2 = autoc2;
989 hw->mac.orig_link_settings_stored = true;
990 } else {
991 if (autoc != hw->mac.orig_autoc)
992 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
993 IXGBE_AUTOC_AN_RESTART));
994
995 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
996 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
997 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
998 autoc2 |= (hw->mac.orig_autoc2 &
999 IXGBE_AUTOC2_UPPER_MASK);
1000 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1001 }
1002 }
1003
1004 /* Store the permanent mac address */
1005 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1006
1007 /*
1008 * Store MAC address from RAR0, clear receive address registers, and
1009 * clear the multicast table. Also reset num_rar_entries to 128,
1010 * since we modify this value when programming the SAN MAC address.
1011 */
1012 hw->mac.num_rar_entries = 128;
1013 hw->mac.ops.init_rx_addrs(hw);
1014
1015 /* Store the permanent SAN mac address */
1016 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1017
1018 /* Add the SAN MAC address to the RAR only if it's a valid address */
1019 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1020 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1021 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1022
1023 /* Reserve the last RAR for the SAN MAC address */
1024 hw->mac.num_rar_entries--;
1025 }
1026
1027 /* Store the alternative WWNN/WWPN prefix */
1028 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1029 &hw->mac.wwpn_prefix);
1030
1031 reset_hw_out:
1032 return status;
1033 }
1034
1035 /**
1036 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1037 * @hw: pointer to hardware structure
1038 **/
1039 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1040 {
1041 int i;
1042 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1043 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1044
1045 /*
1046 * Before starting reinitialization process,
1047 * FDIRCMD.CMD must be zero.
1048 */
1049 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1050 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1051 IXGBE_FDIRCMD_CMD_MASK))
1052 break;
1053 udelay(10);
1054 }
1055 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1056 hw_dbg(hw, "Flow Director previous command isn't complete, "
1057 "aborting table re-initialization.\n");
1058 return IXGBE_ERR_FDIR_REINIT_FAILED;
1059 }
1060
1061 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1062 IXGBE_WRITE_FLUSH(hw);
1063 /*
1064 * 82599 adapters flow director init flow cannot be restarted,
1065 * Workaround 82599 silicon errata by performing the following steps
1066 * before re-writing the FDIRCTRL control register with the same value.
1067 * - write 1 to bit 8 of FDIRCMD register &
1068 * - write 0 to bit 8 of FDIRCMD register
1069 */
1070 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1071 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1072 IXGBE_FDIRCMD_CLEARHT));
1073 IXGBE_WRITE_FLUSH(hw);
1074 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1075 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1076 ~IXGBE_FDIRCMD_CLEARHT));
1077 IXGBE_WRITE_FLUSH(hw);
1078 /*
1079 * Clear FDIR Hash register to clear any leftover hashes
1080 * waiting to be programmed.
1081 */
1082 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1083 IXGBE_WRITE_FLUSH(hw);
1084
1085 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1086 IXGBE_WRITE_FLUSH(hw);
1087
1088 /* Poll init-done after we write FDIRCTRL register */
1089 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1090 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1091 IXGBE_FDIRCTRL_INIT_DONE)
1092 break;
1093 udelay(10);
1094 }
1095 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1096 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1097 return IXGBE_ERR_FDIR_REINIT_FAILED;
1098 }
1099
1100 /* Clear FDIR statistics registers (read to clear) */
1101 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1102 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1103 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1104 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1105 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1106
1107 return 0;
1108 }
1109
1110 /**
1111 * ixgbe_set_fdir_rxpba_82599 - Initialize Flow Director Rx packet buffer
1112 * @hw: pointer to hardware structure
1113 * @pballoc: which mode to allocate filters with
1114 **/
1115 static s32 ixgbe_set_fdir_rxpba_82599(struct ixgbe_hw *hw, const u32 pballoc)
1116 {
1117 u32 fdir_pbsize = hw->mac.rx_pb_size << IXGBE_RXPBSIZE_SHIFT;
1118 u32 current_rxpbsize = 0;
1119 int i;
1120
1121 /* reserve space for Flow Director filters */
1122 switch (pballoc) {
1123 case IXGBE_FDIR_PBALLOC_256K:
1124 fdir_pbsize -= 256 << IXGBE_RXPBSIZE_SHIFT;
1125 break;
1126 case IXGBE_FDIR_PBALLOC_128K:
1127 fdir_pbsize -= 128 << IXGBE_RXPBSIZE_SHIFT;
1128 break;
1129 case IXGBE_FDIR_PBALLOC_64K:
1130 fdir_pbsize -= 64 << IXGBE_RXPBSIZE_SHIFT;
1131 break;
1132 case IXGBE_FDIR_PBALLOC_NONE:
1133 default:
1134 return IXGBE_ERR_PARAM;
1135 }
1136
1137 /* determine current RX packet buffer size */
1138 for (i = 0; i < 8; i++)
1139 current_rxpbsize += IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
1140
1141 /* if there is already room for the filters do nothing */
1142 if (current_rxpbsize <= fdir_pbsize)
1143 return 0;
1144
1145 if (current_rxpbsize > hw->mac.rx_pb_size) {
1146 /*
1147 * if rxpbsize is greater than max then HW max the Rx buffer
1148 * sizes are unconfigured or misconfigured since HW default is
1149 * to give the full buffer to each traffic class resulting in
1150 * the total size being buffer size 8x actual size
1151 *
1152 * This assumes no DCB since the RXPBSIZE registers appear to
1153 * be unconfigured.
1154 */
1155 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), fdir_pbsize);
1156 for (i = 1; i < 8; i++)
1157 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1158 } else {
1159 /*
1160 * Since the Rx packet buffer appears to have already been
1161 * configured we need to shrink each packet buffer by enough
1162 * to make room for the filters. As such we take each rxpbsize
1163 * value and multiply it by a fraction representing the size
1164 * needed over the size we currently have.
1165 *
1166 * We need to reduce fdir_pbsize and current_rxpbsize to
1167 * 1/1024 of their original values in order to avoid
1168 * overflowing the u32 being used to store rxpbsize.
1169 */
1170 fdir_pbsize >>= IXGBE_RXPBSIZE_SHIFT;
1171 current_rxpbsize >>= IXGBE_RXPBSIZE_SHIFT;
1172 for (i = 0; i < 8; i++) {
1173 u32 rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
1174 rxpbsize *= fdir_pbsize;
1175 rxpbsize /= current_rxpbsize;
1176 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
1177 }
1178 }
1179
1180 return 0;
1181 }
1182
1183 /**
1184 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1185 * @hw: pointer to hardware structure
1186 * @fdirctrl: value to write to flow director control register
1187 **/
1188 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1189 {
1190 int i;
1191
1192 /* Prime the keys for hashing */
1193 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1194 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1195
1196 /*
1197 * Poll init-done after we write the register. Estimated times:
1198 * 10G: PBALLOC = 11b, timing is 60us
1199 * 1G: PBALLOC = 11b, timing is 600us
1200 * 100M: PBALLOC = 11b, timing is 6ms
1201 *
1202 * Multiple these timings by 4 if under full Rx load
1203 *
1204 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1205 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1206 * this might not finish in our poll time, but we can live with that
1207 * for now.
1208 */
1209 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1210 IXGBE_WRITE_FLUSH(hw);
1211 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1212 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1213 IXGBE_FDIRCTRL_INIT_DONE)
1214 break;
1215 usleep_range(1000, 2000);
1216 }
1217
1218 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1219 hw_dbg(hw, "Flow Director poll time exceeded!\n");
1220 }
1221
1222 /**
1223 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1224 * @hw: pointer to hardware structure
1225 * @fdirctrl: value to write to flow director control register, initially
1226 * contains just the value of the Rx packet buffer allocation
1227 **/
1228 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1229 {
1230 s32 err;
1231
1232 /* Before enabling Flow Director, verify the Rx Packet Buffer size */
1233 err = ixgbe_set_fdir_rxpba_82599(hw, fdirctrl);
1234 if (err)
1235 return err;
1236
1237 /*
1238 * Continue setup of fdirctrl register bits:
1239 * Move the flexible bytes to use the ethertype - shift 6 words
1240 * Set the maximum length per hash bucket to 0xA filters
1241 * Send interrupt when 64 filters are left
1242 */
1243 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1244 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1245 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1246
1247 /* write hashes and fdirctrl register, poll for completion */
1248 ixgbe_fdir_enable_82599(hw, fdirctrl);
1249
1250 return 0;
1251 }
1252
1253 /**
1254 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1255 * @hw: pointer to hardware structure
1256 * @fdirctrl: value to write to flow director control register, initially
1257 * contains just the value of the Rx packet buffer allocation
1258 **/
1259 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1260 {
1261 s32 err;
1262
1263 /* Before enabling Flow Director, verify the Rx Packet Buffer size */
1264 err = ixgbe_set_fdir_rxpba_82599(hw, fdirctrl);
1265 if (err)
1266 return err;
1267
1268 /*
1269 * Continue setup of fdirctrl register bits:
1270 * Turn perfect match filtering on
1271 * Report hash in RSS field of Rx wb descriptor
1272 * Initialize the drop queue
1273 * Move the flexible bytes to use the ethertype - shift 6 words
1274 * Set the maximum length per hash bucket to 0xA filters
1275 * Send interrupt when 64 (0x4 * 16) filters are left
1276 */
1277 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1278 IXGBE_FDIRCTRL_REPORT_STATUS |
1279 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1280 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1281 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1282 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1283
1284 /* write hashes and fdirctrl register, poll for completion */
1285 ixgbe_fdir_enable_82599(hw, fdirctrl);
1286
1287 return 0;
1288 }
1289
1290 /*
1291 * These defines allow us to quickly generate all of the necessary instructions
1292 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1293 * for values 0 through 15
1294 */
1295 #define IXGBE_ATR_COMMON_HASH_KEY \
1296 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1297 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1298 do { \
1299 u32 n = (_n); \
1300 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1301 common_hash ^= lo_hash_dword >> n; \
1302 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1303 bucket_hash ^= lo_hash_dword >> n; \
1304 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1305 sig_hash ^= lo_hash_dword << (16 - n); \
1306 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1307 common_hash ^= hi_hash_dword >> n; \
1308 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1309 bucket_hash ^= hi_hash_dword >> n; \
1310 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1311 sig_hash ^= hi_hash_dword << (16 - n); \
1312 } while (0);
1313
1314 /**
1315 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1316 * @stream: input bitstream to compute the hash on
1317 *
1318 * This function is almost identical to the function above but contains
1319 * several optomizations such as unwinding all of the loops, letting the
1320 * compiler work out all of the conditional ifs since the keys are static
1321 * defines, and computing two keys at once since the hashed dword stream
1322 * will be the same for both keys.
1323 **/
1324 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1325 union ixgbe_atr_hash_dword common)
1326 {
1327 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1328 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1329
1330 /* record the flow_vm_vlan bits as they are a key part to the hash */
1331 flow_vm_vlan = ntohl(input.dword);
1332
1333 /* generate common hash dword */
1334 hi_hash_dword = ntohl(common.dword);
1335
1336 /* low dword is word swapped version of common */
1337 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1338
1339 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1340 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1341
1342 /* Process bits 0 and 16 */
1343 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1344
1345 /*
1346 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1347 * delay this because bit 0 of the stream should not be processed
1348 * so we do not add the vlan until after bit 0 was processed
1349 */
1350 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1351
1352 /* Process remaining 30 bit of the key */
1353 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1354 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1355 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1356 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1357 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1358 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1359 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1360 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1361 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1362 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1363 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1364 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1365 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1366 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1367 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1368
1369 /* combine common_hash result with signature and bucket hashes */
1370 bucket_hash ^= common_hash;
1371 bucket_hash &= IXGBE_ATR_HASH_MASK;
1372
1373 sig_hash ^= common_hash << 16;
1374 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1375
1376 /* return completed signature hash */
1377 return sig_hash ^ bucket_hash;
1378 }
1379
1380 /**
1381 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1382 * @hw: pointer to hardware structure
1383 * @input: unique input dword
1384 * @common: compressed common input dword
1385 * @queue: queue index to direct traffic to
1386 **/
1387 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1388 union ixgbe_atr_hash_dword input,
1389 union ixgbe_atr_hash_dword common,
1390 u8 queue)
1391 {
1392 u64 fdirhashcmd;
1393 u32 fdircmd;
1394
1395 /*
1396 * Get the flow_type in order to program FDIRCMD properly
1397 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1398 */
1399 switch (input.formatted.flow_type) {
1400 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1401 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1402 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1403 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1404 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1405 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1406 break;
1407 default:
1408 hw_dbg(hw, " Error on flow type input\n");
1409 return IXGBE_ERR_CONFIG;
1410 }
1411
1412 /* configure FDIRCMD register */
1413 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1414 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1415 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1416 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1417
1418 /*
1419 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1420 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1421 */
1422 fdirhashcmd = (u64)fdircmd << 32;
1423 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1424 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1425
1426 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1427
1428 return 0;
1429 }
1430
1431 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1432 do { \
1433 u32 n = (_n); \
1434 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1435 bucket_hash ^= lo_hash_dword >> n; \
1436 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1437 bucket_hash ^= hi_hash_dword >> n; \
1438 } while (0);
1439
1440 /**
1441 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1442 * @atr_input: input bitstream to compute the hash on
1443 * @input_mask: mask for the input bitstream
1444 *
1445 * This function serves two main purposes. First it applys the input_mask
1446 * to the atr_input resulting in a cleaned up atr_input data stream.
1447 * Secondly it computes the hash and stores it in the bkt_hash field at
1448 * the end of the input byte stream. This way it will be available for
1449 * future use without needing to recompute the hash.
1450 **/
1451 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1452 union ixgbe_atr_input *input_mask)
1453 {
1454
1455 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1456 u32 bucket_hash = 0;
1457
1458 /* Apply masks to input data */
1459 input->dword_stream[0] &= input_mask->dword_stream[0];
1460 input->dword_stream[1] &= input_mask->dword_stream[1];
1461 input->dword_stream[2] &= input_mask->dword_stream[2];
1462 input->dword_stream[3] &= input_mask->dword_stream[3];
1463 input->dword_stream[4] &= input_mask->dword_stream[4];
1464 input->dword_stream[5] &= input_mask->dword_stream[5];
1465 input->dword_stream[6] &= input_mask->dword_stream[6];
1466 input->dword_stream[7] &= input_mask->dword_stream[7];
1467 input->dword_stream[8] &= input_mask->dword_stream[8];
1468 input->dword_stream[9] &= input_mask->dword_stream[9];
1469 input->dword_stream[10] &= input_mask->dword_stream[10];
1470
1471 /* record the flow_vm_vlan bits as they are a key part to the hash */
1472 flow_vm_vlan = ntohl(input->dword_stream[0]);
1473
1474 /* generate common hash dword */
1475 hi_hash_dword = ntohl(input->dword_stream[1] ^
1476 input->dword_stream[2] ^
1477 input->dword_stream[3] ^
1478 input->dword_stream[4] ^
1479 input->dword_stream[5] ^
1480 input->dword_stream[6] ^
1481 input->dword_stream[7] ^
1482 input->dword_stream[8] ^
1483 input->dword_stream[9] ^
1484 input->dword_stream[10]);
1485
1486 /* low dword is word swapped version of common */
1487 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1488
1489 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1490 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1491
1492 /* Process bits 0 and 16 */
1493 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1494
1495 /*
1496 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1497 * delay this because bit 0 of the stream should not be processed
1498 * so we do not add the vlan until after bit 0 was processed
1499 */
1500 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1501
1502 /* Process remaining 30 bit of the key */
1503 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1504 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1505 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1506 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1507 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1508 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1509 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1510 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1511 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1512 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1513 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1514 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1515 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1516 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1517 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1518
1519 /*
1520 * Limit hash to 13 bits since max bucket count is 8K.
1521 * Store result at the end of the input stream.
1522 */
1523 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1524 }
1525
1526 /**
1527 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1528 * @input_mask: mask to be bit swapped
1529 *
1530 * The source and destination port masks for flow director are bit swapped
1531 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1532 * generate a correctly swapped value we need to bit swap the mask and that
1533 * is what is accomplished by this function.
1534 **/
1535 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1536 {
1537 u32 mask = ntohs(input_mask->formatted.dst_port);
1538 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1539 mask |= ntohs(input_mask->formatted.src_port);
1540 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1541 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1542 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1543 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1544 }
1545
1546 /*
1547 * These two macros are meant to address the fact that we have registers
1548 * that are either all or in part big-endian. As a result on big-endian
1549 * systems we will end up byte swapping the value to little-endian before
1550 * it is byte swapped again and written to the hardware in the original
1551 * big-endian format.
1552 */
1553 #define IXGBE_STORE_AS_BE32(_value) \
1554 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1555 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1556
1557 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1558 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1559
1560 #define IXGBE_STORE_AS_BE16(_value) \
1561 ntohs(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1562
1563 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1564 union ixgbe_atr_input *input_mask)
1565 {
1566 /* mask IPv6 since it is currently not supported */
1567 u32 fdirm = IXGBE_FDIRM_DIPv6;
1568 u32 fdirtcpm;
1569
1570 /*
1571 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1572 * are zero, then assume a full mask for that field. Also assume that
1573 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1574 * cannot be masked out in this implementation.
1575 *
1576 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1577 * point in time.
1578 */
1579
1580 /* verify bucket hash is cleared on hash generation */
1581 if (input_mask->formatted.bkt_hash)
1582 hw_dbg(hw, " bucket hash should always be 0 in mask\n");
1583
1584 /* Program FDIRM and verify partial masks */
1585 switch (input_mask->formatted.vm_pool & 0x7F) {
1586 case 0x0:
1587 fdirm |= IXGBE_FDIRM_POOL;
1588 case 0x7F:
1589 break;
1590 default:
1591 hw_dbg(hw, " Error on vm pool mask\n");
1592 return IXGBE_ERR_CONFIG;
1593 }
1594
1595 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1596 case 0x0:
1597 fdirm |= IXGBE_FDIRM_L4P;
1598 if (input_mask->formatted.dst_port ||
1599 input_mask->formatted.src_port) {
1600 hw_dbg(hw, " Error on src/dst port mask\n");
1601 return IXGBE_ERR_CONFIG;
1602 }
1603 case IXGBE_ATR_L4TYPE_MASK:
1604 break;
1605 default:
1606 hw_dbg(hw, " Error on flow type mask\n");
1607 return IXGBE_ERR_CONFIG;
1608 }
1609
1610 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) {
1611 case 0x0000:
1612 /* mask VLAN ID, fall through to mask VLAN priority */
1613 fdirm |= IXGBE_FDIRM_VLANID;
1614 case 0x0FFF:
1615 /* mask VLAN priority */
1616 fdirm |= IXGBE_FDIRM_VLANP;
1617 break;
1618 case 0xE000:
1619 /* mask VLAN ID only, fall through */
1620 fdirm |= IXGBE_FDIRM_VLANID;
1621 case 0xEFFF:
1622 /* no VLAN fields masked */
1623 break;
1624 default:
1625 hw_dbg(hw, " Error on VLAN mask\n");
1626 return IXGBE_ERR_CONFIG;
1627 }
1628
1629 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1630 case 0x0000:
1631 /* Mask Flex Bytes, fall through */
1632 fdirm |= IXGBE_FDIRM_FLEX;
1633 case 0xFFFF:
1634 break;
1635 default:
1636 hw_dbg(hw, " Error on flexible byte mask\n");
1637 return IXGBE_ERR_CONFIG;
1638 }
1639
1640 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1641 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1642
1643 /* store the TCP/UDP port masks, bit reversed from port layout */
1644 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1645
1646 /* write both the same so that UDP and TCP use the same mask */
1647 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1648 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1649
1650 /* store source and destination IP masks (big-enian) */
1651 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1652 ~input_mask->formatted.src_ip[0]);
1653 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1654 ~input_mask->formatted.dst_ip[0]);
1655
1656 return 0;
1657 }
1658
1659 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1660 union ixgbe_atr_input *input,
1661 u16 soft_id, u8 queue)
1662 {
1663 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1664
1665 /* currently IPv6 is not supported, must be programmed with 0 */
1666 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1667 input->formatted.src_ip[0]);
1668 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1669 input->formatted.src_ip[1]);
1670 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1671 input->formatted.src_ip[2]);
1672
1673 /* record the source address (big-endian) */
1674 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1675
1676 /* record the first 32 bits of the destination address (big-endian) */
1677 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1678
1679 /* record source and destination port (little-endian)*/
1680 fdirport = ntohs(input->formatted.dst_port);
1681 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1682 fdirport |= ntohs(input->formatted.src_port);
1683 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1684
1685 /* record vlan (little-endian) and flex_bytes(big-endian) */
1686 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1687 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1688 fdirvlan |= ntohs(input->formatted.vlan_id);
1689 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1690
1691 /* configure FDIRHASH register */
1692 fdirhash = input->formatted.bkt_hash;
1693 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1694 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1695
1696 /*
1697 * flush all previous writes to make certain registers are
1698 * programmed prior to issuing the command
1699 */
1700 IXGBE_WRITE_FLUSH(hw);
1701
1702 /* configure FDIRCMD register */
1703 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1704 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1705 if (queue == IXGBE_FDIR_DROP_QUEUE)
1706 fdircmd |= IXGBE_FDIRCMD_DROP;
1707 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1708 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1709 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1710
1711 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1712
1713 return 0;
1714 }
1715
1716 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1717 union ixgbe_atr_input *input,
1718 u16 soft_id)
1719 {
1720 u32 fdirhash;
1721 u32 fdircmd = 0;
1722 u32 retry_count;
1723 s32 err = 0;
1724
1725 /* configure FDIRHASH register */
1726 fdirhash = input->formatted.bkt_hash;
1727 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1728 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1729
1730 /* flush hash to HW */
1731 IXGBE_WRITE_FLUSH(hw);
1732
1733 /* Query if filter is present */
1734 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1735
1736 for (retry_count = 10; retry_count; retry_count--) {
1737 /* allow 10us for query to process */
1738 udelay(10);
1739 /* verify query completed successfully */
1740 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1741 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1742 break;
1743 }
1744
1745 if (!retry_count)
1746 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1747
1748 /* if filter exists in hardware then remove it */
1749 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1750 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1751 IXGBE_WRITE_FLUSH(hw);
1752 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1753 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1754 }
1755
1756 return err;
1757 }
1758
1759 /**
1760 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1761 * @hw: pointer to hardware structure
1762 * @reg: analog register to read
1763 * @val: read value
1764 *
1765 * Performs read operation to Omer analog register specified.
1766 **/
1767 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1768 {
1769 u32 core_ctl;
1770
1771 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1772 (reg << 8));
1773 IXGBE_WRITE_FLUSH(hw);
1774 udelay(10);
1775 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1776 *val = (u8)core_ctl;
1777
1778 return 0;
1779 }
1780
1781 /**
1782 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1783 * @hw: pointer to hardware structure
1784 * @reg: atlas register to write
1785 * @val: value to write
1786 *
1787 * Performs write operation to Omer analog register specified.
1788 **/
1789 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1790 {
1791 u32 core_ctl;
1792
1793 core_ctl = (reg << 8) | val;
1794 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1795 IXGBE_WRITE_FLUSH(hw);
1796 udelay(10);
1797
1798 return 0;
1799 }
1800
1801 /**
1802 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1803 * @hw: pointer to hardware structure
1804 *
1805 * Starts the hardware using the generic start_hw function
1806 * and the generation start_hw function.
1807 * Then performs revision-specific operations, if any.
1808 **/
1809 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1810 {
1811 s32 ret_val = 0;
1812
1813 ret_val = ixgbe_start_hw_generic(hw);
1814 if (ret_val != 0)
1815 goto out;
1816
1817 ret_val = ixgbe_start_hw_gen2(hw);
1818 if (ret_val != 0)
1819 goto out;
1820
1821 /* We need to run link autotry after the driver loads */
1822 hw->mac.autotry_restart = true;
1823 hw->mac.rx_pb_size = IXGBE_82599_RX_PB_SIZE;
1824
1825 if (ret_val == 0)
1826 ret_val = ixgbe_verify_fw_version_82599(hw);
1827 out:
1828 return ret_val;
1829 }
1830
1831 /**
1832 * ixgbe_identify_phy_82599 - Get physical layer module
1833 * @hw: pointer to hardware structure
1834 *
1835 * Determines the physical layer module found on the current adapter.
1836 * If PHY already detected, maintains current PHY type in hw struct,
1837 * otherwise executes the PHY detection routine.
1838 **/
1839 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1840 {
1841 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1842
1843 /* Detect PHY if not unknown - returns success if already detected. */
1844 status = ixgbe_identify_phy_generic(hw);
1845 if (status != 0) {
1846 /* 82599 10GBASE-T requires an external PHY */
1847 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1848 goto out;
1849 else
1850 status = ixgbe_identify_sfp_module_generic(hw);
1851 }
1852
1853 /* Set PHY type none if no PHY detected */
1854 if (hw->phy.type == ixgbe_phy_unknown) {
1855 hw->phy.type = ixgbe_phy_none;
1856 status = 0;
1857 }
1858
1859 /* Return error if SFP module has been detected but is not supported */
1860 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1861 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1862
1863 out:
1864 return status;
1865 }
1866
1867 /**
1868 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1869 * @hw: pointer to hardware structure
1870 *
1871 * Determines physical layer capabilities of the current configuration.
1872 **/
1873 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1874 {
1875 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1876 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1877 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1878 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1879 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1880 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1881 u16 ext_ability = 0;
1882 u8 comp_codes_10g = 0;
1883 u8 comp_codes_1g = 0;
1884
1885 hw->phy.ops.identify(hw);
1886
1887 switch (hw->phy.type) {
1888 case ixgbe_phy_tn:
1889 case ixgbe_phy_aq:
1890 case ixgbe_phy_cu_unknown:
1891 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1892 &ext_ability);
1893 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1894 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1895 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1896 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1897 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1898 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1899 goto out;
1900 default:
1901 break;
1902 }
1903
1904 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1905 case IXGBE_AUTOC_LMS_1G_AN:
1906 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1907 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1908 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1909 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1910 goto out;
1911 } else
1912 /* SFI mode so read SFP module */
1913 goto sfp_check;
1914 break;
1915 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1916 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1917 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1918 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1919 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1920 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1921 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
1922 goto out;
1923 break;
1924 case IXGBE_AUTOC_LMS_10G_SERIAL:
1925 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1926 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1927 goto out;
1928 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1929 goto sfp_check;
1930 break;
1931 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1932 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1933 if (autoc & IXGBE_AUTOC_KX_SUPP)
1934 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1935 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1936 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1937 if (autoc & IXGBE_AUTOC_KR_SUPP)
1938 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1939 goto out;
1940 break;
1941 default:
1942 goto out;
1943 break;
1944 }
1945
1946 sfp_check:
1947 /* SFP check must be done last since DA modules are sometimes used to
1948 * test KR mode - we need to id KR mode correctly before SFP module.
1949 * Call identify_sfp because the pluggable module may have changed */
1950 hw->phy.ops.identify_sfp(hw);
1951 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1952 goto out;
1953
1954 switch (hw->phy.type) {
1955 case ixgbe_phy_sfp_passive_tyco:
1956 case ixgbe_phy_sfp_passive_unknown:
1957 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1958 break;
1959 case ixgbe_phy_sfp_ftl_active:
1960 case ixgbe_phy_sfp_active_unknown:
1961 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1962 break;
1963 case ixgbe_phy_sfp_avago:
1964 case ixgbe_phy_sfp_ftl:
1965 case ixgbe_phy_sfp_intel:
1966 case ixgbe_phy_sfp_unknown:
1967 hw->phy.ops.read_i2c_eeprom(hw,
1968 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1969 hw->phy.ops.read_i2c_eeprom(hw,
1970 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1971 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1972 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1973 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1974 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1975 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1976 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1977 break;
1978 default:
1979 break;
1980 }
1981
1982 out:
1983 return physical_layer;
1984 }
1985
1986 /**
1987 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1988 * @hw: pointer to hardware structure
1989 * @regval: register value to write to RXCTRL
1990 *
1991 * Enables the Rx DMA unit for 82599
1992 **/
1993 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1994 {
1995 #define IXGBE_MAX_SECRX_POLL 30
1996 int i;
1997 int secrxreg;
1998
1999 /*
2000 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2001 * If traffic is incoming before we enable the Rx unit, it could hang
2002 * the Rx DMA unit. Therefore, make sure the security engine is
2003 * completely disabled prior to enabling the Rx unit.
2004 */
2005 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2006 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2007 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2008 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2009 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2010 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2011 break;
2012 else
2013 /* Use interrupt-safe sleep just in case */
2014 udelay(10);
2015 }
2016
2017 /* For informational purposes only */
2018 if (i >= IXGBE_MAX_SECRX_POLL)
2019 hw_dbg(hw, "Rx unit being enabled before security "
2020 "path fully disabled. Continuing with init.\n");
2021
2022 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2023 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2024 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2025 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2026 IXGBE_WRITE_FLUSH(hw);
2027
2028 return 0;
2029 }
2030
2031 /**
2032 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2033 * @hw: pointer to hardware structure
2034 *
2035 * Verifies that installed the firmware version is 0.6 or higher
2036 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2037 *
2038 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2039 * if the FW version is not supported.
2040 **/
2041 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2042 {
2043 s32 status = IXGBE_ERR_EEPROM_VERSION;
2044 u16 fw_offset, fw_ptp_cfg_offset;
2045 u16 fw_version = 0;
2046
2047 /* firmware check is only necessary for SFI devices */
2048 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2049 status = 0;
2050 goto fw_version_out;
2051 }
2052
2053 /* get the offset to the Firmware Module block */
2054 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2055
2056 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2057 goto fw_version_out;
2058
2059 /* get the offset to the Pass Through Patch Configuration block */
2060 hw->eeprom.ops.read(hw, (fw_offset +
2061 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2062 &fw_ptp_cfg_offset);
2063
2064 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2065 goto fw_version_out;
2066
2067 /* get the firmware version */
2068 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2069 IXGBE_FW_PATCH_VERSION_4),
2070 &fw_version);
2071
2072 if (fw_version > 0x5)
2073 status = 0;
2074
2075 fw_version_out:
2076 return status;
2077 }
2078
2079 /**
2080 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2081 * @hw: pointer to hardware structure
2082 *
2083 * Returns true if the LESM FW module is present and enabled. Otherwise
2084 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2085 **/
2086 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2087 {
2088 bool lesm_enabled = false;
2089 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2090 s32 status;
2091
2092 /* get the offset to the Firmware Module block */
2093 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2094
2095 if ((status != 0) ||
2096 (fw_offset == 0) || (fw_offset == 0xFFFF))
2097 goto out;
2098
2099 /* get the offset to the LESM Parameters block */
2100 status = hw->eeprom.ops.read(hw, (fw_offset +
2101 IXGBE_FW_LESM_PARAMETERS_PTR),
2102 &fw_lesm_param_offset);
2103
2104 if ((status != 0) ||
2105 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2106 goto out;
2107
2108 /* get the lesm state word */
2109 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2110 IXGBE_FW_LESM_STATE_1),
2111 &fw_lesm_state);
2112
2113 if ((status == 0) &&
2114 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2115 lesm_enabled = true;
2116
2117 out:
2118 return lesm_enabled;
2119 }
2120
2121 /**
2122 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2123 * fastest available method
2124 *
2125 * @hw: pointer to hardware structure
2126 * @offset: offset of word in EEPROM to read
2127 * @words: number of words
2128 * @data: word(s) read from the EEPROM
2129 *
2130 * Retrieves 16 bit word(s) read from EEPROM
2131 **/
2132 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2133 u16 words, u16 *data)
2134 {
2135 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2136 s32 ret_val = IXGBE_ERR_CONFIG;
2137
2138 /*
2139 * If EEPROM is detected and can be addressed using 14 bits,
2140 * use EERD otherwise use bit bang
2141 */
2142 if ((eeprom->type == ixgbe_eeprom_spi) &&
2143 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2144 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2145 data);
2146 else
2147 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2148 words,
2149 data);
2150
2151 return ret_val;
2152 }
2153
2154 /**
2155 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2156 * fastest available method
2157 *
2158 * @hw: pointer to hardware structure
2159 * @offset: offset of word in the EEPROM to read
2160 * @data: word read from the EEPROM
2161 *
2162 * Reads a 16 bit word from the EEPROM
2163 **/
2164 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2165 u16 offset, u16 *data)
2166 {
2167 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2168 s32 ret_val = IXGBE_ERR_CONFIG;
2169
2170 /*
2171 * If EEPROM is detected and can be addressed using 14 bits,
2172 * use EERD otherwise use bit bang
2173 */
2174 if ((eeprom->type == ixgbe_eeprom_spi) &&
2175 (offset <= IXGBE_EERD_MAX_ADDR))
2176 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2177 else
2178 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2179
2180 return ret_val;
2181 }
2182
2183 static struct ixgbe_mac_operations mac_ops_82599 = {
2184 .init_hw = &ixgbe_init_hw_generic,
2185 .reset_hw = &ixgbe_reset_hw_82599,
2186 .start_hw = &ixgbe_start_hw_82599,
2187 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2188 .get_media_type = &ixgbe_get_media_type_82599,
2189 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2190 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2191 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2192 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
2193 .get_device_caps = &ixgbe_get_device_caps_generic,
2194 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
2195 .stop_adapter = &ixgbe_stop_adapter_generic,
2196 .get_bus_info = &ixgbe_get_bus_info_generic,
2197 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2198 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2199 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2200 .setup_link = &ixgbe_setup_mac_link_82599,
2201 .set_rxpba = &ixgbe_set_rxpba_generic,
2202 .check_link = &ixgbe_check_mac_link_generic,
2203 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2204 .led_on = &ixgbe_led_on_generic,
2205 .led_off = &ixgbe_led_off_generic,
2206 .blink_led_start = &ixgbe_blink_led_start_generic,
2207 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2208 .set_rar = &ixgbe_set_rar_generic,
2209 .clear_rar = &ixgbe_clear_rar_generic,
2210 .set_vmdq = &ixgbe_set_vmdq_generic,
2211 .clear_vmdq = &ixgbe_clear_vmdq_generic,
2212 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2213 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2214 .enable_mc = &ixgbe_enable_mc_generic,
2215 .disable_mc = &ixgbe_disable_mc_generic,
2216 .clear_vfta = &ixgbe_clear_vfta_generic,
2217 .set_vfta = &ixgbe_set_vfta_generic,
2218 .fc_enable = &ixgbe_fc_enable_generic,
2219 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
2220 .init_uta_tables = &ixgbe_init_uta_tables_generic,
2221 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2222 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
2223 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
2224 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
2225 .release_swfw_sync = &ixgbe_release_swfw_sync,
2226
2227 };
2228
2229 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2230 .init_params = &ixgbe_init_eeprom_params_generic,
2231 .read = &ixgbe_read_eeprom_82599,
2232 .read_buffer = &ixgbe_read_eeprom_buffer_82599,
2233 .write = &ixgbe_write_eeprom_generic,
2234 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
2235 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2236 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2237 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2238 };
2239
2240 static struct ixgbe_phy_operations phy_ops_82599 = {
2241 .identify = &ixgbe_identify_phy_82599,
2242 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2243 .init = &ixgbe_init_phy_ops_82599,
2244 .reset = &ixgbe_reset_phy_generic,
2245 .read_reg = &ixgbe_read_phy_reg_generic,
2246 .write_reg = &ixgbe_write_phy_reg_generic,
2247 .setup_link = &ixgbe_setup_phy_link_generic,
2248 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2249 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2250 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2251 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2252 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2253 .check_overtemp = &ixgbe_tn_check_overtemp,
2254 };
2255
2256 struct ixgbe_info ixgbe_82599_info = {
2257 .mac = ixgbe_mac_82599EB,
2258 .get_invariants = &ixgbe_get_invariants_82599,
2259 .mac_ops = &mac_ops_82599,
2260 .eeprom_ops = &eeprom_ops_82599,
2261 .phy_ops = &phy_ops_82599,
2262 .mbx_ops = &mbx_ops_generic,
2263 };