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Staging: hv: mousevsc: Cleanup and properly implement reportdesc_callback()
[zen-stable.git] / drivers / net / mlx4 / fw.c
blob7eb8ba822e9724354a843eeb6610fbc027fdcfd6
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/mlx4/cmd.h>
36 #include <linux/cache.h>
37
38 #include "fw.h"
39 #include "icm.h"
40
41 enum {
42 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
43 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
44 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
45 };
46
47 extern void __buggy_use_of_MLX4_GET(void);
48 extern void __buggy_use_of_MLX4_PUT(void);
49
50 static int enable_qos;
51 module_param(enable_qos, bool, 0444);
52 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
53
54 #define MLX4_GET(dest, source, offset) \
55 do { \
56 void *__p = (char *) (source) + (offset); \
57 switch (sizeof (dest)) { \
58 case 1: (dest) = *(u8 *) __p; break; \
59 case 2: (dest) = be16_to_cpup(__p); break; \
60 case 4: (dest) = be32_to_cpup(__p); break; \
61 case 8: (dest) = be64_to_cpup(__p); break; \
62 default: __buggy_use_of_MLX4_GET(); \
63 } \
64 } while (0)
65
66 #define MLX4_PUT(dest, source, offset) \
67 do { \
68 void *__d = ((char *) (dest) + (offset)); \
69 switch (sizeof(source)) { \
70 case 1: *(u8 *) __d = (source); break; \
71 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
72 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
73 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
74 default: __buggy_use_of_MLX4_PUT(); \
75 } \
76 } while (0)
77
78 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
79 {
80 static const char *fname[] = {
81 [ 0] = "RC transport",
82 [ 1] = "UC transport",
83 [ 2] = "UD transport",
84 [ 3] = "XRC transport",
85 [ 4] = "reliable multicast",
86 [ 5] = "FCoIB support",
87 [ 6] = "SRQ support",
88 [ 7] = "IPoIB checksum offload",
89 [ 8] = "P_Key violation counter",
90 [ 9] = "Q_Key violation counter",
91 [10] = "VMM",
92 [12] = "DPDP",
93 [15] = "Big LSO headers",
94 [16] = "MW support",
95 [17] = "APM support",
96 [18] = "Atomic ops support",
97 [19] = "Raw multicast support",
98 [20] = "Address vector port checking support",
99 [21] = "UD multicast support",
100 [24] = "Demand paging support",
101 [25] = "Router support",
102 [30] = "IBoE support",
103 [32] = "Unicast loopback support",
104 [38] = "Wake On LAN support",
105 [40] = "UDP RSS support",
106 [41] = "Unicast VEP steering support",
107 [42] = "Multicast VEP steering support",
108 [48] = "Counters support",
109 };
110 int i;
111
112 mlx4_dbg(dev, "DEV_CAP flags:\n");
113 for (i = 0; i < ARRAY_SIZE(fname); ++i)
114 if (fname[i] && (flags & (1LL << i)))
115 mlx4_dbg(dev, " %s\n", fname[i]);
116 }
117
118 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
119 {
120 struct mlx4_cmd_mailbox *mailbox;
121 u32 *inbox;
122 int err = 0;
123
124 #define MOD_STAT_CFG_IN_SIZE 0x100
125
126 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
127 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
128
129 mailbox = mlx4_alloc_cmd_mailbox(dev);
130 if (IS_ERR(mailbox))
131 return PTR_ERR(mailbox);
132 inbox = mailbox->buf;
133
134 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
135
136 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
137 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
138
139 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
140 MLX4_CMD_TIME_CLASS_A);
141
142 mlx4_free_cmd_mailbox(dev, mailbox);
143 return err;
144 }
145
146 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
147 {
148 struct mlx4_cmd_mailbox *mailbox;
149 u32 *outbox;
150 u8 field;
151 u32 field32, flags, ext_flags;
152 u16 size;
153 u16 stat_rate;
154 int err;
155 int i;
156
157 #define QUERY_DEV_CAP_OUT_SIZE 0x100
158 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
159 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
160 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
161 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
162 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
163 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
164 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
165 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
166 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
167 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
168 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
169 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
170 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
171 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
172 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
173 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
174 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
175 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
176 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
177 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
178 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
179 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
180 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
181 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
182 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
183 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
184 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
185 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
186 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
187 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
188 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
189 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
190 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
191 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
192 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
193 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
194 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
195 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
196 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
197 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
198 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
199 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
200 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
201 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
202 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
203 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
204 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
205 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
206 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
207 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
208 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
209 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
210 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
211 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
212 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
213 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
214 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
215 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
216 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
217 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
218 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
219 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
220 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
221
222 mailbox = mlx4_alloc_cmd_mailbox(dev);
223 if (IS_ERR(mailbox))
224 return PTR_ERR(mailbox);
225 outbox = mailbox->buf;
226
227 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
228 MLX4_CMD_TIME_CLASS_A);
229 if (err)
230 goto out;
231
232 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
233 dev_cap->reserved_qps = 1 << (field & 0xf);
234 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
235 dev_cap->max_qps = 1 << (field & 0x1f);
236 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
237 dev_cap->reserved_srqs = 1 << (field >> 4);
238 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
239 dev_cap->max_srqs = 1 << (field & 0x1f);
240 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
241 dev_cap->max_cq_sz = 1 << field;
242 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
243 dev_cap->reserved_cqs = 1 << (field & 0xf);
244 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
245 dev_cap->max_cqs = 1 << (field & 0x1f);
246 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
247 dev_cap->max_mpts = 1 << (field & 0x3f);
248 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
249 dev_cap->reserved_eqs = field & 0xf;
250 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
251 dev_cap->max_eqs = 1 << (field & 0xf);
252 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
253 dev_cap->reserved_mtts = 1 << (field >> 4);
254 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
255 dev_cap->max_mrw_sz = 1 << field;
256 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
257 dev_cap->reserved_mrws = 1 << (field & 0xf);
258 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
259 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
260 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
261 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
262 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
263 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
264 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
265 field &= 0x1f;
266 if (!field)
267 dev_cap->max_gso_sz = 0;
268 else
269 dev_cap->max_gso_sz = 1 << field;
270
271 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
272 dev_cap->max_rdma_global = 1 << (field & 0x3f);
273 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
274 dev_cap->local_ca_ack_delay = field & 0x1f;
275 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
276 dev_cap->num_ports = field & 0xf;
277 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
278 dev_cap->max_msg_sz = 1 << (field & 0x1f);
279 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
280 dev_cap->stat_rate_support = stat_rate;
281 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
282 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
283 dev_cap->flags = flags | (u64)ext_flags << 32;
284 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
285 dev_cap->reserved_uars = field >> 4;
286 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
287 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
288 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
289 dev_cap->min_page_sz = 1 << field;
290
291 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
292 if (field & 0x80) {
293 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
294 dev_cap->bf_reg_size = 1 << (field & 0x1f);
295 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
296 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
297 field = 3;
298 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
299 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
300 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
301 } else {
302 dev_cap->bf_reg_size = 0;
303 mlx4_dbg(dev, "BlueFlame not available\n");
304 }
305
306 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
307 dev_cap->max_sq_sg = field;
308 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
309 dev_cap->max_sq_desc_sz = size;
310
311 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
312 dev_cap->max_qp_per_mcg = 1 << field;
313 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
314 dev_cap->reserved_mgms = field & 0xf;
315 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
316 dev_cap->max_mcgs = 1 << field;
317 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
318 dev_cap->reserved_pds = field >> 4;
319 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
320 dev_cap->max_pds = 1 << (field & 0x3f);
321
322 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
323 dev_cap->rdmarc_entry_sz = size;
324 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
325 dev_cap->qpc_entry_sz = size;
326 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
327 dev_cap->aux_entry_sz = size;
328 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
329 dev_cap->altc_entry_sz = size;
330 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
331 dev_cap->eqc_entry_sz = size;
332 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
333 dev_cap->cqc_entry_sz = size;
334 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
335 dev_cap->srq_entry_sz = size;
336 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
337 dev_cap->cmpt_entry_sz = size;
338 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
339 dev_cap->mtt_entry_sz = size;
340 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
341 dev_cap->dmpt_entry_sz = size;
342
343 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
344 dev_cap->max_srq_sz = 1 << field;
345 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
346 dev_cap->max_qp_sz = 1 << field;
347 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
348 dev_cap->resize_srq = field & 1;
349 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
350 dev_cap->max_rq_sg = field;
351 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
352 dev_cap->max_rq_desc_sz = size;
353
354 MLX4_GET(dev_cap->bmme_flags, outbox,
355 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
356 MLX4_GET(dev_cap->reserved_lkey, outbox,
357 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
358 MLX4_GET(dev_cap->max_icm_sz, outbox,
359 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
360 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
361 MLX4_GET(dev_cap->max_counters, outbox,
362 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
363
364 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
365 for (i = 1; i <= dev_cap->num_ports; ++i) {
366 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
367 dev_cap->max_vl[i] = field >> 4;
368 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
369 dev_cap->ib_mtu[i] = field >> 4;
370 dev_cap->max_port_width[i] = field & 0xf;
371 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
372 dev_cap->max_gids[i] = 1 << (field & 0xf);
373 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
374 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
375 }
376 } else {
377 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
378 #define QUERY_PORT_MTU_OFFSET 0x01
379 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
380 #define QUERY_PORT_WIDTH_OFFSET 0x06
381 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
382 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
383 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
384 #define QUERY_PORT_MAC_OFFSET 0x10
385 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
386 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
387 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
388
389 for (i = 1; i <= dev_cap->num_ports; ++i) {
390 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
391 MLX4_CMD_TIME_CLASS_B);
392 if (err)
393 goto out;
394
395 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
396 dev_cap->supported_port_types[i] = field & 3;
397 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
398 dev_cap->ib_mtu[i] = field & 0xf;
399 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
400 dev_cap->max_port_width[i] = field & 0xf;
401 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
402 dev_cap->max_gids[i] = 1 << (field >> 4);
403 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
404 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
405 dev_cap->max_vl[i] = field & 0xf;
406 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
407 dev_cap->log_max_macs[i] = field & 0xf;
408 dev_cap->log_max_vlans[i] = field >> 4;
409 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
410 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
411 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
412 dev_cap->trans_type[i] = field32 >> 24;
413 dev_cap->vendor_oui[i] = field32 & 0xffffff;
414 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
415 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
416 }
417 }
418
419 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
420 dev_cap->bmme_flags, dev_cap->reserved_lkey);
421
422 /*
423 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
424 * we can't use any EQs whose doorbell falls on that page,
425 * even if the EQ itself isn't reserved.
426 */
427 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
428 dev_cap->reserved_eqs);
429
430 mlx4_dbg(dev, "Max ICM size %lld MB\n",
431 (unsigned long long) dev_cap->max_icm_sz >> 20);
432 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
433 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
434 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
435 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
436 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
437 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
438 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
439 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
440 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
441 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
442 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
443 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
444 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
445 dev_cap->max_pds, dev_cap->reserved_mgms);
446 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
447 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
448 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
449 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
450 dev_cap->max_port_width[1]);
451 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
452 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
453 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
454 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
455 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
456 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
457
458 dump_dev_cap_flags(dev, dev_cap->flags);
459
460 out:
461 mlx4_free_cmd_mailbox(dev, mailbox);
462 return err;
463 }
464
465 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
466 {
467 struct mlx4_cmd_mailbox *mailbox;
468 struct mlx4_icm_iter iter;
469 __be64 *pages;
470 int lg;
471 int nent = 0;
472 int i;
473 int err = 0;
474 int ts = 0, tc = 0;
475
476 mailbox = mlx4_alloc_cmd_mailbox(dev);
477 if (IS_ERR(mailbox))
478 return PTR_ERR(mailbox);
479 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
480 pages = mailbox->buf;
481
482 for (mlx4_icm_first(icm, &iter);
483 !mlx4_icm_last(&iter);
484 mlx4_icm_next(&iter)) {
485 /*
486 * We have to pass pages that are aligned to their
487 * size, so find the least significant 1 in the
488 * address or size and use that as our log2 size.
489 */
490 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
491 if (lg < MLX4_ICM_PAGE_SHIFT) {
492 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
493 MLX4_ICM_PAGE_SIZE,
494 (unsigned long long) mlx4_icm_addr(&iter),
495 mlx4_icm_size(&iter));
496 err = -EINVAL;
497 goto out;
498 }
499
500 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
501 if (virt != -1) {
502 pages[nent * 2] = cpu_to_be64(virt);
503 virt += 1 << lg;
504 }
505
506 pages[nent * 2 + 1] =
507 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
508 (lg - MLX4_ICM_PAGE_SHIFT));
509 ts += 1 << (lg - 10);
510 ++tc;
511
512 if (++nent == MLX4_MAILBOX_SIZE / 16) {
513 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
514 MLX4_CMD_TIME_CLASS_B);
515 if (err)
516 goto out;
517 nent = 0;
518 }
519 }
520 }
521
522 if (nent)
523 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, MLX4_CMD_TIME_CLASS_B);
524 if (err)
525 goto out;
526
527 switch (op) {
528 case MLX4_CMD_MAP_FA:
529 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
530 break;
531 case MLX4_CMD_MAP_ICM_AUX:
532 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
533 break;
534 case MLX4_CMD_MAP_ICM:
535 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
536 tc, ts, (unsigned long long) virt - (ts << 10));
537 break;
538 }
539
540 out:
541 mlx4_free_cmd_mailbox(dev, mailbox);
542 return err;
543 }
544
545 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
546 {
547 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
548 }
549
550 int mlx4_UNMAP_FA(struct mlx4_dev *dev)
551 {
552 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, MLX4_CMD_TIME_CLASS_B);
553 }
554
555
556 int mlx4_RUN_FW(struct mlx4_dev *dev)
557 {
558 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, MLX4_CMD_TIME_CLASS_A);
559 }
560
561 int mlx4_QUERY_FW(struct mlx4_dev *dev)
562 {
563 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
564 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
565 struct mlx4_cmd_mailbox *mailbox;
566 u32 *outbox;
567 int err = 0;
568 u64 fw_ver;
569 u16 cmd_if_rev;
570 u8 lg;
571
572 #define QUERY_FW_OUT_SIZE 0x100
573 #define QUERY_FW_VER_OFFSET 0x00
574 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
575 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
576 #define QUERY_FW_ERR_START_OFFSET 0x30
577 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
578 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
579
580 #define QUERY_FW_SIZE_OFFSET 0x00
581 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
582 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
583
584 mailbox = mlx4_alloc_cmd_mailbox(dev);
585 if (IS_ERR(mailbox))
586 return PTR_ERR(mailbox);
587 outbox = mailbox->buf;
588
589 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
590 MLX4_CMD_TIME_CLASS_A);
591 if (err)
592 goto out;
593
594 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
595 /*
596 * FW subminor version is at more significant bits than minor
597 * version, so swap here.
598 */
599 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
600 ((fw_ver & 0xffff0000ull) >> 16) |
601 ((fw_ver & 0x0000ffffull) << 16);
602
603 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
604 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
605 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
606 mlx4_err(dev, "Installed FW has unsupported "
607 "command interface revision %d.\n",
608 cmd_if_rev);
609 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
610 (int) (dev->caps.fw_ver >> 32),
611 (int) (dev->caps.fw_ver >> 16) & 0xffff,
612 (int) dev->caps.fw_ver & 0xffff);
613 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
614 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
615 err = -ENODEV;
616 goto out;
617 }
618
619 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
620 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
621
622 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
623 cmd->max_cmds = 1 << lg;
624
625 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
626 (int) (dev->caps.fw_ver >> 32),
627 (int) (dev->caps.fw_ver >> 16) & 0xffff,
628 (int) dev->caps.fw_ver & 0xffff,
629 cmd_if_rev, cmd->max_cmds);
630
631 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
632 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
633 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
634 fw->catas_bar = (fw->catas_bar >> 6) * 2;
635
636 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
637 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
638
639 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
640 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
641 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
642 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
643
644 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
645
646 /*
647 * Round up number of system pages needed in case
648 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
649 */
650 fw->fw_pages =
651 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
652 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
653
654 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
655 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
656
657 out:
658 mlx4_free_cmd_mailbox(dev, mailbox);
659 return err;
660 }
661
662 static void get_board_id(void *vsd, char *board_id)
663 {
664 int i;
665
666 #define VSD_OFFSET_SIG1 0x00
667 #define VSD_OFFSET_SIG2 0xde
668 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
669 #define VSD_OFFSET_TS_BOARD_ID 0x20
670
671 #define VSD_SIGNATURE_TOPSPIN 0x5ad
672
673 memset(board_id, 0, MLX4_BOARD_ID_LEN);
674
675 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
676 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
677 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
678 } else {
679 /*
680 * The board ID is a string but the firmware byte
681 * swaps each 4-byte word before passing it back to
682 * us. Therefore we need to swab it before printing.
683 */
684 for (i = 0; i < 4; ++i)
685 ((u32 *) board_id)[i] =
686 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
687 }
688 }
689
690 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
691 {
692 struct mlx4_cmd_mailbox *mailbox;
693 u32 *outbox;
694 int err;
695
696 #define QUERY_ADAPTER_OUT_SIZE 0x100
697 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
698 #define QUERY_ADAPTER_VSD_OFFSET 0x20
699
700 mailbox = mlx4_alloc_cmd_mailbox(dev);
701 if (IS_ERR(mailbox))
702 return PTR_ERR(mailbox);
703 outbox = mailbox->buf;
704
705 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
706 MLX4_CMD_TIME_CLASS_A);
707 if (err)
708 goto out;
709
710 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
711
712 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
713 adapter->board_id);
714
715 out:
716 mlx4_free_cmd_mailbox(dev, mailbox);
717 return err;
718 }
719
720 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
721 {
722 struct mlx4_cmd_mailbox *mailbox;
723 __be32 *inbox;
724 int err;
725
726 #define INIT_HCA_IN_SIZE 0x200
727 #define INIT_HCA_VERSION_OFFSET 0x000
728 #define INIT_HCA_VERSION 2
729 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
730 #define INIT_HCA_FLAGS_OFFSET 0x014
731 #define INIT_HCA_QPC_OFFSET 0x020
732 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
733 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
734 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
735 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
736 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
737 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
738 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
739 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
740 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
741 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
742 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
743 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
744 #define INIT_HCA_MCAST_OFFSET 0x0c0
745 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
746 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
747 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
748 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
749 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
750 #define INIT_HCA_TPT_OFFSET 0x0f0
751 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
752 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
753 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
754 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
755 #define INIT_HCA_UAR_OFFSET 0x120
756 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
757 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
758
759 mailbox = mlx4_alloc_cmd_mailbox(dev);
760 if (IS_ERR(mailbox))
761 return PTR_ERR(mailbox);
762 inbox = mailbox->buf;
763
764 memset(inbox, 0, INIT_HCA_IN_SIZE);
765
766 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
767
768 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
769 (ilog2(cache_line_size()) - 4) << 5;
770
771 #if defined(__LITTLE_ENDIAN)
772 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
773 #elif defined(__BIG_ENDIAN)
774 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
775 #else
776 #error Host endianness not defined
777 #endif
778 /* Check port for UD address vector: */
779 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
780
781 /* Enable IPoIB checksumming if we can: */
782 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
783 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
784
785 /* Enable QoS support if module parameter set */
786 if (enable_qos)
787 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
788
789 /* enable counters */
790 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
791 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
792
793 /* QPC/EEC/CQC/EQC/RDMARC attributes */
794
795 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
796 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
797 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
798 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
799 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
800 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
801 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
802 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
803 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
804 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
805 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
806 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
807
808 /* multicast attributes */
809
810 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
811 MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
812 MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
813 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
814 MLX4_PUT(inbox, (u8) (1 << 3), INIT_HCA_UC_STEERING_OFFSET);
815 MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
816
817 /* TPT attributes */
818
819 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
820 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
821 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
822 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
823
824 /* UAR attributes */
825
826 MLX4_PUT(inbox, (u8) (PAGE_SHIFT - 12), INIT_HCA_UAR_PAGE_SZ_OFFSET);
827 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
828
829 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000);
830
831 if (err)
832 mlx4_err(dev, "INIT_HCA returns %d\n", err);
833
834 mlx4_free_cmd_mailbox(dev, mailbox);
835 return err;
836 }
837
838 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
839 {
840 struct mlx4_cmd_mailbox *mailbox;
841 u32 *inbox;
842 int err;
843 u32 flags;
844 u16 field;
845
846 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
847 #define INIT_PORT_IN_SIZE 256
848 #define INIT_PORT_FLAGS_OFFSET 0x00
849 #define INIT_PORT_FLAG_SIG (1 << 18)
850 #define INIT_PORT_FLAG_NG (1 << 17)
851 #define INIT_PORT_FLAG_G0 (1 << 16)
852 #define INIT_PORT_VL_SHIFT 4
853 #define INIT_PORT_PORT_WIDTH_SHIFT 8
854 #define INIT_PORT_MTU_OFFSET 0x04
855 #define INIT_PORT_MAX_GID_OFFSET 0x06
856 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
857 #define INIT_PORT_GUID0_OFFSET 0x10
858 #define INIT_PORT_NODE_GUID_OFFSET 0x18
859 #define INIT_PORT_SI_GUID_OFFSET 0x20
860
861 mailbox = mlx4_alloc_cmd_mailbox(dev);
862 if (IS_ERR(mailbox))
863 return PTR_ERR(mailbox);
864 inbox = mailbox->buf;
865
866 memset(inbox, 0, INIT_PORT_IN_SIZE);
867
868 flags = 0;
869 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
870 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
871 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
872
873 field = 128 << dev->caps.ib_mtu_cap[port];
874 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
875 field = dev->caps.gid_table_len[port];
876 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
877 field = dev->caps.pkey_table_len[port];
878 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
879
880 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
881 MLX4_CMD_TIME_CLASS_A);
882
883 mlx4_free_cmd_mailbox(dev, mailbox);
884 } else
885 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
886 MLX4_CMD_TIME_CLASS_A);
887
888 return err;
889 }
890 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
891
892 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
893 {
894 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000);
895 }
896 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
897
898 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
899 {
900 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000);
901 }
902
903 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
904 {
905 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
906 MLX4_CMD_SET_ICM_SIZE,
907 MLX4_CMD_TIME_CLASS_A);
908 if (ret)
909 return ret;
910
911 /*
912 * Round up number of system pages needed in case
913 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
914 */
915 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
916 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
917
918 return 0;
919 }
920
921 int mlx4_NOP(struct mlx4_dev *dev)
922 {
923 /* Input modifier of 0x1f means "finish as soon as possible." */
924 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100);
925 }
926
927 #define MLX4_WOL_SETUP_MODE (5 << 28)
928 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
929 {
930 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
931
932 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
933 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A);
934 }
935 EXPORT_SYMBOL_GPL(mlx4_wol_read);
936
937 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
938 {
939 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
940
941 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
942 MLX4_CMD_TIME_CLASS_A);
943 }
944 EXPORT_SYMBOL_GPL(mlx4_wol_write);