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Staging: hv: mousevsc: Cleanup and properly implement reportdesc_callback()
[zen-stable.git] / drivers / net / r8169.c
blob02339b3352e7d4340db9106c86b59b61404bf6ea
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
31
32 #include <asm/system.h>
33 #include <asm/io.h>
34 #include <asm/irq.h>
35
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
39
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
46
47 #ifdef RTL8169_DEBUG
48 #define assert(expr) \
49 if (!(expr)) { \
50 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
51 #expr,__FILE__,__func__,__LINE__); \
52 }
53 #define dprintk(fmt, args...) \
54 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
55 #else
56 #define assert(expr) do {} while (0)
57 #define dprintk(fmt, args...) do {} while (0)
58 #endif /* RTL8169_DEBUG */
59
60 #define R8169_MSG_DEFAULT \
61 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
62
63 #define TX_BUFFS_AVAIL(tp) \
64 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
65
66 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
67 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
68 static const int multicast_filter_limit = 32;
69
70 /* MAC address length */
71 #define MAC_ADDR_LEN 6
72
73 #define MAX_READ_REQUEST_SHIFT 12
74 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
75 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
76 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
77
78 #define R8169_REGS_SIZE 256
79 #define R8169_NAPI_WEIGHT 64
80 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
81 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
82 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
83 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
84 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
85
86 #define RTL8169_TX_TIMEOUT (6*HZ)
87 #define RTL8169_PHY_TIMEOUT (10*HZ)
88
89 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
90 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
91 #define RTL_EEPROM_SIG_ADDR 0x0000
92
93 /* write/read MMIO register */
94 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
95 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
96 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
97 #define RTL_R8(reg) readb (ioaddr + (reg))
98 #define RTL_R16(reg) readw (ioaddr + (reg))
99 #define RTL_R32(reg) readl (ioaddr + (reg))
100
101 enum mac_version {
102 RTL_GIGA_MAC_VER_01 = 0,
103 RTL_GIGA_MAC_VER_02,
104 RTL_GIGA_MAC_VER_03,
105 RTL_GIGA_MAC_VER_04,
106 RTL_GIGA_MAC_VER_05,
107 RTL_GIGA_MAC_VER_06,
108 RTL_GIGA_MAC_VER_07,
109 RTL_GIGA_MAC_VER_08,
110 RTL_GIGA_MAC_VER_09,
111 RTL_GIGA_MAC_VER_10,
112 RTL_GIGA_MAC_VER_11,
113 RTL_GIGA_MAC_VER_12,
114 RTL_GIGA_MAC_VER_13,
115 RTL_GIGA_MAC_VER_14,
116 RTL_GIGA_MAC_VER_15,
117 RTL_GIGA_MAC_VER_16,
118 RTL_GIGA_MAC_VER_17,
119 RTL_GIGA_MAC_VER_18,
120 RTL_GIGA_MAC_VER_19,
121 RTL_GIGA_MAC_VER_20,
122 RTL_GIGA_MAC_VER_21,
123 RTL_GIGA_MAC_VER_22,
124 RTL_GIGA_MAC_VER_23,
125 RTL_GIGA_MAC_VER_24,
126 RTL_GIGA_MAC_VER_25,
127 RTL_GIGA_MAC_VER_26,
128 RTL_GIGA_MAC_VER_27,
129 RTL_GIGA_MAC_VER_28,
130 RTL_GIGA_MAC_VER_29,
131 RTL_GIGA_MAC_VER_30,
132 RTL_GIGA_MAC_VER_31,
133 RTL_GIGA_MAC_VER_32,
134 RTL_GIGA_MAC_VER_33,
135 RTL_GIGA_MAC_VER_34,
136 RTL_GIGA_MAC_NONE = 0xff,
137 };
138
139 enum rtl_tx_desc_version {
140 RTL_TD_0 = 0,
141 RTL_TD_1 = 1,
142 };
143
144 #define _R(NAME,TD,FW) \
145 { .name = NAME, .txd_version = TD, .fw_name = FW }
146
147 static const struct {
148 const char *name;
149 enum rtl_tx_desc_version txd_version;
150 const char *fw_name;
151 } rtl_chip_infos[] = {
152 /* PCI devices. */
153 [RTL_GIGA_MAC_VER_01] =
154 _R("RTL8169", RTL_TD_0, NULL),
155 [RTL_GIGA_MAC_VER_02] =
156 _R("RTL8169s", RTL_TD_0, NULL),
157 [RTL_GIGA_MAC_VER_03] =
158 _R("RTL8110s", RTL_TD_0, NULL),
159 [RTL_GIGA_MAC_VER_04] =
160 _R("RTL8169sb/8110sb", RTL_TD_0, NULL),
161 [RTL_GIGA_MAC_VER_05] =
162 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
163 [RTL_GIGA_MAC_VER_06] =
164 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
165 /* PCI-E devices. */
166 [RTL_GIGA_MAC_VER_07] =
167 _R("RTL8102e", RTL_TD_1, NULL),
168 [RTL_GIGA_MAC_VER_08] =
169 _R("RTL8102e", RTL_TD_1, NULL),
170 [RTL_GIGA_MAC_VER_09] =
171 _R("RTL8102e", RTL_TD_1, NULL),
172 [RTL_GIGA_MAC_VER_10] =
173 _R("RTL8101e", RTL_TD_0, NULL),
174 [RTL_GIGA_MAC_VER_11] =
175 _R("RTL8168b/8111b", RTL_TD_0, NULL),
176 [RTL_GIGA_MAC_VER_12] =
177 _R("RTL8168b/8111b", RTL_TD_0, NULL),
178 [RTL_GIGA_MAC_VER_13] =
179 _R("RTL8101e", RTL_TD_0, NULL),
180 [RTL_GIGA_MAC_VER_14] =
181 _R("RTL8100e", RTL_TD_0, NULL),
182 [RTL_GIGA_MAC_VER_15] =
183 _R("RTL8100e", RTL_TD_0, NULL),
184 [RTL_GIGA_MAC_VER_16] =
185 _R("RTL8101e", RTL_TD_0, NULL),
186 [RTL_GIGA_MAC_VER_17] =
187 _R("RTL8168b/8111b", RTL_TD_0, NULL),
188 [RTL_GIGA_MAC_VER_18] =
189 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
190 [RTL_GIGA_MAC_VER_19] =
191 _R("RTL8168c/8111c", RTL_TD_1, NULL),
192 [RTL_GIGA_MAC_VER_20] =
193 _R("RTL8168c/8111c", RTL_TD_1, NULL),
194 [RTL_GIGA_MAC_VER_21] =
195 _R("RTL8168c/8111c", RTL_TD_1, NULL),
196 [RTL_GIGA_MAC_VER_22] =
197 _R("RTL8168c/8111c", RTL_TD_1, NULL),
198 [RTL_GIGA_MAC_VER_23] =
199 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
200 [RTL_GIGA_MAC_VER_24] =
201 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
202 [RTL_GIGA_MAC_VER_25] =
203 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1),
204 [RTL_GIGA_MAC_VER_26] =
205 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2),
206 [RTL_GIGA_MAC_VER_27] =
207 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
208 [RTL_GIGA_MAC_VER_28] =
209 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
210 [RTL_GIGA_MAC_VER_29] =
211 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
212 [RTL_GIGA_MAC_VER_30] =
213 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
214 [RTL_GIGA_MAC_VER_31] =
215 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
216 [RTL_GIGA_MAC_VER_32] =
217 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1),
218 [RTL_GIGA_MAC_VER_33] =
219 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2),
220 [RTL_GIGA_MAC_VER_34] =
221 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3)
222 };
223 #undef _R
224
225 enum cfg_version {
226 RTL_CFG_0 = 0x00,
227 RTL_CFG_1,
228 RTL_CFG_2
229 };
230
231 static void rtl_hw_start_8169(struct net_device *);
232 static void rtl_hw_start_8168(struct net_device *);
233 static void rtl_hw_start_8101(struct net_device *);
234
235 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
236 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
237 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
238 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
239 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
240 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
241 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
242 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
243 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
244 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
245 { PCI_VENDOR_ID_LINKSYS, 0x1032,
246 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
247 { 0x0001, 0x8168,
248 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
249 {0,},
250 };
251
252 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
253
254 static int rx_buf_sz = 16383;
255 static int use_dac;
256 static struct {
257 u32 msg_enable;
258 } debug = { -1 };
259
260 enum rtl_registers {
261 MAC0 = 0, /* Ethernet hardware address. */
262 MAC4 = 4,
263 MAR0 = 8, /* Multicast filter. */
264 CounterAddrLow = 0x10,
265 CounterAddrHigh = 0x14,
266 TxDescStartAddrLow = 0x20,
267 TxDescStartAddrHigh = 0x24,
268 TxHDescStartAddrLow = 0x28,
269 TxHDescStartAddrHigh = 0x2c,
270 FLASH = 0x30,
271 ERSR = 0x36,
272 ChipCmd = 0x37,
273 TxPoll = 0x38,
274 IntrMask = 0x3c,
275 IntrStatus = 0x3e,
276
277 TxConfig = 0x40,
278 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
279 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
280
281 RxConfig = 0x44,
282 #define RX128_INT_EN (1 << 15) /* 8111c and later */
283 #define RX_MULTI_EN (1 << 14) /* 8111c only */
284 #define RXCFG_FIFO_SHIFT 13
285 /* No threshold before first PCI xfer */
286 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
287 #define RXCFG_DMA_SHIFT 8
288 /* Unlimited maximum PCI burst. */
289 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
290
291 RxMissed = 0x4c,
292 Cfg9346 = 0x50,
293 Config0 = 0x51,
294 Config1 = 0x52,
295 Config2 = 0x53,
296 Config3 = 0x54,
297 Config4 = 0x55,
298 Config5 = 0x56,
299 MultiIntr = 0x5c,
300 PHYAR = 0x60,
301 PHYstatus = 0x6c,
302 RxMaxSize = 0xda,
303 CPlusCmd = 0xe0,
304 IntrMitigate = 0xe2,
305 RxDescAddrLow = 0xe4,
306 RxDescAddrHigh = 0xe8,
307 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
308
309 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
310
311 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
312
313 #define TxPacketMax (8064 >> 7)
314
315 FuncEvent = 0xf0,
316 FuncEventMask = 0xf4,
317 FuncPresetState = 0xf8,
318 FuncForceEvent = 0xfc,
319 };
320
321 enum rtl8110_registers {
322 TBICSR = 0x64,
323 TBI_ANAR = 0x68,
324 TBI_LPAR = 0x6a,
325 };
326
327 enum rtl8168_8101_registers {
328 CSIDR = 0x64,
329 CSIAR = 0x68,
330 #define CSIAR_FLAG 0x80000000
331 #define CSIAR_WRITE_CMD 0x80000000
332 #define CSIAR_BYTE_ENABLE 0x0f
333 #define CSIAR_BYTE_ENABLE_SHIFT 12
334 #define CSIAR_ADDR_MASK 0x0fff
335 PMCH = 0x6f,
336 EPHYAR = 0x80,
337 #define EPHYAR_FLAG 0x80000000
338 #define EPHYAR_WRITE_CMD 0x80000000
339 #define EPHYAR_REG_MASK 0x1f
340 #define EPHYAR_REG_SHIFT 16
341 #define EPHYAR_DATA_MASK 0xffff
342 DLLPR = 0xd0,
343 #define PFM_EN (1 << 6)
344 DBG_REG = 0xd1,
345 #define FIX_NAK_1 (1 << 4)
346 #define FIX_NAK_2 (1 << 3)
347 TWSI = 0xd2,
348 MCU = 0xd3,
349 #define NOW_IS_OOB (1 << 7)
350 #define EN_NDP (1 << 3)
351 #define EN_OOB_RESET (1 << 2)
352 EFUSEAR = 0xdc,
353 #define EFUSEAR_FLAG 0x80000000
354 #define EFUSEAR_WRITE_CMD 0x80000000
355 #define EFUSEAR_READ_CMD 0x00000000
356 #define EFUSEAR_REG_MASK 0x03ff
357 #define EFUSEAR_REG_SHIFT 8
358 #define EFUSEAR_DATA_MASK 0xff
359 };
360
361 enum rtl8168_registers {
362 LED_FREQ = 0x1a,
363 EEE_LED = 0x1b,
364 ERIDR = 0x70,
365 ERIAR = 0x74,
366 #define ERIAR_FLAG 0x80000000
367 #define ERIAR_WRITE_CMD 0x80000000
368 #define ERIAR_READ_CMD 0x00000000
369 #define ERIAR_ADDR_BYTE_ALIGN 4
370 #define ERIAR_TYPE_SHIFT 16
371 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
372 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
373 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
374 #define ERIAR_MASK_SHIFT 12
375 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
376 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
377 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
378 EPHY_RXER_NUM = 0x7c,
379 OCPDR = 0xb0, /* OCP GPHY access */
380 #define OCPDR_WRITE_CMD 0x80000000
381 #define OCPDR_READ_CMD 0x00000000
382 #define OCPDR_REG_MASK 0x7f
383 #define OCPDR_GPHY_REG_SHIFT 16
384 #define OCPDR_DATA_MASK 0xffff
385 OCPAR = 0xb4,
386 #define OCPAR_FLAG 0x80000000
387 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
388 #define OCPAR_GPHY_READ_CMD 0x0000f060
389 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
390 MISC = 0xf0, /* 8168e only. */
391 #define TXPLA_RST (1 << 29)
392 #define PWM_EN (1 << 22)
393 };
394
395 enum rtl_register_content {
396 /* InterruptStatusBits */
397 SYSErr = 0x8000,
398 PCSTimeout = 0x4000,
399 SWInt = 0x0100,
400 TxDescUnavail = 0x0080,
401 RxFIFOOver = 0x0040,
402 LinkChg = 0x0020,
403 RxOverflow = 0x0010,
404 TxErr = 0x0008,
405 TxOK = 0x0004,
406 RxErr = 0x0002,
407 RxOK = 0x0001,
408
409 /* RxStatusDesc */
410 RxFOVF = (1 << 23),
411 RxRWT = (1 << 22),
412 RxRES = (1 << 21),
413 RxRUNT = (1 << 20),
414 RxCRC = (1 << 19),
415
416 /* ChipCmdBits */
417 StopReq = 0x80,
418 CmdReset = 0x10,
419 CmdRxEnb = 0x08,
420 CmdTxEnb = 0x04,
421 RxBufEmpty = 0x01,
422
423 /* TXPoll register p.5 */
424 HPQ = 0x80, /* Poll cmd on the high prio queue */
425 NPQ = 0x40, /* Poll cmd on the low prio queue */
426 FSWInt = 0x01, /* Forced software interrupt */
427
428 /* Cfg9346Bits */
429 Cfg9346_Lock = 0x00,
430 Cfg9346_Unlock = 0xc0,
431
432 /* rx_mode_bits */
433 AcceptErr = 0x20,
434 AcceptRunt = 0x10,
435 AcceptBroadcast = 0x08,
436 AcceptMulticast = 0x04,
437 AcceptMyPhys = 0x02,
438 AcceptAllPhys = 0x01,
439 #define RX_CONFIG_ACCEPT_MASK 0x3f
440
441 /* TxConfigBits */
442 TxInterFrameGapShift = 24,
443 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
444
445 /* Config1 register p.24 */
446 LEDS1 = (1 << 7),
447 LEDS0 = (1 << 6),
448 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
449 Speed_down = (1 << 4),
450 MEMMAP = (1 << 3),
451 IOMAP = (1 << 2),
452 VPD = (1 << 1),
453 PMEnable = (1 << 0), /* Power Management Enable */
454
455 /* Config2 register p. 25 */
456 PCI_Clock_66MHz = 0x01,
457 PCI_Clock_33MHz = 0x00,
458
459 /* Config3 register p.25 */
460 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
461 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
462 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
463
464 /* Config5 register p.27 */
465 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
466 MWF = (1 << 5), /* Accept Multicast wakeup frame */
467 UWF = (1 << 4), /* Accept Unicast wakeup frame */
468 Spi_en = (1 << 3),
469 LanWake = (1 << 1), /* LanWake enable/disable */
470 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
471
472 /* TBICSR p.28 */
473 TBIReset = 0x80000000,
474 TBILoopback = 0x40000000,
475 TBINwEnable = 0x20000000,
476 TBINwRestart = 0x10000000,
477 TBILinkOk = 0x02000000,
478 TBINwComplete = 0x01000000,
479
480 /* CPlusCmd p.31 */
481 EnableBist = (1 << 15), // 8168 8101
482 Mac_dbgo_oe = (1 << 14), // 8168 8101
483 Normal_mode = (1 << 13), // unused
484 Force_half_dup = (1 << 12), // 8168 8101
485 Force_rxflow_en = (1 << 11), // 8168 8101
486 Force_txflow_en = (1 << 10), // 8168 8101
487 Cxpl_dbg_sel = (1 << 9), // 8168 8101
488 ASF = (1 << 8), // 8168 8101
489 PktCntrDisable = (1 << 7), // 8168 8101
490 Mac_dbgo_sel = 0x001c, // 8168
491 RxVlan = (1 << 6),
492 RxChkSum = (1 << 5),
493 PCIDAC = (1 << 4),
494 PCIMulRW = (1 << 3),
495 INTT_0 = 0x0000, // 8168
496 INTT_1 = 0x0001, // 8168
497 INTT_2 = 0x0002, // 8168
498 INTT_3 = 0x0003, // 8168
499
500 /* rtl8169_PHYstatus */
501 TBI_Enable = 0x80,
502 TxFlowCtrl = 0x40,
503 RxFlowCtrl = 0x20,
504 _1000bpsF = 0x10,
505 _100bps = 0x08,
506 _10bps = 0x04,
507 LinkStatus = 0x02,
508 FullDup = 0x01,
509
510 /* _TBICSRBit */
511 TBILinkOK = 0x02000000,
512
513 /* DumpCounterCommand */
514 CounterDump = 0x8,
515 };
516
517 enum rtl_desc_bit {
518 /* First doubleword. */
519 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
520 RingEnd = (1 << 30), /* End of descriptor ring */
521 FirstFrag = (1 << 29), /* First segment of a packet */
522 LastFrag = (1 << 28), /* Final segment of a packet */
523 };
524
525 /* Generic case. */
526 enum rtl_tx_desc_bit {
527 /* First doubleword. */
528 TD_LSO = (1 << 27), /* Large Send Offload */
529 #define TD_MSS_MAX 0x07ffu /* MSS value */
530
531 /* Second doubleword. */
532 TxVlanTag = (1 << 17), /* Add VLAN tag */
533 };
534
535 /* 8169, 8168b and 810x except 8102e. */
536 enum rtl_tx_desc_bit_0 {
537 /* First doubleword. */
538 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
539 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
540 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
541 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
542 };
543
544 /* 8102e, 8168c and beyond. */
545 enum rtl_tx_desc_bit_1 {
546 /* Second doubleword. */
547 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
548 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
549 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
550 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
551 };
552
553 static const struct rtl_tx_desc_info {
554 struct {
555 u32 udp;
556 u32 tcp;
557 } checksum;
558 u16 mss_shift;
559 u16 opts_offset;
560 } tx_desc_info [] = {
561 [RTL_TD_0] = {
562 .checksum = {
563 .udp = TD0_IP_CS | TD0_UDP_CS,
564 .tcp = TD0_IP_CS | TD0_TCP_CS
565 },
566 .mss_shift = TD0_MSS_SHIFT,
567 .opts_offset = 0
568 },
569 [RTL_TD_1] = {
570 .checksum = {
571 .udp = TD1_IP_CS | TD1_UDP_CS,
572 .tcp = TD1_IP_CS | TD1_TCP_CS
573 },
574 .mss_shift = TD1_MSS_SHIFT,
575 .opts_offset = 1
576 }
577 };
578
579 enum rtl_rx_desc_bit {
580 /* Rx private */
581 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
582 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
583
584 #define RxProtoUDP (PID1)
585 #define RxProtoTCP (PID0)
586 #define RxProtoIP (PID1 | PID0)
587 #define RxProtoMask RxProtoIP
588
589 IPFail = (1 << 16), /* IP checksum failed */
590 UDPFail = (1 << 15), /* UDP/IP checksum failed */
591 TCPFail = (1 << 14), /* TCP/IP checksum failed */
592 RxVlanTag = (1 << 16), /* VLAN tag available */
593 };
594
595 #define RsvdMask 0x3fffc000
596
597 struct TxDesc {
598 __le32 opts1;
599 __le32 opts2;
600 __le64 addr;
601 };
602
603 struct RxDesc {
604 __le32 opts1;
605 __le32 opts2;
606 __le64 addr;
607 };
608
609 struct ring_info {
610 struct sk_buff *skb;
611 u32 len;
612 u8 __pad[sizeof(void *) - sizeof(u32)];
613 };
614
615 enum features {
616 RTL_FEATURE_WOL = (1 << 0),
617 RTL_FEATURE_MSI = (1 << 1),
618 RTL_FEATURE_GMII = (1 << 2),
619 };
620
621 struct rtl8169_counters {
622 __le64 tx_packets;
623 __le64 rx_packets;
624 __le64 tx_errors;
625 __le32 rx_errors;
626 __le16 rx_missed;
627 __le16 align_errors;
628 __le32 tx_one_collision;
629 __le32 tx_multi_collision;
630 __le64 rx_unicast;
631 __le64 rx_broadcast;
632 __le32 rx_multicast;
633 __le16 tx_aborted;
634 __le16 tx_underun;
635 };
636
637 struct rtl8169_private {
638 void __iomem *mmio_addr; /* memory map physical address */
639 struct pci_dev *pci_dev;
640 struct net_device *dev;
641 struct napi_struct napi;
642 spinlock_t lock;
643 u32 msg_enable;
644 u16 txd_version;
645 u16 mac_version;
646 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
647 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
648 u32 dirty_rx;
649 u32 dirty_tx;
650 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
651 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
652 dma_addr_t TxPhyAddr;
653 dma_addr_t RxPhyAddr;
654 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
655 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
656 struct timer_list timer;
657 u16 cp_cmd;
658 u16 intr_event;
659 u16 napi_event;
660 u16 intr_mask;
661
662 struct mdio_ops {
663 void (*write)(void __iomem *, int, int);
664 int (*read)(void __iomem *, int);
665 } mdio_ops;
666
667 struct pll_power_ops {
668 void (*down)(struct rtl8169_private *);
669 void (*up)(struct rtl8169_private *);
670 } pll_power_ops;
671
672 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
673 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
674 void (*phy_reset_enable)(struct rtl8169_private *tp);
675 void (*hw_start)(struct net_device *);
676 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
677 unsigned int (*link_ok)(void __iomem *);
678 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
679 struct delayed_work task;
680 unsigned features;
681
682 struct mii_if_info mii;
683 struct rtl8169_counters counters;
684 u32 saved_wolopts;
685
686 struct rtl_fw {
687 const struct firmware *fw;
688
689 #define RTL_VER_SIZE 32
690
691 char version[RTL_VER_SIZE];
692
693 struct rtl_fw_phy_action {
694 __le32 *code;
695 size_t size;
696 } phy_action;
697 } *rtl_fw;
698 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
699 };
700
701 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
702 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
703 module_param(use_dac, int, 0);
704 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
705 module_param_named(debug, debug.msg_enable, int, 0);
706 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
707 MODULE_LICENSE("GPL");
708 MODULE_VERSION(RTL8169_VERSION);
709 MODULE_FIRMWARE(FIRMWARE_8168D_1);
710 MODULE_FIRMWARE(FIRMWARE_8168D_2);
711 MODULE_FIRMWARE(FIRMWARE_8168E_1);
712 MODULE_FIRMWARE(FIRMWARE_8168E_2);
713 MODULE_FIRMWARE(FIRMWARE_8105E_1);
714
715 static int rtl8169_open(struct net_device *dev);
716 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
717 struct net_device *dev);
718 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
719 static int rtl8169_init_ring(struct net_device *dev);
720 static void rtl_hw_start(struct net_device *dev);
721 static int rtl8169_close(struct net_device *dev);
722 static void rtl_set_rx_mode(struct net_device *dev);
723 static void rtl8169_tx_timeout(struct net_device *dev);
724 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
725 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
726 void __iomem *, u32 budget);
727 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
728 static void rtl8169_down(struct net_device *dev);
729 static void rtl8169_rx_clear(struct rtl8169_private *tp);
730 static int rtl8169_poll(struct napi_struct *napi, int budget);
731
732 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
733 {
734 void __iomem *ioaddr = tp->mmio_addr;
735 int i;
736
737 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
738 for (i = 0; i < 20; i++) {
739 udelay(100);
740 if (RTL_R32(OCPAR) & OCPAR_FLAG)
741 break;
742 }
743 return RTL_R32(OCPDR);
744 }
745
746 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
747 {
748 void __iomem *ioaddr = tp->mmio_addr;
749 int i;
750
751 RTL_W32(OCPDR, data);
752 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
753 for (i = 0; i < 20; i++) {
754 udelay(100);
755 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
756 break;
757 }
758 }
759
760 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
761 {
762 void __iomem *ioaddr = tp->mmio_addr;
763 int i;
764
765 RTL_W8(ERIDR, cmd);
766 RTL_W32(ERIAR, 0x800010e8);
767 msleep(2);
768 for (i = 0; i < 5; i++) {
769 udelay(100);
770 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
771 break;
772 }
773
774 ocp_write(tp, 0x1, 0x30, 0x00000001);
775 }
776
777 #define OOB_CMD_RESET 0x00
778 #define OOB_CMD_DRIVER_START 0x05
779 #define OOB_CMD_DRIVER_STOP 0x06
780
781 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
782 {
783 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
784 }
785
786 static void rtl8168_driver_start(struct rtl8169_private *tp)
787 {
788 u16 reg;
789 int i;
790
791 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
792
793 reg = rtl8168_get_ocp_reg(tp);
794
795 for (i = 0; i < 10; i++) {
796 msleep(10);
797 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
798 break;
799 }
800 }
801
802 static void rtl8168_driver_stop(struct rtl8169_private *tp)
803 {
804 u16 reg;
805 int i;
806
807 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
808
809 reg = rtl8168_get_ocp_reg(tp);
810
811 for (i = 0; i < 10; i++) {
812 msleep(10);
813 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
814 break;
815 }
816 }
817
818 static int r8168dp_check_dash(struct rtl8169_private *tp)
819 {
820 u16 reg = rtl8168_get_ocp_reg(tp);
821
822 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
823 }
824
825 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
826 {
827 int i;
828
829 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
830
831 for (i = 20; i > 0; i--) {
832 /*
833 * Check if the RTL8169 has completed writing to the specified
834 * MII register.
835 */
836 if (!(RTL_R32(PHYAR) & 0x80000000))
837 break;
838 udelay(25);
839 }
840 /*
841 * According to hardware specs a 20us delay is required after write
842 * complete indication, but before sending next command.
843 */
844 udelay(20);
845 }
846
847 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
848 {
849 int i, value = -1;
850
851 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
852
853 for (i = 20; i > 0; i--) {
854 /*
855 * Check if the RTL8169 has completed retrieving data from
856 * the specified MII register.
857 */
858 if (RTL_R32(PHYAR) & 0x80000000) {
859 value = RTL_R32(PHYAR) & 0xffff;
860 break;
861 }
862 udelay(25);
863 }
864 /*
865 * According to hardware specs a 20us delay is required after read
866 * complete indication, but before sending next command.
867 */
868 udelay(20);
869
870 return value;
871 }
872
873 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
874 {
875 int i;
876
877 RTL_W32(OCPDR, data |
878 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
879 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
880 RTL_W32(EPHY_RXER_NUM, 0);
881
882 for (i = 0; i < 100; i++) {
883 mdelay(1);
884 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
885 break;
886 }
887 }
888
889 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
890 {
891 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
892 (value & OCPDR_DATA_MASK));
893 }
894
895 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
896 {
897 int i;
898
899 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
900
901 mdelay(1);
902 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
903 RTL_W32(EPHY_RXER_NUM, 0);
904
905 for (i = 0; i < 100; i++) {
906 mdelay(1);
907 if (RTL_R32(OCPAR) & OCPAR_FLAG)
908 break;
909 }
910
911 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
912 }
913
914 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
915
916 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
917 {
918 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
919 }
920
921 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
922 {
923 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
924 }
925
926 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
927 {
928 r8168dp_2_mdio_start(ioaddr);
929
930 r8169_mdio_write(ioaddr, reg_addr, value);
931
932 r8168dp_2_mdio_stop(ioaddr);
933 }
934
935 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
936 {
937 int value;
938
939 r8168dp_2_mdio_start(ioaddr);
940
941 value = r8169_mdio_read(ioaddr, reg_addr);
942
943 r8168dp_2_mdio_stop(ioaddr);
944
945 return value;
946 }
947
948 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
949 {
950 tp->mdio_ops.write(tp->mmio_addr, location, val);
951 }
952
953 static int rtl_readphy(struct rtl8169_private *tp, int location)
954 {
955 return tp->mdio_ops.read(tp->mmio_addr, location);
956 }
957
958 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
959 {
960 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
961 }
962
963 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
964 {
965 int val;
966
967 val = rtl_readphy(tp, reg_addr);
968 rtl_writephy(tp, reg_addr, (val | p) & ~m);
969 }
970
971 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
972 int val)
973 {
974 struct rtl8169_private *tp = netdev_priv(dev);
975
976 rtl_writephy(tp, location, val);
977 }
978
979 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
980 {
981 struct rtl8169_private *tp = netdev_priv(dev);
982
983 return rtl_readphy(tp, location);
984 }
985
986 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
987 {
988 unsigned int i;
989
990 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
991 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
992
993 for (i = 0; i < 100; i++) {
994 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
995 break;
996 udelay(10);
997 }
998 }
999
1000 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1001 {
1002 u16 value = 0xffff;
1003 unsigned int i;
1004
1005 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1006
1007 for (i = 0; i < 100; i++) {
1008 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1009 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1010 break;
1011 }
1012 udelay(10);
1013 }
1014
1015 return value;
1016 }
1017
1018 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1019 {
1020 unsigned int i;
1021
1022 RTL_W32(CSIDR, value);
1023 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1024 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1025
1026 for (i = 0; i < 100; i++) {
1027 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1028 break;
1029 udelay(10);
1030 }
1031 }
1032
1033 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1034 {
1035 u32 value = ~0x00;
1036 unsigned int i;
1037
1038 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1039 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1040
1041 for (i = 0; i < 100; i++) {
1042 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1043 value = RTL_R32(CSIDR);
1044 break;
1045 }
1046 udelay(10);
1047 }
1048
1049 return value;
1050 }
1051
1052 static
1053 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1054 {
1055 unsigned int i;
1056
1057 BUG_ON((addr & 3) || (mask == 0));
1058 RTL_W32(ERIDR, val);
1059 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1060
1061 for (i = 0; i < 100; i++) {
1062 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1063 break;
1064 udelay(100);
1065 }
1066 }
1067
1068 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1069 {
1070 u32 value = ~0x00;
1071 unsigned int i;
1072
1073 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1074
1075 for (i = 0; i < 100; i++) {
1076 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1077 value = RTL_R32(ERIDR);
1078 break;
1079 }
1080 udelay(100);
1081 }
1082
1083 return value;
1084 }
1085
1086 static void
1087 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1088 {
1089 u32 val;
1090
1091 val = rtl_eri_read(ioaddr, addr, type);
1092 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1093 }
1094
1095 struct exgmac_reg {
1096 u16 addr;
1097 u16 mask;
1098 u32 val;
1099 };
1100
1101 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1102 const struct exgmac_reg *r, int len)
1103 {
1104 while (len-- > 0) {
1105 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1106 r++;
1107 }
1108 }
1109
1110 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1111 {
1112 u8 value = 0xff;
1113 unsigned int i;
1114
1115 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1116
1117 for (i = 0; i < 300; i++) {
1118 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1119 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1120 break;
1121 }
1122 udelay(100);
1123 }
1124
1125 return value;
1126 }
1127
1128 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1129 {
1130 RTL_W16(IntrMask, 0x0000);
1131
1132 RTL_W16(IntrStatus, 0xffff);
1133 }
1134
1135 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1136 {
1137 void __iomem *ioaddr = tp->mmio_addr;
1138
1139 return RTL_R32(TBICSR) & TBIReset;
1140 }
1141
1142 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1143 {
1144 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1145 }
1146
1147 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1148 {
1149 return RTL_R32(TBICSR) & TBILinkOk;
1150 }
1151
1152 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1153 {
1154 return RTL_R8(PHYstatus) & LinkStatus;
1155 }
1156
1157 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1158 {
1159 void __iomem *ioaddr = tp->mmio_addr;
1160
1161 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1162 }
1163
1164 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1165 {
1166 unsigned int val;
1167
1168 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1169 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1170 }
1171
1172 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1173 {
1174 void __iomem *ioaddr = tp->mmio_addr;
1175 struct net_device *dev = tp->dev;
1176
1177 if (!netif_running(dev))
1178 return;
1179
1180 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1181 if (RTL_R8(PHYstatus) & _1000bpsF) {
1182 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1183 0x00000011, ERIAR_EXGMAC);
1184 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1185 0x00000005, ERIAR_EXGMAC);
1186 } else if (RTL_R8(PHYstatus) & _100bps) {
1187 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1188 0x0000001f, ERIAR_EXGMAC);
1189 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1190 0x00000005, ERIAR_EXGMAC);
1191 } else {
1192 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1193 0x0000001f, ERIAR_EXGMAC);
1194 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1195 0x0000003f, ERIAR_EXGMAC);
1196 }
1197 /* Reset packet filter */
1198 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1199 ERIAR_EXGMAC);
1200 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1201 ERIAR_EXGMAC);
1202 }
1203 }
1204
1205 static void __rtl8169_check_link_status(struct net_device *dev,
1206 struct rtl8169_private *tp,
1207 void __iomem *ioaddr, bool pm)
1208 {
1209 unsigned long flags;
1210
1211 spin_lock_irqsave(&tp->lock, flags);
1212 if (tp->link_ok(ioaddr)) {
1213 rtl_link_chg_patch(tp);
1214 /* This is to cancel a scheduled suspend if there's one. */
1215 if (pm)
1216 pm_request_resume(&tp->pci_dev->dev);
1217 netif_carrier_on(dev);
1218 if (net_ratelimit())
1219 netif_info(tp, ifup, dev, "link up\n");
1220 } else {
1221 netif_carrier_off(dev);
1222 netif_info(tp, ifdown, dev, "link down\n");
1223 if (pm)
1224 pm_schedule_suspend(&tp->pci_dev->dev, 100);
1225 }
1226 spin_unlock_irqrestore(&tp->lock, flags);
1227 }
1228
1229 static void rtl8169_check_link_status(struct net_device *dev,
1230 struct rtl8169_private *tp,
1231 void __iomem *ioaddr)
1232 {
1233 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1234 }
1235
1236 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1237
1238 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1239 {
1240 void __iomem *ioaddr = tp->mmio_addr;
1241 u8 options;
1242 u32 wolopts = 0;
1243
1244 options = RTL_R8(Config1);
1245 if (!(options & PMEnable))
1246 return 0;
1247
1248 options = RTL_R8(Config3);
1249 if (options & LinkUp)
1250 wolopts |= WAKE_PHY;
1251 if (options & MagicPacket)
1252 wolopts |= WAKE_MAGIC;
1253
1254 options = RTL_R8(Config5);
1255 if (options & UWF)
1256 wolopts |= WAKE_UCAST;
1257 if (options & BWF)
1258 wolopts |= WAKE_BCAST;
1259 if (options & MWF)
1260 wolopts |= WAKE_MCAST;
1261
1262 return wolopts;
1263 }
1264
1265 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1266 {
1267 struct rtl8169_private *tp = netdev_priv(dev);
1268
1269 spin_lock_irq(&tp->lock);
1270
1271 wol->supported = WAKE_ANY;
1272 wol->wolopts = __rtl8169_get_wol(tp);
1273
1274 spin_unlock_irq(&tp->lock);
1275 }
1276
1277 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1278 {
1279 void __iomem *ioaddr = tp->mmio_addr;
1280 unsigned int i;
1281 static const struct {
1282 u32 opt;
1283 u16 reg;
1284 u8 mask;
1285 } cfg[] = {
1286 { WAKE_ANY, Config1, PMEnable },
1287 { WAKE_PHY, Config3, LinkUp },
1288 { WAKE_MAGIC, Config3, MagicPacket },
1289 { WAKE_UCAST, Config5, UWF },
1290 { WAKE_BCAST, Config5, BWF },
1291 { WAKE_MCAST, Config5, MWF },
1292 { WAKE_ANY, Config5, LanWake }
1293 };
1294
1295 RTL_W8(Cfg9346, Cfg9346_Unlock);
1296
1297 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1298 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1299 if (wolopts & cfg[i].opt)
1300 options |= cfg[i].mask;
1301 RTL_W8(cfg[i].reg, options);
1302 }
1303
1304 RTL_W8(Cfg9346, Cfg9346_Lock);
1305 }
1306
1307 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1308 {
1309 struct rtl8169_private *tp = netdev_priv(dev);
1310
1311 spin_lock_irq(&tp->lock);
1312
1313 if (wol->wolopts)
1314 tp->features |= RTL_FEATURE_WOL;
1315 else
1316 tp->features &= ~RTL_FEATURE_WOL;
1317 __rtl8169_set_wol(tp, wol->wolopts);
1318 spin_unlock_irq(&tp->lock);
1319
1320 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1321
1322 return 0;
1323 }
1324
1325 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1326 {
1327 return rtl_chip_infos[tp->mac_version].fw_name;
1328 }
1329
1330 static void rtl8169_get_drvinfo(struct net_device *dev,
1331 struct ethtool_drvinfo *info)
1332 {
1333 struct rtl8169_private *tp = netdev_priv(dev);
1334 struct rtl_fw *rtl_fw = tp->rtl_fw;
1335
1336 strcpy(info->driver, MODULENAME);
1337 strcpy(info->version, RTL8169_VERSION);
1338 strcpy(info->bus_info, pci_name(tp->pci_dev));
1339 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1340 strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1341 rtl_fw->version);
1342 }
1343
1344 static int rtl8169_get_regs_len(struct net_device *dev)
1345 {
1346 return R8169_REGS_SIZE;
1347 }
1348
1349 static int rtl8169_set_speed_tbi(struct net_device *dev,
1350 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1351 {
1352 struct rtl8169_private *tp = netdev_priv(dev);
1353 void __iomem *ioaddr = tp->mmio_addr;
1354 int ret = 0;
1355 u32 reg;
1356
1357 reg = RTL_R32(TBICSR);
1358 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1359 (duplex == DUPLEX_FULL)) {
1360 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1361 } else if (autoneg == AUTONEG_ENABLE)
1362 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1363 else {
1364 netif_warn(tp, link, dev,
1365 "incorrect speed setting refused in TBI mode\n");
1366 ret = -EOPNOTSUPP;
1367 }
1368
1369 return ret;
1370 }
1371
1372 static int rtl8169_set_speed_xmii(struct net_device *dev,
1373 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1374 {
1375 struct rtl8169_private *tp = netdev_priv(dev);
1376 int giga_ctrl, bmcr;
1377 int rc = -EINVAL;
1378
1379 rtl_writephy(tp, 0x1f, 0x0000);
1380
1381 if (autoneg == AUTONEG_ENABLE) {
1382 int auto_nego;
1383
1384 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1385 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1386 ADVERTISE_100HALF | ADVERTISE_100FULL);
1387
1388 if (adv & ADVERTISED_10baseT_Half)
1389 auto_nego |= ADVERTISE_10HALF;
1390 if (adv & ADVERTISED_10baseT_Full)
1391 auto_nego |= ADVERTISE_10FULL;
1392 if (adv & ADVERTISED_100baseT_Half)
1393 auto_nego |= ADVERTISE_100HALF;
1394 if (adv & ADVERTISED_100baseT_Full)
1395 auto_nego |= ADVERTISE_100FULL;
1396
1397 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1398
1399 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1400 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1401
1402 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1403 if (tp->mii.supports_gmii) {
1404 if (adv & ADVERTISED_1000baseT_Half)
1405 giga_ctrl |= ADVERTISE_1000HALF;
1406 if (adv & ADVERTISED_1000baseT_Full)
1407 giga_ctrl |= ADVERTISE_1000FULL;
1408 } else if (adv & (ADVERTISED_1000baseT_Half |
1409 ADVERTISED_1000baseT_Full)) {
1410 netif_info(tp, link, dev,
1411 "PHY does not support 1000Mbps\n");
1412 goto out;
1413 }
1414
1415 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1416
1417 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1418 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1419 } else {
1420 giga_ctrl = 0;
1421
1422 if (speed == SPEED_10)
1423 bmcr = 0;
1424 else if (speed == SPEED_100)
1425 bmcr = BMCR_SPEED100;
1426 else
1427 goto out;
1428
1429 if (duplex == DUPLEX_FULL)
1430 bmcr |= BMCR_FULLDPLX;
1431 }
1432
1433 rtl_writephy(tp, MII_BMCR, bmcr);
1434
1435 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1436 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1437 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1438 rtl_writephy(tp, 0x17, 0x2138);
1439 rtl_writephy(tp, 0x0e, 0x0260);
1440 } else {
1441 rtl_writephy(tp, 0x17, 0x2108);
1442 rtl_writephy(tp, 0x0e, 0x0000);
1443 }
1444 }
1445
1446 rc = 0;
1447 out:
1448 return rc;
1449 }
1450
1451 static int rtl8169_set_speed(struct net_device *dev,
1452 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1453 {
1454 struct rtl8169_private *tp = netdev_priv(dev);
1455 int ret;
1456
1457 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1458 if (ret < 0)
1459 goto out;
1460
1461 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1462 (advertising & ADVERTISED_1000baseT_Full)) {
1463 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1464 }
1465 out:
1466 return ret;
1467 }
1468
1469 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1470 {
1471 struct rtl8169_private *tp = netdev_priv(dev);
1472 unsigned long flags;
1473 int ret;
1474
1475 del_timer_sync(&tp->timer);
1476
1477 spin_lock_irqsave(&tp->lock, flags);
1478 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1479 cmd->duplex, cmd->advertising);
1480 spin_unlock_irqrestore(&tp->lock, flags);
1481
1482 return ret;
1483 }
1484
1485 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1486 {
1487 if (dev->mtu > TD_MSS_MAX)
1488 features &= ~NETIF_F_ALL_TSO;
1489
1490 return features;
1491 }
1492
1493 static int rtl8169_set_features(struct net_device *dev, u32 features)
1494 {
1495 struct rtl8169_private *tp = netdev_priv(dev);
1496 void __iomem *ioaddr = tp->mmio_addr;
1497 unsigned long flags;
1498
1499 spin_lock_irqsave(&tp->lock, flags);
1500
1501 if (features & NETIF_F_RXCSUM)
1502 tp->cp_cmd |= RxChkSum;
1503 else
1504 tp->cp_cmd &= ~RxChkSum;
1505
1506 if (dev->features & NETIF_F_HW_VLAN_RX)
1507 tp->cp_cmd |= RxVlan;
1508 else
1509 tp->cp_cmd &= ~RxVlan;
1510
1511 RTL_W16(CPlusCmd, tp->cp_cmd);
1512 RTL_R16(CPlusCmd);
1513
1514 spin_unlock_irqrestore(&tp->lock, flags);
1515
1516 return 0;
1517 }
1518
1519 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1520 struct sk_buff *skb)
1521 {
1522 return (vlan_tx_tag_present(skb)) ?
1523 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1524 }
1525
1526 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1527 {
1528 u32 opts2 = le32_to_cpu(desc->opts2);
1529
1530 if (opts2 & RxVlanTag)
1531 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1532
1533 desc->opts2 = 0;
1534 }
1535
1536 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1537 {
1538 struct rtl8169_private *tp = netdev_priv(dev);
1539 void __iomem *ioaddr = tp->mmio_addr;
1540 u32 status;
1541
1542 cmd->supported =
1543 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1544 cmd->port = PORT_FIBRE;
1545 cmd->transceiver = XCVR_INTERNAL;
1546
1547 status = RTL_R32(TBICSR);
1548 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1549 cmd->autoneg = !!(status & TBINwEnable);
1550
1551 ethtool_cmd_speed_set(cmd, SPEED_1000);
1552 cmd->duplex = DUPLEX_FULL; /* Always set */
1553
1554 return 0;
1555 }
1556
1557 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1558 {
1559 struct rtl8169_private *tp = netdev_priv(dev);
1560
1561 return mii_ethtool_gset(&tp->mii, cmd);
1562 }
1563
1564 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1565 {
1566 struct rtl8169_private *tp = netdev_priv(dev);
1567 unsigned long flags;
1568 int rc;
1569
1570 spin_lock_irqsave(&tp->lock, flags);
1571
1572 rc = tp->get_settings(dev, cmd);
1573
1574 spin_unlock_irqrestore(&tp->lock, flags);
1575 return rc;
1576 }
1577
1578 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1579 void *p)
1580 {
1581 struct rtl8169_private *tp = netdev_priv(dev);
1582 unsigned long flags;
1583
1584 if (regs->len > R8169_REGS_SIZE)
1585 regs->len = R8169_REGS_SIZE;
1586
1587 spin_lock_irqsave(&tp->lock, flags);
1588 memcpy_fromio(p, tp->mmio_addr, regs->len);
1589 spin_unlock_irqrestore(&tp->lock, flags);
1590 }
1591
1592 static u32 rtl8169_get_msglevel(struct net_device *dev)
1593 {
1594 struct rtl8169_private *tp = netdev_priv(dev);
1595
1596 return tp->msg_enable;
1597 }
1598
1599 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1600 {
1601 struct rtl8169_private *tp = netdev_priv(dev);
1602
1603 tp->msg_enable = value;
1604 }
1605
1606 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1607 "tx_packets",
1608 "rx_packets",
1609 "tx_errors",
1610 "rx_errors",
1611 "rx_missed",
1612 "align_errors",
1613 "tx_single_collisions",
1614 "tx_multi_collisions",
1615 "unicast",
1616 "broadcast",
1617 "multicast",
1618 "tx_aborted",
1619 "tx_underrun",
1620 };
1621
1622 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1623 {
1624 switch (sset) {
1625 case ETH_SS_STATS:
1626 return ARRAY_SIZE(rtl8169_gstrings);
1627 default:
1628 return -EOPNOTSUPP;
1629 }
1630 }
1631
1632 static void rtl8169_update_counters(struct net_device *dev)
1633 {
1634 struct rtl8169_private *tp = netdev_priv(dev);
1635 void __iomem *ioaddr = tp->mmio_addr;
1636 struct device *d = &tp->pci_dev->dev;
1637 struct rtl8169_counters *counters;
1638 dma_addr_t paddr;
1639 u32 cmd;
1640 int wait = 1000;
1641
1642 /*
1643 * Some chips are unable to dump tally counters when the receiver
1644 * is disabled.
1645 */
1646 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1647 return;
1648
1649 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1650 if (!counters)
1651 return;
1652
1653 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1654 cmd = (u64)paddr & DMA_BIT_MASK(32);
1655 RTL_W32(CounterAddrLow, cmd);
1656 RTL_W32(CounterAddrLow, cmd | CounterDump);
1657
1658 while (wait--) {
1659 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1660 memcpy(&tp->counters, counters, sizeof(*counters));
1661 break;
1662 }
1663 udelay(10);
1664 }
1665
1666 RTL_W32(CounterAddrLow, 0);
1667 RTL_W32(CounterAddrHigh, 0);
1668
1669 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1670 }
1671
1672 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1673 struct ethtool_stats *stats, u64 *data)
1674 {
1675 struct rtl8169_private *tp = netdev_priv(dev);
1676
1677 ASSERT_RTNL();
1678
1679 rtl8169_update_counters(dev);
1680
1681 data[0] = le64_to_cpu(tp->counters.tx_packets);
1682 data[1] = le64_to_cpu(tp->counters.rx_packets);
1683 data[2] = le64_to_cpu(tp->counters.tx_errors);
1684 data[3] = le32_to_cpu(tp->counters.rx_errors);
1685 data[4] = le16_to_cpu(tp->counters.rx_missed);
1686 data[5] = le16_to_cpu(tp->counters.align_errors);
1687 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1688 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1689 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1690 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1691 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1692 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1693 data[12] = le16_to_cpu(tp->counters.tx_underun);
1694 }
1695
1696 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1697 {
1698 switch(stringset) {
1699 case ETH_SS_STATS:
1700 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1701 break;
1702 }
1703 }
1704
1705 static const struct ethtool_ops rtl8169_ethtool_ops = {
1706 .get_drvinfo = rtl8169_get_drvinfo,
1707 .get_regs_len = rtl8169_get_regs_len,
1708 .get_link = ethtool_op_get_link,
1709 .get_settings = rtl8169_get_settings,
1710 .set_settings = rtl8169_set_settings,
1711 .get_msglevel = rtl8169_get_msglevel,
1712 .set_msglevel = rtl8169_set_msglevel,
1713 .get_regs = rtl8169_get_regs,
1714 .get_wol = rtl8169_get_wol,
1715 .set_wol = rtl8169_set_wol,
1716 .get_strings = rtl8169_get_strings,
1717 .get_sset_count = rtl8169_get_sset_count,
1718 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1719 };
1720
1721 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1722 struct net_device *dev, u8 default_version)
1723 {
1724 void __iomem *ioaddr = tp->mmio_addr;
1725 /*
1726 * The driver currently handles the 8168Bf and the 8168Be identically
1727 * but they can be identified more specifically through the test below
1728 * if needed:
1729 *
1730 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1731 *
1732 * Same thing for the 8101Eb and the 8101Ec:
1733 *
1734 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1735 */
1736 static const struct rtl_mac_info {
1737 u32 mask;
1738 u32 val;
1739 int mac_version;
1740 } mac_info[] = {
1741 /* 8168E family. */
1742 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
1743 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1744 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1745 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1746
1747 /* 8168D family. */
1748 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1749 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1750 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1751
1752 /* 8168DP family. */
1753 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1754 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1755 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
1756
1757 /* 8168C family. */
1758 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1759 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1760 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1761 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1762 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1763 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1764 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1765 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1766 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1767
1768 /* 8168B family. */
1769 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1770 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1771 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1772 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1773
1774 /* 8101 family. */
1775 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
1776 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1777 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1778 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
1779 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1780 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1781 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1782 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1783 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1784 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1785 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1786 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1787 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1788 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1789 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1790 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1791 /* FIXME: where did these entries come from ? -- FR */
1792 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1793 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1794
1795 /* 8110 family. */
1796 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1797 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1798 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1799 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1800 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1801 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1802
1803 /* Catch-all */
1804 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1805 };
1806 const struct rtl_mac_info *p = mac_info;
1807 u32 reg;
1808
1809 reg = RTL_R32(TxConfig);
1810 while ((reg & p->mask) != p->val)
1811 p++;
1812 tp->mac_version = p->mac_version;
1813
1814 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1815 netif_notice(tp, probe, dev,
1816 "unknown MAC, using family default\n");
1817 tp->mac_version = default_version;
1818 }
1819 }
1820
1821 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1822 {
1823 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1824 }
1825
1826 struct phy_reg {
1827 u16 reg;
1828 u16 val;
1829 };
1830
1831 static void rtl_writephy_batch(struct rtl8169_private *tp,
1832 const struct phy_reg *regs, int len)
1833 {
1834 while (len-- > 0) {
1835 rtl_writephy(tp, regs->reg, regs->val);
1836 regs++;
1837 }
1838 }
1839
1840 #define PHY_READ 0x00000000
1841 #define PHY_DATA_OR 0x10000000
1842 #define PHY_DATA_AND 0x20000000
1843 #define PHY_BJMPN 0x30000000
1844 #define PHY_READ_EFUSE 0x40000000
1845 #define PHY_READ_MAC_BYTE 0x50000000
1846 #define PHY_WRITE_MAC_BYTE 0x60000000
1847 #define PHY_CLEAR_READCOUNT 0x70000000
1848 #define PHY_WRITE 0x80000000
1849 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1850 #define PHY_COMP_EQ_SKIPN 0xa0000000
1851 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1852 #define PHY_WRITE_PREVIOUS 0xc0000000
1853 #define PHY_SKIPN 0xd0000000
1854 #define PHY_DELAY_MS 0xe0000000
1855 #define PHY_WRITE_ERI_WORD 0xf0000000
1856
1857 struct fw_info {
1858 u32 magic;
1859 char version[RTL_VER_SIZE];
1860 __le32 fw_start;
1861 __le32 fw_len;
1862 u8 chksum;
1863 } __packed;
1864
1865 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1866
1867 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1868 {
1869 const struct firmware *fw = rtl_fw->fw;
1870 struct fw_info *fw_info = (struct fw_info *)fw->data;
1871 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1872 char *version = rtl_fw->version;
1873 bool rc = false;
1874
1875 if (fw->size < FW_OPCODE_SIZE)
1876 goto out;
1877
1878 if (!fw_info->magic) {
1879 size_t i, size, start;
1880 u8 checksum = 0;
1881
1882 if (fw->size < sizeof(*fw_info))
1883 goto out;
1884
1885 for (i = 0; i < fw->size; i++)
1886 checksum += fw->data[i];
1887 if (checksum != 0)
1888 goto out;
1889
1890 start = le32_to_cpu(fw_info->fw_start);
1891 if (start > fw->size)
1892 goto out;
1893
1894 size = le32_to_cpu(fw_info->fw_len);
1895 if (size > (fw->size - start) / FW_OPCODE_SIZE)
1896 goto out;
1897
1898 memcpy(version, fw_info->version, RTL_VER_SIZE);
1899
1900 pa->code = (__le32 *)(fw->data + start);
1901 pa->size = size;
1902 } else {
1903 if (fw->size % FW_OPCODE_SIZE)
1904 goto out;
1905
1906 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
1907
1908 pa->code = (__le32 *)fw->data;
1909 pa->size = fw->size / FW_OPCODE_SIZE;
1910 }
1911 version[RTL_VER_SIZE - 1] = 0;
1912
1913 rc = true;
1914 out:
1915 return rc;
1916 }
1917
1918 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
1919 struct rtl_fw_phy_action *pa)
1920 {
1921 bool rc = false;
1922 size_t index;
1923
1924 for (index = 0; index < pa->size; index++) {
1925 u32 action = le32_to_cpu(pa->code[index]);
1926 u32 regno = (action & 0x0fff0000) >> 16;
1927
1928 switch(action & 0xf0000000) {
1929 case PHY_READ:
1930 case PHY_DATA_OR:
1931 case PHY_DATA_AND:
1932 case PHY_READ_EFUSE:
1933 case PHY_CLEAR_READCOUNT:
1934 case PHY_WRITE:
1935 case PHY_WRITE_PREVIOUS:
1936 case PHY_DELAY_MS:
1937 break;
1938
1939 case PHY_BJMPN:
1940 if (regno > index) {
1941 netif_err(tp, ifup, tp->dev,
1942 "Out of range of firmware\n");
1943 goto out;
1944 }
1945 break;
1946 case PHY_READCOUNT_EQ_SKIP:
1947 if (index + 2 >= pa->size) {
1948 netif_err(tp, ifup, tp->dev,
1949 "Out of range of firmware\n");
1950 goto out;
1951 }
1952 break;
1953 case PHY_COMP_EQ_SKIPN:
1954 case PHY_COMP_NEQ_SKIPN:
1955 case PHY_SKIPN:
1956 if (index + 1 + regno >= pa->size) {
1957 netif_err(tp, ifup, tp->dev,
1958 "Out of range of firmware\n");
1959 goto out;
1960 }
1961 break;
1962
1963 case PHY_READ_MAC_BYTE:
1964 case PHY_WRITE_MAC_BYTE:
1965 case PHY_WRITE_ERI_WORD:
1966 default:
1967 netif_err(tp, ifup, tp->dev,
1968 "Invalid action 0x%08x\n", action);
1969 goto out;
1970 }
1971 }
1972 rc = true;
1973 out:
1974 return rc;
1975 }
1976
1977 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1978 {
1979 struct net_device *dev = tp->dev;
1980 int rc = -EINVAL;
1981
1982 if (!rtl_fw_format_ok(tp, rtl_fw)) {
1983 netif_err(tp, ifup, dev, "invalid firwmare\n");
1984 goto out;
1985 }
1986
1987 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
1988 rc = 0;
1989 out:
1990 return rc;
1991 }
1992
1993 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1994 {
1995 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1996 u32 predata, count;
1997 size_t index;
1998
1999 predata = count = 0;
2000
2001 for (index = 0; index < pa->size; ) {
2002 u32 action = le32_to_cpu(pa->code[index]);
2003 u32 data = action & 0x0000ffff;
2004 u32 regno = (action & 0x0fff0000) >> 16;
2005
2006 if (!action)
2007 break;
2008
2009 switch(action & 0xf0000000) {
2010 case PHY_READ:
2011 predata = rtl_readphy(tp, regno);
2012 count++;
2013 index++;
2014 break;
2015 case PHY_DATA_OR:
2016 predata |= data;
2017 index++;
2018 break;
2019 case PHY_DATA_AND:
2020 predata &= data;
2021 index++;
2022 break;
2023 case PHY_BJMPN:
2024 index -= regno;
2025 break;
2026 case PHY_READ_EFUSE:
2027 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2028 index++;
2029 break;
2030 case PHY_CLEAR_READCOUNT:
2031 count = 0;
2032 index++;
2033 break;
2034 case PHY_WRITE:
2035 rtl_writephy(tp, regno, data);
2036 index++;
2037 break;
2038 case PHY_READCOUNT_EQ_SKIP:
2039 index += (count == data) ? 2 : 1;
2040 break;
2041 case PHY_COMP_EQ_SKIPN:
2042 if (predata == data)
2043 index += regno;
2044 index++;
2045 break;
2046 case PHY_COMP_NEQ_SKIPN:
2047 if (predata != data)
2048 index += regno;
2049 index++;
2050 break;
2051 case PHY_WRITE_PREVIOUS:
2052 rtl_writephy(tp, regno, predata);
2053 index++;
2054 break;
2055 case PHY_SKIPN:
2056 index += regno + 1;
2057 break;
2058 case PHY_DELAY_MS:
2059 mdelay(data);
2060 index++;
2061 break;
2062
2063 case PHY_READ_MAC_BYTE:
2064 case PHY_WRITE_MAC_BYTE:
2065 case PHY_WRITE_ERI_WORD:
2066 default:
2067 BUG();
2068 }
2069 }
2070 }
2071
2072 static void rtl_release_firmware(struct rtl8169_private *tp)
2073 {
2074 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2075 release_firmware(tp->rtl_fw->fw);
2076 kfree(tp->rtl_fw);
2077 }
2078 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2079 }
2080
2081 static void rtl_apply_firmware(struct rtl8169_private *tp)
2082 {
2083 struct rtl_fw *rtl_fw = tp->rtl_fw;
2084
2085 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2086 if (!IS_ERR_OR_NULL(rtl_fw))
2087 rtl_phy_write_fw(tp, rtl_fw);
2088 }
2089
2090 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2091 {
2092 if (rtl_readphy(tp, reg) != val)
2093 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2094 else
2095 rtl_apply_firmware(tp);
2096 }
2097
2098 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2099 {
2100 static const struct phy_reg phy_reg_init[] = {
2101 { 0x1f, 0x0001 },
2102 { 0x06, 0x006e },
2103 { 0x08, 0x0708 },
2104 { 0x15, 0x4000 },
2105 { 0x18, 0x65c7 },
2106
2107 { 0x1f, 0x0001 },
2108 { 0x03, 0x00a1 },
2109 { 0x02, 0x0008 },
2110 { 0x01, 0x0120 },
2111 { 0x00, 0x1000 },
2112 { 0x04, 0x0800 },
2113 { 0x04, 0x0000 },
2114
2115 { 0x03, 0xff41 },
2116 { 0x02, 0xdf60 },
2117 { 0x01, 0x0140 },
2118 { 0x00, 0x0077 },
2119 { 0x04, 0x7800 },
2120 { 0x04, 0x7000 },
2121
2122 { 0x03, 0x802f },
2123 { 0x02, 0x4f02 },
2124 { 0x01, 0x0409 },
2125 { 0x00, 0xf0f9 },
2126 { 0x04, 0x9800 },
2127 { 0x04, 0x9000 },
2128
2129 { 0x03, 0xdf01 },
2130 { 0x02, 0xdf20 },
2131 { 0x01, 0xff95 },
2132 { 0x00, 0xba00 },
2133 { 0x04, 0xa800 },
2134 { 0x04, 0xa000 },
2135
2136 { 0x03, 0xff41 },
2137 { 0x02, 0xdf20 },
2138 { 0x01, 0x0140 },
2139 { 0x00, 0x00bb },
2140 { 0x04, 0xb800 },
2141 { 0x04, 0xb000 },
2142
2143 { 0x03, 0xdf41 },
2144 { 0x02, 0xdc60 },
2145 { 0x01, 0x6340 },
2146 { 0x00, 0x007d },
2147 { 0x04, 0xd800 },
2148 { 0x04, 0xd000 },
2149
2150 { 0x03, 0xdf01 },
2151 { 0x02, 0xdf20 },
2152 { 0x01, 0x100a },
2153 { 0x00, 0xa0ff },
2154 { 0x04, 0xf800 },
2155 { 0x04, 0xf000 },
2156
2157 { 0x1f, 0x0000 },
2158 { 0x0b, 0x0000 },
2159 { 0x00, 0x9200 }
2160 };
2161
2162 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2163 }
2164
2165 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2166 {
2167 static const struct phy_reg phy_reg_init[] = {
2168 { 0x1f, 0x0002 },
2169 { 0x01, 0x90d0 },
2170 { 0x1f, 0x0000 }
2171 };
2172
2173 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2174 }
2175
2176 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2177 {
2178 struct pci_dev *pdev = tp->pci_dev;
2179
2180 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2181 (pdev->subsystem_device != 0xe000))
2182 return;
2183
2184 rtl_writephy(tp, 0x1f, 0x0001);
2185 rtl_writephy(tp, 0x10, 0xf01b);
2186 rtl_writephy(tp, 0x1f, 0x0000);
2187 }
2188
2189 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2190 {
2191 static const struct phy_reg phy_reg_init[] = {
2192 { 0x1f, 0x0001 },
2193 { 0x04, 0x0000 },
2194 { 0x03, 0x00a1 },
2195 { 0x02, 0x0008 },
2196 { 0x01, 0x0120 },
2197 { 0x00, 0x1000 },
2198 { 0x04, 0x0800 },
2199 { 0x04, 0x9000 },
2200 { 0x03, 0x802f },
2201 { 0x02, 0x4f02 },
2202 { 0x01, 0x0409 },
2203 { 0x00, 0xf099 },
2204 { 0x04, 0x9800 },
2205 { 0x04, 0xa000 },
2206 { 0x03, 0xdf01 },
2207 { 0x02, 0xdf20 },
2208 { 0x01, 0xff95 },
2209 { 0x00, 0xba00 },
2210 { 0x04, 0xa800 },
2211 { 0x04, 0xf000 },
2212 { 0x03, 0xdf01 },
2213 { 0x02, 0xdf20 },
2214 { 0x01, 0x101a },
2215 { 0x00, 0xa0ff },
2216 { 0x04, 0xf800 },
2217 { 0x04, 0x0000 },
2218 { 0x1f, 0x0000 },
2219
2220 { 0x1f, 0x0001 },
2221 { 0x10, 0xf41b },
2222 { 0x14, 0xfb54 },
2223 { 0x18, 0xf5c7 },
2224 { 0x1f, 0x0000 },
2225
2226 { 0x1f, 0x0001 },
2227 { 0x17, 0x0cc0 },
2228 { 0x1f, 0x0000 }
2229 };
2230
2231 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2232
2233 rtl8169scd_hw_phy_config_quirk(tp);
2234 }
2235
2236 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2237 {
2238 static const struct phy_reg phy_reg_init[] = {
2239 { 0x1f, 0x0001 },
2240 { 0x04, 0x0000 },
2241 { 0x03, 0x00a1 },
2242 { 0x02, 0x0008 },
2243 { 0x01, 0x0120 },
2244 { 0x00, 0x1000 },
2245 { 0x04, 0x0800 },
2246 { 0x04, 0x9000 },
2247 { 0x03, 0x802f },
2248 { 0x02, 0x4f02 },
2249 { 0x01, 0x0409 },
2250 { 0x00, 0xf099 },
2251 { 0x04, 0x9800 },
2252 { 0x04, 0xa000 },
2253 { 0x03, 0xdf01 },
2254 { 0x02, 0xdf20 },
2255 { 0x01, 0xff95 },
2256 { 0x00, 0xba00 },
2257 { 0x04, 0xa800 },
2258 { 0x04, 0xf000 },
2259 { 0x03, 0xdf01 },
2260 { 0x02, 0xdf20 },
2261 { 0x01, 0x101a },
2262 { 0x00, 0xa0ff },
2263 { 0x04, 0xf800 },
2264 { 0x04, 0x0000 },
2265 { 0x1f, 0x0000 },
2266
2267 { 0x1f, 0x0001 },
2268 { 0x0b, 0x8480 },
2269 { 0x1f, 0x0000 },
2270
2271 { 0x1f, 0x0001 },
2272 { 0x18, 0x67c7 },
2273 { 0x04, 0x2000 },
2274 { 0x03, 0x002f },
2275 { 0x02, 0x4360 },
2276 { 0x01, 0x0109 },
2277 { 0x00, 0x3022 },
2278 { 0x04, 0x2800 },
2279 { 0x1f, 0x0000 },
2280
2281 { 0x1f, 0x0001 },
2282 { 0x17, 0x0cc0 },
2283 { 0x1f, 0x0000 }
2284 };
2285
2286 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2287 }
2288
2289 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2290 {
2291 static const struct phy_reg phy_reg_init[] = {
2292 { 0x10, 0xf41b },
2293 { 0x1f, 0x0000 }
2294 };
2295
2296 rtl_writephy(tp, 0x1f, 0x0001);
2297 rtl_patchphy(tp, 0x16, 1 << 0);
2298
2299 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2300 }
2301
2302 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2303 {
2304 static const struct phy_reg phy_reg_init[] = {
2305 { 0x1f, 0x0001 },
2306 { 0x10, 0xf41b },
2307 { 0x1f, 0x0000 }
2308 };
2309
2310 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2311 }
2312
2313 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2314 {
2315 static const struct phy_reg phy_reg_init[] = {
2316 { 0x1f, 0x0000 },
2317 { 0x1d, 0x0f00 },
2318 { 0x1f, 0x0002 },
2319 { 0x0c, 0x1ec8 },
2320 { 0x1f, 0x0000 }
2321 };
2322
2323 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2324 }
2325
2326 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2327 {
2328 static const struct phy_reg phy_reg_init[] = {
2329 { 0x1f, 0x0001 },
2330 { 0x1d, 0x3d98 },
2331 { 0x1f, 0x0000 }
2332 };
2333
2334 rtl_writephy(tp, 0x1f, 0x0000);
2335 rtl_patchphy(tp, 0x14, 1 << 5);
2336 rtl_patchphy(tp, 0x0d, 1 << 5);
2337
2338 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2339 }
2340
2341 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2342 {
2343 static const struct phy_reg phy_reg_init[] = {
2344 { 0x1f, 0x0001 },
2345 { 0x12, 0x2300 },
2346 { 0x1f, 0x0002 },
2347 { 0x00, 0x88d4 },
2348 { 0x01, 0x82b1 },
2349 { 0x03, 0x7002 },
2350 { 0x08, 0x9e30 },
2351 { 0x09, 0x01f0 },
2352 { 0x0a, 0x5500 },
2353 { 0x0c, 0x00c8 },
2354 { 0x1f, 0x0003 },
2355 { 0x12, 0xc096 },
2356 { 0x16, 0x000a },
2357 { 0x1f, 0x0000 },
2358 { 0x1f, 0x0000 },
2359 { 0x09, 0x2000 },
2360 { 0x09, 0x0000 }
2361 };
2362
2363 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2364
2365 rtl_patchphy(tp, 0x14, 1 << 5);
2366 rtl_patchphy(tp, 0x0d, 1 << 5);
2367 rtl_writephy(tp, 0x1f, 0x0000);
2368 }
2369
2370 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2371 {
2372 static const struct phy_reg phy_reg_init[] = {
2373 { 0x1f, 0x0001 },
2374 { 0x12, 0x2300 },
2375 { 0x03, 0x802f },
2376 { 0x02, 0x4f02 },
2377 { 0x01, 0x0409 },
2378 { 0x00, 0xf099 },
2379 { 0x04, 0x9800 },
2380 { 0x04, 0x9000 },
2381 { 0x1d, 0x3d98 },
2382 { 0x1f, 0x0002 },
2383 { 0x0c, 0x7eb8 },
2384 { 0x06, 0x0761 },
2385 { 0x1f, 0x0003 },
2386 { 0x16, 0x0f0a },
2387 { 0x1f, 0x0000 }
2388 };
2389
2390 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2391
2392 rtl_patchphy(tp, 0x16, 1 << 0);
2393 rtl_patchphy(tp, 0x14, 1 << 5);
2394 rtl_patchphy(tp, 0x0d, 1 << 5);
2395 rtl_writephy(tp, 0x1f, 0x0000);
2396 }
2397
2398 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2399 {
2400 static const struct phy_reg phy_reg_init[] = {
2401 { 0x1f, 0x0001 },
2402 { 0x12, 0x2300 },
2403 { 0x1d, 0x3d98 },
2404 { 0x1f, 0x0002 },
2405 { 0x0c, 0x7eb8 },
2406 { 0x06, 0x5461 },
2407 { 0x1f, 0x0003 },
2408 { 0x16, 0x0f0a },
2409 { 0x1f, 0x0000 }
2410 };
2411
2412 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2413
2414 rtl_patchphy(tp, 0x16, 1 << 0);
2415 rtl_patchphy(tp, 0x14, 1 << 5);
2416 rtl_patchphy(tp, 0x0d, 1 << 5);
2417 rtl_writephy(tp, 0x1f, 0x0000);
2418 }
2419
2420 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2421 {
2422 rtl8168c_3_hw_phy_config(tp);
2423 }
2424
2425 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2426 {
2427 static const struct phy_reg phy_reg_init_0[] = {
2428 /* Channel Estimation */
2429 { 0x1f, 0x0001 },
2430 { 0x06, 0x4064 },
2431 { 0x07, 0x2863 },
2432 { 0x08, 0x059c },
2433 { 0x09, 0x26b4 },
2434 { 0x0a, 0x6a19 },
2435 { 0x0b, 0xdcc8 },
2436 { 0x10, 0xf06d },
2437 { 0x14, 0x7f68 },
2438 { 0x18, 0x7fd9 },
2439 { 0x1c, 0xf0ff },
2440 { 0x1d, 0x3d9c },
2441 { 0x1f, 0x0003 },
2442 { 0x12, 0xf49f },
2443 { 0x13, 0x070b },
2444 { 0x1a, 0x05ad },
2445 { 0x14, 0x94c0 },
2446
2447 /*
2448 * Tx Error Issue
2449 * Enhance line driver power
2450 */
2451 { 0x1f, 0x0002 },
2452 { 0x06, 0x5561 },
2453 { 0x1f, 0x0005 },
2454 { 0x05, 0x8332 },
2455 { 0x06, 0x5561 },
2456
2457 /*
2458 * Can not link to 1Gbps with bad cable
2459 * Decrease SNR threshold form 21.07dB to 19.04dB
2460 */
2461 { 0x1f, 0x0001 },
2462 { 0x17, 0x0cc0 },
2463
2464 { 0x1f, 0x0000 },
2465 { 0x0d, 0xf880 }
2466 };
2467 void __iomem *ioaddr = tp->mmio_addr;
2468
2469 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2470
2471 /*
2472 * Rx Error Issue
2473 * Fine Tune Switching regulator parameter
2474 */
2475 rtl_writephy(tp, 0x1f, 0x0002);
2476 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2477 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2478
2479 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2480 static const struct phy_reg phy_reg_init[] = {
2481 { 0x1f, 0x0002 },
2482 { 0x05, 0x669a },
2483 { 0x1f, 0x0005 },
2484 { 0x05, 0x8330 },
2485 { 0x06, 0x669a },
2486 { 0x1f, 0x0002 }
2487 };
2488 int val;
2489
2490 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2491
2492 val = rtl_readphy(tp, 0x0d);
2493
2494 if ((val & 0x00ff) != 0x006c) {
2495 static const u32 set[] = {
2496 0x0065, 0x0066, 0x0067, 0x0068,
2497 0x0069, 0x006a, 0x006b, 0x006c
2498 };
2499 int i;
2500
2501 rtl_writephy(tp, 0x1f, 0x0002);
2502
2503 val &= 0xff00;
2504 for (i = 0; i < ARRAY_SIZE(set); i++)
2505 rtl_writephy(tp, 0x0d, val | set[i]);
2506 }
2507 } else {
2508 static const struct phy_reg phy_reg_init[] = {
2509 { 0x1f, 0x0002 },
2510 { 0x05, 0x6662 },
2511 { 0x1f, 0x0005 },
2512 { 0x05, 0x8330 },
2513 { 0x06, 0x6662 }
2514 };
2515
2516 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2517 }
2518
2519 /* RSET couple improve */
2520 rtl_writephy(tp, 0x1f, 0x0002);
2521 rtl_patchphy(tp, 0x0d, 0x0300);
2522 rtl_patchphy(tp, 0x0f, 0x0010);
2523
2524 /* Fine tune PLL performance */
2525 rtl_writephy(tp, 0x1f, 0x0002);
2526 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2527 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2528
2529 rtl_writephy(tp, 0x1f, 0x0005);
2530 rtl_writephy(tp, 0x05, 0x001b);
2531
2532 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2533
2534 rtl_writephy(tp, 0x1f, 0x0000);
2535 }
2536
2537 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2538 {
2539 static const struct phy_reg phy_reg_init_0[] = {
2540 /* Channel Estimation */
2541 { 0x1f, 0x0001 },
2542 { 0x06, 0x4064 },
2543 { 0x07, 0x2863 },
2544 { 0x08, 0x059c },
2545 { 0x09, 0x26b4 },
2546 { 0x0a, 0x6a19 },
2547 { 0x0b, 0xdcc8 },
2548 { 0x10, 0xf06d },
2549 { 0x14, 0x7f68 },
2550 { 0x18, 0x7fd9 },
2551 { 0x1c, 0xf0ff },
2552 { 0x1d, 0x3d9c },
2553 { 0x1f, 0x0003 },
2554 { 0x12, 0xf49f },
2555 { 0x13, 0x070b },
2556 { 0x1a, 0x05ad },
2557 { 0x14, 0x94c0 },
2558
2559 /*
2560 * Tx Error Issue
2561 * Enhance line driver power
2562 */
2563 { 0x1f, 0x0002 },
2564 { 0x06, 0x5561 },
2565 { 0x1f, 0x0005 },
2566 { 0x05, 0x8332 },
2567 { 0x06, 0x5561 },
2568
2569 /*
2570 * Can not link to 1Gbps with bad cable
2571 * Decrease SNR threshold form 21.07dB to 19.04dB
2572 */
2573 { 0x1f, 0x0001 },
2574 { 0x17, 0x0cc0 },
2575
2576 { 0x1f, 0x0000 },
2577 { 0x0d, 0xf880 }
2578 };
2579 void __iomem *ioaddr = tp->mmio_addr;
2580
2581 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2582
2583 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2584 static const struct phy_reg phy_reg_init[] = {
2585 { 0x1f, 0x0002 },
2586 { 0x05, 0x669a },
2587 { 0x1f, 0x0005 },
2588 { 0x05, 0x8330 },
2589 { 0x06, 0x669a },
2590
2591 { 0x1f, 0x0002 }
2592 };
2593 int val;
2594
2595 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2596
2597 val = rtl_readphy(tp, 0x0d);
2598 if ((val & 0x00ff) != 0x006c) {
2599 static const u32 set[] = {
2600 0x0065, 0x0066, 0x0067, 0x0068,
2601 0x0069, 0x006a, 0x006b, 0x006c
2602 };
2603 int i;
2604
2605 rtl_writephy(tp, 0x1f, 0x0002);
2606
2607 val &= 0xff00;
2608 for (i = 0; i < ARRAY_SIZE(set); i++)
2609 rtl_writephy(tp, 0x0d, val | set[i]);
2610 }
2611 } else {
2612 static const struct phy_reg phy_reg_init[] = {
2613 { 0x1f, 0x0002 },
2614 { 0x05, 0x2642 },
2615 { 0x1f, 0x0005 },
2616 { 0x05, 0x8330 },
2617 { 0x06, 0x2642 }
2618 };
2619
2620 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2621 }
2622
2623 /* Fine tune PLL performance */
2624 rtl_writephy(tp, 0x1f, 0x0002);
2625 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2626 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2627
2628 /* Switching regulator Slew rate */
2629 rtl_writephy(tp, 0x1f, 0x0002);
2630 rtl_patchphy(tp, 0x0f, 0x0017);
2631
2632 rtl_writephy(tp, 0x1f, 0x0005);
2633 rtl_writephy(tp, 0x05, 0x001b);
2634
2635 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2636
2637 rtl_writephy(tp, 0x1f, 0x0000);
2638 }
2639
2640 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2641 {
2642 static const struct phy_reg phy_reg_init[] = {
2643 { 0x1f, 0x0002 },
2644 { 0x10, 0x0008 },
2645 { 0x0d, 0x006c },
2646
2647 { 0x1f, 0x0000 },
2648 { 0x0d, 0xf880 },
2649
2650 { 0x1f, 0x0001 },
2651 { 0x17, 0x0cc0 },
2652
2653 { 0x1f, 0x0001 },
2654 { 0x0b, 0xa4d8 },
2655 { 0x09, 0x281c },
2656 { 0x07, 0x2883 },
2657 { 0x0a, 0x6b35 },
2658 { 0x1d, 0x3da4 },
2659 { 0x1c, 0xeffd },
2660 { 0x14, 0x7f52 },
2661 { 0x18, 0x7fc6 },
2662 { 0x08, 0x0601 },
2663 { 0x06, 0x4063 },
2664 { 0x10, 0xf074 },
2665 { 0x1f, 0x0003 },
2666 { 0x13, 0x0789 },
2667 { 0x12, 0xf4bd },
2668 { 0x1a, 0x04fd },
2669 { 0x14, 0x84b0 },
2670 { 0x1f, 0x0000 },
2671 { 0x00, 0x9200 },
2672
2673 { 0x1f, 0x0005 },
2674 { 0x01, 0x0340 },
2675 { 0x1f, 0x0001 },
2676 { 0x04, 0x4000 },
2677 { 0x03, 0x1d21 },
2678 { 0x02, 0x0c32 },
2679 { 0x01, 0x0200 },
2680 { 0x00, 0x5554 },
2681 { 0x04, 0x4800 },
2682 { 0x04, 0x4000 },
2683 { 0x04, 0xf000 },
2684 { 0x03, 0xdf01 },
2685 { 0x02, 0xdf20 },
2686 { 0x01, 0x101a },
2687 { 0x00, 0xa0ff },
2688 { 0x04, 0xf800 },
2689 { 0x04, 0xf000 },
2690 { 0x1f, 0x0000 },
2691
2692 { 0x1f, 0x0007 },
2693 { 0x1e, 0x0023 },
2694 { 0x16, 0x0000 },
2695 { 0x1f, 0x0000 }
2696 };
2697
2698 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2699 }
2700
2701 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2702 {
2703 static const struct phy_reg phy_reg_init[] = {
2704 { 0x1f, 0x0001 },
2705 { 0x17, 0x0cc0 },
2706
2707 { 0x1f, 0x0007 },
2708 { 0x1e, 0x002d },
2709 { 0x18, 0x0040 },
2710 { 0x1f, 0x0000 }
2711 };
2712
2713 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2714 rtl_patchphy(tp, 0x0d, 1 << 5);
2715 }
2716
2717 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2718 {
2719 static const struct phy_reg phy_reg_init[] = {
2720 /* Enable Delay cap */
2721 { 0x1f, 0x0005 },
2722 { 0x05, 0x8b80 },
2723 { 0x06, 0xc896 },
2724 { 0x1f, 0x0000 },
2725
2726 /* Channel estimation fine tune */
2727 { 0x1f, 0x0001 },
2728 { 0x0b, 0x6c20 },
2729 { 0x07, 0x2872 },
2730 { 0x1c, 0xefff },
2731 { 0x1f, 0x0003 },
2732 { 0x14, 0x6420 },
2733 { 0x1f, 0x0000 },
2734
2735 /* Update PFM & 10M TX idle timer */
2736 { 0x1f, 0x0007 },
2737 { 0x1e, 0x002f },
2738 { 0x15, 0x1919 },
2739 { 0x1f, 0x0000 },
2740
2741 { 0x1f, 0x0007 },
2742 { 0x1e, 0x00ac },
2743 { 0x18, 0x0006 },
2744 { 0x1f, 0x0000 }
2745 };
2746
2747 rtl_apply_firmware(tp);
2748
2749 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2750
2751 /* DCO enable for 10M IDLE Power */
2752 rtl_writephy(tp, 0x1f, 0x0007);
2753 rtl_writephy(tp, 0x1e, 0x0023);
2754 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2755 rtl_writephy(tp, 0x1f, 0x0000);
2756
2757 /* For impedance matching */
2758 rtl_writephy(tp, 0x1f, 0x0002);
2759 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2760 rtl_writephy(tp, 0x1f, 0x0000);
2761
2762 /* PHY auto speed down */
2763 rtl_writephy(tp, 0x1f, 0x0007);
2764 rtl_writephy(tp, 0x1e, 0x002d);
2765 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2766 rtl_writephy(tp, 0x1f, 0x0000);
2767 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2768
2769 rtl_writephy(tp, 0x1f, 0x0005);
2770 rtl_writephy(tp, 0x05, 0x8b86);
2771 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2772 rtl_writephy(tp, 0x1f, 0x0000);
2773
2774 rtl_writephy(tp, 0x1f, 0x0005);
2775 rtl_writephy(tp, 0x05, 0x8b85);
2776 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2777 rtl_writephy(tp, 0x1f, 0x0007);
2778 rtl_writephy(tp, 0x1e, 0x0020);
2779 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2780 rtl_writephy(tp, 0x1f, 0x0006);
2781 rtl_writephy(tp, 0x00, 0x5a00);
2782 rtl_writephy(tp, 0x1f, 0x0000);
2783 rtl_writephy(tp, 0x0d, 0x0007);
2784 rtl_writephy(tp, 0x0e, 0x003c);
2785 rtl_writephy(tp, 0x0d, 0x4007);
2786 rtl_writephy(tp, 0x0e, 0x0000);
2787 rtl_writephy(tp, 0x0d, 0x0000);
2788 }
2789
2790 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2791 {
2792 static const struct phy_reg phy_reg_init[] = {
2793 /* Enable Delay cap */
2794 { 0x1f, 0x0004 },
2795 { 0x1f, 0x0007 },
2796 { 0x1e, 0x00ac },
2797 { 0x18, 0x0006 },
2798 { 0x1f, 0x0002 },
2799 { 0x1f, 0x0000 },
2800 { 0x1f, 0x0000 },
2801
2802 /* Channel estimation fine tune */
2803 { 0x1f, 0x0003 },
2804 { 0x09, 0xa20f },
2805 { 0x1f, 0x0000 },
2806 { 0x1f, 0x0000 },
2807
2808 /* Green Setting */
2809 { 0x1f, 0x0005 },
2810 { 0x05, 0x8b5b },
2811 { 0x06, 0x9222 },
2812 { 0x05, 0x8b6d },
2813 { 0x06, 0x8000 },
2814 { 0x05, 0x8b76 },
2815 { 0x06, 0x8000 },
2816 { 0x1f, 0x0000 }
2817 };
2818
2819 rtl_apply_firmware(tp);
2820
2821 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2822
2823 /* For 4-corner performance improve */
2824 rtl_writephy(tp, 0x1f, 0x0005);
2825 rtl_writephy(tp, 0x05, 0x8b80);
2826 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2827 rtl_writephy(tp, 0x1f, 0x0000);
2828
2829 /* PHY auto speed down */
2830 rtl_writephy(tp, 0x1f, 0x0004);
2831 rtl_writephy(tp, 0x1f, 0x0007);
2832 rtl_writephy(tp, 0x1e, 0x002d);
2833 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2834 rtl_writephy(tp, 0x1f, 0x0002);
2835 rtl_writephy(tp, 0x1f, 0x0000);
2836 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2837
2838 /* improve 10M EEE waveform */
2839 rtl_writephy(tp, 0x1f, 0x0005);
2840 rtl_writephy(tp, 0x05, 0x8b86);
2841 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2842 rtl_writephy(tp, 0x1f, 0x0000);
2843
2844 /* Improve 2-pair detection performance */
2845 rtl_writephy(tp, 0x1f, 0x0005);
2846 rtl_writephy(tp, 0x05, 0x8b85);
2847 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2848 rtl_writephy(tp, 0x1f, 0x0000);
2849
2850 /* EEE setting */
2851 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2852 ERIAR_EXGMAC);
2853 rtl_writephy(tp, 0x1f, 0x0005);
2854 rtl_writephy(tp, 0x05, 0x8b85);
2855 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2856 rtl_writephy(tp, 0x1f, 0x0004);
2857 rtl_writephy(tp, 0x1f, 0x0007);
2858 rtl_writephy(tp, 0x1e, 0x0020);
2859 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
2860 rtl_writephy(tp, 0x1f, 0x0002);
2861 rtl_writephy(tp, 0x1f, 0x0000);
2862 rtl_writephy(tp, 0x0d, 0x0007);
2863 rtl_writephy(tp, 0x0e, 0x003c);
2864 rtl_writephy(tp, 0x0d, 0x4007);
2865 rtl_writephy(tp, 0x0e, 0x0000);
2866 rtl_writephy(tp, 0x0d, 0x0000);
2867
2868 /* Green feature */
2869 rtl_writephy(tp, 0x1f, 0x0003);
2870 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
2871 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
2872 rtl_writephy(tp, 0x1f, 0x0000);
2873 }
2874
2875 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2876 {
2877 static const struct phy_reg phy_reg_init[] = {
2878 { 0x1f, 0x0003 },
2879 { 0x08, 0x441d },
2880 { 0x01, 0x9100 },
2881 { 0x1f, 0x0000 }
2882 };
2883
2884 rtl_writephy(tp, 0x1f, 0x0000);
2885 rtl_patchphy(tp, 0x11, 1 << 12);
2886 rtl_patchphy(tp, 0x19, 1 << 13);
2887 rtl_patchphy(tp, 0x10, 1 << 15);
2888
2889 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2890 }
2891
2892 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2893 {
2894 static const struct phy_reg phy_reg_init[] = {
2895 { 0x1f, 0x0005 },
2896 { 0x1a, 0x0000 },
2897 { 0x1f, 0x0000 },
2898
2899 { 0x1f, 0x0004 },
2900 { 0x1c, 0x0000 },
2901 { 0x1f, 0x0000 },
2902
2903 { 0x1f, 0x0001 },
2904 { 0x15, 0x7701 },
2905 { 0x1f, 0x0000 }
2906 };
2907
2908 /* Disable ALDPS before ram code */
2909 rtl_writephy(tp, 0x1f, 0x0000);
2910 rtl_writephy(tp, 0x18, 0x0310);
2911 msleep(100);
2912
2913 rtl_apply_firmware(tp);
2914
2915 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2916 }
2917
2918 static void rtl_hw_phy_config(struct net_device *dev)
2919 {
2920 struct rtl8169_private *tp = netdev_priv(dev);
2921
2922 rtl8169_print_mac_version(tp);
2923
2924 switch (tp->mac_version) {
2925 case RTL_GIGA_MAC_VER_01:
2926 break;
2927 case RTL_GIGA_MAC_VER_02:
2928 case RTL_GIGA_MAC_VER_03:
2929 rtl8169s_hw_phy_config(tp);
2930 break;
2931 case RTL_GIGA_MAC_VER_04:
2932 rtl8169sb_hw_phy_config(tp);
2933 break;
2934 case RTL_GIGA_MAC_VER_05:
2935 rtl8169scd_hw_phy_config(tp);
2936 break;
2937 case RTL_GIGA_MAC_VER_06:
2938 rtl8169sce_hw_phy_config(tp);
2939 break;
2940 case RTL_GIGA_MAC_VER_07:
2941 case RTL_GIGA_MAC_VER_08:
2942 case RTL_GIGA_MAC_VER_09:
2943 rtl8102e_hw_phy_config(tp);
2944 break;
2945 case RTL_GIGA_MAC_VER_11:
2946 rtl8168bb_hw_phy_config(tp);
2947 break;
2948 case RTL_GIGA_MAC_VER_12:
2949 rtl8168bef_hw_phy_config(tp);
2950 break;
2951 case RTL_GIGA_MAC_VER_17:
2952 rtl8168bef_hw_phy_config(tp);
2953 break;
2954 case RTL_GIGA_MAC_VER_18:
2955 rtl8168cp_1_hw_phy_config(tp);
2956 break;
2957 case RTL_GIGA_MAC_VER_19:
2958 rtl8168c_1_hw_phy_config(tp);
2959 break;
2960 case RTL_GIGA_MAC_VER_20:
2961 rtl8168c_2_hw_phy_config(tp);
2962 break;
2963 case RTL_GIGA_MAC_VER_21:
2964 rtl8168c_3_hw_phy_config(tp);
2965 break;
2966 case RTL_GIGA_MAC_VER_22:
2967 rtl8168c_4_hw_phy_config(tp);
2968 break;
2969 case RTL_GIGA_MAC_VER_23:
2970 case RTL_GIGA_MAC_VER_24:
2971 rtl8168cp_2_hw_phy_config(tp);
2972 break;
2973 case RTL_GIGA_MAC_VER_25:
2974 rtl8168d_1_hw_phy_config(tp);
2975 break;
2976 case RTL_GIGA_MAC_VER_26:
2977 rtl8168d_2_hw_phy_config(tp);
2978 break;
2979 case RTL_GIGA_MAC_VER_27:
2980 rtl8168d_3_hw_phy_config(tp);
2981 break;
2982 case RTL_GIGA_MAC_VER_28:
2983 rtl8168d_4_hw_phy_config(tp);
2984 break;
2985 case RTL_GIGA_MAC_VER_29:
2986 case RTL_GIGA_MAC_VER_30:
2987 rtl8105e_hw_phy_config(tp);
2988 break;
2989 case RTL_GIGA_MAC_VER_31:
2990 /* None. */
2991 break;
2992 case RTL_GIGA_MAC_VER_32:
2993 case RTL_GIGA_MAC_VER_33:
2994 rtl8168e_1_hw_phy_config(tp);
2995 break;
2996 case RTL_GIGA_MAC_VER_34:
2997 rtl8168e_2_hw_phy_config(tp);
2998 break;
2999
3000 default:
3001 break;
3002 }
3003 }
3004
3005 static void rtl8169_phy_timer(unsigned long __opaque)
3006 {
3007 struct net_device *dev = (struct net_device *)__opaque;
3008 struct rtl8169_private *tp = netdev_priv(dev);
3009 struct timer_list *timer = &tp->timer;
3010 void __iomem *ioaddr = tp->mmio_addr;
3011 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3012
3013 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3014
3015 spin_lock_irq(&tp->lock);
3016
3017 if (tp->phy_reset_pending(tp)) {
3018 /*
3019 * A busy loop could burn quite a few cycles on nowadays CPU.
3020 * Let's delay the execution of the timer for a few ticks.
3021 */
3022 timeout = HZ/10;
3023 goto out_mod_timer;
3024 }
3025
3026 if (tp->link_ok(ioaddr))
3027 goto out_unlock;
3028
3029 netif_warn(tp, link, dev, "PHY reset until link up\n");
3030
3031 tp->phy_reset_enable(tp);
3032
3033 out_mod_timer:
3034 mod_timer(timer, jiffies + timeout);
3035 out_unlock:
3036 spin_unlock_irq(&tp->lock);
3037 }
3038
3039 #ifdef CONFIG_NET_POLL_CONTROLLER
3040 /*
3041 * Polling 'interrupt' - used by things like netconsole to send skbs
3042 * without having to re-enable interrupts. It's not called while
3043 * the interrupt routine is executing.
3044 */
3045 static void rtl8169_netpoll(struct net_device *dev)
3046 {
3047 struct rtl8169_private *tp = netdev_priv(dev);
3048 struct pci_dev *pdev = tp->pci_dev;
3049
3050 disable_irq(pdev->irq);
3051 rtl8169_interrupt(pdev->irq, dev);
3052 enable_irq(pdev->irq);
3053 }
3054 #endif
3055
3056 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3057 void __iomem *ioaddr)
3058 {
3059 iounmap(ioaddr);
3060 pci_release_regions(pdev);
3061 pci_clear_mwi(pdev);
3062 pci_disable_device(pdev);
3063 free_netdev(dev);
3064 }
3065
3066 static void rtl8169_phy_reset(struct net_device *dev,
3067 struct rtl8169_private *tp)
3068 {
3069 unsigned int i;
3070
3071 tp->phy_reset_enable(tp);
3072 for (i = 0; i < 100; i++) {
3073 if (!tp->phy_reset_pending(tp))
3074 return;
3075 msleep(1);
3076 }
3077 netif_err(tp, link, dev, "PHY reset failed\n");
3078 }
3079
3080 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3081 {
3082 void __iomem *ioaddr = tp->mmio_addr;
3083
3084 rtl_hw_phy_config(dev);
3085
3086 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3087 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3088 RTL_W8(0x82, 0x01);
3089 }
3090
3091 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3092
3093 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3094 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3095
3096 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3097 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3098 RTL_W8(0x82, 0x01);
3099 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3100 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3101 }
3102
3103 rtl8169_phy_reset(dev, tp);
3104
3105 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3106 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3107 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3108 (tp->mii.supports_gmii ?
3109 ADVERTISED_1000baseT_Half |
3110 ADVERTISED_1000baseT_Full : 0));
3111
3112 if (RTL_R8(PHYstatus) & TBI_Enable)
3113 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3114 }
3115
3116 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3117 {
3118 void __iomem *ioaddr = tp->mmio_addr;
3119 u32 high;
3120 u32 low;
3121
3122 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3123 high = addr[4] | (addr[5] << 8);
3124
3125 spin_lock_irq(&tp->lock);
3126
3127 RTL_W8(Cfg9346, Cfg9346_Unlock);
3128
3129 RTL_W32(MAC4, high);
3130 RTL_R32(MAC4);
3131
3132 RTL_W32(MAC0, low);
3133 RTL_R32(MAC0);
3134
3135 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3136 const struct exgmac_reg e[] = {
3137 { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3138 { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3139 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3140 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3141 low >> 16 },
3142 };
3143
3144 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3145 }
3146
3147 RTL_W8(Cfg9346, Cfg9346_Lock);
3148
3149 spin_unlock_irq(&tp->lock);
3150 }
3151
3152 static int rtl_set_mac_address(struct net_device *dev, void *p)
3153 {
3154 struct rtl8169_private *tp = netdev_priv(dev);
3155 struct sockaddr *addr = p;
3156
3157 if (!is_valid_ether_addr(addr->sa_data))
3158 return -EADDRNOTAVAIL;
3159
3160 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3161
3162 rtl_rar_set(tp, dev->dev_addr);
3163
3164 return 0;
3165 }
3166
3167 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3168 {
3169 struct rtl8169_private *tp = netdev_priv(dev);
3170 struct mii_ioctl_data *data = if_mii(ifr);
3171
3172 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3173 }
3174
3175 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3176 struct mii_ioctl_data *data, int cmd)
3177 {
3178 switch (cmd) {
3179 case SIOCGMIIPHY:
3180 data->phy_id = 32; /* Internal PHY */
3181 return 0;
3182
3183 case SIOCGMIIREG:
3184 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3185 return 0;
3186
3187 case SIOCSMIIREG:
3188 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3189 return 0;
3190 }
3191 return -EOPNOTSUPP;
3192 }
3193
3194 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3195 {
3196 return -EOPNOTSUPP;
3197 }
3198
3199 static const struct rtl_cfg_info {
3200 void (*hw_start)(struct net_device *);
3201 unsigned int region;
3202 unsigned int align;
3203 u16 intr_event;
3204 u16 napi_event;
3205 unsigned features;
3206 u8 default_ver;
3207 } rtl_cfg_infos [] = {
3208 [RTL_CFG_0] = {
3209 .hw_start = rtl_hw_start_8169,
3210 .region = 1,
3211 .align = 0,
3212 .intr_event = SYSErr | LinkChg | RxOverflow |
3213 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3214 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3215 .features = RTL_FEATURE_GMII,
3216 .default_ver = RTL_GIGA_MAC_VER_01,
3217 },
3218 [RTL_CFG_1] = {
3219 .hw_start = rtl_hw_start_8168,
3220 .region = 2,
3221 .align = 8,
3222 .intr_event = SYSErr | LinkChg | RxOverflow |
3223 TxErr | TxOK | RxOK | RxErr,
3224 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
3225 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3226 .default_ver = RTL_GIGA_MAC_VER_11,
3227 },
3228 [RTL_CFG_2] = {
3229 .hw_start = rtl_hw_start_8101,
3230 .region = 2,
3231 .align = 8,
3232 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3233 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3234 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3235 .features = RTL_FEATURE_MSI,
3236 .default_ver = RTL_GIGA_MAC_VER_13,
3237 }
3238 };
3239
3240 /* Cfg9346_Unlock assumed. */
3241 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
3242 const struct rtl_cfg_info *cfg)
3243 {
3244 unsigned msi = 0;
3245 u8 cfg2;
3246
3247 cfg2 = RTL_R8(Config2) & ~MSIEnable;
3248 if (cfg->features & RTL_FEATURE_MSI) {
3249 if (pci_enable_msi(pdev)) {
3250 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
3251 } else {
3252 cfg2 |= MSIEnable;
3253 msi = RTL_FEATURE_MSI;
3254 }
3255 }
3256 RTL_W8(Config2, cfg2);
3257 return msi;
3258 }
3259
3260 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3261 {
3262 if (tp->features & RTL_FEATURE_MSI) {
3263 pci_disable_msi(pdev);
3264 tp->features &= ~RTL_FEATURE_MSI;
3265 }
3266 }
3267
3268 static const struct net_device_ops rtl8169_netdev_ops = {
3269 .ndo_open = rtl8169_open,
3270 .ndo_stop = rtl8169_close,
3271 .ndo_get_stats = rtl8169_get_stats,
3272 .ndo_start_xmit = rtl8169_start_xmit,
3273 .ndo_tx_timeout = rtl8169_tx_timeout,
3274 .ndo_validate_addr = eth_validate_addr,
3275 .ndo_change_mtu = rtl8169_change_mtu,
3276 .ndo_fix_features = rtl8169_fix_features,
3277 .ndo_set_features = rtl8169_set_features,
3278 .ndo_set_mac_address = rtl_set_mac_address,
3279 .ndo_do_ioctl = rtl8169_ioctl,
3280 .ndo_set_multicast_list = rtl_set_rx_mode,
3281 #ifdef CONFIG_NET_POLL_CONTROLLER
3282 .ndo_poll_controller = rtl8169_netpoll,
3283 #endif
3284
3285 };
3286
3287 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3288 {
3289 struct mdio_ops *ops = &tp->mdio_ops;
3290
3291 switch (tp->mac_version) {
3292 case RTL_GIGA_MAC_VER_27:
3293 ops->write = r8168dp_1_mdio_write;
3294 ops->read = r8168dp_1_mdio_read;
3295 break;
3296 case RTL_GIGA_MAC_VER_28:
3297 case RTL_GIGA_MAC_VER_31:
3298 ops->write = r8168dp_2_mdio_write;
3299 ops->read = r8168dp_2_mdio_read;
3300 break;
3301 default:
3302 ops->write = r8169_mdio_write;
3303 ops->read = r8169_mdio_read;
3304 break;
3305 }
3306 }
3307
3308 static void r810x_phy_power_down(struct rtl8169_private *tp)
3309 {
3310 rtl_writephy(tp, 0x1f, 0x0000);
3311 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3312 }
3313
3314 static void r810x_phy_power_up(struct rtl8169_private *tp)
3315 {
3316 rtl_writephy(tp, 0x1f, 0x0000);
3317 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3318 }
3319
3320 static void r810x_pll_power_down(struct rtl8169_private *tp)
3321 {
3322 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3323 rtl_writephy(tp, 0x1f, 0x0000);
3324 rtl_writephy(tp, MII_BMCR, 0x0000);
3325 return;
3326 }
3327
3328 r810x_phy_power_down(tp);
3329 }
3330
3331 static void r810x_pll_power_up(struct rtl8169_private *tp)
3332 {
3333 r810x_phy_power_up(tp);
3334 }
3335
3336 static void r8168_phy_power_up(struct rtl8169_private *tp)
3337 {
3338 rtl_writephy(tp, 0x1f, 0x0000);
3339 switch (tp->mac_version) {
3340 case RTL_GIGA_MAC_VER_11:
3341 case RTL_GIGA_MAC_VER_12:
3342 case RTL_GIGA_MAC_VER_17:
3343 case RTL_GIGA_MAC_VER_18:
3344 case RTL_GIGA_MAC_VER_19:
3345 case RTL_GIGA_MAC_VER_20:
3346 case RTL_GIGA_MAC_VER_21:
3347 case RTL_GIGA_MAC_VER_22:
3348 case RTL_GIGA_MAC_VER_23:
3349 case RTL_GIGA_MAC_VER_24:
3350 case RTL_GIGA_MAC_VER_25:
3351 case RTL_GIGA_MAC_VER_26:
3352 case RTL_GIGA_MAC_VER_27:
3353 case RTL_GIGA_MAC_VER_28:
3354 case RTL_GIGA_MAC_VER_31:
3355 rtl_writephy(tp, 0x0e, 0x0000);
3356 break;
3357 default:
3358 break;
3359 }
3360 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3361 }
3362
3363 static void r8168_phy_power_down(struct rtl8169_private *tp)
3364 {
3365 rtl_writephy(tp, 0x1f, 0x0000);
3366 switch (tp->mac_version) {
3367 case RTL_GIGA_MAC_VER_32:
3368 case RTL_GIGA_MAC_VER_33:
3369 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3370 break;
3371
3372 case RTL_GIGA_MAC_VER_11:
3373 case RTL_GIGA_MAC_VER_12:
3374 case RTL_GIGA_MAC_VER_17:
3375 case RTL_GIGA_MAC_VER_18:
3376 case RTL_GIGA_MAC_VER_19:
3377 case RTL_GIGA_MAC_VER_20:
3378 case RTL_GIGA_MAC_VER_21:
3379 case RTL_GIGA_MAC_VER_22:
3380 case RTL_GIGA_MAC_VER_23:
3381 case RTL_GIGA_MAC_VER_24:
3382 case RTL_GIGA_MAC_VER_25:
3383 case RTL_GIGA_MAC_VER_26:
3384 case RTL_GIGA_MAC_VER_27:
3385 case RTL_GIGA_MAC_VER_28:
3386 case RTL_GIGA_MAC_VER_31:
3387 rtl_writephy(tp, 0x0e, 0x0200);
3388 default:
3389 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3390 break;
3391 }
3392 }
3393
3394 static void r8168_pll_power_down(struct rtl8169_private *tp)
3395 {
3396 void __iomem *ioaddr = tp->mmio_addr;
3397
3398 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3399 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3400 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3401 r8168dp_check_dash(tp)) {
3402 return;
3403 }
3404
3405 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3406 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3407 (RTL_R16(CPlusCmd) & ASF)) {
3408 return;
3409 }
3410
3411 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3412 tp->mac_version == RTL_GIGA_MAC_VER_33)
3413 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3414
3415 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3416 rtl_writephy(tp, 0x1f, 0x0000);
3417 rtl_writephy(tp, MII_BMCR, 0x0000);
3418
3419 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3420 tp->mac_version == RTL_GIGA_MAC_VER_33)
3421 RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast |
3422 AcceptMulticast | AcceptMyPhys);
3423 return;
3424 }
3425
3426 r8168_phy_power_down(tp);
3427
3428 switch (tp->mac_version) {
3429 case RTL_GIGA_MAC_VER_25:
3430 case RTL_GIGA_MAC_VER_26:
3431 case RTL_GIGA_MAC_VER_27:
3432 case RTL_GIGA_MAC_VER_28:
3433 case RTL_GIGA_MAC_VER_31:
3434 case RTL_GIGA_MAC_VER_32:
3435 case RTL_GIGA_MAC_VER_33:
3436 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3437 break;
3438 }
3439 }
3440
3441 static void r8168_pll_power_up(struct rtl8169_private *tp)
3442 {
3443 void __iomem *ioaddr = tp->mmio_addr;
3444
3445 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3446 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3447 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3448 r8168dp_check_dash(tp)) {
3449 return;
3450 }
3451
3452 switch (tp->mac_version) {
3453 case RTL_GIGA_MAC_VER_25:
3454 case RTL_GIGA_MAC_VER_26:
3455 case RTL_GIGA_MAC_VER_27:
3456 case RTL_GIGA_MAC_VER_28:
3457 case RTL_GIGA_MAC_VER_31:
3458 case RTL_GIGA_MAC_VER_32:
3459 case RTL_GIGA_MAC_VER_33:
3460 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3461 break;
3462 }
3463
3464 r8168_phy_power_up(tp);
3465 }
3466
3467 static void rtl_pll_power_op(struct rtl8169_private *tp,
3468 void (*op)(struct rtl8169_private *))
3469 {
3470 if (op)
3471 op(tp);
3472 }
3473
3474 static void rtl_pll_power_down(struct rtl8169_private *tp)
3475 {
3476 rtl_pll_power_op(tp, tp->pll_power_ops.down);
3477 }
3478
3479 static void rtl_pll_power_up(struct rtl8169_private *tp)
3480 {
3481 rtl_pll_power_op(tp, tp->pll_power_ops.up);
3482 }
3483
3484 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3485 {
3486 struct pll_power_ops *ops = &tp->pll_power_ops;
3487
3488 switch (tp->mac_version) {
3489 case RTL_GIGA_MAC_VER_07:
3490 case RTL_GIGA_MAC_VER_08:
3491 case RTL_GIGA_MAC_VER_09:
3492 case RTL_GIGA_MAC_VER_10:
3493 case RTL_GIGA_MAC_VER_16:
3494 case RTL_GIGA_MAC_VER_29:
3495 case RTL_GIGA_MAC_VER_30:
3496 ops->down = r810x_pll_power_down;
3497 ops->up = r810x_pll_power_up;
3498 break;
3499
3500 case RTL_GIGA_MAC_VER_11:
3501 case RTL_GIGA_MAC_VER_12:
3502 case RTL_GIGA_MAC_VER_17:
3503 case RTL_GIGA_MAC_VER_18:
3504 case RTL_GIGA_MAC_VER_19:
3505 case RTL_GIGA_MAC_VER_20:
3506 case RTL_GIGA_MAC_VER_21:
3507 case RTL_GIGA_MAC_VER_22:
3508 case RTL_GIGA_MAC_VER_23:
3509 case RTL_GIGA_MAC_VER_24:
3510 case RTL_GIGA_MAC_VER_25:
3511 case RTL_GIGA_MAC_VER_26:
3512 case RTL_GIGA_MAC_VER_27:
3513 case RTL_GIGA_MAC_VER_28:
3514 case RTL_GIGA_MAC_VER_31:
3515 case RTL_GIGA_MAC_VER_32:
3516 case RTL_GIGA_MAC_VER_33:
3517 case RTL_GIGA_MAC_VER_34:
3518 ops->down = r8168_pll_power_down;
3519 ops->up = r8168_pll_power_up;
3520 break;
3521
3522 default:
3523 ops->down = NULL;
3524 ops->up = NULL;
3525 break;
3526 }
3527 }
3528
3529 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3530 {
3531 void __iomem *ioaddr = tp->mmio_addr;
3532
3533 switch (tp->mac_version) {
3534 case RTL_GIGA_MAC_VER_01:
3535 case RTL_GIGA_MAC_VER_02:
3536 case RTL_GIGA_MAC_VER_03:
3537 case RTL_GIGA_MAC_VER_04:
3538 case RTL_GIGA_MAC_VER_05:
3539 case RTL_GIGA_MAC_VER_06:
3540 case RTL_GIGA_MAC_VER_10:
3541 case RTL_GIGA_MAC_VER_11:
3542 case RTL_GIGA_MAC_VER_12:
3543 case RTL_GIGA_MAC_VER_13:
3544 case RTL_GIGA_MAC_VER_14:
3545 case RTL_GIGA_MAC_VER_15:
3546 case RTL_GIGA_MAC_VER_16:
3547 case RTL_GIGA_MAC_VER_17:
3548 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3549 break;
3550 case RTL_GIGA_MAC_VER_18:
3551 case RTL_GIGA_MAC_VER_19:
3552 case RTL_GIGA_MAC_VER_20:
3553 case RTL_GIGA_MAC_VER_21:
3554 case RTL_GIGA_MAC_VER_22:
3555 case RTL_GIGA_MAC_VER_23:
3556 case RTL_GIGA_MAC_VER_24:
3557 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3558 break;
3559 default:
3560 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3561 break;
3562 }
3563 }
3564
3565 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3566 {
3567 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3568 }
3569
3570 static void rtl_hw_reset(struct rtl8169_private *tp)
3571 {
3572 void __iomem *ioaddr = tp->mmio_addr;
3573 int i;
3574
3575 /* Soft reset the chip. */
3576 RTL_W8(ChipCmd, CmdReset);
3577
3578 /* Check that the chip has finished the reset. */
3579 for (i = 0; i < 100; i++) {
3580 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3581 break;
3582 udelay(100);
3583 }
3584
3585 rtl8169_init_ring_indexes(tp);
3586 }
3587
3588 static int __devinit
3589 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3590 {
3591 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3592 const unsigned int region = cfg->region;
3593 struct rtl8169_private *tp;
3594 struct mii_if_info *mii;
3595 struct net_device *dev;
3596 void __iomem *ioaddr;
3597 int chipset, i;
3598 int rc;
3599
3600 if (netif_msg_drv(&debug)) {
3601 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3602 MODULENAME, RTL8169_VERSION);
3603 }
3604
3605 dev = alloc_etherdev(sizeof (*tp));
3606 if (!dev) {
3607 if (netif_msg_drv(&debug))
3608 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3609 rc = -ENOMEM;
3610 goto out;
3611 }
3612
3613 SET_NETDEV_DEV(dev, &pdev->dev);
3614 dev->netdev_ops = &rtl8169_netdev_ops;
3615 tp = netdev_priv(dev);
3616 tp->dev = dev;
3617 tp->pci_dev = pdev;
3618 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3619
3620 mii = &tp->mii;
3621 mii->dev = dev;
3622 mii->mdio_read = rtl_mdio_read;
3623 mii->mdio_write = rtl_mdio_write;
3624 mii->phy_id_mask = 0x1f;
3625 mii->reg_num_mask = 0x1f;
3626 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3627
3628 /* disable ASPM completely as that cause random device stop working
3629 * problems as well as full system hangs for some PCIe devices users */
3630 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3631 PCIE_LINK_STATE_CLKPM);
3632
3633 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3634 rc = pci_enable_device(pdev);
3635 if (rc < 0) {
3636 netif_err(tp, probe, dev, "enable failure\n");
3637 goto err_out_free_dev_1;
3638 }
3639
3640 if (pci_set_mwi(pdev) < 0)
3641 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3642
3643 /* make sure PCI base addr 1 is MMIO */
3644 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3645 netif_err(tp, probe, dev,
3646 "region #%d not an MMIO resource, aborting\n",
3647 region);
3648 rc = -ENODEV;
3649 goto err_out_mwi_2;
3650 }
3651
3652 /* check for weird/broken PCI region reporting */
3653 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3654 netif_err(tp, probe, dev,
3655 "Invalid PCI region size(s), aborting\n");
3656 rc = -ENODEV;
3657 goto err_out_mwi_2;
3658 }
3659
3660 rc = pci_request_regions(pdev, MODULENAME);
3661 if (rc < 0) {
3662 netif_err(tp, probe, dev, "could not request regions\n");
3663 goto err_out_mwi_2;
3664 }
3665
3666 tp->cp_cmd = RxChkSum;
3667
3668 if ((sizeof(dma_addr_t) > 4) &&
3669 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3670 tp->cp_cmd |= PCIDAC;
3671 dev->features |= NETIF_F_HIGHDMA;
3672 } else {
3673 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3674 if (rc < 0) {
3675 netif_err(tp, probe, dev, "DMA configuration failed\n");
3676 goto err_out_free_res_3;
3677 }
3678 }
3679
3680 /* ioremap MMIO region */
3681 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3682 if (!ioaddr) {
3683 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3684 rc = -EIO;
3685 goto err_out_free_res_3;
3686 }
3687 tp->mmio_addr = ioaddr;
3688
3689 if (!pci_is_pcie(pdev))
3690 netif_info(tp, probe, dev, "not PCI Express\n");
3691
3692 /* Identify chip attached to board */
3693 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3694
3695 rtl_init_rxcfg(tp);
3696
3697 RTL_W16(IntrMask, 0x0000);
3698
3699 rtl_hw_reset(tp);
3700
3701 RTL_W16(IntrStatus, 0xffff);
3702
3703 pci_set_master(pdev);
3704
3705 /*
3706 * Pretend we are using VLANs; This bypasses a nasty bug where
3707 * Interrupts stop flowing on high load on 8110SCd controllers.
3708 */
3709 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3710 tp->cp_cmd |= RxVlan;
3711
3712 rtl_init_mdio_ops(tp);
3713 rtl_init_pll_power_ops(tp);
3714
3715 rtl8169_print_mac_version(tp);
3716
3717 chipset = tp->mac_version;
3718 tp->txd_version = rtl_chip_infos[chipset].txd_version;
3719
3720 RTL_W8(Cfg9346, Cfg9346_Unlock);
3721 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3722 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3723 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3724 tp->features |= RTL_FEATURE_WOL;
3725 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3726 tp->features |= RTL_FEATURE_WOL;
3727 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3728 RTL_W8(Cfg9346, Cfg9346_Lock);
3729
3730 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3731 (RTL_R8(PHYstatus) & TBI_Enable)) {
3732 tp->set_speed = rtl8169_set_speed_tbi;
3733 tp->get_settings = rtl8169_gset_tbi;
3734 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3735 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3736 tp->link_ok = rtl8169_tbi_link_ok;
3737 tp->do_ioctl = rtl_tbi_ioctl;
3738 } else {
3739 tp->set_speed = rtl8169_set_speed_xmii;
3740 tp->get_settings = rtl8169_gset_xmii;
3741 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3742 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3743 tp->link_ok = rtl8169_xmii_link_ok;
3744 tp->do_ioctl = rtl_xmii_ioctl;
3745 }
3746
3747 spin_lock_init(&tp->lock);
3748
3749 /* Get MAC address */
3750 for (i = 0; i < MAC_ADDR_LEN; i++)
3751 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3752 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3753
3754 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3755 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3756 dev->irq = pdev->irq;
3757 dev->base_addr = (unsigned long) ioaddr;
3758
3759 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3760
3761 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3762 * properly for all devices */
3763 dev->features |= NETIF_F_RXCSUM |
3764 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3765
3766 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3767 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3768 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3769 NETIF_F_HIGHDMA;
3770
3771 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3772 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3773 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3774
3775 tp->intr_mask = 0xffff;
3776 tp->hw_start = cfg->hw_start;
3777 tp->intr_event = cfg->intr_event;
3778 tp->napi_event = cfg->napi_event;
3779
3780 init_timer(&tp->timer);
3781 tp->timer.data = (unsigned long) dev;
3782 tp->timer.function = rtl8169_phy_timer;
3783
3784 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
3785
3786 rc = register_netdev(dev);
3787 if (rc < 0)
3788 goto err_out_msi_4;
3789
3790 pci_set_drvdata(pdev, dev);
3791
3792 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3793 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
3794 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3795
3796 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3797 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3798 tp->mac_version == RTL_GIGA_MAC_VER_31) {
3799 rtl8168_driver_start(tp);
3800 }
3801
3802 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3803
3804 if (pci_dev_run_wake(pdev))
3805 pm_runtime_put_noidle(&pdev->dev);
3806
3807 netif_carrier_off(dev);
3808
3809 out:
3810 return rc;
3811
3812 err_out_msi_4:
3813 rtl_disable_msi(pdev, tp);
3814 iounmap(ioaddr);
3815 err_out_free_res_3:
3816 pci_release_regions(pdev);
3817 err_out_mwi_2:
3818 pci_clear_mwi(pdev);
3819 pci_disable_device(pdev);
3820 err_out_free_dev_1:
3821 free_netdev(dev);
3822 goto out;
3823 }
3824
3825 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3826 {
3827 struct net_device *dev = pci_get_drvdata(pdev);
3828 struct rtl8169_private *tp = netdev_priv(dev);
3829
3830 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3831 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3832 tp->mac_version == RTL_GIGA_MAC_VER_31) {
3833 rtl8168_driver_stop(tp);
3834 }
3835
3836 cancel_delayed_work_sync(&tp->task);
3837
3838 unregister_netdev(dev);
3839
3840 rtl_release_firmware(tp);
3841
3842 if (pci_dev_run_wake(pdev))
3843 pm_runtime_get_noresume(&pdev->dev);
3844
3845 /* restore original MAC address */
3846 rtl_rar_set(tp, dev->perm_addr);
3847
3848 rtl_disable_msi(pdev, tp);
3849 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3850 pci_set_drvdata(pdev, NULL);
3851 }
3852
3853 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3854 {
3855 struct rtl_fw *rtl_fw;
3856 const char *name;
3857 int rc = -ENOMEM;
3858
3859 name = rtl_lookup_firmware_name(tp);
3860 if (!name)
3861 goto out_no_firmware;
3862
3863 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3864 if (!rtl_fw)
3865 goto err_warn;
3866
3867 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3868 if (rc < 0)
3869 goto err_free;
3870
3871 rc = rtl_check_firmware(tp, rtl_fw);
3872 if (rc < 0)
3873 goto err_release_firmware;
3874
3875 tp->rtl_fw = rtl_fw;
3876 out:
3877 return;
3878
3879 err_release_firmware:
3880 release_firmware(rtl_fw->fw);
3881 err_free:
3882 kfree(rtl_fw);
3883 err_warn:
3884 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3885 name, rc);
3886 out_no_firmware:
3887 tp->rtl_fw = NULL;
3888 goto out;
3889 }
3890
3891 static void rtl_request_firmware(struct rtl8169_private *tp)
3892 {
3893 if (IS_ERR(tp->rtl_fw))
3894 rtl_request_uncached_firmware(tp);
3895 }
3896
3897 static int rtl8169_open(struct net_device *dev)
3898 {
3899 struct rtl8169_private *tp = netdev_priv(dev);
3900 void __iomem *ioaddr = tp->mmio_addr;
3901 struct pci_dev *pdev = tp->pci_dev;
3902 int retval = -ENOMEM;
3903
3904 pm_runtime_get_sync(&pdev->dev);
3905
3906 /*
3907 * Rx and Tx desscriptors needs 256 bytes alignment.
3908 * dma_alloc_coherent provides more.
3909 */
3910 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3911 &tp->TxPhyAddr, GFP_KERNEL);
3912 if (!tp->TxDescArray)
3913 goto err_pm_runtime_put;
3914
3915 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3916 &tp->RxPhyAddr, GFP_KERNEL);
3917 if (!tp->RxDescArray)
3918 goto err_free_tx_0;
3919
3920 retval = rtl8169_init_ring(dev);
3921 if (retval < 0)
3922 goto err_free_rx_1;
3923
3924 INIT_DELAYED_WORK(&tp->task, NULL);
3925
3926 smp_mb();
3927
3928 rtl_request_firmware(tp);
3929
3930 retval = request_irq(dev->irq, rtl8169_interrupt,
3931 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3932 dev->name, dev);
3933 if (retval < 0)
3934 goto err_release_fw_2;
3935
3936 napi_enable(&tp->napi);
3937
3938 rtl8169_init_phy(dev, tp);
3939
3940 rtl8169_set_features(dev, dev->features);
3941
3942 rtl_pll_power_up(tp);
3943
3944 rtl_hw_start(dev);
3945
3946 tp->saved_wolopts = 0;
3947 pm_runtime_put_noidle(&pdev->dev);
3948
3949 rtl8169_check_link_status(dev, tp, ioaddr);
3950 out:
3951 return retval;
3952
3953 err_release_fw_2:
3954 rtl_release_firmware(tp);
3955 rtl8169_rx_clear(tp);
3956 err_free_rx_1:
3957 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3958 tp->RxPhyAddr);
3959 tp->RxDescArray = NULL;
3960 err_free_tx_0:
3961 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3962 tp->TxPhyAddr);
3963 tp->TxDescArray = NULL;
3964 err_pm_runtime_put:
3965 pm_runtime_put_noidle(&pdev->dev);
3966 goto out;
3967 }
3968
3969 static void rtl_rx_close(struct rtl8169_private *tp)
3970 {
3971 void __iomem *ioaddr = tp->mmio_addr;
3972
3973 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
3974 }
3975
3976 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3977 {
3978 void __iomem *ioaddr = tp->mmio_addr;
3979
3980 /* Disable interrupts */
3981 rtl8169_irq_mask_and_ack(ioaddr);
3982
3983 rtl_rx_close(tp);
3984
3985 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3986 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3987 tp->mac_version == RTL_GIGA_MAC_VER_31) {
3988 while (RTL_R8(TxPoll) & NPQ)
3989 udelay(20);
3990 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3991 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
3992 udelay(100);
3993 } else {
3994 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
3995 udelay(100);
3996 }
3997
3998 rtl_hw_reset(tp);
3999 }
4000
4001 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4002 {
4003 void __iomem *ioaddr = tp->mmio_addr;
4004
4005 /* Set DMA burst size and Interframe Gap Time */
4006 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4007 (InterFrameGap << TxInterFrameGapShift));
4008 }
4009
4010 static void rtl_hw_start(struct net_device *dev)
4011 {
4012 struct rtl8169_private *tp = netdev_priv(dev);
4013
4014 tp->hw_start(dev);
4015
4016 netif_start_queue(dev);
4017 }
4018
4019 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4020 void __iomem *ioaddr)
4021 {
4022 /*
4023 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4024 * register to be written before TxDescAddrLow to work.
4025 * Switching from MMIO to I/O access fixes the issue as well.
4026 */
4027 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4028 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4029 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4030 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4031 }
4032
4033 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4034 {
4035 u16 cmd;
4036
4037 cmd = RTL_R16(CPlusCmd);
4038 RTL_W16(CPlusCmd, cmd);
4039 return cmd;
4040 }
4041
4042 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4043 {
4044 /* Low hurts. Let's disable the filtering. */
4045 RTL_W16(RxMaxSize, rx_buf_sz + 1);
4046 }
4047
4048 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4049 {
4050 static const struct rtl_cfg2_info {
4051 u32 mac_version;
4052 u32 clk;
4053 u32 val;
4054 } cfg2_info [] = {
4055 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4056 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4057 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4058 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4059 };
4060 const struct rtl_cfg2_info *p = cfg2_info;
4061 unsigned int i;
4062 u32 clk;
4063
4064 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4065 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4066 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4067 RTL_W32(0x7c, p->val);
4068 break;
4069 }
4070 }
4071 }
4072
4073 static void rtl_hw_start_8169(struct net_device *dev)
4074 {
4075 struct rtl8169_private *tp = netdev_priv(dev);
4076 void __iomem *ioaddr = tp->mmio_addr;
4077 struct pci_dev *pdev = tp->pci_dev;
4078
4079 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4080 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4081 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4082 }
4083
4084 RTL_W8(Cfg9346, Cfg9346_Unlock);
4085 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4086 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4087 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4088 tp->mac_version == RTL_GIGA_MAC_VER_04)
4089 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4090
4091 rtl_init_rxcfg(tp);
4092
4093 RTL_W8(EarlyTxThres, NoEarlyTx);
4094
4095 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4096
4097 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4098 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4099 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4100 tp->mac_version == RTL_GIGA_MAC_VER_04)
4101 rtl_set_rx_tx_config_registers(tp);
4102
4103 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4104
4105 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4106 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4107 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4108 "Bit-3 and bit-14 MUST be 1\n");
4109 tp->cp_cmd |= (1 << 14);
4110 }
4111
4112 RTL_W16(CPlusCmd, tp->cp_cmd);
4113
4114 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4115
4116 /*
4117 * Undocumented corner. Supposedly:
4118 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4119 */
4120 RTL_W16(IntrMitigate, 0x0000);
4121
4122 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4123
4124 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4125 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4126 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4127 tp->mac_version != RTL_GIGA_MAC_VER_04) {
4128 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4129 rtl_set_rx_tx_config_registers(tp);
4130 }
4131
4132 RTL_W8(Cfg9346, Cfg9346_Lock);
4133
4134 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4135 RTL_R8(IntrMask);
4136
4137 RTL_W32(RxMissed, 0);
4138
4139 rtl_set_rx_mode(dev);
4140
4141 /* no early-rx interrupts */
4142 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4143
4144 /* Enable all known interrupts by setting the interrupt mask. */
4145 RTL_W16(IntrMask, tp->intr_event);
4146 }
4147
4148 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
4149 {
4150 int cap = pci_pcie_cap(pdev);
4151
4152 if (cap) {
4153 u16 ctl;
4154
4155 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
4156 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
4157 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
4158 }
4159 }
4160
4161 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4162 {
4163 u32 csi;
4164
4165 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4166 rtl_csi_write(ioaddr, 0x070c, csi | bits);
4167 }
4168
4169 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4170 {
4171 rtl_csi_access_enable(ioaddr, 0x17000000);
4172 }
4173
4174 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4175 {
4176 rtl_csi_access_enable(ioaddr, 0x27000000);
4177 }
4178
4179 struct ephy_info {
4180 unsigned int offset;
4181 u16 mask;
4182 u16 bits;
4183 };
4184
4185 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4186 {
4187 u16 w;
4188
4189 while (len-- > 0) {
4190 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4191 rtl_ephy_write(ioaddr, e->offset, w);
4192 e++;
4193 }
4194 }
4195
4196 static void rtl_disable_clock_request(struct pci_dev *pdev)
4197 {
4198 int cap = pci_pcie_cap(pdev);
4199
4200 if (cap) {
4201 u16 ctl;
4202
4203 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4204 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4205 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4206 }
4207 }
4208
4209 static void rtl_enable_clock_request(struct pci_dev *pdev)
4210 {
4211 int cap = pci_pcie_cap(pdev);
4212
4213 if (cap) {
4214 u16 ctl;
4215
4216 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4217 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4218 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4219 }
4220 }
4221
4222 #define R8168_CPCMD_QUIRK_MASK (\
4223 EnableBist | \
4224 Mac_dbgo_oe | \
4225 Force_half_dup | \
4226 Force_rxflow_en | \
4227 Force_txflow_en | \
4228 Cxpl_dbg_sel | \
4229 ASF | \
4230 PktCntrDisable | \
4231 Mac_dbgo_sel)
4232
4233 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4234 {
4235 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4236
4237 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4238
4239 rtl_tx_performance_tweak(pdev,
4240 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4241 }
4242
4243 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4244 {
4245 rtl_hw_start_8168bb(ioaddr, pdev);
4246
4247 RTL_W8(MaxTxPacketSize, TxPacketMax);
4248
4249 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4250 }
4251
4252 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4253 {
4254 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4255
4256 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4257
4258 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4259
4260 rtl_disable_clock_request(pdev);
4261
4262 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4263 }
4264
4265 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4266 {
4267 static const struct ephy_info e_info_8168cp[] = {
4268 { 0x01, 0, 0x0001 },
4269 { 0x02, 0x0800, 0x1000 },
4270 { 0x03, 0, 0x0042 },
4271 { 0x06, 0x0080, 0x0000 },
4272 { 0x07, 0, 0x2000 }
4273 };
4274
4275 rtl_csi_access_enable_2(ioaddr);
4276
4277 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4278
4279 __rtl_hw_start_8168cp(ioaddr, pdev);
4280 }
4281
4282 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4283 {
4284 rtl_csi_access_enable_2(ioaddr);
4285
4286 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4287
4288 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4289
4290 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4291 }
4292
4293 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4294 {
4295 rtl_csi_access_enable_2(ioaddr);
4296
4297 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4298
4299 /* Magic. */
4300 RTL_W8(DBG_REG, 0x20);
4301
4302 RTL_W8(MaxTxPacketSize, TxPacketMax);
4303
4304 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4305
4306 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4307 }
4308
4309 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4310 {
4311 static const struct ephy_info e_info_8168c_1[] = {
4312 { 0x02, 0x0800, 0x1000 },
4313 { 0x03, 0, 0x0002 },
4314 { 0x06, 0x0080, 0x0000 }
4315 };
4316
4317 rtl_csi_access_enable_2(ioaddr);
4318
4319 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4320
4321 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4322
4323 __rtl_hw_start_8168cp(ioaddr, pdev);
4324 }
4325
4326 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4327 {
4328 static const struct ephy_info e_info_8168c_2[] = {
4329 { 0x01, 0, 0x0001 },
4330 { 0x03, 0x0400, 0x0220 }
4331 };
4332
4333 rtl_csi_access_enable_2(ioaddr);
4334
4335 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4336
4337 __rtl_hw_start_8168cp(ioaddr, pdev);
4338 }
4339
4340 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4341 {
4342 rtl_hw_start_8168c_2(ioaddr, pdev);
4343 }
4344
4345 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4346 {
4347 rtl_csi_access_enable_2(ioaddr);
4348
4349 __rtl_hw_start_8168cp(ioaddr, pdev);
4350 }
4351
4352 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4353 {
4354 rtl_csi_access_enable_2(ioaddr);
4355
4356 rtl_disable_clock_request(pdev);
4357
4358 RTL_W8(MaxTxPacketSize, TxPacketMax);
4359
4360 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4361
4362 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4363 }
4364
4365 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4366 {
4367 rtl_csi_access_enable_1(ioaddr);
4368
4369 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4370
4371 RTL_W8(MaxTxPacketSize, TxPacketMax);
4372
4373 rtl_disable_clock_request(pdev);
4374 }
4375
4376 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4377 {
4378 static const struct ephy_info e_info_8168d_4[] = {
4379 { 0x0b, ~0, 0x48 },
4380 { 0x19, 0x20, 0x50 },
4381 { 0x0c, ~0, 0x20 }
4382 };
4383 int i;
4384
4385 rtl_csi_access_enable_1(ioaddr);
4386
4387 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4388
4389 RTL_W8(MaxTxPacketSize, TxPacketMax);
4390
4391 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4392 const struct ephy_info *e = e_info_8168d_4 + i;
4393 u16 w;
4394
4395 w = rtl_ephy_read(ioaddr, e->offset);
4396 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4397 }
4398
4399 rtl_enable_clock_request(pdev);
4400 }
4401
4402 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4403 {
4404 static const struct ephy_info e_info_8168e_1[] = {
4405 { 0x00, 0x0200, 0x0100 },
4406 { 0x00, 0x0000, 0x0004 },
4407 { 0x06, 0x0002, 0x0001 },
4408 { 0x06, 0x0000, 0x0030 },
4409 { 0x07, 0x0000, 0x2000 },
4410 { 0x00, 0x0000, 0x0020 },
4411 { 0x03, 0x5800, 0x2000 },
4412 { 0x03, 0x0000, 0x0001 },
4413 { 0x01, 0x0800, 0x1000 },
4414 { 0x07, 0x0000, 0x4000 },
4415 { 0x1e, 0x0000, 0x2000 },
4416 { 0x19, 0xffff, 0xfe6c },
4417 { 0x0a, 0x0000, 0x0040 }
4418 };
4419
4420 rtl_csi_access_enable_2(ioaddr);
4421
4422 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4423
4424 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4425
4426 RTL_W8(MaxTxPacketSize, TxPacketMax);
4427
4428 rtl_disable_clock_request(pdev);
4429
4430 /* Reset tx FIFO pointer */
4431 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4432 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4433
4434 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4435 }
4436
4437 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4438 {
4439 static const struct ephy_info e_info_8168e_2[] = {
4440 { 0x09, 0x0000, 0x0080 },
4441 { 0x19, 0x0000, 0x0224 }
4442 };
4443
4444 rtl_csi_access_enable_1(ioaddr);
4445
4446 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4447
4448 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4449
4450 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4451 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4452 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4453 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4454 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4455 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4456 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4457 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4458 ERIAR_EXGMAC);
4459
4460 RTL_W8(MaxTxPacketSize, 0x27);
4461
4462 rtl_disable_clock_request(pdev);
4463
4464 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4465 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4466
4467 /* Adjust EEE LED frequency */
4468 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4469
4470 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4471 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4472 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4473 }
4474
4475 static void rtl_hw_start_8168(struct net_device *dev)
4476 {
4477 struct rtl8169_private *tp = netdev_priv(dev);
4478 void __iomem *ioaddr = tp->mmio_addr;
4479 struct pci_dev *pdev = tp->pci_dev;
4480
4481 RTL_W8(Cfg9346, Cfg9346_Unlock);
4482
4483 RTL_W8(MaxTxPacketSize, TxPacketMax);
4484
4485 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4486
4487 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4488
4489 RTL_W16(CPlusCmd, tp->cp_cmd);
4490
4491 RTL_W16(IntrMitigate, 0x5151);
4492
4493 /* Work around for RxFIFO overflow. */
4494 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4495 tp->mac_version == RTL_GIGA_MAC_VER_22) {
4496 tp->intr_event |= RxFIFOOver | PCSTimeout;
4497 tp->intr_event &= ~RxOverflow;
4498 }
4499
4500 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4501
4502 rtl_set_rx_mode(dev);
4503
4504 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4505 (InterFrameGap << TxInterFrameGapShift));
4506
4507 RTL_R8(IntrMask);
4508
4509 switch (tp->mac_version) {
4510 case RTL_GIGA_MAC_VER_11:
4511 rtl_hw_start_8168bb(ioaddr, pdev);
4512 break;
4513
4514 case RTL_GIGA_MAC_VER_12:
4515 case RTL_GIGA_MAC_VER_17:
4516 rtl_hw_start_8168bef(ioaddr, pdev);
4517 break;
4518
4519 case RTL_GIGA_MAC_VER_18:
4520 rtl_hw_start_8168cp_1(ioaddr, pdev);
4521 break;
4522
4523 case RTL_GIGA_MAC_VER_19:
4524 rtl_hw_start_8168c_1(ioaddr, pdev);
4525 break;
4526
4527 case RTL_GIGA_MAC_VER_20:
4528 rtl_hw_start_8168c_2(ioaddr, pdev);
4529 break;
4530
4531 case RTL_GIGA_MAC_VER_21:
4532 rtl_hw_start_8168c_3(ioaddr, pdev);
4533 break;
4534
4535 case RTL_GIGA_MAC_VER_22:
4536 rtl_hw_start_8168c_4(ioaddr, pdev);
4537 break;
4538
4539 case RTL_GIGA_MAC_VER_23:
4540 rtl_hw_start_8168cp_2(ioaddr, pdev);
4541 break;
4542
4543 case RTL_GIGA_MAC_VER_24:
4544 rtl_hw_start_8168cp_3(ioaddr, pdev);
4545 break;
4546
4547 case RTL_GIGA_MAC_VER_25:
4548 case RTL_GIGA_MAC_VER_26:
4549 case RTL_GIGA_MAC_VER_27:
4550 rtl_hw_start_8168d(ioaddr, pdev);
4551 break;
4552
4553 case RTL_GIGA_MAC_VER_28:
4554 rtl_hw_start_8168d_4(ioaddr, pdev);
4555 break;
4556
4557 case RTL_GIGA_MAC_VER_31:
4558 rtl_hw_start_8168dp(ioaddr, pdev);
4559 break;
4560
4561 case RTL_GIGA_MAC_VER_32:
4562 case RTL_GIGA_MAC_VER_33:
4563 rtl_hw_start_8168e_1(ioaddr, pdev);
4564 break;
4565 case RTL_GIGA_MAC_VER_34:
4566 rtl_hw_start_8168e_2(ioaddr, pdev);
4567 break;
4568
4569 default:
4570 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4571 dev->name, tp->mac_version);
4572 break;
4573 }
4574
4575 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4576
4577 RTL_W8(Cfg9346, Cfg9346_Lock);
4578
4579 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4580
4581 RTL_W16(IntrMask, tp->intr_event);
4582 }
4583
4584 #define R810X_CPCMD_QUIRK_MASK (\
4585 EnableBist | \
4586 Mac_dbgo_oe | \
4587 Force_half_dup | \
4588 Force_rxflow_en | \
4589 Force_txflow_en | \
4590 Cxpl_dbg_sel | \
4591 ASF | \
4592 PktCntrDisable | \
4593 Mac_dbgo_sel)
4594
4595 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4596 {
4597 static const struct ephy_info e_info_8102e_1[] = {
4598 { 0x01, 0, 0x6e65 },
4599 { 0x02, 0, 0x091f },
4600 { 0x03, 0, 0xc2f9 },
4601 { 0x06, 0, 0xafb5 },
4602 { 0x07, 0, 0x0e00 },
4603 { 0x19, 0, 0xec80 },
4604 { 0x01, 0, 0x2e65 },
4605 { 0x01, 0, 0x6e65 }
4606 };
4607 u8 cfg1;
4608
4609 rtl_csi_access_enable_2(ioaddr);
4610
4611 RTL_W8(DBG_REG, FIX_NAK_1);
4612
4613 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4614
4615 RTL_W8(Config1,
4616 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4617 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4618
4619 cfg1 = RTL_R8(Config1);
4620 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4621 RTL_W8(Config1, cfg1 & ~LEDS0);
4622
4623 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4624 }
4625
4626 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4627 {
4628 rtl_csi_access_enable_2(ioaddr);
4629
4630 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4631
4632 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4633 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4634 }
4635
4636 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4637 {
4638 rtl_hw_start_8102e_2(ioaddr, pdev);
4639
4640 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4641 }
4642
4643 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4644 {
4645 static const struct ephy_info e_info_8105e_1[] = {
4646 { 0x07, 0, 0x4000 },
4647 { 0x19, 0, 0x0200 },
4648 { 0x19, 0, 0x0020 },
4649 { 0x1e, 0, 0x2000 },
4650 { 0x03, 0, 0x0001 },
4651 { 0x19, 0, 0x0100 },
4652 { 0x19, 0, 0x0004 },
4653 { 0x0a, 0, 0x0020 }
4654 };
4655
4656 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4657 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4658
4659 /* Disable Early Tally Counter */
4660 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4661
4662 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4663 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4664
4665 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4666 }
4667
4668 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4669 {
4670 rtl_hw_start_8105e_1(ioaddr, pdev);
4671 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4672 }
4673
4674 static void rtl_hw_start_8101(struct net_device *dev)
4675 {
4676 struct rtl8169_private *tp = netdev_priv(dev);
4677 void __iomem *ioaddr = tp->mmio_addr;
4678 struct pci_dev *pdev = tp->pci_dev;
4679
4680 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4681 tp->mac_version == RTL_GIGA_MAC_VER_16) {
4682 int cap = pci_pcie_cap(pdev);
4683
4684 if (cap) {
4685 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4686 PCI_EXP_DEVCTL_NOSNOOP_EN);
4687 }
4688 }
4689
4690 RTL_W8(Cfg9346, Cfg9346_Unlock);
4691
4692 switch (tp->mac_version) {
4693 case RTL_GIGA_MAC_VER_07:
4694 rtl_hw_start_8102e_1(ioaddr, pdev);
4695 break;
4696
4697 case RTL_GIGA_MAC_VER_08:
4698 rtl_hw_start_8102e_3(ioaddr, pdev);
4699 break;
4700
4701 case RTL_GIGA_MAC_VER_09:
4702 rtl_hw_start_8102e_2(ioaddr, pdev);
4703 break;
4704
4705 case RTL_GIGA_MAC_VER_29:
4706 rtl_hw_start_8105e_1(ioaddr, pdev);
4707 break;
4708 case RTL_GIGA_MAC_VER_30:
4709 rtl_hw_start_8105e_2(ioaddr, pdev);
4710 break;
4711 }
4712
4713 RTL_W8(Cfg9346, Cfg9346_Lock);
4714
4715 RTL_W8(MaxTxPacketSize, TxPacketMax);
4716
4717 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4718
4719 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4720 RTL_W16(CPlusCmd, tp->cp_cmd);
4721
4722 RTL_W16(IntrMitigate, 0x0000);
4723
4724 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4725
4726 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4727 rtl_set_rx_tx_config_registers(tp);
4728
4729 RTL_R8(IntrMask);
4730
4731 rtl_set_rx_mode(dev);
4732
4733 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4734
4735 RTL_W16(IntrMask, tp->intr_event);
4736 }
4737
4738 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4739 {
4740 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4741 return -EINVAL;
4742
4743 dev->mtu = new_mtu;
4744 netdev_update_features(dev);
4745
4746 return 0;
4747 }
4748
4749 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4750 {
4751 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4752 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4753 }
4754
4755 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4756 void **data_buff, struct RxDesc *desc)
4757 {
4758 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4759 DMA_FROM_DEVICE);
4760
4761 kfree(*data_buff);
4762 *data_buff = NULL;
4763 rtl8169_make_unusable_by_asic(desc);
4764 }
4765
4766 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4767 {
4768 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4769
4770 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4771 }
4772
4773 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4774 u32 rx_buf_sz)
4775 {
4776 desc->addr = cpu_to_le64(mapping);
4777 wmb();
4778 rtl8169_mark_to_asic(desc, rx_buf_sz);
4779 }
4780
4781 static inline void *rtl8169_align(void *data)
4782 {
4783 return (void *)ALIGN((long)data, 16);
4784 }
4785
4786 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4787 struct RxDesc *desc)
4788 {
4789 void *data;
4790 dma_addr_t mapping;
4791 struct device *d = &tp->pci_dev->dev;
4792 struct net_device *dev = tp->dev;
4793 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4794
4795 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4796 if (!data)
4797 return NULL;
4798
4799 if (rtl8169_align(data) != data) {
4800 kfree(data);
4801 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4802 if (!data)
4803 return NULL;
4804 }
4805
4806 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4807 DMA_FROM_DEVICE);
4808 if (unlikely(dma_mapping_error(d, mapping))) {
4809 if (net_ratelimit())
4810 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4811 goto err_out;
4812 }
4813
4814 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4815 return data;
4816
4817 err_out:
4818 kfree(data);
4819 return NULL;
4820 }
4821
4822 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4823 {
4824 unsigned int i;
4825
4826 for (i = 0; i < NUM_RX_DESC; i++) {
4827 if (tp->Rx_databuff[i]) {
4828 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4829 tp->RxDescArray + i);
4830 }
4831 }
4832 }
4833
4834 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4835 {
4836 desc->opts1 |= cpu_to_le32(RingEnd);
4837 }
4838
4839 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4840 {
4841 unsigned int i;
4842
4843 for (i = 0; i < NUM_RX_DESC; i++) {
4844 void *data;
4845
4846 if (tp->Rx_databuff[i])
4847 continue;
4848
4849 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4850 if (!data) {
4851 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4852 goto err_out;
4853 }
4854 tp->Rx_databuff[i] = data;
4855 }
4856
4857 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4858 return 0;
4859
4860 err_out:
4861 rtl8169_rx_clear(tp);
4862 return -ENOMEM;
4863 }
4864
4865 static int rtl8169_init_ring(struct net_device *dev)
4866 {
4867 struct rtl8169_private *tp = netdev_priv(dev);
4868
4869 rtl8169_init_ring_indexes(tp);
4870
4871 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4872 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4873
4874 return rtl8169_rx_fill(tp);
4875 }
4876
4877 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4878 struct TxDesc *desc)
4879 {
4880 unsigned int len = tx_skb->len;
4881
4882 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4883
4884 desc->opts1 = 0x00;
4885 desc->opts2 = 0x00;
4886 desc->addr = 0x00;
4887 tx_skb->len = 0;
4888 }
4889
4890 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4891 unsigned int n)
4892 {
4893 unsigned int i;
4894
4895 for (i = 0; i < n; i++) {
4896 unsigned int entry = (start + i) % NUM_TX_DESC;
4897 struct ring_info *tx_skb = tp->tx_skb + entry;
4898 unsigned int len = tx_skb->len;
4899
4900 if (len) {
4901 struct sk_buff *skb = tx_skb->skb;
4902
4903 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4904 tp->TxDescArray + entry);
4905 if (skb) {
4906 tp->dev->stats.tx_dropped++;
4907 dev_kfree_skb(skb);
4908 tx_skb->skb = NULL;
4909 }
4910 }
4911 }
4912 }
4913
4914 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4915 {
4916 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4917 tp->cur_tx = tp->dirty_tx = 0;
4918 }
4919
4920 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4921 {
4922 struct rtl8169_private *tp = netdev_priv(dev);
4923
4924 PREPARE_DELAYED_WORK(&tp->task, task);
4925 schedule_delayed_work(&tp->task, 4);
4926 }
4927
4928 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4929 {
4930 struct rtl8169_private *tp = netdev_priv(dev);
4931 void __iomem *ioaddr = tp->mmio_addr;
4932
4933 synchronize_irq(dev->irq);
4934
4935 /* Wait for any pending NAPI task to complete */
4936 napi_disable(&tp->napi);
4937
4938 rtl8169_irq_mask_and_ack(ioaddr);
4939
4940 tp->intr_mask = 0xffff;
4941 RTL_W16(IntrMask, tp->intr_event);
4942 napi_enable(&tp->napi);
4943 }
4944
4945 static void rtl8169_reinit_task(struct work_struct *work)
4946 {
4947 struct rtl8169_private *tp =
4948 container_of(work, struct rtl8169_private, task.work);
4949 struct net_device *dev = tp->dev;
4950 int ret;
4951
4952 rtnl_lock();
4953
4954 if (!netif_running(dev))
4955 goto out_unlock;
4956
4957 rtl8169_wait_for_quiescence(dev);
4958 rtl8169_close(dev);
4959
4960 ret = rtl8169_open(dev);
4961 if (unlikely(ret < 0)) {
4962 if (net_ratelimit())
4963 netif_err(tp, drv, dev,
4964 "reinit failure (status = %d). Rescheduling\n",
4965 ret);
4966 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4967 }
4968
4969 out_unlock:
4970 rtnl_unlock();
4971 }
4972
4973 static void rtl8169_reset_task(struct work_struct *work)
4974 {
4975 struct rtl8169_private *tp =
4976 container_of(work, struct rtl8169_private, task.work);
4977 struct net_device *dev = tp->dev;
4978 int i;
4979
4980 rtnl_lock();
4981
4982 if (!netif_running(dev))
4983 goto out_unlock;
4984
4985 rtl8169_wait_for_quiescence(dev);
4986
4987 for (i = 0; i < NUM_RX_DESC; i++)
4988 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4989
4990 rtl8169_tx_clear(tp);
4991
4992 rtl8169_hw_reset(tp);
4993 rtl_hw_start(dev);
4994 netif_wake_queue(dev);
4995 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4996
4997 out_unlock:
4998 rtnl_unlock();
4999 }
5000
5001 static void rtl8169_tx_timeout(struct net_device *dev)
5002 {
5003 struct rtl8169_private *tp = netdev_priv(dev);
5004
5005 rtl8169_hw_reset(tp);
5006
5007 /* Let's wait a bit while any (async) irq lands on */
5008 rtl8169_schedule_work(dev, rtl8169_reset_task);
5009 }
5010
5011 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5012 u32 *opts)
5013 {
5014 struct skb_shared_info *info = skb_shinfo(skb);
5015 unsigned int cur_frag, entry;
5016 struct TxDesc * uninitialized_var(txd);
5017 struct device *d = &tp->pci_dev->dev;
5018
5019 entry = tp->cur_tx;
5020 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5021 skb_frag_t *frag = info->frags + cur_frag;
5022 dma_addr_t mapping;
5023 u32 status, len;
5024 void *addr;
5025
5026 entry = (entry + 1) % NUM_TX_DESC;
5027
5028 txd = tp->TxDescArray + entry;
5029 len = frag->size;
5030 addr = ((void *) page_address(frag->page)) + frag->page_offset;
5031 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5032 if (unlikely(dma_mapping_error(d, mapping))) {
5033 if (net_ratelimit())
5034 netif_err(tp, drv, tp->dev,
5035 "Failed to map TX fragments DMA!\n");
5036 goto err_out;
5037 }
5038
5039 /* Anti gcc 2.95.3 bugware (sic) */
5040 status = opts[0] | len |
5041 (RingEnd * !((entry + 1) % NUM_TX_DESC));
5042
5043 txd->opts1 = cpu_to_le32(status);
5044 txd->opts2 = cpu_to_le32(opts[1]);
5045 txd->addr = cpu_to_le64(mapping);
5046
5047 tp->tx_skb[entry].len = len;
5048 }
5049
5050 if (cur_frag) {
5051 tp->tx_skb[entry].skb = skb;
5052 txd->opts1 |= cpu_to_le32(LastFrag);
5053 }
5054
5055 return cur_frag;
5056
5057 err_out:
5058 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5059 return -EIO;
5060 }
5061
5062 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5063 struct sk_buff *skb, u32 *opts)
5064 {
5065 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5066 u32 mss = skb_shinfo(skb)->gso_size;
5067 int offset = info->opts_offset;
5068
5069 if (mss) {
5070 opts[0] |= TD_LSO;
5071 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5072 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5073 const struct iphdr *ip = ip_hdr(skb);
5074
5075 if (ip->protocol == IPPROTO_TCP)
5076 opts[offset] |= info->checksum.tcp;
5077 else if (ip->protocol == IPPROTO_UDP)
5078 opts[offset] |= info->checksum.udp;
5079 else
5080 WARN_ON_ONCE(1);
5081 }
5082 }
5083
5084 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5085 struct net_device *dev)
5086 {
5087 struct rtl8169_private *tp = netdev_priv(dev);
5088 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5089 struct TxDesc *txd = tp->TxDescArray + entry;
5090 void __iomem *ioaddr = tp->mmio_addr;
5091 struct device *d = &tp->pci_dev->dev;
5092 dma_addr_t mapping;
5093 u32 status, len;
5094 u32 opts[2];
5095 int frags;
5096
5097 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
5098 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5099 goto err_stop_0;
5100 }
5101
5102 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5103 goto err_stop_0;
5104
5105 len = skb_headlen(skb);
5106 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5107 if (unlikely(dma_mapping_error(d, mapping))) {
5108 if (net_ratelimit())
5109 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5110 goto err_dma_0;
5111 }
5112
5113 tp->tx_skb[entry].len = len;
5114 txd->addr = cpu_to_le64(mapping);
5115
5116 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5117 opts[0] = DescOwn;
5118
5119 rtl8169_tso_csum(tp, skb, opts);
5120
5121 frags = rtl8169_xmit_frags(tp, skb, opts);
5122 if (frags < 0)
5123 goto err_dma_1;
5124 else if (frags)
5125 opts[0] |= FirstFrag;
5126 else {
5127 opts[0] |= FirstFrag | LastFrag;
5128 tp->tx_skb[entry].skb = skb;
5129 }
5130
5131 txd->opts2 = cpu_to_le32(opts[1]);
5132
5133 wmb();
5134
5135 /* Anti gcc 2.95.3 bugware (sic) */
5136 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5137 txd->opts1 = cpu_to_le32(status);
5138
5139 tp->cur_tx += frags + 1;
5140
5141 wmb();
5142
5143 RTL_W8(TxPoll, NPQ);
5144
5145 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5146 netif_stop_queue(dev);
5147 smp_rmb();
5148 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5149 netif_wake_queue(dev);
5150 }
5151
5152 return NETDEV_TX_OK;
5153
5154 err_dma_1:
5155 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5156 err_dma_0:
5157 dev_kfree_skb(skb);
5158 dev->stats.tx_dropped++;
5159 return NETDEV_TX_OK;
5160
5161 err_stop_0:
5162 netif_stop_queue(dev);
5163 dev->stats.tx_dropped++;
5164 return NETDEV_TX_BUSY;
5165 }
5166
5167 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5168 {
5169 struct rtl8169_private *tp = netdev_priv(dev);
5170 struct pci_dev *pdev = tp->pci_dev;
5171 u16 pci_status, pci_cmd;
5172
5173 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5174 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5175
5176 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5177 pci_cmd, pci_status);
5178
5179 /*
5180 * The recovery sequence below admits a very elaborated explanation:
5181 * - it seems to work;
5182 * - I did not see what else could be done;
5183 * - it makes iop3xx happy.
5184 *
5185 * Feel free to adjust to your needs.
5186 */
5187 if (pdev->broken_parity_status)
5188 pci_cmd &= ~PCI_COMMAND_PARITY;
5189 else
5190 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5191
5192 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5193
5194 pci_write_config_word(pdev, PCI_STATUS,
5195 pci_status & (PCI_STATUS_DETECTED_PARITY |
5196 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5197 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5198
5199 /* The infamous DAC f*ckup only happens at boot time */
5200 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5201 void __iomem *ioaddr = tp->mmio_addr;
5202
5203 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5204 tp->cp_cmd &= ~PCIDAC;
5205 RTL_W16(CPlusCmd, tp->cp_cmd);
5206 dev->features &= ~NETIF_F_HIGHDMA;
5207 }
5208
5209 rtl8169_hw_reset(tp);
5210
5211 rtl8169_schedule_work(dev, rtl8169_reinit_task);
5212 }
5213
5214 static void rtl8169_tx_interrupt(struct net_device *dev,
5215 struct rtl8169_private *tp,
5216 void __iomem *ioaddr)
5217 {
5218 unsigned int dirty_tx, tx_left;
5219
5220 dirty_tx = tp->dirty_tx;
5221 smp_rmb();
5222 tx_left = tp->cur_tx - dirty_tx;
5223
5224 while (tx_left > 0) {
5225 unsigned int entry = dirty_tx % NUM_TX_DESC;
5226 struct ring_info *tx_skb = tp->tx_skb + entry;
5227 u32 status;
5228
5229 rmb();
5230 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5231 if (status & DescOwn)
5232 break;
5233
5234 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5235 tp->TxDescArray + entry);
5236 if (status & LastFrag) {
5237 dev->stats.tx_packets++;
5238 dev->stats.tx_bytes += tx_skb->skb->len;
5239 dev_kfree_skb(tx_skb->skb);
5240 tx_skb->skb = NULL;
5241 }
5242 dirty_tx++;
5243 tx_left--;
5244 }
5245
5246 if (tp->dirty_tx != dirty_tx) {
5247 tp->dirty_tx = dirty_tx;
5248 smp_wmb();
5249 if (netif_queue_stopped(dev) &&
5250 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5251 netif_wake_queue(dev);
5252 }
5253 /*
5254 * 8168 hack: TxPoll requests are lost when the Tx packets are
5255 * too close. Let's kick an extra TxPoll request when a burst
5256 * of start_xmit activity is detected (if it is not detected,
5257 * it is slow enough). -- FR
5258 */
5259 smp_rmb();
5260 if (tp->cur_tx != dirty_tx)
5261 RTL_W8(TxPoll, NPQ);
5262 }
5263 }
5264
5265 static inline int rtl8169_fragmented_frame(u32 status)
5266 {
5267 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5268 }
5269
5270 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5271 {
5272 u32 status = opts1 & RxProtoMask;
5273
5274 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5275 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5276 skb->ip_summed = CHECKSUM_UNNECESSARY;
5277 else
5278 skb_checksum_none_assert(skb);
5279 }
5280
5281 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5282 struct rtl8169_private *tp,
5283 int pkt_size,
5284 dma_addr_t addr)
5285 {
5286 struct sk_buff *skb;
5287 struct device *d = &tp->pci_dev->dev;
5288
5289 data = rtl8169_align(data);
5290 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5291 prefetch(data);
5292 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5293 if (skb)
5294 memcpy(skb->data, data, pkt_size);
5295 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5296
5297 return skb;
5298 }
5299
5300 static int rtl8169_rx_interrupt(struct net_device *dev,
5301 struct rtl8169_private *tp,
5302 void __iomem *ioaddr, u32 budget)
5303 {
5304 unsigned int cur_rx, rx_left;
5305 unsigned int count;
5306
5307 cur_rx = tp->cur_rx;
5308 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5309 rx_left = min(rx_left, budget);
5310
5311 for (; rx_left > 0; rx_left--, cur_rx++) {
5312 unsigned int entry = cur_rx % NUM_RX_DESC;
5313 struct RxDesc *desc = tp->RxDescArray + entry;
5314 u32 status;
5315
5316 rmb();
5317 status = le32_to_cpu(desc->opts1);
5318
5319 if (status & DescOwn)
5320 break;
5321 if (unlikely(status & RxRES)) {
5322 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5323 status);
5324 dev->stats.rx_errors++;
5325 if (status & (RxRWT | RxRUNT))
5326 dev->stats.rx_length_errors++;
5327 if (status & RxCRC)
5328 dev->stats.rx_crc_errors++;
5329 if (status & RxFOVF) {
5330 rtl8169_schedule_work(dev, rtl8169_reset_task);
5331 dev->stats.rx_fifo_errors++;
5332 }
5333 rtl8169_mark_to_asic(desc, rx_buf_sz);
5334 } else {
5335 struct sk_buff *skb;
5336 dma_addr_t addr = le64_to_cpu(desc->addr);
5337 int pkt_size = (status & 0x00001FFF) - 4;
5338
5339 /*
5340 * The driver does not support incoming fragmented
5341 * frames. They are seen as a symptom of over-mtu
5342 * sized frames.
5343 */
5344 if (unlikely(rtl8169_fragmented_frame(status))) {
5345 dev->stats.rx_dropped++;
5346 dev->stats.rx_length_errors++;
5347 rtl8169_mark_to_asic(desc, rx_buf_sz);
5348 continue;
5349 }
5350
5351 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5352 tp, pkt_size, addr);
5353 rtl8169_mark_to_asic(desc, rx_buf_sz);
5354 if (!skb) {
5355 dev->stats.rx_dropped++;
5356 continue;
5357 }
5358
5359 rtl8169_rx_csum(skb, status);
5360 skb_put(skb, pkt_size);
5361 skb->protocol = eth_type_trans(skb, dev);
5362
5363 rtl8169_rx_vlan_tag(desc, skb);
5364
5365 napi_gro_receive(&tp->napi, skb);
5366
5367 dev->stats.rx_bytes += pkt_size;
5368 dev->stats.rx_packets++;
5369 }
5370
5371 /* Work around for AMD plateform. */
5372 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5373 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5374 desc->opts2 = 0;
5375 cur_rx++;
5376 }
5377 }
5378
5379 count = cur_rx - tp->cur_rx;
5380 tp->cur_rx = cur_rx;
5381
5382 tp->dirty_rx += count;
5383
5384 return count;
5385 }
5386
5387 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5388 {
5389 struct net_device *dev = dev_instance;
5390 struct rtl8169_private *tp = netdev_priv(dev);
5391 void __iomem *ioaddr = tp->mmio_addr;
5392 int handled = 0;
5393 int status;
5394
5395 /* loop handling interrupts until we have no new ones or
5396 * we hit a invalid/hotplug case.
5397 */
5398 status = RTL_R16(IntrStatus);
5399 while (status && status != 0xffff) {
5400 handled = 1;
5401
5402 /* Handle all of the error cases first. These will reset
5403 * the chip, so just exit the loop.
5404 */
5405 if (unlikely(!netif_running(dev))) {
5406 rtl8169_hw_reset(tp);
5407 break;
5408 }
5409
5410 if (unlikely(status & RxFIFOOver)) {
5411 switch (tp->mac_version) {
5412 /* Work around for rx fifo overflow */
5413 case RTL_GIGA_MAC_VER_11:
5414 case RTL_GIGA_MAC_VER_22:
5415 case RTL_GIGA_MAC_VER_26:
5416 netif_stop_queue(dev);
5417 rtl8169_tx_timeout(dev);
5418 goto done;
5419 /* Testers needed. */
5420 case RTL_GIGA_MAC_VER_17:
5421 case RTL_GIGA_MAC_VER_19:
5422 case RTL_GIGA_MAC_VER_20:
5423 case RTL_GIGA_MAC_VER_21:
5424 case RTL_GIGA_MAC_VER_23:
5425 case RTL_GIGA_MAC_VER_24:
5426 case RTL_GIGA_MAC_VER_27:
5427 case RTL_GIGA_MAC_VER_28:
5428 case RTL_GIGA_MAC_VER_31:
5429 /* Experimental science. Pktgen proof. */
5430 case RTL_GIGA_MAC_VER_12:
5431 case RTL_GIGA_MAC_VER_25:
5432 if (status == RxFIFOOver)
5433 goto done;
5434 break;
5435 default:
5436 break;
5437 }
5438 }
5439
5440 if (unlikely(status & SYSErr)) {
5441 rtl8169_pcierr_interrupt(dev);
5442 break;
5443 }
5444
5445 if (status & LinkChg)
5446 __rtl8169_check_link_status(dev, tp, ioaddr, true);
5447
5448 /* We need to see the lastest version of tp->intr_mask to
5449 * avoid ignoring an MSI interrupt and having to wait for
5450 * another event which may never come.
5451 */
5452 smp_rmb();
5453 if (status & tp->intr_mask & tp->napi_event) {
5454 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5455 tp->intr_mask = ~tp->napi_event;
5456
5457 if (likely(napi_schedule_prep(&tp->napi)))
5458 __napi_schedule(&tp->napi);
5459 else
5460 netif_info(tp, intr, dev,
5461 "interrupt %04x in poll\n", status);
5462 }
5463
5464 /* We only get a new MSI interrupt when all active irq
5465 * sources on the chip have been acknowledged. So, ack
5466 * everything we've seen and check if new sources have become
5467 * active to avoid blocking all interrupts from the chip.
5468 */
5469 RTL_W16(IntrStatus,
5470 (status & RxFIFOOver) ? (status | RxOverflow) : status);
5471 status = RTL_R16(IntrStatus);
5472 }
5473 done:
5474 return IRQ_RETVAL(handled);
5475 }
5476
5477 static int rtl8169_poll(struct napi_struct *napi, int budget)
5478 {
5479 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5480 struct net_device *dev = tp->dev;
5481 void __iomem *ioaddr = tp->mmio_addr;
5482 int work_done;
5483
5484 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5485 rtl8169_tx_interrupt(dev, tp, ioaddr);
5486
5487 if (work_done < budget) {
5488 napi_complete(napi);
5489
5490 /* We need for force the visibility of tp->intr_mask
5491 * for other CPUs, as we can loose an MSI interrupt
5492 * and potentially wait for a retransmit timeout if we don't.
5493 * The posted write to IntrMask is safe, as it will
5494 * eventually make it to the chip and we won't loose anything
5495 * until it does.
5496 */
5497 tp->intr_mask = 0xffff;
5498 wmb();
5499 RTL_W16(IntrMask, tp->intr_event);
5500 }
5501
5502 return work_done;
5503 }
5504
5505 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5506 {
5507 struct rtl8169_private *tp = netdev_priv(dev);
5508
5509 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5510 return;
5511
5512 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5513 RTL_W32(RxMissed, 0);
5514 }
5515
5516 static void rtl8169_down(struct net_device *dev)
5517 {
5518 struct rtl8169_private *tp = netdev_priv(dev);
5519 void __iomem *ioaddr = tp->mmio_addr;
5520
5521 del_timer_sync(&tp->timer);
5522
5523 netif_stop_queue(dev);
5524
5525 napi_disable(&tp->napi);
5526
5527 spin_lock_irq(&tp->lock);
5528
5529 rtl8169_hw_reset(tp);
5530 /*
5531 * At this point device interrupts can not be enabled in any function,
5532 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5533 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5534 */
5535 rtl8169_rx_missed(dev, ioaddr);
5536
5537 spin_unlock_irq(&tp->lock);
5538
5539 synchronize_irq(dev->irq);
5540
5541 /* Give a racing hard_start_xmit a few cycles to complete. */
5542 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
5543
5544 rtl8169_tx_clear(tp);
5545
5546 rtl8169_rx_clear(tp);
5547
5548 rtl_pll_power_down(tp);
5549 }
5550
5551 static int rtl8169_close(struct net_device *dev)
5552 {
5553 struct rtl8169_private *tp = netdev_priv(dev);
5554 struct pci_dev *pdev = tp->pci_dev;
5555
5556 pm_runtime_get_sync(&pdev->dev);
5557
5558 /* Update counters before going down */
5559 rtl8169_update_counters(dev);
5560
5561 rtl8169_down(dev);
5562
5563 free_irq(dev->irq, dev);
5564
5565 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5566 tp->RxPhyAddr);
5567 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5568 tp->TxPhyAddr);
5569 tp->TxDescArray = NULL;
5570 tp->RxDescArray = NULL;
5571
5572 pm_runtime_put_sync(&pdev->dev);
5573
5574 return 0;
5575 }
5576
5577 static void rtl_set_rx_mode(struct net_device *dev)
5578 {
5579 struct rtl8169_private *tp = netdev_priv(dev);
5580 void __iomem *ioaddr = tp->mmio_addr;
5581 unsigned long flags;
5582 u32 mc_filter[2]; /* Multicast hash filter */
5583 int rx_mode;
5584 u32 tmp = 0;
5585
5586 if (dev->flags & IFF_PROMISC) {
5587 /* Unconditionally log net taps. */
5588 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5589 rx_mode =
5590 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5591 AcceptAllPhys;
5592 mc_filter[1] = mc_filter[0] = 0xffffffff;
5593 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5594 (dev->flags & IFF_ALLMULTI)) {
5595 /* Too many to filter perfectly -- accept all multicasts. */
5596 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5597 mc_filter[1] = mc_filter[0] = 0xffffffff;
5598 } else {
5599 struct netdev_hw_addr *ha;
5600
5601 rx_mode = AcceptBroadcast | AcceptMyPhys;
5602 mc_filter[1] = mc_filter[0] = 0;
5603 netdev_for_each_mc_addr(ha, dev) {
5604 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5605 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5606 rx_mode |= AcceptMulticast;
5607 }
5608 }
5609
5610 spin_lock_irqsave(&tp->lock, flags);
5611
5612 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5613
5614 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5615 u32 data = mc_filter[0];
5616
5617 mc_filter[0] = swab32(mc_filter[1]);
5618 mc_filter[1] = swab32(data);
5619 }
5620
5621 RTL_W32(MAR0 + 4, mc_filter[1]);
5622 RTL_W32(MAR0 + 0, mc_filter[0]);
5623
5624 RTL_W32(RxConfig, tmp);
5625
5626 spin_unlock_irqrestore(&tp->lock, flags);
5627 }
5628
5629 /**
5630 * rtl8169_get_stats - Get rtl8169 read/write statistics
5631 * @dev: The Ethernet Device to get statistics for
5632 *
5633 * Get TX/RX statistics for rtl8169
5634 */
5635 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5636 {
5637 struct rtl8169_private *tp = netdev_priv(dev);
5638 void __iomem *ioaddr = tp->mmio_addr;
5639 unsigned long flags;
5640
5641 if (netif_running(dev)) {
5642 spin_lock_irqsave(&tp->lock, flags);
5643 rtl8169_rx_missed(dev, ioaddr);
5644 spin_unlock_irqrestore(&tp->lock, flags);
5645 }
5646
5647 return &dev->stats;
5648 }
5649
5650 static void rtl8169_net_suspend(struct net_device *dev)
5651 {
5652 struct rtl8169_private *tp = netdev_priv(dev);
5653
5654 if (!netif_running(dev))
5655 return;
5656
5657 rtl_pll_power_down(tp);
5658
5659 netif_device_detach(dev);
5660 netif_stop_queue(dev);
5661 }
5662
5663 #ifdef CONFIG_PM
5664
5665 static int rtl8169_suspend(struct device *device)
5666 {
5667 struct pci_dev *pdev = to_pci_dev(device);
5668 struct net_device *dev = pci_get_drvdata(pdev);
5669
5670 rtl8169_net_suspend(dev);
5671
5672 return 0;
5673 }
5674
5675 static void __rtl8169_resume(struct net_device *dev)
5676 {
5677 struct rtl8169_private *tp = netdev_priv(dev);
5678
5679 netif_device_attach(dev);
5680
5681 rtl_pll_power_up(tp);
5682
5683 rtl8169_schedule_work(dev, rtl8169_reset_task);
5684 }
5685
5686 static int rtl8169_resume(struct device *device)
5687 {
5688 struct pci_dev *pdev = to_pci_dev(device);
5689 struct net_device *dev = pci_get_drvdata(pdev);
5690 struct rtl8169_private *tp = netdev_priv(dev);
5691
5692 rtl8169_init_phy(dev, tp);
5693
5694 if (netif_running(dev))
5695 __rtl8169_resume(dev);
5696
5697 return 0;
5698 }
5699
5700 static int rtl8169_runtime_suspend(struct device *device)
5701 {
5702 struct pci_dev *pdev = to_pci_dev(device);
5703 struct net_device *dev = pci_get_drvdata(pdev);
5704 struct rtl8169_private *tp = netdev_priv(dev);
5705
5706 if (!tp->TxDescArray)
5707 return 0;
5708
5709 spin_lock_irq(&tp->lock);
5710 tp->saved_wolopts = __rtl8169_get_wol(tp);
5711 __rtl8169_set_wol(tp, WAKE_ANY);
5712 spin_unlock_irq(&tp->lock);
5713
5714 rtl8169_net_suspend(dev);
5715
5716 return 0;
5717 }
5718
5719 static int rtl8169_runtime_resume(struct device *device)
5720 {
5721 struct pci_dev *pdev = to_pci_dev(device);
5722 struct net_device *dev = pci_get_drvdata(pdev);
5723 struct rtl8169_private *tp = netdev_priv(dev);
5724
5725 if (!tp->TxDescArray)
5726 return 0;
5727
5728 spin_lock_irq(&tp->lock);
5729 __rtl8169_set_wol(tp, tp->saved_wolopts);
5730 tp->saved_wolopts = 0;
5731 spin_unlock_irq(&tp->lock);
5732
5733 rtl8169_init_phy(dev, tp);
5734
5735 __rtl8169_resume(dev);
5736
5737 return 0;
5738 }
5739
5740 static int rtl8169_runtime_idle(struct device *device)
5741 {
5742 struct pci_dev *pdev = to_pci_dev(device);
5743 struct net_device *dev = pci_get_drvdata(pdev);
5744 struct rtl8169_private *tp = netdev_priv(dev);
5745
5746 return tp->TxDescArray ? -EBUSY : 0;
5747 }
5748
5749 static const struct dev_pm_ops rtl8169_pm_ops = {
5750 .suspend = rtl8169_suspend,
5751 .resume = rtl8169_resume,
5752 .freeze = rtl8169_suspend,
5753 .thaw = rtl8169_resume,
5754 .poweroff = rtl8169_suspend,
5755 .restore = rtl8169_resume,
5756 .runtime_suspend = rtl8169_runtime_suspend,
5757 .runtime_resume = rtl8169_runtime_resume,
5758 .runtime_idle = rtl8169_runtime_idle,
5759 };
5760
5761 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
5762
5763 #else /* !CONFIG_PM */
5764
5765 #define RTL8169_PM_OPS NULL
5766
5767 #endif /* !CONFIG_PM */
5768
5769 static void rtl_shutdown(struct pci_dev *pdev)
5770 {
5771 struct net_device *dev = pci_get_drvdata(pdev);
5772 struct rtl8169_private *tp = netdev_priv(dev);
5773 void __iomem *ioaddr = tp->mmio_addr;
5774
5775 rtl8169_net_suspend(dev);
5776
5777 /* Restore original MAC address */
5778 rtl_rar_set(tp, dev->perm_addr);
5779
5780 spin_lock_irq(&tp->lock);
5781
5782 rtl8169_hw_reset(tp);
5783
5784 spin_unlock_irq(&tp->lock);
5785
5786 if (system_state == SYSTEM_POWER_OFF) {
5787 /* WoL fails with 8168b when the receiver is disabled. */
5788 if ((tp->mac_version == RTL_GIGA_MAC_VER_11 ||
5789 tp->mac_version == RTL_GIGA_MAC_VER_12 ||
5790 tp->mac_version == RTL_GIGA_MAC_VER_17) &&
5791 (tp->features & RTL_FEATURE_WOL)) {
5792 pci_clear_master(pdev);
5793
5794 RTL_W8(ChipCmd, CmdRxEnb);
5795 /* PCI commit */
5796 RTL_R8(ChipCmd);
5797 }
5798
5799 pci_wake_from_d3(pdev, true);
5800 pci_set_power_state(pdev, PCI_D3hot);
5801 }
5802 }
5803
5804 static struct pci_driver rtl8169_pci_driver = {
5805 .name = MODULENAME,
5806 .id_table = rtl8169_pci_tbl,
5807 .probe = rtl8169_init_one,
5808 .remove = __devexit_p(rtl8169_remove_one),
5809 .shutdown = rtl_shutdown,
5810 .driver.pm = RTL8169_PM_OPS,
5811 };
5812
5813 static int __init rtl8169_init_module(void)
5814 {
5815 return pci_register_driver(&rtl8169_pci_driver);
5816 }
5817
5818 static void __exit rtl8169_cleanup_module(void)
5819 {
5820 pci_unregister_driver(&rtl8169_pci_driver);
5821 }
5822
5823 module_init(rtl8169_init_module);
5824 module_exit(rtl8169_cleanup_module);