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Staging: hv: mousevsc: Cleanup and properly implement reportdesc_callback()
[zen-stable.git] / drivers / net / sfc / siena.c
blob5735e84c69de6eba4a5589a3b10e23173e7a5fa7
1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2010 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/random.h>
17 #include "net_driver.h"
18 #include "bitfield.h"
19 #include "efx.h"
20 #include "nic.h"
21 #include "mac.h"
22 #include "spi.h"
23 #include "regs.h"
24 #include "io.h"
25 #include "phy.h"
26 #include "workarounds.h"
27 #include "mcdi.h"
28 #include "mcdi_pcol.h"
29
30 /* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
31
32 static void siena_init_wol(struct efx_nic *efx);
33
34
35 static void siena_push_irq_moderation(struct efx_channel *channel)
36 {
37 efx_dword_t timer_cmd;
38
39 if (channel->irq_moderation)
40 EFX_POPULATE_DWORD_2(timer_cmd,
41 FRF_CZ_TC_TIMER_MODE,
42 FFE_CZ_TIMER_MODE_INT_HLDOFF,
43 FRF_CZ_TC_TIMER_VAL,
44 channel->irq_moderation - 1);
45 else
46 EFX_POPULATE_DWORD_2(timer_cmd,
47 FRF_CZ_TC_TIMER_MODE,
48 FFE_CZ_TIMER_MODE_DIS,
49 FRF_CZ_TC_TIMER_VAL, 0);
50 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
51 channel->channel);
52 }
53
54 static void siena_push_multicast_hash(struct efx_nic *efx)
55 {
56 WARN_ON(!mutex_is_locked(&efx->mac_lock));
57
58 efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
59 efx->multicast_hash.byte, sizeof(efx->multicast_hash),
60 NULL, 0, NULL);
61 }
62
63 static int siena_mdio_write(struct net_device *net_dev,
64 int prtad, int devad, u16 addr, u16 value)
65 {
66 struct efx_nic *efx = netdev_priv(net_dev);
67 uint32_t status;
68 int rc;
69
70 rc = efx_mcdi_mdio_write(efx, efx->mdio_bus, prtad, devad,
71 addr, value, &status);
72 if (rc)
73 return rc;
74 if (status != MC_CMD_MDIO_STATUS_GOOD)
75 return -EIO;
76
77 return 0;
78 }
79
80 static int siena_mdio_read(struct net_device *net_dev,
81 int prtad, int devad, u16 addr)
82 {
83 struct efx_nic *efx = netdev_priv(net_dev);
84 uint16_t value;
85 uint32_t status;
86 int rc;
87
88 rc = efx_mcdi_mdio_read(efx, efx->mdio_bus, prtad, devad,
89 addr, &value, &status);
90 if (rc)
91 return rc;
92 if (status != MC_CMD_MDIO_STATUS_GOOD)
93 return -EIO;
94
95 return (int)value;
96 }
97
98 /* This call is responsible for hooking in the MAC and PHY operations */
99 static int siena_probe_port(struct efx_nic *efx)
100 {
101 int rc;
102
103 /* Hook in PHY operations table */
104 efx->phy_op = &efx_mcdi_phy_ops;
105
106 /* Set up MDIO structure for PHY */
107 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
108 efx->mdio.mdio_read = siena_mdio_read;
109 efx->mdio.mdio_write = siena_mdio_write;
110
111 /* Fill out MDIO structure, loopback modes, and initial link state */
112 rc = efx->phy_op->probe(efx);
113 if (rc != 0)
114 return rc;
115
116 /* Allocate buffer for stats */
117 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
118 MC_CMD_MAC_NSTATS * sizeof(u64));
119 if (rc)
120 return rc;
121 netif_dbg(efx, probe, efx->net_dev,
122 "stats buffer at %llx (virt %p phys %llx)\n",
123 (u64)efx->stats_buffer.dma_addr,
124 efx->stats_buffer.addr,
125 (u64)virt_to_phys(efx->stats_buffer.addr));
126
127 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 1);
128
129 return 0;
130 }
131
132 static void siena_remove_port(struct efx_nic *efx)
133 {
134 efx->phy_op->remove(efx);
135 efx_nic_free_buffer(efx, &efx->stats_buffer);
136 }
137
138 static const struct efx_nic_register_test siena_register_tests[] = {
139 { FR_AZ_ADR_REGION,
140 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
141 { FR_CZ_USR_EV_CFG,
142 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
143 { FR_AZ_RX_CFG,
144 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
145 { FR_AZ_TX_CFG,
146 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
147 { FR_AZ_TX_RESERVED,
148 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
149 { FR_AZ_SRM_TX_DC_CFG,
150 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
151 { FR_AZ_RX_DC_CFG,
152 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
153 { FR_AZ_RX_DC_PF_WM,
154 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
155 { FR_BZ_DP_CTRL,
156 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
157 { FR_BZ_RX_RSS_TKEY,
158 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
159 { FR_CZ_RX_RSS_IPV6_REG1,
160 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
161 { FR_CZ_RX_RSS_IPV6_REG2,
162 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
163 { FR_CZ_RX_RSS_IPV6_REG3,
164 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
165 };
166
167 static int siena_test_registers(struct efx_nic *efx)
168 {
169 return efx_nic_test_registers(efx, siena_register_tests,
170 ARRAY_SIZE(siena_register_tests));
171 }
172
173 /**************************************************************************
174 *
175 * Device reset
176 *
177 **************************************************************************
178 */
179
180 static enum reset_type siena_map_reset_reason(enum reset_type reason)
181 {
182 return RESET_TYPE_ALL;
183 }
184
185 static int siena_map_reset_flags(u32 *flags)
186 {
187 enum {
188 SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
189 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
190 ETH_RESET_PHY),
191 SIENA_RESET_MC = (SIENA_RESET_PORT |
192 ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
193 };
194
195 if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
196 *flags &= ~SIENA_RESET_MC;
197 return RESET_TYPE_WORLD;
198 }
199
200 if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
201 *flags &= ~SIENA_RESET_PORT;
202 return RESET_TYPE_ALL;
203 }
204
205 /* no invisible reset implemented */
206
207 return -EINVAL;
208 }
209
210 static int siena_reset_hw(struct efx_nic *efx, enum reset_type method)
211 {
212 int rc;
213
214 /* Recover from a failed assertion pre-reset */
215 rc = efx_mcdi_handle_assertion(efx);
216 if (rc)
217 return rc;
218
219 if (method == RESET_TYPE_WORLD)
220 return efx_mcdi_reset_mc(efx);
221 else
222 return efx_mcdi_reset_port(efx);
223 }
224
225 static int siena_probe_nvconfig(struct efx_nic *efx)
226 {
227 return efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL);
228 }
229
230 static int siena_probe_nic(struct efx_nic *efx)
231 {
232 struct siena_nic_data *nic_data;
233 bool already_attached = 0;
234 efx_oword_t reg;
235 int rc;
236
237 /* Allocate storage for hardware specific data */
238 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
239 if (!nic_data)
240 return -ENOMEM;
241 efx->nic_data = nic_data;
242
243 if (efx_nic_fpga_ver(efx) != 0) {
244 netif_err(efx, probe, efx->net_dev,
245 "Siena FPGA not supported\n");
246 rc = -ENODEV;
247 goto fail1;
248 }
249
250 efx_reado(efx, &reg, FR_AZ_CS_DEBUG);
251 efx->net_dev->dev_id = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
252
253 /* Initialise MCDI */
254 nic_data->mcdi_smem = ioremap_nocache(efx->membase_phys +
255 FR_CZ_MC_TREG_SMEM,
256 FR_CZ_MC_TREG_SMEM_STEP *
257 FR_CZ_MC_TREG_SMEM_ROWS);
258 if (!nic_data->mcdi_smem) {
259 netif_err(efx, probe, efx->net_dev,
260 "could not map MCDI at %llx+%x\n",
261 (unsigned long long)efx->membase_phys +
262 FR_CZ_MC_TREG_SMEM,
263 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS);
264 rc = -ENOMEM;
265 goto fail1;
266 }
267 efx_mcdi_init(efx);
268
269 /* Recover from a failed assertion before probing */
270 rc = efx_mcdi_handle_assertion(efx);
271 if (rc)
272 goto fail2;
273
274 /* Let the BMC know that the driver is now in charge of link and
275 * filter settings. We must do this before we reset the NIC */
276 rc = efx_mcdi_drv_attach(efx, true, &already_attached);
277 if (rc) {
278 netif_err(efx, probe, efx->net_dev,
279 "Unable to register driver with MCPU\n");
280 goto fail2;
281 }
282 if (already_attached)
283 /* Not a fatal error */
284 netif_err(efx, probe, efx->net_dev,
285 "Host already registered with MCPU\n");
286
287 /* Now we can reset the NIC */
288 rc = siena_reset_hw(efx, RESET_TYPE_ALL);
289 if (rc) {
290 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
291 goto fail3;
292 }
293
294 siena_init_wol(efx);
295
296 /* Allocate memory for INT_KER */
297 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
298 if (rc)
299 goto fail4;
300 BUG_ON(efx->irq_status.dma_addr & 0x0f);
301
302 netif_dbg(efx, probe, efx->net_dev,
303 "INT_KER at %llx (virt %p phys %llx)\n",
304 (unsigned long long)efx->irq_status.dma_addr,
305 efx->irq_status.addr,
306 (unsigned long long)virt_to_phys(efx->irq_status.addr));
307
308 /* Read in the non-volatile configuration */
309 rc = siena_probe_nvconfig(efx);
310 if (rc == -EINVAL) {
311 netif_err(efx, probe, efx->net_dev,
312 "NVRAM is invalid therefore using defaults\n");
313 efx->phy_type = PHY_TYPE_NONE;
314 efx->mdio.prtad = MDIO_PRTAD_NONE;
315 } else if (rc) {
316 goto fail5;
317 }
318
319 return 0;
320
321 fail5:
322 efx_nic_free_buffer(efx, &efx->irq_status);
323 fail4:
324 fail3:
325 efx_mcdi_drv_attach(efx, false, NULL);
326 fail2:
327 iounmap(nic_data->mcdi_smem);
328 fail1:
329 kfree(efx->nic_data);
330 return rc;
331 }
332
333 /* This call performs hardware-specific global initialisation, such as
334 * defining the descriptor cache sizes and number of RSS channels.
335 * It does not set up any buffers, descriptor rings or event queues.
336 */
337 static int siena_init_nic(struct efx_nic *efx)
338 {
339 efx_oword_t temp;
340 int rc;
341
342 /* Recover from a failed assertion post-reset */
343 rc = efx_mcdi_handle_assertion(efx);
344 if (rc)
345 return rc;
346
347 /* Squash TX of packets of 16 bytes or less */
348 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
349 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
350 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
351
352 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
353 * descriptors (which is bad).
354 */
355 efx_reado(efx, &temp, FR_AZ_TX_CFG);
356 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
357 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
358 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
359
360 efx_reado(efx, &temp, FR_AZ_RX_CFG);
361 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
362 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
363 /* Enable hash insertion. This is broken for the 'Falcon' hash
364 * if IPv6 hashing is also enabled, so also select Toeplitz
365 * TCP/IPv4 and IPv4 hashes. */
366 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
367 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
368 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
369 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
370
371 /* Set hash key for IPv4 */
372 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
373 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
374
375 /* Enable IPv6 RSS */
376 BUILD_BUG_ON(sizeof(efx->rx_hash_key) <
377 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
378 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
379 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
380 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
381 memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp));
382 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
383 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
384 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
385 memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp),
386 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
387 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
388
389 /* Enable event logging */
390 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
391 if (rc)
392 return rc;
393
394 /* Set destination of both TX and RX Flush events */
395 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
396 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
397
398 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
399 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
400
401 efx_nic_init_common(efx);
402 return 0;
403 }
404
405 static void siena_remove_nic(struct efx_nic *efx)
406 {
407 struct siena_nic_data *nic_data = efx->nic_data;
408
409 efx_nic_free_buffer(efx, &efx->irq_status);
410
411 siena_reset_hw(efx, RESET_TYPE_ALL);
412
413 /* Relinquish the device back to the BMC */
414 if (efx_nic_has_mc(efx))
415 efx_mcdi_drv_attach(efx, false, NULL);
416
417 /* Tear down the private nic state */
418 iounmap(nic_data->mcdi_smem);
419 kfree(nic_data);
420 efx->nic_data = NULL;
421 }
422
423 #define STATS_GENERATION_INVALID ((__force __le64)(-1))
424
425 static int siena_try_update_nic_stats(struct efx_nic *efx)
426 {
427 __le64 *dma_stats;
428 struct efx_mac_stats *mac_stats;
429 __le64 generation_start, generation_end;
430
431 mac_stats = &efx->mac_stats;
432 dma_stats = efx->stats_buffer.addr;
433
434 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
435 if (generation_end == STATS_GENERATION_INVALID)
436 return 0;
437 rmb();
438
439 #define MAC_STAT(M, D) \
440 mac_stats->M = le64_to_cpu(dma_stats[MC_CMD_MAC_ ## D])
441
442 MAC_STAT(tx_bytes, TX_BYTES);
443 MAC_STAT(tx_bad_bytes, TX_BAD_BYTES);
444 mac_stats->tx_good_bytes = (mac_stats->tx_bytes -
445 mac_stats->tx_bad_bytes);
446 MAC_STAT(tx_packets, TX_PKTS);
447 MAC_STAT(tx_bad, TX_BAD_FCS_PKTS);
448 MAC_STAT(tx_pause, TX_PAUSE_PKTS);
449 MAC_STAT(tx_control, TX_CONTROL_PKTS);
450 MAC_STAT(tx_unicast, TX_UNICAST_PKTS);
451 MAC_STAT(tx_multicast, TX_MULTICAST_PKTS);
452 MAC_STAT(tx_broadcast, TX_BROADCAST_PKTS);
453 MAC_STAT(tx_lt64, TX_LT64_PKTS);
454 MAC_STAT(tx_64, TX_64_PKTS);
455 MAC_STAT(tx_65_to_127, TX_65_TO_127_PKTS);
456 MAC_STAT(tx_128_to_255, TX_128_TO_255_PKTS);
457 MAC_STAT(tx_256_to_511, TX_256_TO_511_PKTS);
458 MAC_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS);
459 MAC_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS);
460 MAC_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS);
461 MAC_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS);
462 mac_stats->tx_collision = 0;
463 MAC_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS);
464 MAC_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS);
465 MAC_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS);
466 MAC_STAT(tx_deferred, TX_DEFERRED_PKTS);
467 MAC_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS);
468 mac_stats->tx_collision = (mac_stats->tx_single_collision +
469 mac_stats->tx_multiple_collision +
470 mac_stats->tx_excessive_collision +
471 mac_stats->tx_late_collision);
472 MAC_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS);
473 MAC_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS);
474 MAC_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS);
475 MAC_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS);
476 MAC_STAT(rx_bytes, RX_BYTES);
477 MAC_STAT(rx_bad_bytes, RX_BAD_BYTES);
478 mac_stats->rx_good_bytes = (mac_stats->rx_bytes -
479 mac_stats->rx_bad_bytes);
480 MAC_STAT(rx_packets, RX_PKTS);
481 MAC_STAT(rx_good, RX_GOOD_PKTS);
482 MAC_STAT(rx_bad, RX_BAD_FCS_PKTS);
483 MAC_STAT(rx_pause, RX_PAUSE_PKTS);
484 MAC_STAT(rx_control, RX_CONTROL_PKTS);
485 MAC_STAT(rx_unicast, RX_UNICAST_PKTS);
486 MAC_STAT(rx_multicast, RX_MULTICAST_PKTS);
487 MAC_STAT(rx_broadcast, RX_BROADCAST_PKTS);
488 MAC_STAT(rx_lt64, RX_UNDERSIZE_PKTS);
489 MAC_STAT(rx_64, RX_64_PKTS);
490 MAC_STAT(rx_65_to_127, RX_65_TO_127_PKTS);
491 MAC_STAT(rx_128_to_255, RX_128_TO_255_PKTS);
492 MAC_STAT(rx_256_to_511, RX_256_TO_511_PKTS);
493 MAC_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS);
494 MAC_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS);
495 MAC_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS);
496 MAC_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS);
497 mac_stats->rx_bad_lt64 = 0;
498 mac_stats->rx_bad_64_to_15xx = 0;
499 mac_stats->rx_bad_15xx_to_jumbo = 0;
500 MAC_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS);
501 MAC_STAT(rx_overflow, RX_OVERFLOW_PKTS);
502 mac_stats->rx_missed = 0;
503 MAC_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS);
504 MAC_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS);
505 MAC_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS);
506 MAC_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS);
507 MAC_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS);
508 mac_stats->rx_good_lt64 = 0;
509
510 efx->n_rx_nodesc_drop_cnt =
511 le64_to_cpu(dma_stats[MC_CMD_MAC_RX_NODESC_DROPS]);
512
513 #undef MAC_STAT
514
515 rmb();
516 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
517 if (generation_end != generation_start)
518 return -EAGAIN;
519
520 return 0;
521 }
522
523 static void siena_update_nic_stats(struct efx_nic *efx)
524 {
525 int retry;
526
527 /* If we're unlucky enough to read statistics wduring the DMA, wait
528 * up to 10ms for it to finish (typically takes <500us) */
529 for (retry = 0; retry < 100; ++retry) {
530 if (siena_try_update_nic_stats(efx) == 0)
531 return;
532 udelay(100);
533 }
534
535 /* Use the old values instead */
536 }
537
538 static void siena_start_nic_stats(struct efx_nic *efx)
539 {
540 __le64 *dma_stats = efx->stats_buffer.addr;
541
542 dma_stats[MC_CMD_MAC_GENERATION_END] = STATS_GENERATION_INVALID;
543
544 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr,
545 MC_CMD_MAC_NSTATS * sizeof(u64), 1, 0);
546 }
547
548 static void siena_stop_nic_stats(struct efx_nic *efx)
549 {
550 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 0);
551 }
552
553 /**************************************************************************
554 *
555 * Wake on LAN
556 *
557 **************************************************************************
558 */
559
560 static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
561 {
562 struct siena_nic_data *nic_data = efx->nic_data;
563
564 wol->supported = WAKE_MAGIC;
565 if (nic_data->wol_filter_id != -1)
566 wol->wolopts = WAKE_MAGIC;
567 else
568 wol->wolopts = 0;
569 memset(&wol->sopass, 0, sizeof(wol->sopass));
570 }
571
572
573 static int siena_set_wol(struct efx_nic *efx, u32 type)
574 {
575 struct siena_nic_data *nic_data = efx->nic_data;
576 int rc;
577
578 if (type & ~WAKE_MAGIC)
579 return -EINVAL;
580
581 if (type & WAKE_MAGIC) {
582 if (nic_data->wol_filter_id != -1)
583 efx_mcdi_wol_filter_remove(efx,
584 nic_data->wol_filter_id);
585 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
586 &nic_data->wol_filter_id);
587 if (rc)
588 goto fail;
589
590 pci_wake_from_d3(efx->pci_dev, true);
591 } else {
592 rc = efx_mcdi_wol_filter_reset(efx);
593 nic_data->wol_filter_id = -1;
594 pci_wake_from_d3(efx->pci_dev, false);
595 if (rc)
596 goto fail;
597 }
598
599 return 0;
600 fail:
601 netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
602 __func__, type, rc);
603 return rc;
604 }
605
606
607 static void siena_init_wol(struct efx_nic *efx)
608 {
609 struct siena_nic_data *nic_data = efx->nic_data;
610 int rc;
611
612 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
613
614 if (rc != 0) {
615 /* If it failed, attempt to get into a synchronised
616 * state with MC by resetting any set WoL filters */
617 efx_mcdi_wol_filter_reset(efx);
618 nic_data->wol_filter_id = -1;
619 } else if (nic_data->wol_filter_id != -1) {
620 pci_wake_from_d3(efx->pci_dev, true);
621 }
622 }
623
624
625 /**************************************************************************
626 *
627 * Revision-dependent attributes used by efx.c and nic.c
628 *
629 **************************************************************************
630 */
631
632 const struct efx_nic_type siena_a0_nic_type = {
633 .probe = siena_probe_nic,
634 .remove = siena_remove_nic,
635 .init = siena_init_nic,
636 .fini = efx_port_dummy_op_void,
637 .monitor = NULL,
638 .map_reset_reason = siena_map_reset_reason,
639 .map_reset_flags = siena_map_reset_flags,
640 .reset = siena_reset_hw,
641 .probe_port = siena_probe_port,
642 .remove_port = siena_remove_port,
643 .prepare_flush = efx_port_dummy_op_void,
644 .update_stats = siena_update_nic_stats,
645 .start_stats = siena_start_nic_stats,
646 .stop_stats = siena_stop_nic_stats,
647 .set_id_led = efx_mcdi_set_id_led,
648 .push_irq_moderation = siena_push_irq_moderation,
649 .push_multicast_hash = siena_push_multicast_hash,
650 .reconfigure_port = efx_mcdi_phy_reconfigure,
651 .get_wol = siena_get_wol,
652 .set_wol = siena_set_wol,
653 .resume_wol = siena_init_wol,
654 .test_registers = siena_test_registers,
655 .test_nvram = efx_mcdi_nvram_test_all,
656 .default_mac_ops = &efx_mcdi_mac_operations,
657
658 .revision = EFX_REV_SIENA_A0,
659 .mem_map_size = FR_CZ_MC_TREG_SMEM, /* MC_TREG_SMEM mapped separately */
660 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
661 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
662 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
663 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
664 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
665 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
666 .rx_buffer_hash_size = 0x10,
667 .rx_buffer_padding = 0,
668 .max_interrupt_mode = EFX_INT_MODE_MSIX,
669 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
670 * interrupt handler only supports 32
671 * channels */
672 .tx_dc_base = 0x88000,
673 .rx_dc_base = 0x68000,
674 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
675 NETIF_F_RXHASH | NETIF_F_NTUPLE),
676 };