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Staging: hv: mousevsc: Cleanup and properly implement reportdesc_callback()
[zen-stable.git] / drivers / net / smsc9420.c
blob459726f5475417f6effcb8fad59284f1f6a09d28
1 /***************************************************************************
2 *
3 * Copyright (C) 2007,2008 SMSC
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 *
19 ***************************************************************************
20 */
21
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/netdevice.h>
25 #include <linux/phy.h>
26 #include <linux/pci.h>
27 #include <linux/if_vlan.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/crc32.h>
30 #include <linux/slab.h>
31 #include <asm/unaligned.h>
32 #include "smsc9420.h"
33
34 #define DRV_NAME "smsc9420"
35 #define PFX DRV_NAME ": "
36 #define DRV_MDIONAME "smsc9420-mdio"
37 #define DRV_DESCRIPTION "SMSC LAN9420 driver"
38 #define DRV_VERSION "1.01"
39
40 MODULE_LICENSE("GPL");
41 MODULE_VERSION(DRV_VERSION);
42
43 struct smsc9420_dma_desc {
44 u32 status;
45 u32 length;
46 u32 buffer1;
47 u32 buffer2;
48 };
49
50 struct smsc9420_ring_info {
51 struct sk_buff *skb;
52 dma_addr_t mapping;
53 };
54
55 struct smsc9420_pdata {
56 void __iomem *base_addr;
57 struct pci_dev *pdev;
58 struct net_device *dev;
59
60 struct smsc9420_dma_desc *rx_ring;
61 struct smsc9420_dma_desc *tx_ring;
62 struct smsc9420_ring_info *tx_buffers;
63 struct smsc9420_ring_info *rx_buffers;
64 dma_addr_t rx_dma_addr;
65 dma_addr_t tx_dma_addr;
66 int tx_ring_head, tx_ring_tail;
67 int rx_ring_head, rx_ring_tail;
68
69 spinlock_t int_lock;
70 spinlock_t phy_lock;
71
72 struct napi_struct napi;
73
74 bool software_irq_signal;
75 bool rx_csum;
76 u32 msg_enable;
77
78 struct phy_device *phy_dev;
79 struct mii_bus *mii_bus;
80 int phy_irq[PHY_MAX_ADDR];
81 int last_duplex;
82 int last_carrier;
83 };
84
85 static DEFINE_PCI_DEVICE_TABLE(smsc9420_id_table) = {
86 { PCI_VENDOR_ID_9420, PCI_DEVICE_ID_9420, PCI_ANY_ID, PCI_ANY_ID, },
87 { 0, }
88 };
89
90 MODULE_DEVICE_TABLE(pci, smsc9420_id_table);
91
92 #define SMSC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
93
94 static uint smsc_debug;
95 static uint debug = -1;
96 module_param(debug, uint, 0);
97 MODULE_PARM_DESC(debug, "debug level");
98
99 #define smsc_dbg(TYPE, f, a...) \
100 do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
101 printk(KERN_DEBUG PFX f "\n", ## a); \
102 } while (0)
103
104 #define smsc_info(TYPE, f, a...) \
105 do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
106 printk(KERN_INFO PFX f "\n", ## a); \
107 } while (0)
108
109 #define smsc_warn(TYPE, f, a...) \
110 do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
111 printk(KERN_WARNING PFX f "\n", ## a); \
112 } while (0)
113
114 static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset)
115 {
116 return ioread32(pd->base_addr + offset);
117 }
118
119 static inline void
120 smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value)
121 {
122 iowrite32(value, pd->base_addr + offset);
123 }
124
125 static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd)
126 {
127 /* to ensure PCI write completion, we must perform a PCI read */
128 smsc9420_reg_read(pd, ID_REV);
129 }
130
131 static int smsc9420_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
132 {
133 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
134 unsigned long flags;
135 u32 addr;
136 int i, reg = -EIO;
137
138 spin_lock_irqsave(&pd->phy_lock, flags);
139
140 /* confirm MII not busy */
141 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
142 smsc_warn(DRV, "MII is busy???");
143 goto out;
144 }
145
146 /* set the address, index & direction (read from PHY) */
147 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
148 MII_ACCESS_MII_READ_;
149 smsc9420_reg_write(pd, MII_ACCESS, addr);
150
151 /* wait for read to complete with 50us timeout */
152 for (i = 0; i < 5; i++) {
153 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
154 MII_ACCESS_MII_BUSY_)) {
155 reg = (u16)smsc9420_reg_read(pd, MII_DATA);
156 goto out;
157 }
158 udelay(10);
159 }
160
161 smsc_warn(DRV, "MII busy timeout!");
162
163 out:
164 spin_unlock_irqrestore(&pd->phy_lock, flags);
165 return reg;
166 }
167
168 static int smsc9420_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
169 u16 val)
170 {
171 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
172 unsigned long flags;
173 u32 addr;
174 int i, reg = -EIO;
175
176 spin_lock_irqsave(&pd->phy_lock, flags);
177
178 /* confirm MII not busy */
179 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
180 smsc_warn(DRV, "MII is busy???");
181 goto out;
182 }
183
184 /* put the data to write in the MAC */
185 smsc9420_reg_write(pd, MII_DATA, (u32)val);
186
187 /* set the address, index & direction (write to PHY) */
188 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
189 MII_ACCESS_MII_WRITE_;
190 smsc9420_reg_write(pd, MII_ACCESS, addr);
191
192 /* wait for write to complete with 50us timeout */
193 for (i = 0; i < 5; i++) {
194 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
195 MII_ACCESS_MII_BUSY_)) {
196 reg = 0;
197 goto out;
198 }
199 udelay(10);
200 }
201
202 smsc_warn(DRV, "MII busy timeout!");
203
204 out:
205 spin_unlock_irqrestore(&pd->phy_lock, flags);
206 return reg;
207 }
208
209 /* Returns hash bit number for given MAC address
210 * Example:
211 * 01 00 5E 00 00 01 -> returns bit number 31 */
212 static u32 smsc9420_hash(u8 addr[ETH_ALEN])
213 {
214 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
215 }
216
217 static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd)
218 {
219 int timeout = 100000;
220
221 BUG_ON(!pd);
222
223 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
224 smsc_dbg(DRV, "smsc9420_eeprom_reload: Eeprom busy");
225 return -EIO;
226 }
227
228 smsc9420_reg_write(pd, E2P_CMD,
229 (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_));
230
231 do {
232 udelay(10);
233 if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_))
234 return 0;
235 } while (timeout--);
236
237 smsc_warn(DRV, "smsc9420_eeprom_reload: Eeprom timed out");
238 return -EIO;
239 }
240
241 /* Standard ioctls for mii-tool */
242 static int smsc9420_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
243 {
244 struct smsc9420_pdata *pd = netdev_priv(dev);
245
246 if (!netif_running(dev) || !pd->phy_dev)
247 return -EINVAL;
248
249 return phy_mii_ioctl(pd->phy_dev, ifr, cmd);
250 }
251
252 static int smsc9420_ethtool_get_settings(struct net_device *dev,
253 struct ethtool_cmd *cmd)
254 {
255 struct smsc9420_pdata *pd = netdev_priv(dev);
256
257 if (!pd->phy_dev)
258 return -ENODEV;
259
260 cmd->maxtxpkt = 1;
261 cmd->maxrxpkt = 1;
262 return phy_ethtool_gset(pd->phy_dev, cmd);
263 }
264
265 static int smsc9420_ethtool_set_settings(struct net_device *dev,
266 struct ethtool_cmd *cmd)
267 {
268 struct smsc9420_pdata *pd = netdev_priv(dev);
269
270 if (!pd->phy_dev)
271 return -ENODEV;
272
273 return phy_ethtool_sset(pd->phy_dev, cmd);
274 }
275
276 static void smsc9420_ethtool_get_drvinfo(struct net_device *netdev,
277 struct ethtool_drvinfo *drvinfo)
278 {
279 struct smsc9420_pdata *pd = netdev_priv(netdev);
280
281 strcpy(drvinfo->driver, DRV_NAME);
282 strcpy(drvinfo->bus_info, pci_name(pd->pdev));
283 strcpy(drvinfo->version, DRV_VERSION);
284 }
285
286 static u32 smsc9420_ethtool_get_msglevel(struct net_device *netdev)
287 {
288 struct smsc9420_pdata *pd = netdev_priv(netdev);
289 return pd->msg_enable;
290 }
291
292 static void smsc9420_ethtool_set_msglevel(struct net_device *netdev, u32 data)
293 {
294 struct smsc9420_pdata *pd = netdev_priv(netdev);
295 pd->msg_enable = data;
296 }
297
298 static int smsc9420_ethtool_nway_reset(struct net_device *netdev)
299 {
300 struct smsc9420_pdata *pd = netdev_priv(netdev);
301
302 if (!pd->phy_dev)
303 return -ENODEV;
304
305 return phy_start_aneg(pd->phy_dev);
306 }
307
308 static int smsc9420_ethtool_getregslen(struct net_device *dev)
309 {
310 /* all smsc9420 registers plus all phy registers */
311 return 0x100 + (32 * sizeof(u32));
312 }
313
314 static void
315 smsc9420_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
316 void *buf)
317 {
318 struct smsc9420_pdata *pd = netdev_priv(dev);
319 struct phy_device *phy_dev = pd->phy_dev;
320 unsigned int i, j = 0;
321 u32 *data = buf;
322
323 regs->version = smsc9420_reg_read(pd, ID_REV);
324 for (i = 0; i < 0x100; i += (sizeof(u32)))
325 data[j++] = smsc9420_reg_read(pd, i);
326
327 // cannot read phy registers if the net device is down
328 if (!phy_dev)
329 return;
330
331 for (i = 0; i <= 31; i++)
332 data[j++] = smsc9420_mii_read(phy_dev->bus, phy_dev->addr, i);
333 }
334
335 static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd)
336 {
337 unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG);
338 temp &= ~GPIO_CFG_EEPR_EN_;
339 smsc9420_reg_write(pd, GPIO_CFG, temp);
340 msleep(1);
341 }
342
343 static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op)
344 {
345 int timeout = 100;
346 u32 e2cmd;
347
348 smsc_dbg(HW, "op 0x%08x", op);
349 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
350 smsc_warn(HW, "Busy at start");
351 return -EBUSY;
352 }
353
354 e2cmd = op | E2P_CMD_EPC_BUSY_;
355 smsc9420_reg_write(pd, E2P_CMD, e2cmd);
356
357 do {
358 msleep(1);
359 e2cmd = smsc9420_reg_read(pd, E2P_CMD);
360 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
361
362 if (!timeout) {
363 smsc_info(HW, "TIMED OUT");
364 return -EAGAIN;
365 }
366
367 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
368 smsc_info(HW, "Error occurred during eeprom operation");
369 return -EINVAL;
370 }
371
372 return 0;
373 }
374
375 static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd,
376 u8 address, u8 *data)
377 {
378 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
379 int ret;
380
381 smsc_dbg(HW, "address 0x%x", address);
382 ret = smsc9420_eeprom_send_cmd(pd, op);
383
384 if (!ret)
385 data[address] = smsc9420_reg_read(pd, E2P_DATA);
386
387 return ret;
388 }
389
390 static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd,
391 u8 address, u8 data)
392 {
393 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
394 int ret;
395
396 smsc_dbg(HW, "address 0x%x, data 0x%x", address, data);
397 ret = smsc9420_eeprom_send_cmd(pd, op);
398
399 if (!ret) {
400 op = E2P_CMD_EPC_CMD_WRITE_ | address;
401 smsc9420_reg_write(pd, E2P_DATA, (u32)data);
402 ret = smsc9420_eeprom_send_cmd(pd, op);
403 }
404
405 return ret;
406 }
407
408 static int smsc9420_ethtool_get_eeprom_len(struct net_device *dev)
409 {
410 return SMSC9420_EEPROM_SIZE;
411 }
412
413 static int smsc9420_ethtool_get_eeprom(struct net_device *dev,
414 struct ethtool_eeprom *eeprom, u8 *data)
415 {
416 struct smsc9420_pdata *pd = netdev_priv(dev);
417 u8 eeprom_data[SMSC9420_EEPROM_SIZE];
418 int len, i;
419
420 smsc9420_eeprom_enable_access(pd);
421
422 len = min(eeprom->len, SMSC9420_EEPROM_SIZE);
423 for (i = 0; i < len; i++) {
424 int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data);
425 if (ret < 0) {
426 eeprom->len = 0;
427 return ret;
428 }
429 }
430
431 memcpy(data, &eeprom_data[eeprom->offset], len);
432 eeprom->magic = SMSC9420_EEPROM_MAGIC;
433 eeprom->len = len;
434 return 0;
435 }
436
437 static int smsc9420_ethtool_set_eeprom(struct net_device *dev,
438 struct ethtool_eeprom *eeprom, u8 *data)
439 {
440 struct smsc9420_pdata *pd = netdev_priv(dev);
441 int ret;
442
443 if (eeprom->magic != SMSC9420_EEPROM_MAGIC)
444 return -EINVAL;
445
446 smsc9420_eeprom_enable_access(pd);
447 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_);
448 ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data);
449 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_);
450
451 /* Single byte write, according to man page */
452 eeprom->len = 1;
453
454 return ret;
455 }
456
457 static const struct ethtool_ops smsc9420_ethtool_ops = {
458 .get_settings = smsc9420_ethtool_get_settings,
459 .set_settings = smsc9420_ethtool_set_settings,
460 .get_drvinfo = smsc9420_ethtool_get_drvinfo,
461 .get_msglevel = smsc9420_ethtool_get_msglevel,
462 .set_msglevel = smsc9420_ethtool_set_msglevel,
463 .nway_reset = smsc9420_ethtool_nway_reset,
464 .get_link = ethtool_op_get_link,
465 .get_eeprom_len = smsc9420_ethtool_get_eeprom_len,
466 .get_eeprom = smsc9420_ethtool_get_eeprom,
467 .set_eeprom = smsc9420_ethtool_set_eeprom,
468 .get_regs_len = smsc9420_ethtool_getregslen,
469 .get_regs = smsc9420_ethtool_getregs,
470 };
471
472 /* Sets the device MAC address to dev_addr */
473 static void smsc9420_set_mac_address(struct net_device *dev)
474 {
475 struct smsc9420_pdata *pd = netdev_priv(dev);
476 u8 *dev_addr = dev->dev_addr;
477 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
478 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
479 (dev_addr[1] << 8) | dev_addr[0];
480
481 smsc9420_reg_write(pd, ADDRH, mac_high16);
482 smsc9420_reg_write(pd, ADDRL, mac_low32);
483 }
484
485 static void smsc9420_check_mac_address(struct net_device *dev)
486 {
487 struct smsc9420_pdata *pd = netdev_priv(dev);
488
489 /* Check if mac address has been specified when bringing interface up */
490 if (is_valid_ether_addr(dev->dev_addr)) {
491 smsc9420_set_mac_address(dev);
492 smsc_dbg(PROBE, "MAC Address is specified by configuration");
493 } else {
494 /* Try reading mac address from device. if EEPROM is present
495 * it will already have been set */
496 u32 mac_high16 = smsc9420_reg_read(pd, ADDRH);
497 u32 mac_low32 = smsc9420_reg_read(pd, ADDRL);
498 dev->dev_addr[0] = (u8)(mac_low32);
499 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
500 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
501 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
502 dev->dev_addr[4] = (u8)(mac_high16);
503 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
504
505 if (is_valid_ether_addr(dev->dev_addr)) {
506 /* eeprom values are valid so use them */
507 smsc_dbg(PROBE, "Mac Address is read from EEPROM");
508 } else {
509 /* eeprom values are invalid, generate random MAC */
510 random_ether_addr(dev->dev_addr);
511 smsc9420_set_mac_address(dev);
512 smsc_dbg(PROBE,
513 "MAC Address is set to random_ether_addr");
514 }
515 }
516 }
517
518 static void smsc9420_stop_tx(struct smsc9420_pdata *pd)
519 {
520 u32 dmac_control, mac_cr, dma_intr_ena;
521 int timeout = 1000;
522
523 /* disable TX DMAC */
524 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
525 dmac_control &= (~DMAC_CONTROL_ST_);
526 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
527
528 /* Wait max 10ms for transmit process to stop */
529 while (--timeout) {
530 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_)
531 break;
532 udelay(10);
533 }
534
535 if (!timeout)
536 smsc_warn(IFDOWN, "TX DMAC failed to stop");
537
538 /* ACK Tx DMAC stop bit */
539 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_);
540
541 /* mask TX DMAC interrupts */
542 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
543 dma_intr_ena &= ~(DMAC_INTR_ENA_TX_);
544 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
545 smsc9420_pci_flush_write(pd);
546
547 /* stop MAC TX */
548 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_);
549 smsc9420_reg_write(pd, MAC_CR, mac_cr);
550 smsc9420_pci_flush_write(pd);
551 }
552
553 static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd)
554 {
555 int i;
556
557 BUG_ON(!pd->tx_ring);
558
559 if (!pd->tx_buffers)
560 return;
561
562 for (i = 0; i < TX_RING_SIZE; i++) {
563 struct sk_buff *skb = pd->tx_buffers[i].skb;
564
565 if (skb) {
566 BUG_ON(!pd->tx_buffers[i].mapping);
567 pci_unmap_single(pd->pdev, pd->tx_buffers[i].mapping,
568 skb->len, PCI_DMA_TODEVICE);
569 dev_kfree_skb_any(skb);
570 }
571
572 pd->tx_ring[i].status = 0;
573 pd->tx_ring[i].length = 0;
574 pd->tx_ring[i].buffer1 = 0;
575 pd->tx_ring[i].buffer2 = 0;
576 }
577 wmb();
578
579 kfree(pd->tx_buffers);
580 pd->tx_buffers = NULL;
581
582 pd->tx_ring_head = 0;
583 pd->tx_ring_tail = 0;
584 }
585
586 static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd)
587 {
588 int i;
589
590 BUG_ON(!pd->rx_ring);
591
592 if (!pd->rx_buffers)
593 return;
594
595 for (i = 0; i < RX_RING_SIZE; i++) {
596 if (pd->rx_buffers[i].skb)
597 dev_kfree_skb_any(pd->rx_buffers[i].skb);
598
599 if (pd->rx_buffers[i].mapping)
600 pci_unmap_single(pd->pdev, pd->rx_buffers[i].mapping,
601 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
602
603 pd->rx_ring[i].status = 0;
604 pd->rx_ring[i].length = 0;
605 pd->rx_ring[i].buffer1 = 0;
606 pd->rx_ring[i].buffer2 = 0;
607 }
608 wmb();
609
610 kfree(pd->rx_buffers);
611 pd->rx_buffers = NULL;
612
613 pd->rx_ring_head = 0;
614 pd->rx_ring_tail = 0;
615 }
616
617 static void smsc9420_stop_rx(struct smsc9420_pdata *pd)
618 {
619 int timeout = 1000;
620 u32 mac_cr, dmac_control, dma_intr_ena;
621
622 /* mask RX DMAC interrupts */
623 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
624 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
625 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
626 smsc9420_pci_flush_write(pd);
627
628 /* stop RX MAC prior to stoping DMA */
629 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_);
630 smsc9420_reg_write(pd, MAC_CR, mac_cr);
631 smsc9420_pci_flush_write(pd);
632
633 /* stop RX DMAC */
634 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
635 dmac_control &= (~DMAC_CONTROL_SR_);
636 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
637 smsc9420_pci_flush_write(pd);
638
639 /* wait up to 10ms for receive to stop */
640 while (--timeout) {
641 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_)
642 break;
643 udelay(10);
644 }
645
646 if (!timeout)
647 smsc_warn(IFDOWN, "RX DMAC did not stop! timeout.");
648
649 /* ACK the Rx DMAC stop bit */
650 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_);
651 }
652
653 static irqreturn_t smsc9420_isr(int irq, void *dev_id)
654 {
655 struct smsc9420_pdata *pd = dev_id;
656 u32 int_cfg, int_sts, int_ctl;
657 irqreturn_t ret = IRQ_NONE;
658 ulong flags;
659
660 BUG_ON(!pd);
661 BUG_ON(!pd->base_addr);
662
663 int_cfg = smsc9420_reg_read(pd, INT_CFG);
664
665 /* check if it's our interrupt */
666 if ((int_cfg & (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) !=
667 (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_))
668 return IRQ_NONE;
669
670 int_sts = smsc9420_reg_read(pd, INT_STAT);
671
672 if (likely(INT_STAT_DMAC_INT_ & int_sts)) {
673 u32 status = smsc9420_reg_read(pd, DMAC_STATUS);
674 u32 ints_to_clear = 0;
675
676 if (status & DMAC_STS_TX_) {
677 ints_to_clear |= (DMAC_STS_TX_ | DMAC_STS_NIS_);
678 netif_wake_queue(pd->dev);
679 }
680
681 if (status & DMAC_STS_RX_) {
682 /* mask RX DMAC interrupts */
683 u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
684 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
685 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
686 smsc9420_pci_flush_write(pd);
687
688 ints_to_clear |= (DMAC_STS_RX_ | DMAC_STS_NIS_);
689 napi_schedule(&pd->napi);
690 }
691
692 if (ints_to_clear)
693 smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear);
694
695 ret = IRQ_HANDLED;
696 }
697
698 if (unlikely(INT_STAT_SW_INT_ & int_sts)) {
699 /* mask software interrupt */
700 spin_lock_irqsave(&pd->int_lock, flags);
701 int_ctl = smsc9420_reg_read(pd, INT_CTL);
702 int_ctl &= (~INT_CTL_SW_INT_EN_);
703 smsc9420_reg_write(pd, INT_CTL, int_ctl);
704 spin_unlock_irqrestore(&pd->int_lock, flags);
705
706 smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_);
707 pd->software_irq_signal = true;
708 smp_wmb();
709
710 ret = IRQ_HANDLED;
711 }
712
713 /* to ensure PCI write completion, we must perform a PCI read */
714 smsc9420_pci_flush_write(pd);
715
716 return ret;
717 }
718
719 #ifdef CONFIG_NET_POLL_CONTROLLER
720 static void smsc9420_poll_controller(struct net_device *dev)
721 {
722 disable_irq(dev->irq);
723 smsc9420_isr(0, dev);
724 enable_irq(dev->irq);
725 }
726 #endif /* CONFIG_NET_POLL_CONTROLLER */
727
728 static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd)
729 {
730 smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_);
731 smsc9420_reg_read(pd, BUS_MODE);
732 udelay(2);
733 if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_)
734 smsc_warn(DRV, "Software reset not cleared");
735 }
736
737 static int smsc9420_stop(struct net_device *dev)
738 {
739 struct smsc9420_pdata *pd = netdev_priv(dev);
740 u32 int_cfg;
741 ulong flags;
742
743 BUG_ON(!pd);
744 BUG_ON(!pd->phy_dev);
745
746 /* disable master interrupt */
747 spin_lock_irqsave(&pd->int_lock, flags);
748 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
749 smsc9420_reg_write(pd, INT_CFG, int_cfg);
750 spin_unlock_irqrestore(&pd->int_lock, flags);
751
752 netif_tx_disable(dev);
753 napi_disable(&pd->napi);
754
755 smsc9420_stop_tx(pd);
756 smsc9420_free_tx_ring(pd);
757
758 smsc9420_stop_rx(pd);
759 smsc9420_free_rx_ring(pd);
760
761 free_irq(dev->irq, pd);
762
763 smsc9420_dmac_soft_reset(pd);
764
765 phy_stop(pd->phy_dev);
766
767 phy_disconnect(pd->phy_dev);
768 pd->phy_dev = NULL;
769 mdiobus_unregister(pd->mii_bus);
770 mdiobus_free(pd->mii_bus);
771
772 return 0;
773 }
774
775 static void smsc9420_rx_count_stats(struct net_device *dev, u32 desc_status)
776 {
777 if (unlikely(desc_status & RDES0_ERROR_SUMMARY_)) {
778 dev->stats.rx_errors++;
779 if (desc_status & RDES0_DESCRIPTOR_ERROR_)
780 dev->stats.rx_over_errors++;
781 else if (desc_status & (RDES0_FRAME_TOO_LONG_ |
782 RDES0_RUNT_FRAME_ | RDES0_COLLISION_SEEN_))
783 dev->stats.rx_frame_errors++;
784 else if (desc_status & RDES0_CRC_ERROR_)
785 dev->stats.rx_crc_errors++;
786 }
787
788 if (unlikely(desc_status & RDES0_LENGTH_ERROR_))
789 dev->stats.rx_length_errors++;
790
791 if (unlikely(!((desc_status & RDES0_LAST_DESCRIPTOR_) &&
792 (desc_status & RDES0_FIRST_DESCRIPTOR_))))
793 dev->stats.rx_length_errors++;
794
795 if (desc_status & RDES0_MULTICAST_FRAME_)
796 dev->stats.multicast++;
797 }
798
799 static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index,
800 const u32 status)
801 {
802 struct net_device *dev = pd->dev;
803 struct sk_buff *skb;
804 u16 packet_length = (status & RDES0_FRAME_LENGTH_MASK_)
805 >> RDES0_FRAME_LENGTH_SHFT_;
806
807 /* remove crc from packet lendth */
808 packet_length -= 4;
809
810 if (pd->rx_csum)
811 packet_length -= 2;
812
813 dev->stats.rx_packets++;
814 dev->stats.rx_bytes += packet_length;
815
816 pci_unmap_single(pd->pdev, pd->rx_buffers[index].mapping,
817 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
818 pd->rx_buffers[index].mapping = 0;
819
820 skb = pd->rx_buffers[index].skb;
821 pd->rx_buffers[index].skb = NULL;
822
823 if (pd->rx_csum) {
824 u16 hw_csum = get_unaligned_le16(skb_tail_pointer(skb) +
825 NET_IP_ALIGN + packet_length + 4);
826 put_unaligned_le16(hw_csum, &skb->csum);
827 skb->ip_summed = CHECKSUM_COMPLETE;
828 }
829
830 skb_reserve(skb, NET_IP_ALIGN);
831 skb_put(skb, packet_length);
832
833 skb->protocol = eth_type_trans(skb, dev);
834
835 netif_receive_skb(skb);
836 }
837
838 static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index)
839 {
840 struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ);
841 dma_addr_t mapping;
842
843 BUG_ON(pd->rx_buffers[index].skb);
844 BUG_ON(pd->rx_buffers[index].mapping);
845
846 if (unlikely(!skb)) {
847 smsc_warn(RX_ERR, "Failed to allocate new skb!");
848 return -ENOMEM;
849 }
850
851 skb->dev = pd->dev;
852
853 mapping = pci_map_single(pd->pdev, skb_tail_pointer(skb),
854 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
855 if (pci_dma_mapping_error(pd->pdev, mapping)) {
856 dev_kfree_skb_any(skb);
857 smsc_warn(RX_ERR, "pci_map_single failed!");
858 return -ENOMEM;
859 }
860
861 pd->rx_buffers[index].skb = skb;
862 pd->rx_buffers[index].mapping = mapping;
863 pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN;
864 pd->rx_ring[index].status = RDES0_OWN_;
865 wmb();
866
867 return 0;
868 }
869
870 static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd)
871 {
872 while (pd->rx_ring_tail != pd->rx_ring_head) {
873 if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail))
874 break;
875
876 pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE;
877 }
878 }
879
880 static int smsc9420_rx_poll(struct napi_struct *napi, int budget)
881 {
882 struct smsc9420_pdata *pd =
883 container_of(napi, struct smsc9420_pdata, napi);
884 struct net_device *dev = pd->dev;
885 u32 drop_frame_cnt, dma_intr_ena, status;
886 int work_done;
887
888 for (work_done = 0; work_done < budget; work_done++) {
889 rmb();
890 status = pd->rx_ring[pd->rx_ring_head].status;
891
892 /* stop if DMAC owns this dma descriptor */
893 if (status & RDES0_OWN_)
894 break;
895
896 smsc9420_rx_count_stats(dev, status);
897 smsc9420_rx_handoff(pd, pd->rx_ring_head, status);
898 pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE;
899 smsc9420_alloc_new_rx_buffers(pd);
900 }
901
902 drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
903 dev->stats.rx_dropped +=
904 (drop_frame_cnt & 0xFFFF) + ((drop_frame_cnt >> 17) & 0x3FF);
905
906 /* Kick RXDMA */
907 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
908 smsc9420_pci_flush_write(pd);
909
910 if (work_done < budget) {
911 napi_complete(&pd->napi);
912
913 /* re-enable RX DMA interrupts */
914 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
915 dma_intr_ena |= (DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
916 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
917 smsc9420_pci_flush_write(pd);
918 }
919 return work_done;
920 }
921
922 static void
923 smsc9420_tx_update_stats(struct net_device *dev, u32 status, u32 length)
924 {
925 if (unlikely(status & TDES0_ERROR_SUMMARY_)) {
926 dev->stats.tx_errors++;
927 if (status & (TDES0_EXCESSIVE_DEFERRAL_ |
928 TDES0_EXCESSIVE_COLLISIONS_))
929 dev->stats.tx_aborted_errors++;
930
931 if (status & (TDES0_LOSS_OF_CARRIER_ | TDES0_NO_CARRIER_))
932 dev->stats.tx_carrier_errors++;
933 } else {
934 dev->stats.tx_packets++;
935 dev->stats.tx_bytes += (length & 0x7FF);
936 }
937
938 if (unlikely(status & TDES0_EXCESSIVE_COLLISIONS_)) {
939 dev->stats.collisions += 16;
940 } else {
941 dev->stats.collisions +=
942 (status & TDES0_COLLISION_COUNT_MASK_) >>
943 TDES0_COLLISION_COUNT_SHFT_;
944 }
945
946 if (unlikely(status & TDES0_HEARTBEAT_FAIL_))
947 dev->stats.tx_heartbeat_errors++;
948 }
949
950 /* Check for completed dma transfers, update stats and free skbs */
951 static void smsc9420_complete_tx(struct net_device *dev)
952 {
953 struct smsc9420_pdata *pd = netdev_priv(dev);
954
955 while (pd->tx_ring_tail != pd->tx_ring_head) {
956 int index = pd->tx_ring_tail;
957 u32 status, length;
958
959 rmb();
960 status = pd->tx_ring[index].status;
961 length = pd->tx_ring[index].length;
962
963 /* Check if DMA still owns this descriptor */
964 if (unlikely(TDES0_OWN_ & status))
965 break;
966
967 smsc9420_tx_update_stats(dev, status, length);
968
969 BUG_ON(!pd->tx_buffers[index].skb);
970 BUG_ON(!pd->tx_buffers[index].mapping);
971
972 pci_unmap_single(pd->pdev, pd->tx_buffers[index].mapping,
973 pd->tx_buffers[index].skb->len, PCI_DMA_TODEVICE);
974 pd->tx_buffers[index].mapping = 0;
975
976 dev_kfree_skb_any(pd->tx_buffers[index].skb);
977 pd->tx_buffers[index].skb = NULL;
978
979 pd->tx_ring[index].buffer1 = 0;
980 wmb();
981
982 pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE;
983 }
984 }
985
986 static netdev_tx_t smsc9420_hard_start_xmit(struct sk_buff *skb,
987 struct net_device *dev)
988 {
989 struct smsc9420_pdata *pd = netdev_priv(dev);
990 dma_addr_t mapping;
991 int index = pd->tx_ring_head;
992 u32 tmp_desc1;
993 bool about_to_take_last_desc =
994 (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail);
995
996 smsc9420_complete_tx(dev);
997
998 rmb();
999 BUG_ON(pd->tx_ring[index].status & TDES0_OWN_);
1000 BUG_ON(pd->tx_buffers[index].skb);
1001 BUG_ON(pd->tx_buffers[index].mapping);
1002
1003 mapping = pci_map_single(pd->pdev, skb->data,
1004 skb->len, PCI_DMA_TODEVICE);
1005 if (pci_dma_mapping_error(pd->pdev, mapping)) {
1006 smsc_warn(TX_ERR, "pci_map_single failed, dropping packet");
1007 return NETDEV_TX_BUSY;
1008 }
1009
1010 pd->tx_buffers[index].skb = skb;
1011 pd->tx_buffers[index].mapping = mapping;
1012
1013 tmp_desc1 = (TDES1_LS_ | ((u32)skb->len & 0x7FF));
1014 if (unlikely(about_to_take_last_desc)) {
1015 tmp_desc1 |= TDES1_IC_;
1016 netif_stop_queue(pd->dev);
1017 }
1018
1019 /* check if we are at the last descriptor and need to set EOR */
1020 if (unlikely(index == (TX_RING_SIZE - 1)))
1021 tmp_desc1 |= TDES1_TER_;
1022
1023 pd->tx_ring[index].buffer1 = mapping;
1024 pd->tx_ring[index].length = tmp_desc1;
1025 wmb();
1026
1027 /* increment head */
1028 pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE;
1029
1030 /* assign ownership to DMAC */
1031 pd->tx_ring[index].status = TDES0_OWN_;
1032 wmb();
1033
1034 skb_tx_timestamp(skb);
1035
1036 /* kick the DMA */
1037 smsc9420_reg_write(pd, TX_POLL_DEMAND, 1);
1038 smsc9420_pci_flush_write(pd);
1039
1040 return NETDEV_TX_OK;
1041 }
1042
1043 static struct net_device_stats *smsc9420_get_stats(struct net_device *dev)
1044 {
1045 struct smsc9420_pdata *pd = netdev_priv(dev);
1046 u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
1047 dev->stats.rx_dropped +=
1048 (counter & 0x0000FFFF) + ((counter >> 17) & 0x000003FF);
1049 return &dev->stats;
1050 }
1051
1052 static void smsc9420_set_multicast_list(struct net_device *dev)
1053 {
1054 struct smsc9420_pdata *pd = netdev_priv(dev);
1055 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1056
1057 if (dev->flags & IFF_PROMISC) {
1058 smsc_dbg(HW, "Promiscuous Mode Enabled");
1059 mac_cr |= MAC_CR_PRMS_;
1060 mac_cr &= (~MAC_CR_MCPAS_);
1061 mac_cr &= (~MAC_CR_HPFILT_);
1062 } else if (dev->flags & IFF_ALLMULTI) {
1063 smsc_dbg(HW, "Receive all Multicast Enabled");
1064 mac_cr &= (~MAC_CR_PRMS_);
1065 mac_cr |= MAC_CR_MCPAS_;
1066 mac_cr &= (~MAC_CR_HPFILT_);
1067 } else if (!netdev_mc_empty(dev)) {
1068 struct netdev_hw_addr *ha;
1069 u32 hash_lo = 0, hash_hi = 0;
1070
1071 smsc_dbg(HW, "Multicast filter enabled");
1072 netdev_for_each_mc_addr(ha, dev) {
1073 u32 bit_num = smsc9420_hash(ha->addr);
1074 u32 mask = 1 << (bit_num & 0x1F);
1075
1076 if (bit_num & 0x20)
1077 hash_hi |= mask;
1078 else
1079 hash_lo |= mask;
1080
1081 }
1082 smsc9420_reg_write(pd, HASHH, hash_hi);
1083 smsc9420_reg_write(pd, HASHL, hash_lo);
1084
1085 mac_cr &= (~MAC_CR_PRMS_);
1086 mac_cr &= (~MAC_CR_MCPAS_);
1087 mac_cr |= MAC_CR_HPFILT_;
1088 } else {
1089 smsc_dbg(HW, "Receive own packets only.");
1090 smsc9420_reg_write(pd, HASHH, 0);
1091 smsc9420_reg_write(pd, HASHL, 0);
1092
1093 mac_cr &= (~MAC_CR_PRMS_);
1094 mac_cr &= (~MAC_CR_MCPAS_);
1095 mac_cr &= (~MAC_CR_HPFILT_);
1096 }
1097
1098 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1099 smsc9420_pci_flush_write(pd);
1100 }
1101
1102 static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd)
1103 {
1104 struct phy_device *phy_dev = pd->phy_dev;
1105 u32 flow;
1106
1107 if (phy_dev->duplex == DUPLEX_FULL) {
1108 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
1109 u16 rmtadv = phy_read(phy_dev, MII_LPA);
1110 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1111
1112 if (cap & FLOW_CTRL_RX)
1113 flow = 0xFFFF0002;
1114 else
1115 flow = 0;
1116
1117 smsc_info(LINK, "rx pause %s, tx pause %s",
1118 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
1119 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
1120 } else {
1121 smsc_info(LINK, "half duplex");
1122 flow = 0;
1123 }
1124
1125 smsc9420_reg_write(pd, FLOW, flow);
1126 }
1127
1128 /* Update link mode if anything has changed. Called periodically when the
1129 * PHY is in polling mode, even if nothing has changed. */
1130 static void smsc9420_phy_adjust_link(struct net_device *dev)
1131 {
1132 struct smsc9420_pdata *pd = netdev_priv(dev);
1133 struct phy_device *phy_dev = pd->phy_dev;
1134 int carrier;
1135
1136 if (phy_dev->duplex != pd->last_duplex) {
1137 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1138 if (phy_dev->duplex) {
1139 smsc_dbg(LINK, "full duplex mode");
1140 mac_cr |= MAC_CR_FDPX_;
1141 } else {
1142 smsc_dbg(LINK, "half duplex mode");
1143 mac_cr &= ~MAC_CR_FDPX_;
1144 }
1145 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1146
1147 smsc9420_phy_update_flowcontrol(pd);
1148 pd->last_duplex = phy_dev->duplex;
1149 }
1150
1151 carrier = netif_carrier_ok(dev);
1152 if (carrier != pd->last_carrier) {
1153 if (carrier)
1154 smsc_dbg(LINK, "carrier OK");
1155 else
1156 smsc_dbg(LINK, "no carrier");
1157 pd->last_carrier = carrier;
1158 }
1159 }
1160
1161 static int smsc9420_mii_probe(struct net_device *dev)
1162 {
1163 struct smsc9420_pdata *pd = netdev_priv(dev);
1164 struct phy_device *phydev = NULL;
1165
1166 BUG_ON(pd->phy_dev);
1167
1168 /* Device only supports internal PHY at address 1 */
1169 if (!pd->mii_bus->phy_map[1]) {
1170 pr_err("%s: no PHY found at address 1\n", dev->name);
1171 return -ENODEV;
1172 }
1173
1174 phydev = pd->mii_bus->phy_map[1];
1175 smsc_info(PROBE, "PHY addr %d, phy_id 0x%08X", phydev->addr,
1176 phydev->phy_id);
1177
1178 phydev = phy_connect(dev, dev_name(&phydev->dev),
1179 smsc9420_phy_adjust_link, 0, PHY_INTERFACE_MODE_MII);
1180
1181 if (IS_ERR(phydev)) {
1182 pr_err("%s: Could not attach to PHY\n", dev->name);
1183 return PTR_ERR(phydev);
1184 }
1185
1186 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1187 dev->name, phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
1188
1189 /* mask with MAC supported features */
1190 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
1191 SUPPORTED_Asym_Pause);
1192 phydev->advertising = phydev->supported;
1193
1194 pd->phy_dev = phydev;
1195 pd->last_duplex = -1;
1196 pd->last_carrier = -1;
1197
1198 return 0;
1199 }
1200
1201 static int smsc9420_mii_init(struct net_device *dev)
1202 {
1203 struct smsc9420_pdata *pd = netdev_priv(dev);
1204 int err = -ENXIO, i;
1205
1206 pd->mii_bus = mdiobus_alloc();
1207 if (!pd->mii_bus) {
1208 err = -ENOMEM;
1209 goto err_out_1;
1210 }
1211 pd->mii_bus->name = DRV_MDIONAME;
1212 snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x",
1213 (pd->pdev->bus->number << 8) | pd->pdev->devfn);
1214 pd->mii_bus->priv = pd;
1215 pd->mii_bus->read = smsc9420_mii_read;
1216 pd->mii_bus->write = smsc9420_mii_write;
1217 pd->mii_bus->irq = pd->phy_irq;
1218 for (i = 0; i < PHY_MAX_ADDR; ++i)
1219 pd->mii_bus->irq[i] = PHY_POLL;
1220
1221 /* Mask all PHYs except ID 1 (internal) */
1222 pd->mii_bus->phy_mask = ~(1 << 1);
1223
1224 if (mdiobus_register(pd->mii_bus)) {
1225 smsc_warn(PROBE, "Error registering mii bus");
1226 goto err_out_free_bus_2;
1227 }
1228
1229 if (smsc9420_mii_probe(dev) < 0) {
1230 smsc_warn(PROBE, "Error probing mii bus");
1231 goto err_out_unregister_bus_3;
1232 }
1233
1234 return 0;
1235
1236 err_out_unregister_bus_3:
1237 mdiobus_unregister(pd->mii_bus);
1238 err_out_free_bus_2:
1239 mdiobus_free(pd->mii_bus);
1240 err_out_1:
1241 return err;
1242 }
1243
1244 static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd)
1245 {
1246 int i;
1247
1248 BUG_ON(!pd->tx_ring);
1249
1250 pd->tx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) *
1251 TX_RING_SIZE), GFP_KERNEL);
1252 if (!pd->tx_buffers) {
1253 smsc_warn(IFUP, "Failed to allocated tx_buffers");
1254 return -ENOMEM;
1255 }
1256
1257 /* Initialize the TX Ring */
1258 for (i = 0; i < TX_RING_SIZE; i++) {
1259 pd->tx_buffers[i].skb = NULL;
1260 pd->tx_buffers[i].mapping = 0;
1261 pd->tx_ring[i].status = 0;
1262 pd->tx_ring[i].length = 0;
1263 pd->tx_ring[i].buffer1 = 0;
1264 pd->tx_ring[i].buffer2 = 0;
1265 }
1266 pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_;
1267 wmb();
1268
1269 pd->tx_ring_head = 0;
1270 pd->tx_ring_tail = 0;
1271
1272 smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr);
1273 smsc9420_pci_flush_write(pd);
1274
1275 return 0;
1276 }
1277
1278 static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd)
1279 {
1280 int i;
1281
1282 BUG_ON(!pd->rx_ring);
1283
1284 pd->rx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) *
1285 RX_RING_SIZE), GFP_KERNEL);
1286 if (pd->rx_buffers == NULL) {
1287 smsc_warn(IFUP, "Failed to allocated rx_buffers");
1288 goto out;
1289 }
1290
1291 /* initialize the rx ring */
1292 for (i = 0; i < RX_RING_SIZE; i++) {
1293 pd->rx_ring[i].status = 0;
1294 pd->rx_ring[i].length = PKT_BUF_SZ;
1295 pd->rx_ring[i].buffer2 = 0;
1296 pd->rx_buffers[i].skb = NULL;
1297 pd->rx_buffers[i].mapping = 0;
1298 }
1299 pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_);
1300
1301 /* now allocate the entire ring of skbs */
1302 for (i = 0; i < RX_RING_SIZE; i++) {
1303 if (smsc9420_alloc_rx_buffer(pd, i)) {
1304 smsc_warn(IFUP, "failed to allocate rx skb %d", i);
1305 goto out_free_rx_skbs;
1306 }
1307 }
1308
1309 pd->rx_ring_head = 0;
1310 pd->rx_ring_tail = 0;
1311
1312 smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q);
1313 smsc_dbg(IFUP, "VLAN1 = 0x%08x", smsc9420_reg_read(pd, VLAN1));
1314
1315 if (pd->rx_csum) {
1316 /* Enable RX COE */
1317 u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN;
1318 smsc9420_reg_write(pd, COE_CR, coe);
1319 smsc_dbg(IFUP, "COE_CR = 0x%08x", coe);
1320 }
1321
1322 smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr);
1323 smsc9420_pci_flush_write(pd);
1324
1325 return 0;
1326
1327 out_free_rx_skbs:
1328 smsc9420_free_rx_ring(pd);
1329 out:
1330 return -ENOMEM;
1331 }
1332
1333 static int smsc9420_open(struct net_device *dev)
1334 {
1335 struct smsc9420_pdata *pd;
1336 u32 bus_mode, mac_cr, dmac_control, int_cfg, dma_intr_ena, int_ctl;
1337 unsigned long flags;
1338 int result = 0, timeout;
1339
1340 BUG_ON(!dev);
1341 pd = netdev_priv(dev);
1342 BUG_ON(!pd);
1343
1344 if (!is_valid_ether_addr(dev->dev_addr)) {
1345 smsc_warn(IFUP, "dev_addr is not a valid MAC address");
1346 result = -EADDRNOTAVAIL;
1347 goto out_0;
1348 }
1349
1350 netif_carrier_off(dev);
1351
1352 /* disable, mask and acknowledge all interrupts */
1353 spin_lock_irqsave(&pd->int_lock, flags);
1354 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1355 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1356 smsc9420_reg_write(pd, INT_CTL, 0);
1357 spin_unlock_irqrestore(&pd->int_lock, flags);
1358 smsc9420_reg_write(pd, DMAC_INTR_ENA, 0);
1359 smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF);
1360 smsc9420_pci_flush_write(pd);
1361
1362 if (request_irq(dev->irq, smsc9420_isr, IRQF_SHARED | IRQF_DISABLED,
1363 DRV_NAME, pd)) {
1364 smsc_warn(IFUP, "Unable to use IRQ = %d", dev->irq);
1365 result = -ENODEV;
1366 goto out_0;
1367 }
1368
1369 smsc9420_dmac_soft_reset(pd);
1370
1371 /* make sure MAC_CR is sane */
1372 smsc9420_reg_write(pd, MAC_CR, 0);
1373
1374 smsc9420_set_mac_address(dev);
1375
1376 /* Configure GPIO pins to drive LEDs */
1377 smsc9420_reg_write(pd, GPIO_CFG,
1378 (GPIO_CFG_LED_3_ | GPIO_CFG_LED_2_ | GPIO_CFG_LED_1_));
1379
1380 bus_mode = BUS_MODE_DMA_BURST_LENGTH_16;
1381
1382 #ifdef __BIG_ENDIAN
1383 bus_mode |= BUS_MODE_DBO_;
1384 #endif
1385
1386 smsc9420_reg_write(pd, BUS_MODE, bus_mode);
1387
1388 smsc9420_pci_flush_write(pd);
1389
1390 /* set bus master bridge arbitration priority for Rx and TX DMA */
1391 smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1);
1392
1393 smsc9420_reg_write(pd, DMAC_CONTROL,
1394 (DMAC_CONTROL_SF_ | DMAC_CONTROL_OSF_));
1395
1396 smsc9420_pci_flush_write(pd);
1397
1398 /* test the IRQ connection to the ISR */
1399 smsc_dbg(IFUP, "Testing ISR using IRQ %d", dev->irq);
1400 pd->software_irq_signal = false;
1401
1402 spin_lock_irqsave(&pd->int_lock, flags);
1403 /* configure interrupt deassertion timer and enable interrupts */
1404 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1405 int_cfg &= ~(INT_CFG_INT_DEAS_MASK);
1406 int_cfg |= (INT_DEAS_TIME & INT_CFG_INT_DEAS_MASK);
1407 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1408
1409 /* unmask software interrupt */
1410 int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_;
1411 smsc9420_reg_write(pd, INT_CTL, int_ctl);
1412 spin_unlock_irqrestore(&pd->int_lock, flags);
1413 smsc9420_pci_flush_write(pd);
1414
1415 timeout = 1000;
1416 while (timeout--) {
1417 if (pd->software_irq_signal)
1418 break;
1419 msleep(1);
1420 }
1421
1422 /* disable interrupts */
1423 spin_lock_irqsave(&pd->int_lock, flags);
1424 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1425 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1426 spin_unlock_irqrestore(&pd->int_lock, flags);
1427
1428 if (!pd->software_irq_signal) {
1429 smsc_warn(IFUP, "ISR failed signaling test");
1430 result = -ENODEV;
1431 goto out_free_irq_1;
1432 }
1433
1434 smsc_dbg(IFUP, "ISR passed test using IRQ %d", dev->irq);
1435
1436 result = smsc9420_alloc_tx_ring(pd);
1437 if (result) {
1438 smsc_warn(IFUP, "Failed to Initialize tx dma ring");
1439 result = -ENOMEM;
1440 goto out_free_irq_1;
1441 }
1442
1443 result = smsc9420_alloc_rx_ring(pd);
1444 if (result) {
1445 smsc_warn(IFUP, "Failed to Initialize rx dma ring");
1446 result = -ENOMEM;
1447 goto out_free_tx_ring_2;
1448 }
1449
1450 result = smsc9420_mii_init(dev);
1451 if (result) {
1452 smsc_warn(IFUP, "Failed to initialize Phy");
1453 result = -ENODEV;
1454 goto out_free_rx_ring_3;
1455 }
1456
1457 /* Bring the PHY up */
1458 phy_start(pd->phy_dev);
1459
1460 napi_enable(&pd->napi);
1461
1462 /* start tx and rx */
1463 mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_;
1464 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1465
1466 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
1467 dmac_control |= DMAC_CONTROL_ST_ | DMAC_CONTROL_SR_;
1468 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
1469 smsc9420_pci_flush_write(pd);
1470
1471 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
1472 dma_intr_ena |=
1473 (DMAC_INTR_ENA_TX_ | DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
1474 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
1475 smsc9420_pci_flush_write(pd);
1476
1477 netif_wake_queue(dev);
1478
1479 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
1480
1481 /* enable interrupts */
1482 spin_lock_irqsave(&pd->int_lock, flags);
1483 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1484 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1485 spin_unlock_irqrestore(&pd->int_lock, flags);
1486
1487 return 0;
1488
1489 out_free_rx_ring_3:
1490 smsc9420_free_rx_ring(pd);
1491 out_free_tx_ring_2:
1492 smsc9420_free_tx_ring(pd);
1493 out_free_irq_1:
1494 free_irq(dev->irq, pd);
1495 out_0:
1496 return result;
1497 }
1498
1499 #ifdef CONFIG_PM
1500
1501 static int smsc9420_suspend(struct pci_dev *pdev, pm_message_t state)
1502 {
1503 struct net_device *dev = pci_get_drvdata(pdev);
1504 struct smsc9420_pdata *pd = netdev_priv(dev);
1505 u32 int_cfg;
1506 ulong flags;
1507
1508 /* disable interrupts */
1509 spin_lock_irqsave(&pd->int_lock, flags);
1510 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1511 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1512 spin_unlock_irqrestore(&pd->int_lock, flags);
1513
1514 if (netif_running(dev)) {
1515 netif_tx_disable(dev);
1516 smsc9420_stop_tx(pd);
1517 smsc9420_free_tx_ring(pd);
1518
1519 napi_disable(&pd->napi);
1520 smsc9420_stop_rx(pd);
1521 smsc9420_free_rx_ring(pd);
1522
1523 free_irq(dev->irq, pd);
1524
1525 netif_device_detach(dev);
1526 }
1527
1528 pci_save_state(pdev);
1529 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1530 pci_disable_device(pdev);
1531 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1532
1533 return 0;
1534 }
1535
1536 static int smsc9420_resume(struct pci_dev *pdev)
1537 {
1538 struct net_device *dev = pci_get_drvdata(pdev);
1539 struct smsc9420_pdata *pd = netdev_priv(dev);
1540 int err;
1541
1542 pci_set_power_state(pdev, PCI_D0);
1543 pci_restore_state(pdev);
1544
1545 err = pci_enable_device(pdev);
1546 if (err)
1547 return err;
1548
1549 pci_set_master(pdev);
1550
1551 err = pci_enable_wake(pdev, 0, 0);
1552 if (err)
1553 smsc_warn(IFUP, "pci_enable_wake failed: %d", err);
1554
1555 if (netif_running(dev)) {
1556 err = smsc9420_open(dev);
1557 netif_device_attach(dev);
1558 }
1559 return err;
1560 }
1561
1562 #endif /* CONFIG_PM */
1563
1564 static const struct net_device_ops smsc9420_netdev_ops = {
1565 .ndo_open = smsc9420_open,
1566 .ndo_stop = smsc9420_stop,
1567 .ndo_start_xmit = smsc9420_hard_start_xmit,
1568 .ndo_get_stats = smsc9420_get_stats,
1569 .ndo_set_multicast_list = smsc9420_set_multicast_list,
1570 .ndo_do_ioctl = smsc9420_do_ioctl,
1571 .ndo_validate_addr = eth_validate_addr,
1572 .ndo_set_mac_address = eth_mac_addr,
1573 #ifdef CONFIG_NET_POLL_CONTROLLER
1574 .ndo_poll_controller = smsc9420_poll_controller,
1575 #endif /* CONFIG_NET_POLL_CONTROLLER */
1576 };
1577
1578 static int __devinit
1579 smsc9420_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1580 {
1581 struct net_device *dev;
1582 struct smsc9420_pdata *pd;
1583 void __iomem *virt_addr;
1584 int result = 0;
1585 u32 id_rev;
1586
1587 printk(KERN_INFO DRV_DESCRIPTION " version " DRV_VERSION "\n");
1588
1589 /* First do the PCI initialisation */
1590 result = pci_enable_device(pdev);
1591 if (unlikely(result)) {
1592 printk(KERN_ERR "Cannot enable smsc9420\n");
1593 goto out_0;
1594 }
1595
1596 pci_set_master(pdev);
1597
1598 dev = alloc_etherdev(sizeof(*pd));
1599 if (!dev) {
1600 printk(KERN_ERR "ether device alloc failed\n");
1601 goto out_disable_pci_device_1;
1602 }
1603
1604 SET_NETDEV_DEV(dev, &pdev->dev);
1605
1606 if (!(pci_resource_flags(pdev, SMSC_BAR) & IORESOURCE_MEM)) {
1607 printk(KERN_ERR "Cannot find PCI device base address\n");
1608 goto out_free_netdev_2;
1609 }
1610
1611 if ((pci_request_regions(pdev, DRV_NAME))) {
1612 printk(KERN_ERR "Cannot obtain PCI resources, aborting.\n");
1613 goto out_free_netdev_2;
1614 }
1615
1616 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1617 printk(KERN_ERR "No usable DMA configuration, aborting.\n");
1618 goto out_free_regions_3;
1619 }
1620
1621 virt_addr = ioremap(pci_resource_start(pdev, SMSC_BAR),
1622 pci_resource_len(pdev, SMSC_BAR));
1623 if (!virt_addr) {
1624 printk(KERN_ERR "Cannot map device registers, aborting.\n");
1625 goto out_free_regions_3;
1626 }
1627
1628 /* registers are double mapped with 0 offset for LE and 0x200 for BE */
1629 virt_addr += LAN9420_CPSR_ENDIAN_OFFSET;
1630
1631 dev->base_addr = (ulong)virt_addr;
1632
1633 pd = netdev_priv(dev);
1634
1635 /* pci descriptors are created in the PCI consistent area */
1636 pd->rx_ring = pci_alloc_consistent(pdev,
1637 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE +
1638 sizeof(struct smsc9420_dma_desc) * TX_RING_SIZE,
1639 &pd->rx_dma_addr);
1640
1641 if (!pd->rx_ring)
1642 goto out_free_io_4;
1643
1644 /* descriptors are aligned due to the nature of pci_alloc_consistent */
1645 pd->tx_ring = (struct smsc9420_dma_desc *)
1646 (pd->rx_ring + RX_RING_SIZE);
1647 pd->tx_dma_addr = pd->rx_dma_addr +
1648 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE;
1649
1650 pd->pdev = pdev;
1651 pd->dev = dev;
1652 pd->base_addr = virt_addr;
1653 pd->msg_enable = smsc_debug;
1654 pd->rx_csum = true;
1655
1656 smsc_dbg(PROBE, "lan_base=0x%08lx", (ulong)virt_addr);
1657
1658 id_rev = smsc9420_reg_read(pd, ID_REV);
1659 switch (id_rev & 0xFFFF0000) {
1660 case 0x94200000:
1661 smsc_info(PROBE, "LAN9420 identified, ID_REV=0x%08X", id_rev);
1662 break;
1663 default:
1664 smsc_warn(PROBE, "LAN9420 NOT identified");
1665 smsc_warn(PROBE, "ID_REV=0x%08X", id_rev);
1666 goto out_free_dmadesc_5;
1667 }
1668
1669 smsc9420_dmac_soft_reset(pd);
1670 smsc9420_eeprom_reload(pd);
1671 smsc9420_check_mac_address(dev);
1672
1673 dev->netdev_ops = &smsc9420_netdev_ops;
1674 dev->ethtool_ops = &smsc9420_ethtool_ops;
1675 dev->irq = pdev->irq;
1676
1677 netif_napi_add(dev, &pd->napi, smsc9420_rx_poll, NAPI_WEIGHT);
1678
1679 result = register_netdev(dev);
1680 if (result) {
1681 smsc_warn(PROBE, "error %i registering device", result);
1682 goto out_free_dmadesc_5;
1683 }
1684
1685 pci_set_drvdata(pdev, dev);
1686
1687 spin_lock_init(&pd->int_lock);
1688 spin_lock_init(&pd->phy_lock);
1689
1690 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
1691
1692 return 0;
1693
1694 out_free_dmadesc_5:
1695 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1696 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1697 out_free_io_4:
1698 iounmap(virt_addr - LAN9420_CPSR_ENDIAN_OFFSET);
1699 out_free_regions_3:
1700 pci_release_regions(pdev);
1701 out_free_netdev_2:
1702 free_netdev(dev);
1703 out_disable_pci_device_1:
1704 pci_disable_device(pdev);
1705 out_0:
1706 return -ENODEV;
1707 }
1708
1709 static void __devexit smsc9420_remove(struct pci_dev *pdev)
1710 {
1711 struct net_device *dev;
1712 struct smsc9420_pdata *pd;
1713
1714 dev = pci_get_drvdata(pdev);
1715 if (!dev)
1716 return;
1717
1718 pci_set_drvdata(pdev, NULL);
1719
1720 pd = netdev_priv(dev);
1721 unregister_netdev(dev);
1722
1723 /* tx_buffers and rx_buffers are freed in stop */
1724 BUG_ON(pd->tx_buffers);
1725 BUG_ON(pd->rx_buffers);
1726
1727 BUG_ON(!pd->tx_ring);
1728 BUG_ON(!pd->rx_ring);
1729
1730 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1731 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1732
1733 iounmap(pd->base_addr - LAN9420_CPSR_ENDIAN_OFFSET);
1734 pci_release_regions(pdev);
1735 free_netdev(dev);
1736 pci_disable_device(pdev);
1737 }
1738
1739 static struct pci_driver smsc9420_driver = {
1740 .name = DRV_NAME,
1741 .id_table = smsc9420_id_table,
1742 .probe = smsc9420_probe,
1743 .remove = __devexit_p(smsc9420_remove),
1744 #ifdef CONFIG_PM
1745 .suspend = smsc9420_suspend,
1746 .resume = smsc9420_resume,
1747 #endif /* CONFIG_PM */
1748 };
1749
1750 static int __init smsc9420_init_module(void)
1751 {
1752 smsc_debug = netif_msg_init(debug, SMSC_MSG_DEFAULT);
1753
1754 return pci_register_driver(&smsc9420_driver);
1755 }
1756
1757 static void __exit smsc9420_exit_module(void)
1758 {
1759 pci_unregister_driver(&smsc9420_driver);
1760 }
1761
1762 module_init(smsc9420_init_module);
1763 module_exit(smsc9420_exit_module);