drivers/net/stmmac/common.h

   1 /*******************************************************************************
   2   STMMAC Common Header File
   3
   4   Copyright (C) 2007-2009  STMicroelectronics Ltd
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  23 *******************************************************************************/
  24
  25 #include <linux/netdevice.h>
  26 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  27 #define STMMAC_VLAN_TAG_USED
  28 #include <linux/if_vlan.h>
  29 #endif
  30
  31 #include "descs.h"
  32
  33 #undef CHIP_DEBUG_PRINT
  34 /* Turn-on extra printk debug for MAC core, dma and descriptors */
  35 /* #define CHIP_DEBUG_PRINT */
  36
  37 #ifdef CHIP_DEBUG_PRINT
  38 #define CHIP_DBG(fmt, args...)  printk(fmt, ## args)
  39 #else
  40 #define CHIP_DBG(fmt, args...)  do { } while (0)
  41 #endif
  42
  43 #undef FRAME_FILTER_DEBUG
  44 /* #define FRAME_FILTER_DEBUG */
  45
  46 struct stmmac_extra_stats {
  47         /* Transmit errors */
  48         unsigned long tx_underflow ____cacheline_aligned;
  49         unsigned long tx_carrier;
  50         unsigned long tx_losscarrier;
  51         unsigned long tx_heartbeat;
  52         unsigned long tx_deferred;
  53         unsigned long tx_vlan;
  54         unsigned long tx_jabber;
  55         unsigned long tx_frame_flushed;
  56         unsigned long tx_payload_error;
  57         unsigned long tx_ip_header_error;
  58         /* Receive errors */
  59         unsigned long rx_desc;
  60         unsigned long rx_partial;
  61         unsigned long rx_runt;
  62         unsigned long rx_toolong;
  63         unsigned long rx_collision;
  64         unsigned long rx_crc;
  65         unsigned long rx_length;
  66         unsigned long rx_mii;
  67         unsigned long rx_multicast;
  68         unsigned long rx_gmac_overflow;
  69         unsigned long rx_watchdog;
  70         unsigned long da_rx_filter_fail;
  71         unsigned long sa_rx_filter_fail;
  72         unsigned long rx_missed_cntr;
  73         unsigned long rx_overflow_cntr;
  74         unsigned long rx_vlan;
  75         /* Tx/Rx IRQ errors */
  76         unsigned long tx_undeflow_irq;
  77         unsigned long tx_process_stopped_irq;
  78         unsigned long tx_jabber_irq;
  79         unsigned long rx_overflow_irq;
  80         unsigned long rx_buf_unav_irq;
  81         unsigned long rx_process_stopped_irq;
  82         unsigned long rx_watchdog_irq;
  83         unsigned long tx_early_irq;
  84         unsigned long fatal_bus_error_irq;
  85         /* Extra info */
  86         unsigned long threshold;
  87         unsigned long tx_pkt_n;
  88         unsigned long rx_pkt_n;
  89         unsigned long poll_n;
  90         unsigned long sched_timer_n;
  91         unsigned long normal_irq_n;
  92 };
  93
  94 #define HASH_TABLE_SIZE 64
  95 #define PAUSE_TIME 0x200
  96
  97 /* Flow Control defines */
  98 #define FLOW_OFF        0
  99 #define FLOW_RX         1
 100 #define FLOW_TX         2
 101 #define FLOW_AUTO       (FLOW_TX | FLOW_RX)
 102
 103 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
 104
 105 enum rx_frame_status { /* IPC status */
 106         good_frame = 0,
 107         discard_frame = 1,
 108         csum_none = 2,
 109         llc_snap = 4,
 110 };
 111
 112 enum tx_dma_irq_status {
 113         tx_hard_error = 1,
 114         tx_hard_error_bump_tc = 2,
 115         handle_tx_rx = 3,
 116 };
 117
 118 /* GMAC TX FIFO is 8K, Rx FIFO is 16K */
 119 #define BUF_SIZE_16KiB 16384
 120 #define BUF_SIZE_8KiB 8192
 121 #define BUF_SIZE_4KiB 4096
 122 #define BUF_SIZE_2KiB 2048
 123
 124 /* Power Down and WOL */
 125 #define PMT_NOT_SUPPORTED 0
 126 #define PMT_SUPPORTED 1
 127
 128 /* Common MAC defines */
 129 #define MAC_CTRL_REG            0x00000000      /* MAC Control */
 130 #define MAC_ENABLE_TX           0x00000008      /* Transmitter Enable */
 131 #define MAC_RNABLE_RX           0x00000004      /* Receiver Enable */
 132
 133 /* MAC Management Counters register */
 134 #define MMC_CONTROL             0x00000100      /* MMC Control */
 135 #define MMC_HIGH_INTR           0x00000104      /* MMC High Interrupt */
 136 #define MMC_LOW_INTR            0x00000108      /* MMC Low Interrupt */
 137 #define MMC_HIGH_INTR_MASK      0x0000010c      /* MMC High Interrupt Mask */
 138 #define MMC_LOW_INTR_MASK       0x00000110      /* MMC Low Interrupt Mask */
 139
 140 #define MMC_CONTROL_MAX_FRM_MASK        0x0003ff8       /* Maximum Frame Size */
 141 #define MMC_CONTROL_MAX_FRM_SHIFT       3
 142 #define MMC_CONTROL_MAX_FRAME           0x7FF
 143
 144 struct stmmac_desc_ops {
 145         /* DMA RX descriptor ring initialization */
 146         void (*init_rx_desc) (struct dma_desc *p, unsigned int ring_size,
 147                               int disable_rx_ic);
 148         /* DMA TX descriptor ring initialization */
 149         void (*init_tx_desc) (struct dma_desc *p, unsigned int ring_size);
 150
 151         /* Invoked by the xmit function to prepare the tx descriptor */
 152         void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
 153                                  int csum_flag);
 154         /* Set/get the owner of the descriptor */
 155         void (*set_tx_owner) (struct dma_desc *p);
 156         int (*get_tx_owner) (struct dma_desc *p);
 157         /* Invoked by the xmit function to close the tx descriptor */
 158         void (*close_tx_desc) (struct dma_desc *p);
 159         /* Clean the tx descriptor as soon as the tx irq is received */
 160         void (*release_tx_desc) (struct dma_desc *p);
 161         /* Clear interrupt on tx frame completion. When this bit is
 162          * set an interrupt happens as soon as the frame is transmitted */
 163         void (*clear_tx_ic) (struct dma_desc *p);
 164         /* Last tx segment reports the transmit status */
 165         int (*get_tx_ls) (struct dma_desc *p);
 166         /* Return the transmit status looking at the TDES1 */
 167         int (*tx_status) (void *data, struct stmmac_extra_stats *x,
 168                           struct dma_desc *p, void __iomem *ioaddr);
 169         /* Get the buffer size from the descriptor */
 170         int (*get_tx_len) (struct dma_desc *p);
 171         /* Handle extra events on specific interrupts hw dependent */
 172         int (*get_rx_owner) (struct dma_desc *p);
 173         void (*set_rx_owner) (struct dma_desc *p);
 174         /* Get the receive frame size */
 175         int (*get_rx_frame_len) (struct dma_desc *p);
 176         /* Return the reception status looking at the RDES1 */
 177         int (*rx_status) (void *data, struct stmmac_extra_stats *x,
 178                           struct dma_desc *p);
 179 };
 180
 181 struct stmmac_dma_ops {
 182         /* DMA core initialization */
 183         int (*init) (void __iomem *ioaddr, int pbl, u32 dma_tx, u32 dma_rx);
 184         /* Dump DMA registers */
 185         void (*dump_regs) (void __iomem *ioaddr);
 186         /* Set tx/rx threshold in the csr6 register
 187          * An invalid value enables the store-and-forward mode */
 188         void (*dma_mode) (void __iomem *ioaddr, int txmode, int rxmode);
 189         /* To track extra statistic (if supported) */
 190         void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
 191                                    void __iomem *ioaddr);
 192         void (*enable_dma_transmission) (void __iomem *ioaddr);
 193         void (*enable_dma_irq) (void __iomem *ioaddr);
 194         void (*disable_dma_irq) (void __iomem *ioaddr);
 195         void (*start_tx) (void __iomem *ioaddr);
 196         void (*stop_tx) (void __iomem *ioaddr);
 197         void (*start_rx) (void __iomem *ioaddr);
 198         void (*stop_rx) (void __iomem *ioaddr);
 199         int (*dma_interrupt) (void __iomem *ioaddr,
 200                               struct stmmac_extra_stats *x);
 201 };
 202
 203 struct stmmac_ops {
 204         /* MAC core initialization */
 205         void (*core_init) (void __iomem *ioaddr) ____cacheline_aligned;
 206         /* Support checksum offload engine */
 207         int  (*rx_coe) (void __iomem *ioaddr);
 208         /* Dump MAC registers */
 209         void (*dump_regs) (void __iomem *ioaddr);
 210         /* Handle extra events on specific interrupts hw dependent */
 211         void (*host_irq_status) (void __iomem *ioaddr);
 212         /* Multicast filter setting */
 213         void (*set_filter) (struct net_device *dev);
 214         /* Flow control setting */
 215         void (*flow_ctrl) (void __iomem *ioaddr, unsigned int duplex,
 216                            unsigned int fc, unsigned int pause_time);
 217         /* Set power management mode (e.g. magic frame) */
 218         void (*pmt) (void __iomem *ioaddr, unsigned long mode);
 219         /* Set/Get Unicast MAC addresses */
 220         void (*set_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
 221                                unsigned int reg_n);
 222         void (*get_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
 223                                unsigned int reg_n);
 224 };
 225
 226 struct mac_link {
 227         int port;
 228         int duplex;
 229         int speed;
 230 };
 231
 232 struct mii_regs {
 233         unsigned int addr;      /* MII Address */
 234         unsigned int data;      /* MII Data */
 235 };
 236
 237 struct mac_device_info {
 238         const struct stmmac_ops         *mac;
 239         const struct stmmac_desc_ops    *desc;
 240         const struct stmmac_dma_ops     *dma;
 241         struct mii_regs mii;    /* MII register Addresses */
 242         struct mac_link link;
 243 };
 244
 245 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr);
 246 struct mac_device_info *dwmac100_setup(void __iomem *ioaddr);
 247
 248 extern void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
 249                                 unsigned int high, unsigned int low);
 250 extern void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
 251                                 unsigned int high, unsigned int low);
 252 extern void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);