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Staging: hv: mousevsc: Cleanup and properly implement reportdesc_callback()
[zen-stable.git] / drivers / net / stmmac / stmmac_main.c
blobc6e567e04effdb1ba3a5c77c228956e757dbef22
1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
4
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
22
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
24
25 Documentation available at:
26 http://www.stlinux.com
27 Support available at:
28 https://bugzilla.stlinux.com/
29 *******************************************************************************/
30
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/kernel.h>
34 #include <linux/interrupt.h>
35 #include <linux/etherdevice.h>
36 #include <linux/platform_device.h>
37 #include <linux/ip.h>
38 #include <linux/tcp.h>
39 #include <linux/skbuff.h>
40 #include <linux/ethtool.h>
41 #include <linux/if_ether.h>
42 #include <linux/crc32.h>
43 #include <linux/mii.h>
44 #include <linux/phy.h>
45 #include <linux/if_vlan.h>
46 #include <linux/dma-mapping.h>
47 #include <linux/slab.h>
48 #include <linux/prefetch.h>
49 #include "stmmac.h"
50
51 #define STMMAC_RESOURCE_NAME "stmmaceth"
52
53 #undef STMMAC_DEBUG
54 /*#define STMMAC_DEBUG*/
55 #ifdef STMMAC_DEBUG
56 #define DBG(nlevel, klevel, fmt, args...) \
57 ((void)(netif_msg_##nlevel(priv) && \
58 printk(KERN_##klevel fmt, ## args)))
59 #else
60 #define DBG(nlevel, klevel, fmt, args...) do { } while (0)
61 #endif
62
63 #undef STMMAC_RX_DEBUG
64 /*#define STMMAC_RX_DEBUG*/
65 #ifdef STMMAC_RX_DEBUG
66 #define RX_DBG(fmt, args...) printk(fmt, ## args)
67 #else
68 #define RX_DBG(fmt, args...) do { } while (0)
69 #endif
70
71 #undef STMMAC_XMIT_DEBUG
72 /*#define STMMAC_XMIT_DEBUG*/
73 #ifdef STMMAC_TX_DEBUG
74 #define TX_DBG(fmt, args...) printk(fmt, ## args)
75 #else
76 #define TX_DBG(fmt, args...) do { } while (0)
77 #endif
78
79 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
80 #define JUMBO_LEN 9000
81
82 /* Module parameters */
83 #define TX_TIMEO 5000 /* default 5 seconds */
84 static int watchdog = TX_TIMEO;
85 module_param(watchdog, int, S_IRUGO | S_IWUSR);
86 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
87
88 static int debug = -1; /* -1: default, 0: no output, 16: all */
89 module_param(debug, int, S_IRUGO | S_IWUSR);
90 MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
91
92 static int phyaddr = -1;
93 module_param(phyaddr, int, S_IRUGO);
94 MODULE_PARM_DESC(phyaddr, "Physical device address");
95
96 #define DMA_TX_SIZE 256
97 static int dma_txsize = DMA_TX_SIZE;
98 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
99 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
100
101 #define DMA_RX_SIZE 256
102 static int dma_rxsize = DMA_RX_SIZE;
103 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
104 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
105
106 static int flow_ctrl = FLOW_OFF;
107 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
108 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
109
110 static int pause = PAUSE_TIME;
111 module_param(pause, int, S_IRUGO | S_IWUSR);
112 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
113
114 #define TC_DEFAULT 64
115 static int tc = TC_DEFAULT;
116 module_param(tc, int, S_IRUGO | S_IWUSR);
117 MODULE_PARM_DESC(tc, "DMA threshold control value");
118
119 /* Pay attention to tune this parameter; take care of both
120 * hardware capability and network stabitily/performance impact.
121 * Many tests showed that ~4ms latency seems to be good enough. */
122 #ifdef CONFIG_STMMAC_TIMER
123 #define DEFAULT_PERIODIC_RATE 256
124 static int tmrate = DEFAULT_PERIODIC_RATE;
125 module_param(tmrate, int, S_IRUGO | S_IWUSR);
126 MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)");
127 #endif
128
129 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
130 static int buf_sz = DMA_BUFFER_SIZE;
131 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
132 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
133
134 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
135 NETIF_MSG_LINK | NETIF_MSG_IFUP |
136 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
137
138 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
139
140 /**
141 * stmmac_verify_args - verify the driver parameters.
142 * Description: it verifies if some wrong parameter is passed to the driver.
143 * Note that wrong parameters are replaced with the default values.
144 */
145 static void stmmac_verify_args(void)
146 {
147 if (unlikely(watchdog < 0))
148 watchdog = TX_TIMEO;
149 if (unlikely(dma_rxsize < 0))
150 dma_rxsize = DMA_RX_SIZE;
151 if (unlikely(dma_txsize < 0))
152 dma_txsize = DMA_TX_SIZE;
153 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
154 buf_sz = DMA_BUFFER_SIZE;
155 if (unlikely(flow_ctrl > 1))
156 flow_ctrl = FLOW_AUTO;
157 else if (likely(flow_ctrl < 0))
158 flow_ctrl = FLOW_OFF;
159 if (unlikely((pause < 0) || (pause > 0xffff)))
160 pause = PAUSE_TIME;
161 }
162
163 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
164 static void print_pkt(unsigned char *buf, int len)
165 {
166 int j;
167 pr_info("len = %d byte, buf addr: 0x%p", len, buf);
168 for (j = 0; j < len; j++) {
169 if ((j % 16) == 0)
170 pr_info("\n %03x:", j);
171 pr_info(" %02x", buf[j]);
172 }
173 pr_info("\n");
174 }
175 #endif
176
177 /* minimum number of free TX descriptors required to wake up TX process */
178 #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
179
180 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
181 {
182 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
183 }
184
185 /* On some ST platforms, some HW system configuraton registers have to be
186 * set according to the link speed negotiated.
187 */
188 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
189 {
190 struct phy_device *phydev = priv->phydev;
191
192 if (likely(priv->plat->fix_mac_speed))
193 priv->plat->fix_mac_speed(priv->plat->bsp_priv,
194 phydev->speed);
195 }
196
197 /**
198 * stmmac_adjust_link
199 * @dev: net device structure
200 * Description: it adjusts the link parameters.
201 */
202 static void stmmac_adjust_link(struct net_device *dev)
203 {
204 struct stmmac_priv *priv = netdev_priv(dev);
205 struct phy_device *phydev = priv->phydev;
206 unsigned long flags;
207 int new_state = 0;
208 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
209
210 if (phydev == NULL)
211 return;
212
213 DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n",
214 phydev->addr, phydev->link);
215
216 spin_lock_irqsave(&priv->lock, flags);
217 if (phydev->link) {
218 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
219
220 /* Now we make sure that we can be in full duplex mode.
221 * If not, we operate in half-duplex mode. */
222 if (phydev->duplex != priv->oldduplex) {
223 new_state = 1;
224 if (!(phydev->duplex))
225 ctrl &= ~priv->hw->link.duplex;
226 else
227 ctrl |= priv->hw->link.duplex;
228 priv->oldduplex = phydev->duplex;
229 }
230 /* Flow Control operation */
231 if (phydev->pause)
232 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
233 fc, pause_time);
234
235 if (phydev->speed != priv->speed) {
236 new_state = 1;
237 switch (phydev->speed) {
238 case 1000:
239 if (likely(priv->plat->has_gmac))
240 ctrl &= ~priv->hw->link.port;
241 stmmac_hw_fix_mac_speed(priv);
242 break;
243 case 100:
244 case 10:
245 if (priv->plat->has_gmac) {
246 ctrl |= priv->hw->link.port;
247 if (phydev->speed == SPEED_100) {
248 ctrl |= priv->hw->link.speed;
249 } else {
250 ctrl &= ~(priv->hw->link.speed);
251 }
252 } else {
253 ctrl &= ~priv->hw->link.port;
254 }
255 stmmac_hw_fix_mac_speed(priv);
256 break;
257 default:
258 if (netif_msg_link(priv))
259 pr_warning("%s: Speed (%d) is not 10"
260 " or 100!\n", dev->name, phydev->speed);
261 break;
262 }
263
264 priv->speed = phydev->speed;
265 }
266
267 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
268
269 if (!priv->oldlink) {
270 new_state = 1;
271 priv->oldlink = 1;
272 }
273 } else if (priv->oldlink) {
274 new_state = 1;
275 priv->oldlink = 0;
276 priv->speed = 0;
277 priv->oldduplex = -1;
278 }
279
280 if (new_state && netif_msg_link(priv))
281 phy_print_status(phydev);
282
283 spin_unlock_irqrestore(&priv->lock, flags);
284
285 DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
286 }
287
288 /**
289 * stmmac_init_phy - PHY initialization
290 * @dev: net device structure
291 * Description: it initializes the driver's PHY state, and attaches the PHY
292 * to the mac driver.
293 * Return value:
294 * 0 on success
295 */
296 static int stmmac_init_phy(struct net_device *dev)
297 {
298 struct stmmac_priv *priv = netdev_priv(dev);
299 struct phy_device *phydev;
300 char phy_id[MII_BUS_ID_SIZE + 3];
301 char bus_id[MII_BUS_ID_SIZE];
302
303 priv->oldlink = 0;
304 priv->speed = 0;
305 priv->oldduplex = -1;
306
307 snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->plat->bus_id);
308 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
309 priv->plat->phy_addr);
310 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id);
311
312 phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0,
313 priv->plat->interface);
314
315 if (IS_ERR(phydev)) {
316 pr_err("%s: Could not attach to PHY\n", dev->name);
317 return PTR_ERR(phydev);
318 }
319
320 /*
321 * Broken HW is sometimes missing the pull-up resistor on the
322 * MDIO line, which results in reads to non-existent devices returning
323 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
324 * device as well.
325 * Note: phydev->phy_id is the result of reading the UID PHY registers.
326 */
327 if (phydev->phy_id == 0) {
328 phy_disconnect(phydev);
329 return -ENODEV;
330 }
331 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
332 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
333
334 priv->phydev = phydev;
335
336 return 0;
337 }
338
339 static inline void stmmac_enable_mac(void __iomem *ioaddr)
340 {
341 u32 value = readl(ioaddr + MAC_CTRL_REG);
342
343 value |= MAC_RNABLE_RX | MAC_ENABLE_TX;
344 writel(value, ioaddr + MAC_CTRL_REG);
345 }
346
347 static inline void stmmac_disable_mac(void __iomem *ioaddr)
348 {
349 u32 value = readl(ioaddr + MAC_CTRL_REG);
350
351 value &= ~(MAC_ENABLE_TX | MAC_RNABLE_RX);
352 writel(value, ioaddr + MAC_CTRL_REG);
353 }
354
355 /**
356 * display_ring
357 * @p: pointer to the ring.
358 * @size: size of the ring.
359 * Description: display all the descriptors within the ring.
360 */
361 static void display_ring(struct dma_desc *p, int size)
362 {
363 struct tmp_s {
364 u64 a;
365 unsigned int b;
366 unsigned int c;
367 };
368 int i;
369 for (i = 0; i < size; i++) {
370 struct tmp_s *x = (struct tmp_s *)(p + i);
371 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
372 i, (unsigned int)virt_to_phys(&p[i]),
373 (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
374 x->b, x->c);
375 pr_info("\n");
376 }
377 }
378
379 /**
380 * init_dma_desc_rings - init the RX/TX descriptor rings
381 * @dev: net device structure
382 * Description: this function initializes the DMA RX/TX descriptors
383 * and allocates the socket buffers.
384 */
385 static void init_dma_desc_rings(struct net_device *dev)
386 {
387 int i;
388 struct stmmac_priv *priv = netdev_priv(dev);
389 struct sk_buff *skb;
390 unsigned int txsize = priv->dma_tx_size;
391 unsigned int rxsize = priv->dma_rx_size;
392 unsigned int bfsize = priv->dma_buf_sz;
393 int buff2_needed = 0, dis_ic = 0;
394
395 /* Set the Buffer size according to the MTU;
396 * indeed, in case of jumbo we need to bump-up the buffer sizes.
397 */
398 if (unlikely(dev->mtu >= BUF_SIZE_8KiB))
399 bfsize = BUF_SIZE_16KiB;
400 else if (unlikely(dev->mtu >= BUF_SIZE_4KiB))
401 bfsize = BUF_SIZE_8KiB;
402 else if (unlikely(dev->mtu >= BUF_SIZE_2KiB))
403 bfsize = BUF_SIZE_4KiB;
404 else if (unlikely(dev->mtu >= DMA_BUFFER_SIZE))
405 bfsize = BUF_SIZE_2KiB;
406 else
407 bfsize = DMA_BUFFER_SIZE;
408
409 #ifdef CONFIG_STMMAC_TIMER
410 /* Disable interrupts on completion for the reception if timer is on */
411 if (likely(priv->tm->enable))
412 dis_ic = 1;
413 #endif
414 /* If the MTU exceeds 8k so use the second buffer in the chain */
415 if (bfsize >= BUF_SIZE_8KiB)
416 buff2_needed = 1;
417
418 DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
419 txsize, rxsize, bfsize);
420
421 priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL);
422 priv->rx_skbuff =
423 kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL);
424 priv->dma_rx =
425 (struct dma_desc *)dma_alloc_coherent(priv->device,
426 rxsize *
427 sizeof(struct dma_desc),
428 &priv->dma_rx_phy,
429 GFP_KERNEL);
430 priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize,
431 GFP_KERNEL);
432 priv->dma_tx =
433 (struct dma_desc *)dma_alloc_coherent(priv->device,
434 txsize *
435 sizeof(struct dma_desc),
436 &priv->dma_tx_phy,
437 GFP_KERNEL);
438
439 if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) {
440 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__);
441 return;
442 }
443
444 DBG(probe, INFO, "stmmac (%s) DMA desc rings: virt addr (Rx %p, "
445 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
446 dev->name, priv->dma_rx, priv->dma_tx,
447 (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
448
449 /* RX INITIALIZATION */
450 DBG(probe, INFO, "stmmac: SKB addresses:\n"
451 "skb\t\tskb data\tdma data\n");
452
453 for (i = 0; i < rxsize; i++) {
454 struct dma_desc *p = priv->dma_rx + i;
455
456 skb = netdev_alloc_skb_ip_align(dev, bfsize);
457 if (unlikely(skb == NULL)) {
458 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
459 break;
460 }
461 priv->rx_skbuff[i] = skb;
462 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
463 bfsize, DMA_FROM_DEVICE);
464
465 p->des2 = priv->rx_skbuff_dma[i];
466 if (unlikely(buff2_needed))
467 p->des3 = p->des2 + BUF_SIZE_8KiB;
468 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
469 priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
470 }
471 priv->cur_rx = 0;
472 priv->dirty_rx = (unsigned int)(i - rxsize);
473 priv->dma_buf_sz = bfsize;
474 buf_sz = bfsize;
475
476 /* TX INITIALIZATION */
477 for (i = 0; i < txsize; i++) {
478 priv->tx_skbuff[i] = NULL;
479 priv->dma_tx[i].des2 = 0;
480 }
481 priv->dirty_tx = 0;
482 priv->cur_tx = 0;
483
484 /* Clear the Rx/Tx descriptors */
485 priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
486 priv->hw->desc->init_tx_desc(priv->dma_tx, txsize);
487
488 if (netif_msg_hw(priv)) {
489 pr_info("RX descriptor ring:\n");
490 display_ring(priv->dma_rx, rxsize);
491 pr_info("TX descriptor ring:\n");
492 display_ring(priv->dma_tx, txsize);
493 }
494 }
495
496 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
497 {
498 int i;
499
500 for (i = 0; i < priv->dma_rx_size; i++) {
501 if (priv->rx_skbuff[i]) {
502 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
503 priv->dma_buf_sz, DMA_FROM_DEVICE);
504 dev_kfree_skb_any(priv->rx_skbuff[i]);
505 }
506 priv->rx_skbuff[i] = NULL;
507 }
508 }
509
510 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
511 {
512 int i;
513
514 for (i = 0; i < priv->dma_tx_size; i++) {
515 if (priv->tx_skbuff[i] != NULL) {
516 struct dma_desc *p = priv->dma_tx + i;
517 if (p->des2)
518 dma_unmap_single(priv->device, p->des2,
519 priv->hw->desc->get_tx_len(p),
520 DMA_TO_DEVICE);
521 dev_kfree_skb_any(priv->tx_skbuff[i]);
522 priv->tx_skbuff[i] = NULL;
523 }
524 }
525 }
526
527 static void free_dma_desc_resources(struct stmmac_priv *priv)
528 {
529 /* Release the DMA TX/RX socket buffers */
530 dma_free_rx_skbufs(priv);
531 dma_free_tx_skbufs(priv);
532
533 /* Free the region of consistent memory previously allocated for
534 * the DMA */
535 dma_free_coherent(priv->device,
536 priv->dma_tx_size * sizeof(struct dma_desc),
537 priv->dma_tx, priv->dma_tx_phy);
538 dma_free_coherent(priv->device,
539 priv->dma_rx_size * sizeof(struct dma_desc),
540 priv->dma_rx, priv->dma_rx_phy);
541 kfree(priv->rx_skbuff_dma);
542 kfree(priv->rx_skbuff);
543 kfree(priv->tx_skbuff);
544 }
545
546 /**
547 * stmmac_dma_operation_mode - HW DMA operation mode
548 * @priv : pointer to the private device structure.
549 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
550 * or Store-And-Forward capability.
551 */
552 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
553 {
554 if (likely(priv->plat->force_sf_dma_mode ||
555 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
556 /*
557 * In case of GMAC, SF mode can be enabled
558 * to perform the TX COE in HW. This depends on:
559 * 1) TX COE if actually supported
560 * 2) There is no bugged Jumbo frame support
561 * that needs to not insert csum in the TDES.
562 */
563 priv->hw->dma->dma_mode(priv->ioaddr,
564 SF_DMA_MODE, SF_DMA_MODE);
565 tc = SF_DMA_MODE;
566 } else
567 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
568 }
569
570 /**
571 * stmmac_tx:
572 * @priv: private driver structure
573 * Description: it reclaims resources after transmission completes.
574 */
575 static void stmmac_tx(struct stmmac_priv *priv)
576 {
577 unsigned int txsize = priv->dma_tx_size;
578
579 while (priv->dirty_tx != priv->cur_tx) {
580 int last;
581 unsigned int entry = priv->dirty_tx % txsize;
582 struct sk_buff *skb = priv->tx_skbuff[entry];
583 struct dma_desc *p = priv->dma_tx + entry;
584
585 /* Check if the descriptor is owned by the DMA. */
586 if (priv->hw->desc->get_tx_owner(p))
587 break;
588
589 /* Verify tx error by looking at the last segment */
590 last = priv->hw->desc->get_tx_ls(p);
591 if (likely(last)) {
592 int tx_error =
593 priv->hw->desc->tx_status(&priv->dev->stats,
594 &priv->xstats, p,
595 priv->ioaddr);
596 if (likely(tx_error == 0)) {
597 priv->dev->stats.tx_packets++;
598 priv->xstats.tx_pkt_n++;
599 } else
600 priv->dev->stats.tx_errors++;
601 }
602 TX_DBG("%s: curr %d, dirty %d\n", __func__,
603 priv->cur_tx, priv->dirty_tx);
604
605 if (likely(p->des2))
606 dma_unmap_single(priv->device, p->des2,
607 priv->hw->desc->get_tx_len(p),
608 DMA_TO_DEVICE);
609 if (unlikely(p->des3))
610 p->des3 = 0;
611
612 if (likely(skb != NULL)) {
613 /*
614 * If there's room in the queue (limit it to size)
615 * we add this skb back into the pool,
616 * if it's the right size.
617 */
618 if ((skb_queue_len(&priv->rx_recycle) <
619 priv->dma_rx_size) &&
620 skb_recycle_check(skb, priv->dma_buf_sz))
621 __skb_queue_head(&priv->rx_recycle, skb);
622 else
623 dev_kfree_skb(skb);
624
625 priv->tx_skbuff[entry] = NULL;
626 }
627
628 priv->hw->desc->release_tx_desc(p);
629
630 entry = (++priv->dirty_tx) % txsize;
631 }
632 if (unlikely(netif_queue_stopped(priv->dev) &&
633 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
634 netif_tx_lock(priv->dev);
635 if (netif_queue_stopped(priv->dev) &&
636 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
637 TX_DBG("%s: restart transmit\n", __func__);
638 netif_wake_queue(priv->dev);
639 }
640 netif_tx_unlock(priv->dev);
641 }
642 }
643
644 static inline void stmmac_enable_irq(struct stmmac_priv *priv)
645 {
646 #ifdef CONFIG_STMMAC_TIMER
647 if (likely(priv->tm->enable))
648 priv->tm->timer_start(tmrate);
649 else
650 #endif
651 priv->hw->dma->enable_dma_irq(priv->ioaddr);
652 }
653
654 static inline void stmmac_disable_irq(struct stmmac_priv *priv)
655 {
656 #ifdef CONFIG_STMMAC_TIMER
657 if (likely(priv->tm->enable))
658 priv->tm->timer_stop();
659 else
660 #endif
661 priv->hw->dma->disable_dma_irq(priv->ioaddr);
662 }
663
664 static int stmmac_has_work(struct stmmac_priv *priv)
665 {
666 unsigned int has_work = 0;
667 int rxret, tx_work = 0;
668
669 rxret = priv->hw->desc->get_rx_owner(priv->dma_rx +
670 (priv->cur_rx % priv->dma_rx_size));
671
672 if (priv->dirty_tx != priv->cur_tx)
673 tx_work = 1;
674
675 if (likely(!rxret || tx_work))
676 has_work = 1;
677
678 return has_work;
679 }
680
681 static inline void _stmmac_schedule(struct stmmac_priv *priv)
682 {
683 if (likely(stmmac_has_work(priv))) {
684 stmmac_disable_irq(priv);
685 napi_schedule(&priv->napi);
686 }
687 }
688
689 #ifdef CONFIG_STMMAC_TIMER
690 void stmmac_schedule(struct net_device *dev)
691 {
692 struct stmmac_priv *priv = netdev_priv(dev);
693
694 priv->xstats.sched_timer_n++;
695
696 _stmmac_schedule(priv);
697 }
698
699 static void stmmac_no_timer_started(unsigned int x)
700 {;
701 };
702
703 static void stmmac_no_timer_stopped(void)
704 {;
705 };
706 #endif
707
708 /**
709 * stmmac_tx_err:
710 * @priv: pointer to the private device structure
711 * Description: it cleans the descriptors and restarts the transmission
712 * in case of errors.
713 */
714 static void stmmac_tx_err(struct stmmac_priv *priv)
715 {
716
717 netif_stop_queue(priv->dev);
718
719 priv->hw->dma->stop_tx(priv->ioaddr);
720 dma_free_tx_skbufs(priv);
721 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
722 priv->dirty_tx = 0;
723 priv->cur_tx = 0;
724 priv->hw->dma->start_tx(priv->ioaddr);
725
726 priv->dev->stats.tx_errors++;
727 netif_wake_queue(priv->dev);
728 }
729
730
731 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
732 {
733 int status;
734
735 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
736 if (likely(status == handle_tx_rx))
737 _stmmac_schedule(priv);
738
739 else if (unlikely(status == tx_hard_error_bump_tc)) {
740 /* Try to bump up the dma threshold on this failure */
741 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
742 tc += 64;
743 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
744 priv->xstats.threshold = tc;
745 }
746 } else if (unlikely(status == tx_hard_error))
747 stmmac_tx_err(priv);
748 }
749
750 /**
751 * stmmac_open - open entry point of the driver
752 * @dev : pointer to the device structure.
753 * Description:
754 * This function is the open entry point of the driver.
755 * Return value:
756 * 0 on success and an appropriate (-)ve integer as defined in errno.h
757 * file on failure.
758 */
759 static int stmmac_open(struct net_device *dev)
760 {
761 struct stmmac_priv *priv = netdev_priv(dev);
762 int ret;
763
764 /* Check that the MAC address is valid. If its not, refuse
765 * to bring the device up. The user must specify an
766 * address using the following linux command:
767 * ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx */
768 if (!is_valid_ether_addr(dev->dev_addr)) {
769 random_ether_addr(dev->dev_addr);
770 pr_warning("%s: generated random MAC address %pM\n", dev->name,
771 dev->dev_addr);
772 }
773
774 stmmac_verify_args();
775
776 #ifdef CONFIG_STMMAC_TIMER
777 priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL);
778 if (unlikely(priv->tm == NULL)) {
779 pr_err("%s: ERROR: timer memory alloc failed\n", __func__);
780 return -ENOMEM;
781 }
782 priv->tm->freq = tmrate;
783
784 /* Test if the external timer can be actually used.
785 * In case of failure continue without timer. */
786 if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) {
787 pr_warning("stmmaceth: cannot attach the external timer.\n");
788 priv->tm->freq = 0;
789 priv->tm->timer_start = stmmac_no_timer_started;
790 priv->tm->timer_stop = stmmac_no_timer_stopped;
791 } else
792 priv->tm->enable = 1;
793 #endif
794 ret = stmmac_init_phy(dev);
795 if (unlikely(ret)) {
796 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
797 goto open_error;
798 }
799
800 /* Create and initialize the TX/RX descriptors chains. */
801 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
802 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
803 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
804 init_dma_desc_rings(dev);
805
806 /* DMA initialization and SW reset */
807 ret = priv->hw->dma->init(priv->ioaddr, priv->plat->pbl,
808 priv->dma_tx_phy, priv->dma_rx_phy);
809 if (ret < 0) {
810 pr_err("%s: DMA initialization failed\n", __func__);
811 goto open_error;
812 }
813
814 /* Copy the MAC addr into the HW */
815 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
816 /* If required, perform hw setup of the bus. */
817 if (priv->plat->bus_setup)
818 priv->plat->bus_setup(priv->ioaddr);
819 /* Initialize the MAC Core */
820 priv->hw->mac->core_init(priv->ioaddr);
821
822 priv->rx_coe = priv->hw->mac->rx_coe(priv->ioaddr);
823 if (priv->rx_coe)
824 pr_info("stmmac: Rx Checksum Offload Engine supported\n");
825 if (priv->plat->tx_coe)
826 pr_info("\tTX Checksum insertion supported\n");
827 netdev_update_features(dev);
828
829 /* Initialise the MMC (if present) to disable all interrupts. */
830 writel(0xffffffff, priv->ioaddr + MMC_HIGH_INTR_MASK);
831 writel(0xffffffff, priv->ioaddr + MMC_LOW_INTR_MASK);
832
833 /* Request the IRQ lines */
834 ret = request_irq(dev->irq, stmmac_interrupt,
835 IRQF_SHARED, dev->name, dev);
836 if (unlikely(ret < 0)) {
837 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
838 __func__, dev->irq, ret);
839 goto open_error;
840 }
841
842 /* Enable the MAC Rx/Tx */
843 stmmac_enable_mac(priv->ioaddr);
844
845 /* Set the HW DMA mode and the COE */
846 stmmac_dma_operation_mode(priv);
847
848 /* Extra statistics */
849 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
850 priv->xstats.threshold = tc;
851
852 /* Start the ball rolling... */
853 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
854 priv->hw->dma->start_tx(priv->ioaddr);
855 priv->hw->dma->start_rx(priv->ioaddr);
856
857 #ifdef CONFIG_STMMAC_TIMER
858 priv->tm->timer_start(tmrate);
859 #endif
860 /* Dump DMA/MAC registers */
861 if (netif_msg_hw(priv)) {
862 priv->hw->mac->dump_regs(priv->ioaddr);
863 priv->hw->dma->dump_regs(priv->ioaddr);
864 }
865
866 if (priv->phydev)
867 phy_start(priv->phydev);
868
869 napi_enable(&priv->napi);
870 skb_queue_head_init(&priv->rx_recycle);
871 netif_start_queue(dev);
872
873 return 0;
874
875 open_error:
876 #ifdef CONFIG_STMMAC_TIMER
877 kfree(priv->tm);
878 #endif
879 if (priv->phydev)
880 phy_disconnect(priv->phydev);
881
882 return ret;
883 }
884
885 /**
886 * stmmac_release - close entry point of the driver
887 * @dev : device pointer.
888 * Description:
889 * This is the stop entry point of the driver.
890 */
891 static int stmmac_release(struct net_device *dev)
892 {
893 struct stmmac_priv *priv = netdev_priv(dev);
894
895 /* Stop and disconnect the PHY */
896 if (priv->phydev) {
897 phy_stop(priv->phydev);
898 phy_disconnect(priv->phydev);
899 priv->phydev = NULL;
900 }
901
902 netif_stop_queue(dev);
903
904 #ifdef CONFIG_STMMAC_TIMER
905 /* Stop and release the timer */
906 stmmac_close_ext_timer();
907 if (priv->tm != NULL)
908 kfree(priv->tm);
909 #endif
910 napi_disable(&priv->napi);
911 skb_queue_purge(&priv->rx_recycle);
912
913 /* Free the IRQ lines */
914 free_irq(dev->irq, dev);
915
916 /* Stop TX/RX DMA and clear the descriptors */
917 priv->hw->dma->stop_tx(priv->ioaddr);
918 priv->hw->dma->stop_rx(priv->ioaddr);
919
920 /* Release and free the Rx/Tx resources */
921 free_dma_desc_resources(priv);
922
923 /* Disable the MAC Rx/Tx */
924 stmmac_disable_mac(priv->ioaddr);
925
926 netif_carrier_off(dev);
927
928 return 0;
929 }
930
931 static unsigned int stmmac_handle_jumbo_frames(struct sk_buff *skb,
932 struct net_device *dev,
933 int csum_insertion)
934 {
935 struct stmmac_priv *priv = netdev_priv(dev);
936 unsigned int nopaged_len = skb_headlen(skb);
937 unsigned int txsize = priv->dma_tx_size;
938 unsigned int entry = priv->cur_tx % txsize;
939 struct dma_desc *desc = priv->dma_tx + entry;
940
941 if (nopaged_len > BUF_SIZE_8KiB) {
942
943 int buf2_size = nopaged_len - BUF_SIZE_8KiB;
944
945 desc->des2 = dma_map_single(priv->device, skb->data,
946 BUF_SIZE_8KiB, DMA_TO_DEVICE);
947 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
948 priv->hw->desc->prepare_tx_desc(desc, 1, BUF_SIZE_8KiB,
949 csum_insertion);
950
951 entry = (++priv->cur_tx) % txsize;
952 desc = priv->dma_tx + entry;
953
954 desc->des2 = dma_map_single(priv->device,
955 skb->data + BUF_SIZE_8KiB,
956 buf2_size, DMA_TO_DEVICE);
957 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
958 priv->hw->desc->prepare_tx_desc(desc, 0, buf2_size,
959 csum_insertion);
960 priv->hw->desc->set_tx_owner(desc);
961 priv->tx_skbuff[entry] = NULL;
962 } else {
963 desc->des2 = dma_map_single(priv->device, skb->data,
964 nopaged_len, DMA_TO_DEVICE);
965 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
966 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
967 csum_insertion);
968 }
969 return entry;
970 }
971
972 /**
973 * stmmac_xmit:
974 * @skb : the socket buffer
975 * @dev : device pointer
976 * Description : Tx entry point of the driver.
977 */
978 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
979 {
980 struct stmmac_priv *priv = netdev_priv(dev);
981 unsigned int txsize = priv->dma_tx_size;
982 unsigned int entry;
983 int i, csum_insertion = 0;
984 int nfrags = skb_shinfo(skb)->nr_frags;
985 struct dma_desc *desc, *first;
986
987 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
988 if (!netif_queue_stopped(dev)) {
989 netif_stop_queue(dev);
990 /* This is a hard error, log it. */
991 pr_err("%s: BUG! Tx Ring full when queue awake\n",
992 __func__);
993 }
994 return NETDEV_TX_BUSY;
995 }
996
997 entry = priv->cur_tx % txsize;
998
999 #ifdef STMMAC_XMIT_DEBUG
1000 if ((skb->len > ETH_FRAME_LEN) || nfrags)
1001 pr_info("stmmac xmit:\n"
1002 "\tskb addr %p - len: %d - nopaged_len: %d\n"
1003 "\tn_frags: %d - ip_summed: %d - %s gso\n",
1004 skb, skb->len, skb_headlen(skb), nfrags, skb->ip_summed,
1005 !skb_is_gso(skb) ? "isn't" : "is");
1006 #endif
1007
1008 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1009
1010 desc = priv->dma_tx + entry;
1011 first = desc;
1012
1013 #ifdef STMMAC_XMIT_DEBUG
1014 if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1015 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n"
1016 "\t\tn_frags: %d, ip_summed: %d\n",
1017 skb->len, skb_headlen(skb), nfrags, skb->ip_summed);
1018 #endif
1019 priv->tx_skbuff[entry] = skb;
1020 if (unlikely(skb->len >= BUF_SIZE_4KiB)) {
1021 entry = stmmac_handle_jumbo_frames(skb, dev, csum_insertion);
1022 desc = priv->dma_tx + entry;
1023 } else {
1024 unsigned int nopaged_len = skb_headlen(skb);
1025 desc->des2 = dma_map_single(priv->device, skb->data,
1026 nopaged_len, DMA_TO_DEVICE);
1027 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1028 csum_insertion);
1029 }
1030
1031 for (i = 0; i < nfrags; i++) {
1032 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1033 int len = frag->size;
1034
1035 entry = (++priv->cur_tx) % txsize;
1036 desc = priv->dma_tx + entry;
1037
1038 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1039 desc->des2 = dma_map_page(priv->device, frag->page,
1040 frag->page_offset,
1041 len, DMA_TO_DEVICE);
1042 priv->tx_skbuff[entry] = NULL;
1043 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion);
1044 wmb();
1045 priv->hw->desc->set_tx_owner(desc);
1046 }
1047
1048 /* Interrupt on completition only for the latest segment */
1049 priv->hw->desc->close_tx_desc(desc);
1050
1051 #ifdef CONFIG_STMMAC_TIMER
1052 /* Clean IC while using timer */
1053 if (likely(priv->tm->enable))
1054 priv->hw->desc->clear_tx_ic(desc);
1055 #endif
1056
1057 wmb();
1058
1059 /* To avoid raise condition */
1060 priv->hw->desc->set_tx_owner(first);
1061
1062 priv->cur_tx++;
1063
1064 #ifdef STMMAC_XMIT_DEBUG
1065 if (netif_msg_pktdata(priv)) {
1066 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1067 "first=%p, nfrags=%d\n",
1068 (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1069 entry, first, nfrags);
1070 display_ring(priv->dma_tx, txsize);
1071 pr_info(">>> frame to be transmitted: ");
1072 print_pkt(skb->data, skb->len);
1073 }
1074 #endif
1075 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1076 TX_DBG("%s: stop transmitted packets\n", __func__);
1077 netif_stop_queue(dev);
1078 }
1079
1080 dev->stats.tx_bytes += skb->len;
1081
1082 skb_tx_timestamp(skb);
1083
1084 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1085
1086 return NETDEV_TX_OK;
1087 }
1088
1089 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1090 {
1091 unsigned int rxsize = priv->dma_rx_size;
1092 int bfsize = priv->dma_buf_sz;
1093 struct dma_desc *p = priv->dma_rx;
1094
1095 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1096 unsigned int entry = priv->dirty_rx % rxsize;
1097 if (likely(priv->rx_skbuff[entry] == NULL)) {
1098 struct sk_buff *skb;
1099
1100 skb = __skb_dequeue(&priv->rx_recycle);
1101 if (skb == NULL)
1102 skb = netdev_alloc_skb_ip_align(priv->dev,
1103 bfsize);
1104
1105 if (unlikely(skb == NULL))
1106 break;
1107
1108 priv->rx_skbuff[entry] = skb;
1109 priv->rx_skbuff_dma[entry] =
1110 dma_map_single(priv->device, skb->data, bfsize,
1111 DMA_FROM_DEVICE);
1112
1113 (p + entry)->des2 = priv->rx_skbuff_dma[entry];
1114 if (unlikely(priv->plat->has_gmac)) {
1115 if (bfsize >= BUF_SIZE_8KiB)
1116 (p + entry)->des3 =
1117 (p + entry)->des2 + BUF_SIZE_8KiB;
1118 }
1119 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1120 }
1121 wmb();
1122 priv->hw->desc->set_rx_owner(p + entry);
1123 }
1124 }
1125
1126 static int stmmac_rx(struct stmmac_priv *priv, int limit)
1127 {
1128 unsigned int rxsize = priv->dma_rx_size;
1129 unsigned int entry = priv->cur_rx % rxsize;
1130 unsigned int next_entry;
1131 unsigned int count = 0;
1132 struct dma_desc *p = priv->dma_rx + entry;
1133 struct dma_desc *p_next;
1134
1135 #ifdef STMMAC_RX_DEBUG
1136 if (netif_msg_hw(priv)) {
1137 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1138 display_ring(priv->dma_rx, rxsize);
1139 }
1140 #endif
1141 count = 0;
1142 while (!priv->hw->desc->get_rx_owner(p)) {
1143 int status;
1144
1145 if (count >= limit)
1146 break;
1147
1148 count++;
1149
1150 next_entry = (++priv->cur_rx) % rxsize;
1151 p_next = priv->dma_rx + next_entry;
1152 prefetch(p_next);
1153
1154 /* read the status of the incoming frame */
1155 status = (priv->hw->desc->rx_status(&priv->dev->stats,
1156 &priv->xstats, p));
1157 if (unlikely(status == discard_frame))
1158 priv->dev->stats.rx_errors++;
1159 else {
1160 struct sk_buff *skb;
1161 int frame_len;
1162
1163 frame_len = priv->hw->desc->get_rx_frame_len(p);
1164 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1165 * Type frames (LLC/LLC-SNAP) */
1166 if (unlikely(status != llc_snap))
1167 frame_len -= ETH_FCS_LEN;
1168 #ifdef STMMAC_RX_DEBUG
1169 if (frame_len > ETH_FRAME_LEN)
1170 pr_debug("\tRX frame size %d, COE status: %d\n",
1171 frame_len, status);
1172
1173 if (netif_msg_hw(priv))
1174 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1175 p, entry, p->des2);
1176 #endif
1177 skb = priv->rx_skbuff[entry];
1178 if (unlikely(!skb)) {
1179 pr_err("%s: Inconsistent Rx descriptor chain\n",
1180 priv->dev->name);
1181 priv->dev->stats.rx_dropped++;
1182 break;
1183 }
1184 prefetch(skb->data - NET_IP_ALIGN);
1185 priv->rx_skbuff[entry] = NULL;
1186
1187 skb_put(skb, frame_len);
1188 dma_unmap_single(priv->device,
1189 priv->rx_skbuff_dma[entry],
1190 priv->dma_buf_sz, DMA_FROM_DEVICE);
1191 #ifdef STMMAC_RX_DEBUG
1192 if (netif_msg_pktdata(priv)) {
1193 pr_info(" frame received (%dbytes)", frame_len);
1194 print_pkt(skb->data, frame_len);
1195 }
1196 #endif
1197 skb->protocol = eth_type_trans(skb, priv->dev);
1198
1199 if (unlikely(status == csum_none)) {
1200 /* always for the old mac 10/100 */
1201 skb_checksum_none_assert(skb);
1202 netif_receive_skb(skb);
1203 } else {
1204 skb->ip_summed = CHECKSUM_UNNECESSARY;
1205 napi_gro_receive(&priv->napi, skb);
1206 }
1207
1208 priv->dev->stats.rx_packets++;
1209 priv->dev->stats.rx_bytes += frame_len;
1210 }
1211 entry = next_entry;
1212 p = p_next; /* use prefetched values */
1213 }
1214
1215 stmmac_rx_refill(priv);
1216
1217 priv->xstats.rx_pkt_n += count;
1218
1219 return count;
1220 }
1221
1222 /**
1223 * stmmac_poll - stmmac poll method (NAPI)
1224 * @napi : pointer to the napi structure.
1225 * @budget : maximum number of packets that the current CPU can receive from
1226 * all interfaces.
1227 * Description :
1228 * This function implements the the reception process.
1229 * Also it runs the TX completion thread
1230 */
1231 static int stmmac_poll(struct napi_struct *napi, int budget)
1232 {
1233 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1234 int work_done = 0;
1235
1236 priv->xstats.poll_n++;
1237 stmmac_tx(priv);
1238 work_done = stmmac_rx(priv, budget);
1239
1240 if (work_done < budget) {
1241 napi_complete(napi);
1242 stmmac_enable_irq(priv);
1243 }
1244 return work_done;
1245 }
1246
1247 /**
1248 * stmmac_tx_timeout
1249 * @dev : Pointer to net device structure
1250 * Description: this function is called when a packet transmission fails to
1251 * complete within a reasonable tmrate. The driver will mark the error in the
1252 * netdev structure and arrange for the device to be reset to a sane state
1253 * in order to transmit a new packet.
1254 */
1255 static void stmmac_tx_timeout(struct net_device *dev)
1256 {
1257 struct stmmac_priv *priv = netdev_priv(dev);
1258
1259 /* Clear Tx resources and restart transmitting again */
1260 stmmac_tx_err(priv);
1261 }
1262
1263 /* Configuration changes (passed on by ifconfig) */
1264 static int stmmac_config(struct net_device *dev, struct ifmap *map)
1265 {
1266 if (dev->flags & IFF_UP) /* can't act on a running interface */
1267 return -EBUSY;
1268
1269 /* Don't allow changing the I/O address */
1270 if (map->base_addr != dev->base_addr) {
1271 pr_warning("%s: can't change I/O address\n", dev->name);
1272 return -EOPNOTSUPP;
1273 }
1274
1275 /* Don't allow changing the IRQ */
1276 if (map->irq != dev->irq) {
1277 pr_warning("%s: can't change IRQ number %d\n",
1278 dev->name, dev->irq);
1279 return -EOPNOTSUPP;
1280 }
1281
1282 /* ignore other fields */
1283 return 0;
1284 }
1285
1286 /**
1287 * stmmac_multicast_list - entry point for multicast addressing
1288 * @dev : pointer to the device structure
1289 * Description:
1290 * This function is a driver entry point which gets called by the kernel
1291 * whenever multicast addresses must be enabled/disabled.
1292 * Return value:
1293 * void.
1294 */
1295 static void stmmac_multicast_list(struct net_device *dev)
1296 {
1297 struct stmmac_priv *priv = netdev_priv(dev);
1298
1299 spin_lock(&priv->lock);
1300 priv->hw->mac->set_filter(dev);
1301 spin_unlock(&priv->lock);
1302 }
1303
1304 /**
1305 * stmmac_change_mtu - entry point to change MTU size for the device.
1306 * @dev : device pointer.
1307 * @new_mtu : the new MTU size for the device.
1308 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
1309 * to drive packet transmission. Ethernet has an MTU of 1500 octets
1310 * (ETH_DATA_LEN). This value can be changed with ifconfig.
1311 * Return value:
1312 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1313 * file on failure.
1314 */
1315 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1316 {
1317 struct stmmac_priv *priv = netdev_priv(dev);
1318 int max_mtu;
1319
1320 if (netif_running(dev)) {
1321 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1322 return -EBUSY;
1323 }
1324
1325 if (priv->plat->has_gmac)
1326 max_mtu = JUMBO_LEN;
1327 else
1328 max_mtu = ETH_DATA_LEN;
1329
1330 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1331 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1332 return -EINVAL;
1333 }
1334
1335 dev->mtu = new_mtu;
1336 netdev_update_features(dev);
1337
1338 return 0;
1339 }
1340
1341 static u32 stmmac_fix_features(struct net_device *dev, u32 features)
1342 {
1343 struct stmmac_priv *priv = netdev_priv(dev);
1344
1345 if (!priv->rx_coe)
1346 features &= ~NETIF_F_RXCSUM;
1347 if (!priv->plat->tx_coe)
1348 features &= ~NETIF_F_ALL_CSUM;
1349
1350 /* Some GMAC devices have a bugged Jumbo frame support that
1351 * needs to have the Tx COE disabled for oversized frames
1352 * (due to limited buffer sizes). In this case we disable
1353 * the TX csum insertionin the TDES and not use SF. */
1354 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
1355 features &= ~NETIF_F_ALL_CSUM;
1356
1357 return features;
1358 }
1359
1360 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1361 {
1362 struct net_device *dev = (struct net_device *)dev_id;
1363 struct stmmac_priv *priv = netdev_priv(dev);
1364
1365 if (unlikely(!dev)) {
1366 pr_err("%s: invalid dev pointer\n", __func__);
1367 return IRQ_NONE;
1368 }
1369
1370 if (priv->plat->has_gmac)
1371 /* To handle GMAC own interrupts */
1372 priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr);
1373
1374 stmmac_dma_interrupt(priv);
1375
1376 return IRQ_HANDLED;
1377 }
1378
1379 #ifdef CONFIG_NET_POLL_CONTROLLER
1380 /* Polling receive - used by NETCONSOLE and other diagnostic tools
1381 * to allow network I/O with interrupts disabled. */
1382 static void stmmac_poll_controller(struct net_device *dev)
1383 {
1384 disable_irq(dev->irq);
1385 stmmac_interrupt(dev->irq, dev);
1386 enable_irq(dev->irq);
1387 }
1388 #endif
1389
1390 /**
1391 * stmmac_ioctl - Entry point for the Ioctl
1392 * @dev: Device pointer.
1393 * @rq: An IOCTL specefic structure, that can contain a pointer to
1394 * a proprietary structure used to pass information to the driver.
1395 * @cmd: IOCTL command
1396 * Description:
1397 * Currently there are no special functionality supported in IOCTL, just the
1398 * phy_mii_ioctl(...) can be invoked.
1399 */
1400 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1401 {
1402 struct stmmac_priv *priv = netdev_priv(dev);
1403 int ret;
1404
1405 if (!netif_running(dev))
1406 return -EINVAL;
1407
1408 if (!priv->phydev)
1409 return -EINVAL;
1410
1411 spin_lock(&priv->lock);
1412 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
1413 spin_unlock(&priv->lock);
1414
1415 return ret;
1416 }
1417
1418 static const struct net_device_ops stmmac_netdev_ops = {
1419 .ndo_open = stmmac_open,
1420 .ndo_start_xmit = stmmac_xmit,
1421 .ndo_stop = stmmac_release,
1422 .ndo_change_mtu = stmmac_change_mtu,
1423 .ndo_fix_features = stmmac_fix_features,
1424 .ndo_set_multicast_list = stmmac_multicast_list,
1425 .ndo_tx_timeout = stmmac_tx_timeout,
1426 .ndo_do_ioctl = stmmac_ioctl,
1427 .ndo_set_config = stmmac_config,
1428 #ifdef CONFIG_NET_POLL_CONTROLLER
1429 .ndo_poll_controller = stmmac_poll_controller,
1430 #endif
1431 .ndo_set_mac_address = eth_mac_addr,
1432 };
1433
1434 /**
1435 * stmmac_probe - Initialization of the adapter .
1436 * @dev : device pointer
1437 * Description: The function initializes the network device structure for
1438 * the STMMAC driver. It also calls the low level routines
1439 * in order to init the HW (i.e. the DMA engine)
1440 */
1441 static int stmmac_probe(struct net_device *dev)
1442 {
1443 int ret = 0;
1444 struct stmmac_priv *priv = netdev_priv(dev);
1445
1446 ether_setup(dev);
1447
1448 dev->netdev_ops = &stmmac_netdev_ops;
1449 stmmac_set_ethtool_ops(dev);
1450
1451 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1452 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
1453 dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1454 #ifdef STMMAC_VLAN_TAG_USED
1455 /* Both mac100 and gmac support receive VLAN tag detection */
1456 dev->features |= NETIF_F_HW_VLAN_RX;
1457 #endif
1458 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1459
1460 if (flow_ctrl)
1461 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
1462
1463 priv->pause = pause;
1464 netif_napi_add(dev, &priv->napi, stmmac_poll, 64);
1465
1466 /* Get the MAC address */
1467 priv->hw->mac->get_umac_addr((void __iomem *) dev->base_addr,
1468 dev->dev_addr, 0);
1469
1470 if (!is_valid_ether_addr(dev->dev_addr))
1471 pr_warning("\tno valid MAC address;"
1472 "please, use ifconfig or nwhwconfig!\n");
1473
1474 spin_lock_init(&priv->lock);
1475
1476 ret = register_netdev(dev);
1477 if (ret) {
1478 pr_err("%s: ERROR %i registering the device\n",
1479 __func__, ret);
1480 return -ENODEV;
1481 }
1482
1483 DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n",
1484 dev->name, (dev->features & NETIF_F_SG) ? "on" : "off",
1485 (dev->features & NETIF_F_IP_CSUM) ? "on" : "off");
1486
1487 return ret;
1488 }
1489
1490 /**
1491 * stmmac_mac_device_setup
1492 * @dev : device pointer
1493 * Description: select and initialise the mac device (mac100 or Gmac).
1494 */
1495 static int stmmac_mac_device_setup(struct net_device *dev)
1496 {
1497 struct stmmac_priv *priv = netdev_priv(dev);
1498
1499 struct mac_device_info *device;
1500
1501 if (priv->plat->has_gmac)
1502 device = dwmac1000_setup(priv->ioaddr);
1503 else
1504 device = dwmac100_setup(priv->ioaddr);
1505
1506 if (!device)
1507 return -ENOMEM;
1508
1509 if (priv->plat->enh_desc) {
1510 device->desc = &enh_desc_ops;
1511 pr_info("\tEnhanced descriptor structure\n");
1512 } else
1513 device->desc = &ndesc_ops;
1514
1515 priv->hw = device;
1516
1517 if (device_can_wakeup(priv->device)) {
1518 priv->wolopts = WAKE_MAGIC; /* Magic Frame as default */
1519 enable_irq_wake(dev->irq);
1520 }
1521
1522 return 0;
1523 }
1524
1525 /**
1526 * stmmac_dvr_probe
1527 * @pdev: platform device pointer
1528 * Description: the driver is initialized through platform_device.
1529 */
1530 static int stmmac_dvr_probe(struct platform_device *pdev)
1531 {
1532 int ret = 0;
1533 struct resource *res;
1534 void __iomem *addr = NULL;
1535 struct net_device *ndev = NULL;
1536 struct stmmac_priv *priv = NULL;
1537 struct plat_stmmacenet_data *plat_dat;
1538
1539 pr_info("STMMAC driver:\n\tplatform registration... ");
1540 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1541 if (!res)
1542 return -ENODEV;
1543 pr_info("\tdone!\n");
1544
1545 if (!request_mem_region(res->start, resource_size(res),
1546 pdev->name)) {
1547 pr_err("%s: ERROR: memory allocation failed"
1548 "cannot get the I/O addr 0x%x\n",
1549 __func__, (unsigned int)res->start);
1550 return -EBUSY;
1551 }
1552
1553 addr = ioremap(res->start, resource_size(res));
1554 if (!addr) {
1555 pr_err("%s: ERROR: memory mapping failed\n", __func__);
1556 ret = -ENOMEM;
1557 goto out_release_region;
1558 }
1559
1560 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
1561 if (!ndev) {
1562 pr_err("%s: ERROR: allocating the device\n", __func__);
1563 ret = -ENOMEM;
1564 goto out_unmap;
1565 }
1566
1567 SET_NETDEV_DEV(ndev, &pdev->dev);
1568
1569 /* Get the MAC information */
1570 ndev->irq = platform_get_irq_byname(pdev, "macirq");
1571 if (ndev->irq == -ENXIO) {
1572 pr_err("%s: ERROR: MAC IRQ configuration "
1573 "information not found\n", __func__);
1574 ret = -ENXIO;
1575 goto out_free_ndev;
1576 }
1577
1578 priv = netdev_priv(ndev);
1579 priv->device = &(pdev->dev);
1580 priv->dev = ndev;
1581 plat_dat = pdev->dev.platform_data;
1582
1583 priv->plat = plat_dat;
1584
1585 priv->ioaddr = addr;
1586
1587 /* PMT module is not integrated in all the MAC devices. */
1588 if (plat_dat->pmt) {
1589 pr_info("\tPMT module supported\n");
1590 device_set_wakeup_capable(&pdev->dev, 1);
1591 }
1592
1593 platform_set_drvdata(pdev, ndev);
1594
1595 /* Set the I/O base addr */
1596 ndev->base_addr = (unsigned long)addr;
1597
1598 /* Custom initialisation */
1599 if (priv->plat->init) {
1600 ret = priv->plat->init(pdev);
1601 if (unlikely(ret))
1602 goto out_free_ndev;
1603 }
1604
1605 /* MAC HW revice detection */
1606 ret = stmmac_mac_device_setup(ndev);
1607 if (ret < 0)
1608 goto out_plat_exit;
1609
1610 /* Network Device Registration */
1611 ret = stmmac_probe(ndev);
1612 if (ret < 0)
1613 goto out_plat_exit;
1614
1615 /* Override with kernel parameters if supplied XXX CRS XXX
1616 * this needs to have multiple instances */
1617 if ((phyaddr >= 0) && (phyaddr <= 31))
1618 priv->plat->phy_addr = phyaddr;
1619
1620 pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n"
1621 "\tIO base addr: 0x%p)\n", ndev->name, pdev->name,
1622 pdev->id, ndev->irq, addr);
1623
1624 /* MDIO bus Registration */
1625 pr_debug("\tMDIO bus (id: %d)...", priv->plat->bus_id);
1626 ret = stmmac_mdio_register(ndev);
1627 if (ret < 0)
1628 goto out_unregister;
1629 pr_debug("registered!\n");
1630 return 0;
1631
1632 out_unregister:
1633 unregister_netdev(ndev);
1634 out_plat_exit:
1635 if (priv->plat->exit)
1636 priv->plat->exit(pdev);
1637 out_free_ndev:
1638 free_netdev(ndev);
1639 platform_set_drvdata(pdev, NULL);
1640 out_unmap:
1641 iounmap(addr);
1642 out_release_region:
1643 release_mem_region(res->start, resource_size(res));
1644
1645 return ret;
1646 }
1647
1648 /**
1649 * stmmac_dvr_remove
1650 * @pdev: platform device pointer
1651 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
1652 * changes the link status, releases the DMA descriptor rings,
1653 * unregisters the MDIO bus and unmaps the allocated memory.
1654 */
1655 static int stmmac_dvr_remove(struct platform_device *pdev)
1656 {
1657 struct net_device *ndev = platform_get_drvdata(pdev);
1658 struct stmmac_priv *priv = netdev_priv(ndev);
1659 struct resource *res;
1660
1661 pr_info("%s:\n\tremoving driver", __func__);
1662
1663 priv->hw->dma->stop_rx(priv->ioaddr);
1664 priv->hw->dma->stop_tx(priv->ioaddr);
1665
1666 stmmac_disable_mac(priv->ioaddr);
1667
1668 netif_carrier_off(ndev);
1669
1670 stmmac_mdio_unregister(ndev);
1671
1672 if (priv->plat->exit)
1673 priv->plat->exit(pdev);
1674
1675 platform_set_drvdata(pdev, NULL);
1676 unregister_netdev(ndev);
1677
1678 iounmap((void *)priv->ioaddr);
1679 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1680 release_mem_region(res->start, resource_size(res));
1681
1682 free_netdev(ndev);
1683
1684 return 0;
1685 }
1686
1687 #ifdef CONFIG_PM
1688 static int stmmac_suspend(struct device *dev)
1689 {
1690 struct net_device *ndev = dev_get_drvdata(dev);
1691 struct stmmac_priv *priv = netdev_priv(ndev);
1692 int dis_ic = 0;
1693
1694 if (!ndev || !netif_running(ndev))
1695 return 0;
1696
1697 spin_lock(&priv->lock);
1698
1699 netif_device_detach(ndev);
1700 netif_stop_queue(ndev);
1701 if (priv->phydev)
1702 phy_stop(priv->phydev);
1703
1704 #ifdef CONFIG_STMMAC_TIMER
1705 priv->tm->timer_stop();
1706 if (likely(priv->tm->enable))
1707 dis_ic = 1;
1708 #endif
1709 napi_disable(&priv->napi);
1710
1711 /* Stop TX/RX DMA */
1712 priv->hw->dma->stop_tx(priv->ioaddr);
1713 priv->hw->dma->stop_rx(priv->ioaddr);
1714 /* Clear the Rx/Tx descriptors */
1715 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
1716 dis_ic);
1717 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
1718
1719 /* Enable Power down mode by programming the PMT regs */
1720 if (device_may_wakeup(priv->device))
1721 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
1722 else
1723 stmmac_disable_mac(priv->ioaddr);
1724
1725 spin_unlock(&priv->lock);
1726 return 0;
1727 }
1728
1729 static int stmmac_resume(struct device *dev)
1730 {
1731 struct net_device *ndev = dev_get_drvdata(dev);
1732 struct stmmac_priv *priv = netdev_priv(ndev);
1733
1734 if (!netif_running(ndev))
1735 return 0;
1736
1737 spin_lock(&priv->lock);
1738
1739 /* Power Down bit, into the PM register, is cleared
1740 * automatically as soon as a magic packet or a Wake-up frame
1741 * is received. Anyway, it's better to manually clear
1742 * this bit because it can generate problems while resuming
1743 * from another devices (e.g. serial console). */
1744 if (device_may_wakeup(priv->device))
1745 priv->hw->mac->pmt(priv->ioaddr, 0);
1746
1747 netif_device_attach(ndev);
1748
1749 /* Enable the MAC and DMA */
1750 stmmac_enable_mac(priv->ioaddr);
1751 priv->hw->dma->start_tx(priv->ioaddr);
1752 priv->hw->dma->start_rx(priv->ioaddr);
1753
1754 #ifdef CONFIG_STMMAC_TIMER
1755 if (likely(priv->tm->enable))
1756 priv->tm->timer_start(tmrate);
1757 #endif
1758 napi_enable(&priv->napi);
1759
1760 if (priv->phydev)
1761 phy_start(priv->phydev);
1762
1763 netif_start_queue(ndev);
1764
1765 spin_unlock(&priv->lock);
1766 return 0;
1767 }
1768
1769 static int stmmac_freeze(struct device *dev)
1770 {
1771 struct net_device *ndev = dev_get_drvdata(dev);
1772
1773 if (!ndev || !netif_running(ndev))
1774 return 0;
1775
1776 return stmmac_release(ndev);
1777 }
1778
1779 static int stmmac_restore(struct device *dev)
1780 {
1781 struct net_device *ndev = dev_get_drvdata(dev);
1782
1783 if (!ndev || !netif_running(ndev))
1784 return 0;
1785
1786 return stmmac_open(ndev);
1787 }
1788
1789 static const struct dev_pm_ops stmmac_pm_ops = {
1790 .suspend = stmmac_suspend,
1791 .resume = stmmac_resume,
1792 .freeze = stmmac_freeze,
1793 .thaw = stmmac_restore,
1794 .restore = stmmac_restore,
1795 };
1796 #else
1797 static const struct dev_pm_ops stmmac_pm_ops;
1798 #endif /* CONFIG_PM */
1799
1800 static struct platform_driver stmmac_driver = {
1801 .probe = stmmac_dvr_probe,
1802 .remove = stmmac_dvr_remove,
1803 .driver = {
1804 .name = STMMAC_RESOURCE_NAME,
1805 .owner = THIS_MODULE,
1806 .pm = &stmmac_pm_ops,
1807 },
1808 };
1809
1810 /**
1811 * stmmac_init_module - Entry point for the driver
1812 * Description: This function is the entry point for the driver.
1813 */
1814 static int __init stmmac_init_module(void)
1815 {
1816 int ret;
1817
1818 ret = platform_driver_register(&stmmac_driver);
1819 return ret;
1820 }
1821
1822 /**
1823 * stmmac_cleanup_module - Cleanup routine for the driver
1824 * Description: This function is the cleanup routine for the driver.
1825 */
1826 static void __exit stmmac_cleanup_module(void)
1827 {
1828 platform_driver_unregister(&stmmac_driver);
1829 }
1830
1831 #ifndef MODULE
1832 static int __init stmmac_cmdline_opt(char *str)
1833 {
1834 char *opt;
1835
1836 if (!str || !*str)
1837 return -EINVAL;
1838 while ((opt = strsep(&str, ",")) != NULL) {
1839 if (!strncmp(opt, "debug:", 6)) {
1840 if (strict_strtoul(opt + 6, 0, (unsigned long *)&debug))
1841 goto err;
1842 } else if (!strncmp(opt, "phyaddr:", 8)) {
1843 if (strict_strtoul(opt + 8, 0,
1844 (unsigned long *)&phyaddr))
1845 goto err;
1846 } else if (!strncmp(opt, "dma_txsize:", 11)) {
1847 if (strict_strtoul(opt + 11, 0,
1848 (unsigned long *)&dma_txsize))
1849 goto err;
1850 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
1851 if (strict_strtoul(opt + 11, 0,
1852 (unsigned long *)&dma_rxsize))
1853 goto err;
1854 } else if (!strncmp(opt, "buf_sz:", 7)) {
1855 if (strict_strtoul(opt + 7, 0,
1856 (unsigned long *)&buf_sz))
1857 goto err;
1858 } else if (!strncmp(opt, "tc:", 3)) {
1859 if (strict_strtoul(opt + 3, 0, (unsigned long *)&tc))
1860 goto err;
1861 } else if (!strncmp(opt, "watchdog:", 9)) {
1862 if (strict_strtoul(opt + 9, 0,
1863 (unsigned long *)&watchdog))
1864 goto err;
1865 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
1866 if (strict_strtoul(opt + 10, 0,
1867 (unsigned long *)&flow_ctrl))
1868 goto err;
1869 } else if (!strncmp(opt, "pause:", 6)) {
1870 if (strict_strtoul(opt + 6, 0, (unsigned long *)&pause))
1871 goto err;
1872 #ifdef CONFIG_STMMAC_TIMER
1873 } else if (!strncmp(opt, "tmrate:", 7)) {
1874 if (strict_strtoul(opt + 7, 0,
1875 (unsigned long *)&tmrate))
1876 goto err;
1877 #endif
1878 }
1879 }
1880 return 0;
1881
1882 err:
1883 pr_err("%s: ERROR broken module parameter conversion", __func__);
1884 return -EINVAL;
1885 }
1886
1887 __setup("stmmaceth=", stmmac_cmdline_opt);
1888 #endif
1889
1890 module_init(stmmac_init_module);
1891 module_exit(stmmac_cleanup_module);
1892
1893 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet driver");
1894 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
1895 MODULE_LICENSE("GPL");