drivers/net/stmmac/stmmac_mdio.c

   1 /*******************************************************************************
   2   STMMAC Ethernet Driver -- MDIO bus implementation
   3   Provides Bus interface for MII registers
   4
   5   Copyright (C) 2007-2009  STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Carl Shaw <carl.shaw@st.com>
  24   Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  25 *******************************************************************************/
  26
  27 #include <linux/mii.h>
  28 #include <linux/phy.h>
  29 #include <linux/slab.h>
  30 #include <asm/io.h>
  31
  32 #include "stmmac.h"
  33
  34 #define MII_BUSY 0x00000001
  35 #define MII_WRITE 0x00000002
  36
  37 /**
  38  * stmmac_mdio_read
  39  * @bus: points to the mii_bus structure
  40  * @phyaddr: MII addr reg bits 15-11
  41  * @phyreg: MII addr reg bits 10-6
  42  * Description: it reads data from the MII register from within the phy device.
  43  * For the 7111 GMAC, we must set the bit 0 in the MII address register while
  44  * accessing the PHY registers.
  45  * Fortunately, it seems this has no drawback for the 7109 MAC.
  46  */
  47 static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
  48 {
  49         struct net_device *ndev = bus->priv;
  50         struct stmmac_priv *priv = netdev_priv(ndev);
  51         unsigned int mii_address = priv->hw->mii.addr;
  52         unsigned int mii_data = priv->hw->mii.data;
  53
  54         int data;
  55         u16 regValue = (((phyaddr << 11) & (0x0000F800)) |
  56                         ((phyreg << 6) & (0x000007C0)));
  57         regValue |= MII_BUSY | ((priv->plat->clk_csr & 7) << 2);
  58
  59         do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
  60         writel(regValue, priv->ioaddr + mii_address);
  61         do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
  62
  63         /* Read the data from the MII data register */
  64         data = (int)readl(priv->ioaddr + mii_data);
  65
  66         return data;
  67 }
  68
  69 /**
  70  * stmmac_mdio_write
  71  * @bus: points to the mii_bus structure
  72  * @phyaddr: MII addr reg bits 15-11
  73  * @phyreg: MII addr reg bits 10-6
  74  * @phydata: phy data
  75  * Description: it writes the data into the MII register from within the device.
  76  */
  77 static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
  78                              u16 phydata)
  79 {
  80         struct net_device *ndev = bus->priv;
  81         struct stmmac_priv *priv = netdev_priv(ndev);
  82         unsigned int mii_address = priv->hw->mii.addr;
  83         unsigned int mii_data = priv->hw->mii.data;
  84
  85         u16 value =
  86             (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0)))
  87             | MII_WRITE;
  88
  89         value |= MII_BUSY | ((priv->plat->clk_csr & 7) << 2);
  90
  91
  92         /* Wait until any existing MII operation is complete */
  93         do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
  94
  95         /* Set the MII address register to write */
  96         writel(phydata, priv->ioaddr + mii_data);
  97         writel(value, priv->ioaddr + mii_address);
  98
  99         /* Wait until any existing MII operation is complete */
 100         do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
 101
 102         return 0;
 103 }
 104
 105 /**
 106  * stmmac_mdio_reset
 107  * @bus: points to the mii_bus structure
 108  * Description: reset the MII bus
 109  */
 110 static int stmmac_mdio_reset(struct mii_bus *bus)
 111 {
 112         struct net_device *ndev = bus->priv;
 113         struct stmmac_priv *priv = netdev_priv(ndev);
 114         unsigned int mii_address = priv->hw->mii.addr;
 115
 116         if (priv->plat->mdio_bus_data->phy_reset) {
 117                 pr_debug("stmmac_mdio_reset: calling phy_reset\n");
 118                 priv->plat->mdio_bus_data->phy_reset(priv->plat->bsp_priv);
 119         }
 120
 121         /* This is a workaround for problems with the STE101P PHY.
 122          * It doesn't complete its reset until at least one clock cycle
 123          * on MDC, so perform a dummy mdio read.
 124          */
 125         writel(0, priv->ioaddr + mii_address);
 126
 127         return 0;
 128 }
 129
 130 /**
 131  * stmmac_mdio_register
 132  * @ndev: net device structure
 133  * Description: it registers the MII bus
 134  */
 135 int stmmac_mdio_register(struct net_device *ndev)
 136 {
 137         int err = 0;
 138         struct mii_bus *new_bus;
 139         int *irqlist;
 140         struct stmmac_priv *priv = netdev_priv(ndev);
 141         struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
 142         int addr, found;
 143
 144         if (!mdio_bus_data)
 145                 return 0;
 146
 147         new_bus = mdiobus_alloc();
 148         if (new_bus == NULL)
 149                 return -ENOMEM;
 150
 151         if (mdio_bus_data->irqs)
 152                 irqlist = mdio_bus_data->irqs;
 153         else
 154                 irqlist = priv->mii_irq;
 155
 156         new_bus->name = "STMMAC MII Bus";
 157         new_bus->read = &stmmac_mdio_read;
 158         new_bus->write = &stmmac_mdio_write;
 159         new_bus->reset = &stmmac_mdio_reset;
 160         snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", mdio_bus_data->bus_id);
 161         new_bus->priv = ndev;
 162         new_bus->irq = irqlist;
 163         new_bus->phy_mask = mdio_bus_data->phy_mask;
 164         new_bus->parent = priv->device;
 165         err = mdiobus_register(new_bus);
 166         if (err != 0) {
 167                 pr_err("%s: Cannot register as MDIO bus\n", new_bus->name);
 168                 goto bus_register_fail;
 169         }
 170
 171         priv->mii = new_bus;
 172
 173         found = 0;
 174         for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
 175                 struct phy_device *phydev = new_bus->phy_map[addr];
 176                 if (phydev) {
 177                         int act = 0;
 178                         char irq_num[4];
 179                         char *irq_str;
 180
 181                         /*
 182                          * If an IRQ was provided to be assigned after
 183                          * the bus probe, do it here.
 184                          */
 185                         if ((mdio_bus_data->irqs == NULL) &&
 186                             (mdio_bus_data->probed_phy_irq > 0)) {
 187                                 irqlist[addr] = mdio_bus_data->probed_phy_irq;
 188                                 phydev->irq = mdio_bus_data->probed_phy_irq;
 189                         }
 190
 191                         /*
 192                          * If we're  going to bind the MAC to this PHY bus,
 193                          * and no PHY number was provided to the MAC,
 194                          * use the one probed here.
 195                          */
 196                         if ((priv->plat->bus_id == mdio_bus_data->bus_id) &&
 197                             (priv->plat->phy_addr == -1))
 198                                 priv->plat->phy_addr = addr;
 199
 200                         act = (priv->plat->bus_id == mdio_bus_data->bus_id) &&
 201                                 (priv->plat->phy_addr == addr);
 202                         switch (phydev->irq) {
 203                         case PHY_POLL:
 204                                 irq_str = "POLL";
 205                                 break;
 206                         case PHY_IGNORE_INTERRUPT:
 207                                 irq_str = "IGNORE";
 208                                 break;
 209                         default:
 210                                 sprintf(irq_num, "%d", phydev->irq);
 211                                 irq_str = irq_num;
 212                                 break;
 213                         }
 214                         pr_info("%s: PHY ID %08x at %d IRQ %s (%s)%s\n",
 215                                 ndev->name, phydev->phy_id, addr,
 216                                 irq_str, dev_name(&phydev->dev),
 217                                 act ? " active" : "");
 218                         found = 1;
 219                 }
 220         }
 221
 222         if (!found)
 223                 pr_warning("%s: No PHY found\n", ndev->name);
 224
 225         return 0;
 226
 227 bus_register_fail:
 228         mdiobus_free(new_bus);
 229         return err;
 230 }
 231
 232 /**
 233  * stmmac_mdio_unregister
 234  * @ndev: net device structure
 235  * Description: it unregisters the MII bus
 236  */
 237 int stmmac_mdio_unregister(struct net_device *ndev)
 238 {
 239         struct stmmac_priv *priv = netdev_priv(ndev);
 240
 241         mdiobus_unregister(priv->mii);
 242         priv->mii->priv = NULL;
 243         mdiobus_free(priv->mii);
 244         priv->mii = NULL;
 245
 246         return 0;
 247 }