arch/powerpc/boot/dts/mpc8548cds.dts

   1 /*
   2  * MPC8548 CDS Device Tree Source
   3  *
   4  * Copyright 2006, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /include/ "fsl/mpc8548si-pre.dtsi"
  13
  14 / {
  15         model = "MPC8548CDS";
  16         compatible = "MPC8548CDS", "MPC85xxCDS";
  17
  18         aliases {
  19                 ethernet0 = &enet0;
  20                 ethernet1 = &enet1;
  21                 ethernet2 = &enet2;
  22                 ethernet3 = &enet3;
  23                 serial0 = &serial0;
  24                 serial1 = &serial1;
  25                 pci0 = &pci0;
  26                 pci1 = &pci1;
  27                 pci2 = &pci2;
  28         };
  29
  30         memory {
  31                 device_type = "memory";
  32                 reg = <0 0 0x0 0x8000000>;      // 128M at 0x0
  33         };
  34
  35         lbc: localbus@e0005000 {
  36                 reg = <0 0xe0005000 0 0x1000>;
  37         };
  38
  39         soc: soc8548@e0000000 {
  40                 ranges = <0 0x0 0xe0000000 0x100000>;
  41
  42                 i2c@3000 {
  43                         eeprom@50 {
  44                                 compatible = "atmel,24c64";
  45                                 reg = <0x50>;
  46                         };
  47
  48                         eeprom@56 {
  49                                 compatible = "atmel,24c64";
  50                                 reg = <0x56>;
  51                         };
  52
  53                         eeprom@57 {
  54                                 compatible = "atmel,24c64";
  55                                 reg = <0x57>;
  56                         };
  57                 };
  58
  59                 i2c@3100 {
  60                         eeprom@50 {
  61                                 compatible = "atmel,24c64";
  62                                 reg = <0x50>;
  63                         };
  64                 };
  65
  66                 enet0: ethernet@24000 {
  67                         tbi-handle = <&tbi0>;
  68                         phy-handle = <&phy0>;
  69                 };
  70
  71                 mdio@24520 {
  72                         phy0: ethernet-phy@0 {
  73                                 interrupts = <5 1 0 0>;
  74                                 reg = <0x0>;
  75                                 device_type = "ethernet-phy";
  76                         };
  77                         phy1: ethernet-phy@1 {
  78                                 interrupts = <5 1 0 0>;
  79                                 reg = <0x1>;
  80                                 device_type = "ethernet-phy";
  81                         };
  82                         phy2: ethernet-phy@2 {
  83                                 interrupts = <5 1 0 0>;
  84                                 reg = <0x2>;
  85                                 device_type = "ethernet-phy";
  86                         };
  87                         phy3: ethernet-phy@3 {
  88                                 interrupts = <5 1 0 0>;
  89                                 reg = <0x3>;
  90                                 device_type = "ethernet-phy";
  91                         };
  92                         tbi0: tbi-phy@11 {
  93                                 reg = <0x11>;
  94                                 device_type = "tbi-phy";
  95                         };
  96                 };
  97
  98                 enet1: ethernet@25000 {
  99                         tbi-handle = <&tbi1>;
 100                         phy-handle = <&phy1>;
 101                 };
 102
 103                 mdio@25520 {
 104                         tbi1: tbi-phy@11 {
 105                                 reg = <0x11>;
 106                                 device_type = "tbi-phy";
 107                         };
 108                 };
 109
 110                 enet2: ethernet@26000 {
 111                         tbi-handle = <&tbi2>;
 112                         phy-handle = <&phy2>;
 113                 };
 114
 115                 mdio@26520 {
 116                         tbi2: tbi-phy@11 {
 117                                 reg = <0x11>;
 118                                 device_type = "tbi-phy";
 119                         };
 120                 };
 121
 122                 enet3: ethernet@27000 {
 123                         tbi-handle = <&tbi3>;
 124                         phy-handle = <&phy3>;
 125                 };
 126
 127                 mdio@27520 {
 128                         tbi3: tbi-phy@11 {
 129                                 reg = <0x11>;
 130                                 device_type = "tbi-phy";
 131                         };
 132                 };
 133         };
 134
 135         pci0: pci@e0008000 {
 136                 reg = <0 0xe0008000 0 0x1000>;
 137                 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
 138                           0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;
 139                 clock-frequency = <66666666>;
 140                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 141                 interrupt-map = <
 142                         /* IDSEL 0x4 (PCIX Slot 2) */
 143                         0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
 144                         0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 145                         0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 146                         0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
 147
 148                         /* IDSEL 0x5 (PCIX Slot 3) */
 149                         0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
 150                         0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
 151                         0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
 152                         0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
 153
 154                         /* IDSEL 0x6 (PCIX Slot 4) */
 155                         0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
 156                         0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
 157                         0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
 158                         0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
 159
 160                         /* IDSEL 0x8 (PCIX Slot 5) */
 161                         0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
 162                         0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 163                         0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 164                         0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
 165
 166                         /* IDSEL 0xC (Tsi310 bridge) */
 167                         0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
 168                         0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 169                         0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 170                         0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
 171
 172                         /* IDSEL 0x14 (Slot 2) */
 173                         0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
 174                         0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 175                         0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 176                         0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
 177
 178                         /* IDSEL 0x15 (Slot 3) */
 179                         0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
 180                         0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
 181                         0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
 182                         0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
 183
 184                         /* IDSEL 0x16 (Slot 4) */
 185                         0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
 186                         0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
 187                         0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
 188                         0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
 189
 190                         /* IDSEL 0x18 (Slot 5) */
 191                         0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
 192                         0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 193                         0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 194                         0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
 195
 196                         /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
 197                         0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
 198                         0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 199                         0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 200                         0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
 201
 202                 pci_bridge@1c {
 203                         interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 204                         interrupt-map = <
 205
 206                                 /* IDSEL 0x00 (PrPMC Site) */
 207                                 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
 208                                 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 209                                 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 210                                 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
 211
 212                                 /* IDSEL 0x04 (VIA chip) */
 213                                 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
 214                                 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 215                                 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 216                                 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
 217
 218                                 /* IDSEL 0x05 (8139) */
 219                                 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
 220
 221                                 /* IDSEL 0x06 (Slot 6) */
 222                                 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
 223                                 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
 224                                 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
 225                                 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
 226
 227                                 /* IDESL 0x07 (Slot 7) */
 228                                 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
 229                                 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0
 230                                 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
 231                                 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>;
 232
 233                         reg = <0xe000 0x0 0x0 0x0 0x0>;
 234                         #interrupt-cells = <1>;
 235                         #size-cells = <2>;
 236                         #address-cells = <3>;
 237                         ranges = <0x2000000 0x0 0x80000000
 238                                   0x2000000 0x0 0x80000000
 239                                   0x0 0x20000000
 240                                   0x1000000 0x0 0x0
 241                                   0x1000000 0x0 0x0
 242                                   0x0 0x80000>;
 243                         clock-frequency = <33333333>;
 244
 245                         isa@4 {
 246                                 device_type = "isa";
 247                                 #interrupt-cells = <2>;
 248                                 #size-cells = <1>;
 249                                 #address-cells = <2>;
 250                                 reg = <0x2000 0x0 0x0 0x0 0x0>;
 251                                 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
 252                                 interrupt-parent = <&i8259>;
 253
 254                                 i8259: interrupt-controller@20 {
 255                                         interrupt-controller;
 256                                         device_type = "interrupt-controller";
 257                                         reg = <0x1 0x20 0x2
 258                                                0x1 0xa0 0x2
 259                                                0x1 0x4d0 0x2>;
 260                                         #address-cells = <0>;
 261                                         #interrupt-cells = <2>;
 262                                         compatible = "chrp,iic";
 263                                         interrupts = <0 1 0 0>;
 264                                         interrupt-parent = <&mpic>;
 265                                 };
 266
 267                                 rtc@70 {
 268                                         compatible = "pnpPNP,b00";
 269                                         reg = <0x1 0x70 0x2>;
 270                                 };
 271                         };
 272                 };
 273         };
 274
 275         pci1: pci@e0009000 {
 276                 reg = <0 0xe0009000 0 0x1000>;
 277                 ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
 278                           0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x800000>;
 279                 clock-frequency = <66666666>;
 280                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 281                 interrupt-map = <
 282
 283                         /* IDSEL 0x15 */
 284                         0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
 285                         0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 286                         0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 287                         0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
 288         };
 289
 290         pci2: pcie@e000a000 {
 291                 reg = <0 0xe000a000 0 0x1000>;
 292                 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
 293                           0x1000000 0x0 0x00000000 0 0xe3000000 0x0 0x100000>;
 294                 pcie@0 {
 295                         ranges = <0x2000000 0x0 0xa0000000
 296                                   0x2000000 0x0 0xa0000000
 297                                   0x0 0x20000000
 298
 299                                   0x1000000 0x0 0x0
 300                                   0x1000000 0x0 0x0
 301                                   0x0 0x100000>;
 302                 };
 303         };
 304 };
 305
 306 /include/ "fsl/mpc8548si-post.dtsi"