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OMAPDSS: VENC: fix NULL pointer dereference in DSS2 VENC sysfs debug attr on OMAP4
[zen-stable.git] / drivers / edac / cpc925_edac.c
bloba774c0ddaf5b06f05e19ddacccf0423a824f1423
1 /*
2 * cpc925_edac.c, EDAC driver for IBM CPC925 Bridge and Memory Controller.
3 *
4 * Copyright (c) 2008 Wind River Systems, Inc.
5 *
6 * Authors: Cao Qingtao <qingtao.cao@windriver.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
15 * See the GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 #include <linux/module.h>
23 #include <linux/init.h>
24 #include <linux/io.h>
25 #include <linux/edac.h>
26 #include <linux/of.h>
27 #include <linux/platform_device.h>
28 #include <linux/gfp.h>
29
30 #include "edac_core.h"
31 #include "edac_module.h"
32
33 #define CPC925_EDAC_REVISION " Ver: 1.0.0"
34 #define CPC925_EDAC_MOD_STR "cpc925_edac"
35
36 #define cpc925_printk(level, fmt, arg...) \
37 edac_printk(level, "CPC925", fmt, ##arg)
38
39 #define cpc925_mc_printk(mci, level, fmt, arg...) \
40 edac_mc_chipset_printk(mci, level, "CPC925", fmt, ##arg)
41
42 /*
43 * CPC925 registers are of 32 bits with bit0 defined at the
44 * most significant bit and bit31 at that of least significant.
45 */
46 #define CPC925_BITS_PER_REG 32
47 #define CPC925_BIT(nr) (1UL << (CPC925_BITS_PER_REG - 1 - nr))
48
49 /*
50 * EDAC device names for the error detections of
51 * CPU Interface and Hypertransport Link.
52 */
53 #define CPC925_CPU_ERR_DEV "cpu"
54 #define CPC925_HT_LINK_DEV "htlink"
55
56 /* Suppose DDR Refresh cycle is 15.6 microsecond */
57 #define CPC925_REF_FREQ 0xFA69
58 #define CPC925_SCRUB_BLOCK_SIZE 64 /* bytes */
59 #define CPC925_NR_CSROWS 8
60
61 /*
62 * All registers and bits definitions are taken from
63 * "CPC925 Bridge and Memory Controller User Manual, SA14-2761-02".
64 */
65
66 /*
67 * CPU and Memory Controller Registers
68 */
69 /************************************************************
70 * Processor Interface Exception Mask Register (APIMASK)
71 ************************************************************/
72 #define REG_APIMASK_OFFSET 0x30070
73 enum apimask_bits {
74 APIMASK_DART = CPC925_BIT(0), /* DART Exception */
75 APIMASK_ADI0 = CPC925_BIT(1), /* Handshake Error on PI0_ADI */
76 APIMASK_ADI1 = CPC925_BIT(2), /* Handshake Error on PI1_ADI */
77 APIMASK_STAT = CPC925_BIT(3), /* Status Exception */
78 APIMASK_DERR = CPC925_BIT(4), /* Data Error Exception */
79 APIMASK_ADRS0 = CPC925_BIT(5), /* Addressing Exception on PI0 */
80 APIMASK_ADRS1 = CPC925_BIT(6), /* Addressing Exception on PI1 */
81 /* BIT(7) Reserved */
82 APIMASK_ECC_UE_H = CPC925_BIT(8), /* UECC upper */
83 APIMASK_ECC_CE_H = CPC925_BIT(9), /* CECC upper */
84 APIMASK_ECC_UE_L = CPC925_BIT(10), /* UECC lower */
85 APIMASK_ECC_CE_L = CPC925_BIT(11), /* CECC lower */
86
87 CPU_MASK_ENABLE = (APIMASK_DART | APIMASK_ADI0 | APIMASK_ADI1 |
88 APIMASK_STAT | APIMASK_DERR | APIMASK_ADRS0 |
89 APIMASK_ADRS1),
90 ECC_MASK_ENABLE = (APIMASK_ECC_UE_H | APIMASK_ECC_CE_H |
91 APIMASK_ECC_UE_L | APIMASK_ECC_CE_L),
92 };
93 #define APIMASK_ADI(n) CPC925_BIT(((n)+1))
94
95 /************************************************************
96 * Processor Interface Exception Register (APIEXCP)
97 ************************************************************/
98 #define REG_APIEXCP_OFFSET 0x30060
99 enum apiexcp_bits {
100 APIEXCP_DART = CPC925_BIT(0), /* DART Exception */
101 APIEXCP_ADI0 = CPC925_BIT(1), /* Handshake Error on PI0_ADI */
102 APIEXCP_ADI1 = CPC925_BIT(2), /* Handshake Error on PI1_ADI */
103 APIEXCP_STAT = CPC925_BIT(3), /* Status Exception */
104 APIEXCP_DERR = CPC925_BIT(4), /* Data Error Exception */
105 APIEXCP_ADRS0 = CPC925_BIT(5), /* Addressing Exception on PI0 */
106 APIEXCP_ADRS1 = CPC925_BIT(6), /* Addressing Exception on PI1 */
107 /* BIT(7) Reserved */
108 APIEXCP_ECC_UE_H = CPC925_BIT(8), /* UECC upper */
109 APIEXCP_ECC_CE_H = CPC925_BIT(9), /* CECC upper */
110 APIEXCP_ECC_UE_L = CPC925_BIT(10), /* UECC lower */
111 APIEXCP_ECC_CE_L = CPC925_BIT(11), /* CECC lower */
112
113 CPU_EXCP_DETECTED = (APIEXCP_DART | APIEXCP_ADI0 | APIEXCP_ADI1 |
114 APIEXCP_STAT | APIEXCP_DERR | APIEXCP_ADRS0 |
115 APIEXCP_ADRS1),
116 UECC_EXCP_DETECTED = (APIEXCP_ECC_UE_H | APIEXCP_ECC_UE_L),
117 CECC_EXCP_DETECTED = (APIEXCP_ECC_CE_H | APIEXCP_ECC_CE_L),
118 ECC_EXCP_DETECTED = (UECC_EXCP_DETECTED | CECC_EXCP_DETECTED),
119 };
120
121 /************************************************************
122 * Memory Bus Configuration Register (MBCR)
123 ************************************************************/
124 #define REG_MBCR_OFFSET 0x2190
125 #define MBCR_64BITCFG_SHIFT 23
126 #define MBCR_64BITCFG_MASK (1UL << MBCR_64BITCFG_SHIFT)
127 #define MBCR_64BITBUS_SHIFT 22
128 #define MBCR_64BITBUS_MASK (1UL << MBCR_64BITBUS_SHIFT)
129
130 /************************************************************
131 * Memory Bank Mode Register (MBMR)
132 ************************************************************/
133 #define REG_MBMR_OFFSET 0x21C0
134 #define MBMR_MODE_MAX_VALUE 0xF
135 #define MBMR_MODE_SHIFT 25
136 #define MBMR_MODE_MASK (MBMR_MODE_MAX_VALUE << MBMR_MODE_SHIFT)
137 #define MBMR_BBA_SHIFT 24
138 #define MBMR_BBA_MASK (1UL << MBMR_BBA_SHIFT)
139
140 /************************************************************
141 * Memory Bank Boundary Address Register (MBBAR)
142 ************************************************************/
143 #define REG_MBBAR_OFFSET 0x21D0
144 #define MBBAR_BBA_MAX_VALUE 0xFF
145 #define MBBAR_BBA_SHIFT 24
146 #define MBBAR_BBA_MASK (MBBAR_BBA_MAX_VALUE << MBBAR_BBA_SHIFT)
147
148 /************************************************************
149 * Memory Scrub Control Register (MSCR)
150 ************************************************************/
151 #define REG_MSCR_OFFSET 0x2400
152 #define MSCR_SCRUB_MOD_MASK 0xC0000000 /* scrub_mod - bit0:1*/
153 #define MSCR_BACKGR_SCRUB 0x40000000 /* 01 */
154 #define MSCR_SI_SHIFT 16 /* si - bit8:15*/
155 #define MSCR_SI_MAX_VALUE 0xFF
156 #define MSCR_SI_MASK (MSCR_SI_MAX_VALUE << MSCR_SI_SHIFT)
157
158 /************************************************************
159 * Memory Scrub Range Start Register (MSRSR)
160 ************************************************************/
161 #define REG_MSRSR_OFFSET 0x2410
162
163 /************************************************************
164 * Memory Scrub Range End Register (MSRER)
165 ************************************************************/
166 #define REG_MSRER_OFFSET 0x2420
167
168 /************************************************************
169 * Memory Scrub Pattern Register (MSPR)
170 ************************************************************/
171 #define REG_MSPR_OFFSET 0x2430
172
173 /************************************************************
174 * Memory Check Control Register (MCCR)
175 ************************************************************/
176 #define REG_MCCR_OFFSET 0x2440
177 enum mccr_bits {
178 MCCR_ECC_EN = CPC925_BIT(0), /* ECC high and low check */
179 };
180
181 /************************************************************
182 * Memory Check Range End Register (MCRER)
183 ************************************************************/
184 #define REG_MCRER_OFFSET 0x2450
185
186 /************************************************************
187 * Memory Error Address Register (MEAR)
188 ************************************************************/
189 #define REG_MEAR_OFFSET 0x2460
190 #define MEAR_BCNT_MAX_VALUE 0x3
191 #define MEAR_BCNT_SHIFT 30
192 #define MEAR_BCNT_MASK (MEAR_BCNT_MAX_VALUE << MEAR_BCNT_SHIFT)
193 #define MEAR_RANK_MAX_VALUE 0x7
194 #define MEAR_RANK_SHIFT 27
195 #define MEAR_RANK_MASK (MEAR_RANK_MAX_VALUE << MEAR_RANK_SHIFT)
196 #define MEAR_COL_MAX_VALUE 0x7FF
197 #define MEAR_COL_SHIFT 16
198 #define MEAR_COL_MASK (MEAR_COL_MAX_VALUE << MEAR_COL_SHIFT)
199 #define MEAR_BANK_MAX_VALUE 0x3
200 #define MEAR_BANK_SHIFT 14
201 #define MEAR_BANK_MASK (MEAR_BANK_MAX_VALUE << MEAR_BANK_SHIFT)
202 #define MEAR_ROW_MASK 0x00003FFF
203
204 /************************************************************
205 * Memory Error Syndrome Register (MESR)
206 ************************************************************/
207 #define REG_MESR_OFFSET 0x2470
208 #define MESR_ECC_SYN_H_MASK 0xFF00
209 #define MESR_ECC_SYN_L_MASK 0x00FF
210
211 /************************************************************
212 * Memory Mode Control Register (MMCR)
213 ************************************************************/
214 #define REG_MMCR_OFFSET 0x2500
215 enum mmcr_bits {
216 MMCR_REG_DIMM_MODE = CPC925_BIT(3),
217 };
218
219 /*
220 * HyperTransport Link Registers
221 */
222 /************************************************************
223 * Error Handling/Enumeration Scratch Pad Register (ERRCTRL)
224 ************************************************************/
225 #define REG_ERRCTRL_OFFSET 0x70140
226 enum errctrl_bits { /* nonfatal interrupts for */
227 ERRCTRL_SERR_NF = CPC925_BIT(0), /* system error */
228 ERRCTRL_CRC_NF = CPC925_BIT(1), /* CRC error */
229 ERRCTRL_RSP_NF = CPC925_BIT(2), /* Response error */
230 ERRCTRL_EOC_NF = CPC925_BIT(3), /* End-Of-Chain error */
231 ERRCTRL_OVF_NF = CPC925_BIT(4), /* Overflow error */
232 ERRCTRL_PROT_NF = CPC925_BIT(5), /* Protocol error */
233
234 ERRCTRL_RSP_ERR = CPC925_BIT(6), /* Response error received */
235 ERRCTRL_CHN_FAL = CPC925_BIT(7), /* Sync flooding detected */
236
237 HT_ERRCTRL_ENABLE = (ERRCTRL_SERR_NF | ERRCTRL_CRC_NF |
238 ERRCTRL_RSP_NF | ERRCTRL_EOC_NF |
239 ERRCTRL_OVF_NF | ERRCTRL_PROT_NF),
240 HT_ERRCTRL_DETECTED = (ERRCTRL_RSP_ERR | ERRCTRL_CHN_FAL),
241 };
242
243 /************************************************************
244 * Link Configuration and Link Control Register (LINKCTRL)
245 ************************************************************/
246 #define REG_LINKCTRL_OFFSET 0x70110
247 enum linkctrl_bits {
248 LINKCTRL_CRC_ERR = (CPC925_BIT(22) | CPC925_BIT(23)),
249 LINKCTRL_LINK_FAIL = CPC925_BIT(27),
250
251 HT_LINKCTRL_DETECTED = (LINKCTRL_CRC_ERR | LINKCTRL_LINK_FAIL),
252 };
253
254 /************************************************************
255 * Link FreqCap/Error/Freq/Revision ID Register (LINKERR)
256 ************************************************************/
257 #define REG_LINKERR_OFFSET 0x70120
258 enum linkerr_bits {
259 LINKERR_EOC_ERR = CPC925_BIT(17), /* End-Of-Chain error */
260 LINKERR_OVF_ERR = CPC925_BIT(18), /* Receive Buffer Overflow */
261 LINKERR_PROT_ERR = CPC925_BIT(19), /* Protocol error */
262
263 HT_LINKERR_DETECTED = (LINKERR_EOC_ERR | LINKERR_OVF_ERR |
264 LINKERR_PROT_ERR),
265 };
266
267 /************************************************************
268 * Bridge Control Register (BRGCTRL)
269 ************************************************************/
270 #define REG_BRGCTRL_OFFSET 0x70300
271 enum brgctrl_bits {
272 BRGCTRL_DETSERR = CPC925_BIT(0), /* SERR on Secondary Bus */
273 BRGCTRL_SECBUSRESET = CPC925_BIT(9), /* Secondary Bus Reset */
274 };
275
276 /* Private structure for edac memory controller */
277 struct cpc925_mc_pdata {
278 void __iomem *vbase;
279 unsigned long total_mem;
280 const char *name;
281 int edac_idx;
282 };
283
284 /* Private structure for common edac device */
285 struct cpc925_dev_info {
286 void __iomem *vbase;
287 struct platform_device *pdev;
288 char *ctl_name;
289 int edac_idx;
290 struct edac_device_ctl_info *edac_dev;
291 void (*init)(struct cpc925_dev_info *dev_info);
292 void (*exit)(struct cpc925_dev_info *dev_info);
293 void (*check)(struct edac_device_ctl_info *edac_dev);
294 };
295
296 /* Get total memory size from Open Firmware DTB */
297 static void get_total_mem(struct cpc925_mc_pdata *pdata)
298 {
299 struct device_node *np = NULL;
300 const unsigned int *reg, *reg_end;
301 int len, sw, aw;
302 unsigned long start, size;
303
304 np = of_find_node_by_type(NULL, "memory");
305 if (!np)
306 return;
307
308 aw = of_n_addr_cells(np);
309 sw = of_n_size_cells(np);
310 reg = (const unsigned int *)of_get_property(np, "reg", &len);
311 reg_end = reg + len/4;
312
313 pdata->total_mem = 0;
314 do {
315 start = of_read_number(reg, aw);
316 reg += aw;
317 size = of_read_number(reg, sw);
318 reg += sw;
319 debugf1("%s: start 0x%lx, size 0x%lx\n", __func__,
320 start, size);
321 pdata->total_mem += size;
322 } while (reg < reg_end);
323
324 of_node_put(np);
325 debugf0("%s: total_mem 0x%lx\n", __func__, pdata->total_mem);
326 }
327
328 static void cpc925_init_csrows(struct mem_ctl_info *mci)
329 {
330 struct cpc925_mc_pdata *pdata = mci->pvt_info;
331 struct csrow_info *csrow;
332 int index;
333 u32 mbmr, mbbar, bba;
334 unsigned long row_size, last_nr_pages = 0;
335
336 get_total_mem(pdata);
337
338 for (index = 0; index < mci->nr_csrows; index++) {
339 mbmr = __raw_readl(pdata->vbase + REG_MBMR_OFFSET +
340 0x20 * index);
341 mbbar = __raw_readl(pdata->vbase + REG_MBBAR_OFFSET +
342 0x20 + index);
343 bba = (((mbmr & MBMR_BBA_MASK) >> MBMR_BBA_SHIFT) << 8) |
344 ((mbbar & MBBAR_BBA_MASK) >> MBBAR_BBA_SHIFT);
345
346 if (bba == 0)
347 continue; /* not populated */
348
349 csrow = &mci->csrows[index];
350
351 row_size = bba * (1UL << 28); /* 256M */
352 csrow->first_page = last_nr_pages;
353 csrow->nr_pages = row_size >> PAGE_SHIFT;
354 csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
355 last_nr_pages = csrow->last_page + 1;
356
357 csrow->mtype = MEM_RDDR;
358 csrow->edac_mode = EDAC_SECDED;
359
360 switch (csrow->nr_channels) {
361 case 1: /* Single channel */
362 csrow->grain = 32; /* four-beat burst of 32 bytes */
363 break;
364 case 2: /* Dual channel */
365 default:
366 csrow->grain = 64; /* four-beat burst of 64 bytes */
367 break;
368 }
369
370 switch ((mbmr & MBMR_MODE_MASK) >> MBMR_MODE_SHIFT) {
371 case 6: /* 0110, no way to differentiate X8 VS X16 */
372 case 5: /* 0101 */
373 case 8: /* 1000 */
374 csrow->dtype = DEV_X16;
375 break;
376 case 7: /* 0111 */
377 case 9: /* 1001 */
378 csrow->dtype = DEV_X8;
379 break;
380 default:
381 csrow->dtype = DEV_UNKNOWN;
382 break;
383 }
384 }
385 }
386
387 /* Enable memory controller ECC detection */
388 static void cpc925_mc_init(struct mem_ctl_info *mci)
389 {
390 struct cpc925_mc_pdata *pdata = mci->pvt_info;
391 u32 apimask;
392 u32 mccr;
393
394 /* Enable various ECC error exceptions */
395 apimask = __raw_readl(pdata->vbase + REG_APIMASK_OFFSET);
396 if ((apimask & ECC_MASK_ENABLE) == 0) {
397 apimask |= ECC_MASK_ENABLE;
398 __raw_writel(apimask, pdata->vbase + REG_APIMASK_OFFSET);
399 }
400
401 /* Enable ECC detection */
402 mccr = __raw_readl(pdata->vbase + REG_MCCR_OFFSET);
403 if ((mccr & MCCR_ECC_EN) == 0) {
404 mccr |= MCCR_ECC_EN;
405 __raw_writel(mccr, pdata->vbase + REG_MCCR_OFFSET);
406 }
407 }
408
409 /* Disable memory controller ECC detection */
410 static void cpc925_mc_exit(struct mem_ctl_info *mci)
411 {
412 /*
413 * WARNING:
414 * We are supposed to clear the ECC error detection bits,
415 * and it will be no problem to do so. However, once they
416 * are cleared here if we want to re-install CPC925 EDAC
417 * module later, setting them up in cpc925_mc_init() will
418 * trigger machine check exception.
419 * Also, it's ok to leave ECC error detection bits enabled,
420 * since they are reset to 1 by default or by boot loader.
421 */
422
423 return;
424 }
425
426 /*
427 * Revert DDR column/row/bank addresses into page frame number and
428 * offset in page.
429 *
430 * Suppose memory mode is 0x0111(128-bit mode, identical DIMM pairs),
431 * physical address(PA) bits to column address(CA) bits mappings are:
432 * CA 0 1 2 3 4 5 6 7 8 9 10
433 * PA 59 58 57 56 55 54 53 52 51 50 49
434 *
435 * physical address(PA) bits to bank address(BA) bits mappings are:
436 * BA 0 1
437 * PA 43 44
438 *
439 * physical address(PA) bits to row address(RA) bits mappings are:
440 * RA 0 1 2 3 4 5 6 7 8 9 10 11 12
441 * PA 36 35 34 48 47 46 45 40 41 42 39 38 37
442 */
443 static void cpc925_mc_get_pfn(struct mem_ctl_info *mci, u32 mear,
444 unsigned long *pfn, unsigned long *offset, int *csrow)
445 {
446 u32 bcnt, rank, col, bank, row;
447 u32 c;
448 unsigned long pa;
449 int i;
450
451 bcnt = (mear & MEAR_BCNT_MASK) >> MEAR_BCNT_SHIFT;
452 rank = (mear & MEAR_RANK_MASK) >> MEAR_RANK_SHIFT;
453 col = (mear & MEAR_COL_MASK) >> MEAR_COL_SHIFT;
454 bank = (mear & MEAR_BANK_MASK) >> MEAR_BANK_SHIFT;
455 row = mear & MEAR_ROW_MASK;
456
457 *csrow = rank;
458
459 #ifdef CONFIG_EDAC_DEBUG
460 if (mci->csrows[rank].first_page == 0) {
461 cpc925_mc_printk(mci, KERN_ERR, "ECC occurs in a "
462 "non-populated csrow, broken hardware?\n");
463 return;
464 }
465 #endif
466
467 /* Revert csrow number */
468 pa = mci->csrows[rank].first_page << PAGE_SHIFT;
469
470 /* Revert column address */
471 col += bcnt;
472 for (i = 0; i < 11; i++) {
473 c = col & 0x1;
474 col >>= 1;
475 pa |= c << (14 - i);
476 }
477
478 /* Revert bank address */
479 pa |= bank << 19;
480
481 /* Revert row address, in 4 steps */
482 for (i = 0; i < 3; i++) {
483 c = row & 0x1;
484 row >>= 1;
485 pa |= c << (26 - i);
486 }
487
488 for (i = 0; i < 3; i++) {
489 c = row & 0x1;
490 row >>= 1;
491 pa |= c << (21 + i);
492 }
493
494 for (i = 0; i < 4; i++) {
495 c = row & 0x1;
496 row >>= 1;
497 pa |= c << (18 - i);
498 }
499
500 for (i = 0; i < 3; i++) {
501 c = row & 0x1;
502 row >>= 1;
503 pa |= c << (29 - i);
504 }
505
506 *offset = pa & (PAGE_SIZE - 1);
507 *pfn = pa >> PAGE_SHIFT;
508
509 debugf0("%s: ECC physical address 0x%lx\n", __func__, pa);
510 }
511
512 static int cpc925_mc_find_channel(struct mem_ctl_info *mci, u16 syndrome)
513 {
514 if ((syndrome & MESR_ECC_SYN_H_MASK) == 0)
515 return 0;
516
517 if ((syndrome & MESR_ECC_SYN_L_MASK) == 0)
518 return 1;
519
520 cpc925_mc_printk(mci, KERN_INFO, "Unexpected syndrome value: 0x%x\n",
521 syndrome);
522 return 1;
523 }
524
525 /* Check memory controller registers for ECC errors */
526 static void cpc925_mc_check(struct mem_ctl_info *mci)
527 {
528 struct cpc925_mc_pdata *pdata = mci->pvt_info;
529 u32 apiexcp;
530 u32 mear;
531 u32 mesr;
532 u16 syndrome;
533 unsigned long pfn = 0, offset = 0;
534 int csrow = 0, channel = 0;
535
536 /* APIEXCP is cleared when read */
537 apiexcp = __raw_readl(pdata->vbase + REG_APIEXCP_OFFSET);
538 if ((apiexcp & ECC_EXCP_DETECTED) == 0)
539 return;
540
541 mesr = __raw_readl(pdata->vbase + REG_MESR_OFFSET);
542 syndrome = mesr | (MESR_ECC_SYN_H_MASK | MESR_ECC_SYN_L_MASK);
543
544 mear = __raw_readl(pdata->vbase + REG_MEAR_OFFSET);
545
546 /* Revert column/row addresses into page frame number, etc */
547 cpc925_mc_get_pfn(mci, mear, &pfn, &offset, &csrow);
548
549 if (apiexcp & CECC_EXCP_DETECTED) {
550 cpc925_mc_printk(mci, KERN_INFO, "DRAM CECC Fault\n");
551 channel = cpc925_mc_find_channel(mci, syndrome);
552 edac_mc_handle_ce(mci, pfn, offset, syndrome,
553 csrow, channel, mci->ctl_name);
554 }
555
556 if (apiexcp & UECC_EXCP_DETECTED) {
557 cpc925_mc_printk(mci, KERN_INFO, "DRAM UECC Fault\n");
558 edac_mc_handle_ue(mci, pfn, offset, csrow, mci->ctl_name);
559 }
560
561 cpc925_mc_printk(mci, KERN_INFO, "Dump registers:\n");
562 cpc925_mc_printk(mci, KERN_INFO, "APIMASK 0x%08x\n",
563 __raw_readl(pdata->vbase + REG_APIMASK_OFFSET));
564 cpc925_mc_printk(mci, KERN_INFO, "APIEXCP 0x%08x\n",
565 apiexcp);
566 cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Ctrl 0x%08x\n",
567 __raw_readl(pdata->vbase + REG_MSCR_OFFSET));
568 cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Rge Start 0x%08x\n",
569 __raw_readl(pdata->vbase + REG_MSRSR_OFFSET));
570 cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Rge End 0x%08x\n",
571 __raw_readl(pdata->vbase + REG_MSRER_OFFSET));
572 cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Pattern 0x%08x\n",
573 __raw_readl(pdata->vbase + REG_MSPR_OFFSET));
574 cpc925_mc_printk(mci, KERN_INFO, "Mem Chk Ctrl 0x%08x\n",
575 __raw_readl(pdata->vbase + REG_MCCR_OFFSET));
576 cpc925_mc_printk(mci, KERN_INFO, "Mem Chk Rge End 0x%08x\n",
577 __raw_readl(pdata->vbase + REG_MCRER_OFFSET));
578 cpc925_mc_printk(mci, KERN_INFO, "Mem Err Address 0x%08x\n",
579 mesr);
580 cpc925_mc_printk(mci, KERN_INFO, "Mem Err Syndrome 0x%08x\n",
581 syndrome);
582 }
583
584 /******************** CPU err device********************************/
585 static u32 cpc925_cpu_mask_disabled(void)
586 {
587 struct device_node *cpus;
588 struct device_node *cpunode = NULL;
589 static u32 mask = 0;
590
591 /* use cached value if available */
592 if (mask != 0)
593 return mask;
594
595 mask = APIMASK_ADI0 | APIMASK_ADI1;
596
597 cpus = of_find_node_by_path("/cpus");
598 if (cpus == NULL) {
599 cpc925_printk(KERN_DEBUG, "No /cpus node !\n");
600 return 0;
601 }
602
603 while ((cpunode = of_get_next_child(cpus, cpunode)) != NULL) {
604 const u32 *reg = of_get_property(cpunode, "reg", NULL);
605
606 if (strcmp(cpunode->type, "cpu")) {
607 cpc925_printk(KERN_ERR, "Not a cpu node in /cpus: %s\n", cpunode->name);
608 continue;
609 }
610
611 if (reg == NULL || *reg > 2) {
612 cpc925_printk(KERN_ERR, "Bad reg value at %s\n", cpunode->full_name);
613 continue;
614 }
615
616 mask &= ~APIMASK_ADI(*reg);
617 }
618
619 if (mask != (APIMASK_ADI0 | APIMASK_ADI1)) {
620 /* We assume that each CPU sits on it's own PI and that
621 * for present CPUs the reg property equals to the PI
622 * interface id */
623 cpc925_printk(KERN_WARNING,
624 "Assuming PI id is equal to CPU MPIC id!\n");
625 }
626
627 of_node_put(cpunode);
628 of_node_put(cpus);
629
630 return mask;
631 }
632
633 /* Enable CPU Errors detection */
634 static void cpc925_cpu_init(struct cpc925_dev_info *dev_info)
635 {
636 u32 apimask;
637 u32 cpumask;
638
639 apimask = __raw_readl(dev_info->vbase + REG_APIMASK_OFFSET);
640
641 cpumask = cpc925_cpu_mask_disabled();
642 if (apimask & cpumask) {
643 cpc925_printk(KERN_WARNING, "CPU(s) not present, "
644 "but enabled in APIMASK, disabling\n");
645 apimask &= ~cpumask;
646 }
647
648 if ((apimask & CPU_MASK_ENABLE) == 0)
649 apimask |= CPU_MASK_ENABLE;
650
651 __raw_writel(apimask, dev_info->vbase + REG_APIMASK_OFFSET);
652 }
653
654 /* Disable CPU Errors detection */
655 static void cpc925_cpu_exit(struct cpc925_dev_info *dev_info)
656 {
657 /*
658 * WARNING:
659 * We are supposed to clear the CPU error detection bits,
660 * and it will be no problem to do so. However, once they
661 * are cleared here if we want to re-install CPC925 EDAC
662 * module later, setting them up in cpc925_cpu_init() will
663 * trigger machine check exception.
664 * Also, it's ok to leave CPU error detection bits enabled,
665 * since they are reset to 1 by default.
666 */
667
668 return;
669 }
670
671 /* Check for CPU Errors */
672 static void cpc925_cpu_check(struct edac_device_ctl_info *edac_dev)
673 {
674 struct cpc925_dev_info *dev_info = edac_dev->pvt_info;
675 u32 apiexcp;
676 u32 apimask;
677
678 /* APIEXCP is cleared when read */
679 apiexcp = __raw_readl(dev_info->vbase + REG_APIEXCP_OFFSET);
680 if ((apiexcp & CPU_EXCP_DETECTED) == 0)
681 return;
682
683 if ((apiexcp & ~cpc925_cpu_mask_disabled()) == 0)
684 return;
685
686 apimask = __raw_readl(dev_info->vbase + REG_APIMASK_OFFSET);
687 cpc925_printk(KERN_INFO, "Processor Interface Fault\n"
688 "Processor Interface register dump:\n");
689 cpc925_printk(KERN_INFO, "APIMASK 0x%08x\n", apimask);
690 cpc925_printk(KERN_INFO, "APIEXCP 0x%08x\n", apiexcp);
691
692 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
693 }
694
695 /******************** HT Link err device****************************/
696 /* Enable HyperTransport Link Error detection */
697 static void cpc925_htlink_init(struct cpc925_dev_info *dev_info)
698 {
699 u32 ht_errctrl;
700
701 ht_errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET);
702 if ((ht_errctrl & HT_ERRCTRL_ENABLE) == 0) {
703 ht_errctrl |= HT_ERRCTRL_ENABLE;
704 __raw_writel(ht_errctrl, dev_info->vbase + REG_ERRCTRL_OFFSET);
705 }
706 }
707
708 /* Disable HyperTransport Link Error detection */
709 static void cpc925_htlink_exit(struct cpc925_dev_info *dev_info)
710 {
711 u32 ht_errctrl;
712
713 ht_errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET);
714 ht_errctrl &= ~HT_ERRCTRL_ENABLE;
715 __raw_writel(ht_errctrl, dev_info->vbase + REG_ERRCTRL_OFFSET);
716 }
717
718 /* Check for HyperTransport Link errors */
719 static void cpc925_htlink_check(struct edac_device_ctl_info *edac_dev)
720 {
721 struct cpc925_dev_info *dev_info = edac_dev->pvt_info;
722 u32 brgctrl = __raw_readl(dev_info->vbase + REG_BRGCTRL_OFFSET);
723 u32 linkctrl = __raw_readl(dev_info->vbase + REG_LINKCTRL_OFFSET);
724 u32 errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET);
725 u32 linkerr = __raw_readl(dev_info->vbase + REG_LINKERR_OFFSET);
726
727 if (!((brgctrl & BRGCTRL_DETSERR) ||
728 (linkctrl & HT_LINKCTRL_DETECTED) ||
729 (errctrl & HT_ERRCTRL_DETECTED) ||
730 (linkerr & HT_LINKERR_DETECTED)))
731 return;
732
733 cpc925_printk(KERN_INFO, "HT Link Fault\n"
734 "HT register dump:\n");
735 cpc925_printk(KERN_INFO, "Bridge Ctrl 0x%08x\n",
736 brgctrl);
737 cpc925_printk(KERN_INFO, "Link Config Ctrl 0x%08x\n",
738 linkctrl);
739 cpc925_printk(KERN_INFO, "Error Enum and Ctrl 0x%08x\n",
740 errctrl);
741 cpc925_printk(KERN_INFO, "Link Error 0x%08x\n",
742 linkerr);
743
744 /* Clear by write 1 */
745 if (brgctrl & BRGCTRL_DETSERR)
746 __raw_writel(BRGCTRL_DETSERR,
747 dev_info->vbase + REG_BRGCTRL_OFFSET);
748
749 if (linkctrl & HT_LINKCTRL_DETECTED)
750 __raw_writel(HT_LINKCTRL_DETECTED,
751 dev_info->vbase + REG_LINKCTRL_OFFSET);
752
753 /* Initiate Secondary Bus Reset to clear the chain failure */
754 if (errctrl & ERRCTRL_CHN_FAL)
755 __raw_writel(BRGCTRL_SECBUSRESET,
756 dev_info->vbase + REG_BRGCTRL_OFFSET);
757
758 if (errctrl & ERRCTRL_RSP_ERR)
759 __raw_writel(ERRCTRL_RSP_ERR,
760 dev_info->vbase + REG_ERRCTRL_OFFSET);
761
762 if (linkerr & HT_LINKERR_DETECTED)
763 __raw_writel(HT_LINKERR_DETECTED,
764 dev_info->vbase + REG_LINKERR_OFFSET);
765
766 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name);
767 }
768
769 static struct cpc925_dev_info cpc925_devs[] = {
770 {
771 .ctl_name = CPC925_CPU_ERR_DEV,
772 .init = cpc925_cpu_init,
773 .exit = cpc925_cpu_exit,
774 .check = cpc925_cpu_check,
775 },
776 {
777 .ctl_name = CPC925_HT_LINK_DEV,
778 .init = cpc925_htlink_init,
779 .exit = cpc925_htlink_exit,
780 .check = cpc925_htlink_check,
781 },
782 {0}, /* Terminated by NULL */
783 };
784
785 /*
786 * Add CPU Err detection and HyperTransport Link Err detection
787 * as common "edac_device", they have no corresponding device
788 * nodes in the Open Firmware DTB and we have to add platform
789 * devices for them. Also, they will share the MMIO with that
790 * of memory controller.
791 */
792 static void cpc925_add_edac_devices(void __iomem *vbase)
793 {
794 struct cpc925_dev_info *dev_info;
795
796 if (!vbase) {
797 cpc925_printk(KERN_ERR, "MMIO not established yet\n");
798 return;
799 }
800
801 for (dev_info = &cpc925_devs[0]; dev_info->init; dev_info++) {
802 dev_info->vbase = vbase;
803 dev_info->pdev = platform_device_register_simple(
804 dev_info->ctl_name, 0, NULL, 0);
805 if (IS_ERR(dev_info->pdev)) {
806 cpc925_printk(KERN_ERR,
807 "Can't register platform device for %s\n",
808 dev_info->ctl_name);
809 continue;
810 }
811
812 /*
813 * Don't have to allocate private structure but
814 * make use of cpc925_devs[] instead.
815 */
816 dev_info->edac_idx = edac_device_alloc_index();
817 dev_info->edac_dev =
818 edac_device_alloc_ctl_info(0, dev_info->ctl_name,
819 1, NULL, 0, 0, NULL, 0, dev_info->edac_idx);
820 if (!dev_info->edac_dev) {
821 cpc925_printk(KERN_ERR, "No memory for edac device\n");
822 goto err1;
823 }
824
825 dev_info->edac_dev->pvt_info = dev_info;
826 dev_info->edac_dev->dev = &dev_info->pdev->dev;
827 dev_info->edac_dev->ctl_name = dev_info->ctl_name;
828 dev_info->edac_dev->mod_name = CPC925_EDAC_MOD_STR;
829 dev_info->edac_dev->dev_name = dev_name(&dev_info->pdev->dev);
830
831 if (edac_op_state == EDAC_OPSTATE_POLL)
832 dev_info->edac_dev->edac_check = dev_info->check;
833
834 if (dev_info->init)
835 dev_info->init(dev_info);
836
837 if (edac_device_add_device(dev_info->edac_dev) > 0) {
838 cpc925_printk(KERN_ERR,
839 "Unable to add edac device for %s\n",
840 dev_info->ctl_name);
841 goto err2;
842 }
843
844 debugf0("%s: Successfully added edac device for %s\n",
845 __func__, dev_info->ctl_name);
846
847 continue;
848
849 err2:
850 if (dev_info->exit)
851 dev_info->exit(dev_info);
852 edac_device_free_ctl_info(dev_info->edac_dev);
853 err1:
854 platform_device_unregister(dev_info->pdev);
855 }
856 }
857
858 /*
859 * Delete the common "edac_device" for CPU Err Detection
860 * and HyperTransport Link Err Detection
861 */
862 static void cpc925_del_edac_devices(void)
863 {
864 struct cpc925_dev_info *dev_info;
865
866 for (dev_info = &cpc925_devs[0]; dev_info->init; dev_info++) {
867 if (dev_info->edac_dev) {
868 edac_device_del_device(dev_info->edac_dev->dev);
869 edac_device_free_ctl_info(dev_info->edac_dev);
870 platform_device_unregister(dev_info->pdev);
871 }
872
873 if (dev_info->exit)
874 dev_info->exit(dev_info);
875
876 debugf0("%s: Successfully deleted edac device for %s\n",
877 __func__, dev_info->ctl_name);
878 }
879 }
880
881 /* Convert current back-ground scrub rate into byte/sec bandwidth */
882 static int cpc925_get_sdram_scrub_rate(struct mem_ctl_info *mci)
883 {
884 struct cpc925_mc_pdata *pdata = mci->pvt_info;
885 int bw;
886 u32 mscr;
887 u8 si;
888
889 mscr = __raw_readl(pdata->vbase + REG_MSCR_OFFSET);
890 si = (mscr & MSCR_SI_MASK) >> MSCR_SI_SHIFT;
891
892 debugf0("%s, Mem Scrub Ctrl Register 0x%x\n", __func__, mscr);
893
894 if (((mscr & MSCR_SCRUB_MOD_MASK) != MSCR_BACKGR_SCRUB) ||
895 (si == 0)) {
896 cpc925_mc_printk(mci, KERN_INFO, "Scrub mode not enabled\n");
897 bw = 0;
898 } else
899 bw = CPC925_SCRUB_BLOCK_SIZE * 0xFA67 / si;
900
901 return bw;
902 }
903
904 /* Return 0 for single channel; 1 for dual channel */
905 static int cpc925_mc_get_channels(void __iomem *vbase)
906 {
907 int dual = 0;
908 u32 mbcr;
909
910 mbcr = __raw_readl(vbase + REG_MBCR_OFFSET);
911
912 /*
913 * Dual channel only when 128-bit wide physical bus
914 * and 128-bit configuration.
915 */
916 if (((mbcr & MBCR_64BITCFG_MASK) == 0) &&
917 ((mbcr & MBCR_64BITBUS_MASK) == 0))
918 dual = 1;
919
920 debugf0("%s: %s channel\n", __func__,
921 (dual > 0) ? "Dual" : "Single");
922
923 return dual;
924 }
925
926 static int __devinit cpc925_probe(struct platform_device *pdev)
927 {
928 static int edac_mc_idx;
929 struct mem_ctl_info *mci;
930 void __iomem *vbase;
931 struct cpc925_mc_pdata *pdata;
932 struct resource *r;
933 int res = 0, nr_channels;
934
935 debugf0("%s: %s platform device found!\n", __func__, pdev->name);
936
937 if (!devres_open_group(&pdev->dev, cpc925_probe, GFP_KERNEL)) {
938 res = -ENOMEM;
939 goto out;
940 }
941
942 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
943 if (!r) {
944 cpc925_printk(KERN_ERR, "Unable to get resource\n");
945 res = -ENOENT;
946 goto err1;
947 }
948
949 if (!devm_request_mem_region(&pdev->dev,
950 r->start,
951 resource_size(r),
952 pdev->name)) {
953 cpc925_printk(KERN_ERR, "Unable to request mem region\n");
954 res = -EBUSY;
955 goto err1;
956 }
957
958 vbase = devm_ioremap(&pdev->dev, r->start, resource_size(r));
959 if (!vbase) {
960 cpc925_printk(KERN_ERR, "Unable to ioremap device\n");
961 res = -ENOMEM;
962 goto err2;
963 }
964
965 nr_channels = cpc925_mc_get_channels(vbase);
966 mci = edac_mc_alloc(sizeof(struct cpc925_mc_pdata),
967 CPC925_NR_CSROWS, nr_channels + 1, edac_mc_idx);
968 if (!mci) {
969 cpc925_printk(KERN_ERR, "No memory for mem_ctl_info\n");
970 res = -ENOMEM;
971 goto err2;
972 }
973
974 pdata = mci->pvt_info;
975 pdata->vbase = vbase;
976 pdata->edac_idx = edac_mc_idx++;
977 pdata->name = pdev->name;
978
979 mci->dev = &pdev->dev;
980 platform_set_drvdata(pdev, mci);
981 mci->dev_name = dev_name(&pdev->dev);
982 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR;
983 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
984 mci->edac_cap = EDAC_FLAG_SECDED;
985 mci->mod_name = CPC925_EDAC_MOD_STR;
986 mci->mod_ver = CPC925_EDAC_REVISION;
987 mci->ctl_name = pdev->name;
988
989 if (edac_op_state == EDAC_OPSTATE_POLL)
990 mci->edac_check = cpc925_mc_check;
991
992 mci->ctl_page_to_phys = NULL;
993 mci->scrub_mode = SCRUB_SW_SRC;
994 mci->set_sdram_scrub_rate = NULL;
995 mci->get_sdram_scrub_rate = cpc925_get_sdram_scrub_rate;
996
997 cpc925_init_csrows(mci);
998
999 /* Setup memory controller registers */
1000 cpc925_mc_init(mci);
1001
1002 if (edac_mc_add_mc(mci) > 0) {
1003 cpc925_mc_printk(mci, KERN_ERR, "Failed edac_mc_add_mc()\n");
1004 goto err3;
1005 }
1006
1007 cpc925_add_edac_devices(vbase);
1008
1009 /* get this far and it's successful */
1010 debugf0("%s: success\n", __func__);
1011
1012 res = 0;
1013 goto out;
1014
1015 err3:
1016 cpc925_mc_exit(mci);
1017 edac_mc_free(mci);
1018 err2:
1019 devm_release_mem_region(&pdev->dev, r->start, resource_size(r));
1020 err1:
1021 devres_release_group(&pdev->dev, cpc925_probe);
1022 out:
1023 return res;
1024 }
1025
1026 static int cpc925_remove(struct platform_device *pdev)
1027 {
1028 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
1029
1030 /*
1031 * Delete common edac devices before edac mc, because
1032 * the former share the MMIO of the latter.
1033 */
1034 cpc925_del_edac_devices();
1035 cpc925_mc_exit(mci);
1036
1037 edac_mc_del_mc(&pdev->dev);
1038 edac_mc_free(mci);
1039
1040 return 0;
1041 }
1042
1043 static struct platform_driver cpc925_edac_driver = {
1044 .probe = cpc925_probe,
1045 .remove = cpc925_remove,
1046 .driver = {
1047 .name = "cpc925_edac",
1048 }
1049 };
1050
1051 static int __init cpc925_edac_init(void)
1052 {
1053 int ret = 0;
1054
1055 printk(KERN_INFO "IBM CPC925 EDAC driver " CPC925_EDAC_REVISION "\n");
1056 printk(KERN_INFO "\t(c) 2008 Wind River Systems, Inc\n");
1057
1058 /* Only support POLL mode so far */
1059 edac_op_state = EDAC_OPSTATE_POLL;
1060
1061 ret = platform_driver_register(&cpc925_edac_driver);
1062 if (ret) {
1063 printk(KERN_WARNING "Failed to register %s\n",
1064 CPC925_EDAC_MOD_STR);
1065 }
1066
1067 return ret;
1068 }
1069
1070 static void __exit cpc925_edac_exit(void)
1071 {
1072 platform_driver_unregister(&cpc925_edac_driver);
1073 }
1074
1075 module_init(cpc925_edac_init);
1076 module_exit(cpc925_edac_exit);
1077
1078 MODULE_LICENSE("GPL");
1079 MODULE_AUTHOR("Cao Qingtao <qingtao.cao@windriver.com>");
1080 MODULE_DESCRIPTION("IBM CPC925 Bridge and MC EDAC kernel module");