OMAPDSS: VENC: fix NULL pointer dereference in DSS2 VENC sysfs debug attr on OMAP4
[zen-stable.git] / drivers / gpu / drm / exynos / regs-mixer.h
blobfd2f4d14cf6d746473c5ea1863f1aeb476a8c0a4
1 /*
3 * Cloned from drivers/media/video/s5p-tv/regs-mixer.h
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com/
8 * Mixer register header file for Samsung Mixer driver
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 #ifndef SAMSUNG_REGS_MIXER_H
15 #define SAMSUNG_REGS_MIXER_H
18 * Register part
20 #define MXR_STATUS 0x0000
21 #define MXR_CFG 0x0004
22 #define MXR_INT_EN 0x0008
23 #define MXR_INT_STATUS 0x000C
24 #define MXR_LAYER_CFG 0x0010
25 #define MXR_VIDEO_CFG 0x0014
26 #define MXR_GRAPHIC0_CFG 0x0020
27 #define MXR_GRAPHIC0_BASE 0x0024
28 #define MXR_GRAPHIC0_SPAN 0x0028
29 #define MXR_GRAPHIC0_SXY 0x002C
30 #define MXR_GRAPHIC0_WH 0x0030
31 #define MXR_GRAPHIC0_DXY 0x0034
32 #define MXR_GRAPHIC0_BLANK 0x0038
33 #define MXR_GRAPHIC1_CFG 0x0040
34 #define MXR_GRAPHIC1_BASE 0x0044
35 #define MXR_GRAPHIC1_SPAN 0x0048
36 #define MXR_GRAPHIC1_SXY 0x004C
37 #define MXR_GRAPHIC1_WH 0x0050
38 #define MXR_GRAPHIC1_DXY 0x0054
39 #define MXR_GRAPHIC1_BLANK 0x0058
40 #define MXR_BG_CFG 0x0060
41 #define MXR_BG_COLOR0 0x0064
42 #define MXR_BG_COLOR1 0x0068
43 #define MXR_BG_COLOR2 0x006C
44 #define MXR_CM_COEFF_Y 0x0080
45 #define MXR_CM_COEFF_CB 0x0084
46 #define MXR_CM_COEFF_CR 0x0088
47 #define MXR_GRAPHIC0_BASE_S 0x2024
48 #define MXR_GRAPHIC1_BASE_S 0x2044
50 /* for parametrized access to layer registers */
51 #define MXR_GRAPHIC_CFG(i) (0x0020 + (i) * 0x20)
52 #define MXR_GRAPHIC_BASE(i) (0x0024 + (i) * 0x20)
53 #define MXR_GRAPHIC_SPAN(i) (0x0028 + (i) * 0x20)
54 #define MXR_GRAPHIC_SXY(i) (0x002C + (i) * 0x20)
55 #define MXR_GRAPHIC_WH(i) (0x0030 + (i) * 0x20)
56 #define MXR_GRAPHIC_DXY(i) (0x0034 + (i) * 0x20)
57 #define MXR_GRAPHIC_BLANK(i) (0x0038 + (i) * 0x20)
58 #define MXR_GRAPHIC_BASE_S(i) (0x2024 + (i) * 0x20)
61 * Bit definition part
64 /* generates mask for range of bits */
65 #define MXR_MASK(high_bit, low_bit) \
66 (((2 << ((high_bit) - (low_bit))) - 1) << (low_bit))
68 #define MXR_MASK_VAL(val, high_bit, low_bit) \
69 (((val) << (low_bit)) & MXR_MASK(high_bit, low_bit))
71 /* bits for MXR_STATUS */
72 #define MXR_STATUS_16_BURST (1 << 7)
73 #define MXR_STATUS_BURST_MASK (1 << 7)
74 #define MXR_STATUS_BIG_ENDIAN (1 << 3)
75 #define MXR_STATUS_ENDIAN_MASK (1 << 3)
76 #define MXR_STATUS_SYNC_ENABLE (1 << 2)
77 #define MXR_STATUS_REG_RUN (1 << 0)
79 /* bits for MXR_CFG */
80 #define MXR_CFG_RGB601_0_255 (0 << 9)
81 #define MXR_CFG_RGB601_16_235 (1 << 9)
82 #define MXR_CFG_RGB709_0_255 (2 << 9)
83 #define MXR_CFG_RGB709_16_235 (3 << 9)
84 #define MXR_CFG_RGB_FMT_MASK 0x600
85 #define MXR_CFG_OUT_YUV444 (0 << 8)
86 #define MXR_CFG_OUT_RGB888 (1 << 8)
87 #define MXR_CFG_OUT_MASK (1 << 8)
88 #define MXR_CFG_DST_SDO (0 << 7)
89 #define MXR_CFG_DST_HDMI (1 << 7)
90 #define MXR_CFG_DST_MASK (1 << 7)
91 #define MXR_CFG_SCAN_HD_720 (0 << 6)
92 #define MXR_CFG_SCAN_HD_1080 (1 << 6)
93 #define MXR_CFG_GRP1_ENABLE (1 << 5)
94 #define MXR_CFG_GRP0_ENABLE (1 << 4)
95 #define MXR_CFG_VP_ENABLE (1 << 3)
96 #define MXR_CFG_SCAN_INTERLACE (0 << 2)
97 #define MXR_CFG_SCAN_PROGRASSIVE (1 << 2)
98 #define MXR_CFG_SCAN_NTSC (0 << 1)
99 #define MXR_CFG_SCAN_PAL (1 << 1)
100 #define MXR_CFG_SCAN_SD (0 << 0)
101 #define MXR_CFG_SCAN_HD (1 << 0)
102 #define MXR_CFG_SCAN_MASK 0x47
104 /* bits for MXR_GRAPHICn_CFG */
105 #define MXR_GRP_CFG_COLOR_KEY_DISABLE (1 << 21)
106 #define MXR_GRP_CFG_BLEND_PRE_MUL (1 << 20)
107 #define MXR_GRP_CFG_WIN_BLEND_EN (1 << 17)
108 #define MXR_GRP_CFG_PIXEL_BLEND_EN (1 << 16)
109 #define MXR_GRP_CFG_FORMAT_VAL(x) MXR_MASK_VAL(x, 11, 8)
110 #define MXR_GRP_CFG_FORMAT_MASK MXR_GRP_CFG_FORMAT_VAL(~0)
111 #define MXR_GRP_CFG_ALPHA_VAL(x) MXR_MASK_VAL(x, 7, 0)
113 /* bits for MXR_GRAPHICn_WH */
114 #define MXR_GRP_WH_H_SCALE(x) MXR_MASK_VAL(x, 28, 28)
115 #define MXR_GRP_WH_V_SCALE(x) MXR_MASK_VAL(x, 12, 12)
116 #define MXR_GRP_WH_WIDTH(x) MXR_MASK_VAL(x, 26, 16)
117 #define MXR_GRP_WH_HEIGHT(x) MXR_MASK_VAL(x, 10, 0)
119 /* bits for MXR_GRAPHICn_SXY */
120 #define MXR_GRP_SXY_SX(x) MXR_MASK_VAL(x, 26, 16)
121 #define MXR_GRP_SXY_SY(x) MXR_MASK_VAL(x, 10, 0)
123 /* bits for MXR_GRAPHICn_DXY */
124 #define MXR_GRP_DXY_DX(x) MXR_MASK_VAL(x, 26, 16)
125 #define MXR_GRP_DXY_DY(x) MXR_MASK_VAL(x, 10, 0)
127 /* bits for MXR_INT_EN */
128 #define MXR_INT_EN_VSYNC (1 << 11)
129 #define MXR_INT_EN_ALL (0x0f << 8)
131 /* bit for MXR_INT_STATUS */
132 #define MXR_INT_CLEAR_VSYNC (1 << 11)
133 #define MXR_INT_STATUS_VSYNC (1 << 0)
135 /* bit for MXR_LAYER_CFG */
136 #define MXR_LAYER_CFG_GRP1_VAL(x) MXR_MASK_VAL(x, 11, 8)
137 #define MXR_LAYER_CFG_GRP0_VAL(x) MXR_MASK_VAL(x, 7, 4)
138 #define MXR_LAYER_CFG_VP_VAL(x) MXR_MASK_VAL(x, 3, 0)
140 #endif /* SAMSUNG_REGS_MIXER_H */