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OMAPDSS: VENC: fix NULL pointer dereference in DSS2 VENC sysfs debug attr on OMAP4
[zen-stable.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
blobb827098289311bf94012f66b91d1d17c2159f333
1 /*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
27
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
34
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
38
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
41
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
47
48 struct nouveau_fpriv {
49 spinlock_t lock;
50 struct list_head channels;
51 struct nouveau_vm *vm;
52 };
53
54 static inline struct nouveau_fpriv *
55 nouveau_fpriv(struct drm_file *file_priv)
56 {
57 return file_priv ? file_priv->driver_priv : NULL;
58 }
59
60 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
61
62 #include "nouveau_drm.h"
63 #include "nouveau_reg.h"
64 #include "nouveau_bios.h"
65 #include "nouveau_util.h"
66
67 struct nouveau_grctx;
68 struct nouveau_mem;
69 #include "nouveau_vm.h"
70
71 #define MAX_NUM_DCB_ENTRIES 16
72
73 #define NOUVEAU_MAX_CHANNEL_NR 128
74 #define NOUVEAU_MAX_TILE_NR 15
75
76 struct nouveau_mem {
77 struct drm_device *dev;
78
79 struct nouveau_vma bar_vma;
80 struct nouveau_vma vma[2];
81 u8 page_shift;
82
83 struct drm_mm_node *tag;
84 struct list_head regions;
85 dma_addr_t *pages;
86 u32 memtype;
87 u64 offset;
88 u64 size;
89 };
90
91 struct nouveau_tile_reg {
92 bool used;
93 uint32_t addr;
94 uint32_t limit;
95 uint32_t pitch;
96 uint32_t zcomp;
97 struct drm_mm_node *tag_mem;
98 struct nouveau_fence *fence;
99 };
100
101 struct nouveau_bo {
102 struct ttm_buffer_object bo;
103 struct ttm_placement placement;
104 u32 valid_domains;
105 u32 placements[3];
106 u32 busy_placements[3];
107 struct ttm_bo_kmap_obj kmap;
108 struct list_head head;
109
110 /* protected by ttm_bo_reserve() */
111 struct drm_file *reserved_by;
112 struct list_head entry;
113 int pbbo_index;
114 bool validate_mapped;
115
116 struct nouveau_channel *channel;
117
118 struct list_head vma_list;
119 unsigned page_shift;
120
121 uint32_t tile_mode;
122 uint32_t tile_flags;
123 struct nouveau_tile_reg *tile;
124
125 struct drm_gem_object *gem;
126 int pin_refcnt;
127 };
128
129 #define nouveau_bo_tile_layout(nvbo) \
130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
131
132 static inline struct nouveau_bo *
133 nouveau_bo(struct ttm_buffer_object *bo)
134 {
135 return container_of(bo, struct nouveau_bo, bo);
136 }
137
138 static inline struct nouveau_bo *
139 nouveau_gem_object(struct drm_gem_object *gem)
140 {
141 return gem ? gem->driver_private : NULL;
142 }
143
144 /* TODO: submit equivalent to TTM generic API upstream? */
145 static inline void __iomem *
146 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
147 {
148 bool is_iomem;
149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
150 &nvbo->kmap, &is_iomem);
151 WARN_ON_ONCE(ioptr && !is_iomem);
152 return ioptr;
153 }
154
155 enum nouveau_flags {
156 NV_NFORCE = 0x10000000,
157 NV_NFORCE2 = 0x20000000
158 };
159
160 #define NVOBJ_ENGINE_SW 0
161 #define NVOBJ_ENGINE_GR 1
162 #define NVOBJ_ENGINE_CRYPT 2
163 #define NVOBJ_ENGINE_COPY0 3
164 #define NVOBJ_ENGINE_COPY1 4
165 #define NVOBJ_ENGINE_MPEG 5
166 #define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG
167 #define NVOBJ_ENGINE_BSP 6
168 #define NVOBJ_ENGINE_VP 7
169 #define NVOBJ_ENGINE_DISPLAY 15
170 #define NVOBJ_ENGINE_NR 16
171
172 #define NVOBJ_FLAG_DONT_MAP (1 << 0)
173 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
174 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
175 #define NVOBJ_FLAG_VM (1 << 3)
176 #define NVOBJ_FLAG_VM_USER (1 << 4)
177
178 #define NVOBJ_CINST_GLOBAL 0xdeadbeef
179
180 struct nouveau_gpuobj {
181 struct drm_device *dev;
182 struct kref refcount;
183 struct list_head list;
184
185 void *node;
186 u32 *suspend;
187
188 uint32_t flags;
189
190 u32 size;
191 u32 pinst; /* PRAMIN BAR offset */
192 u32 cinst; /* Channel offset */
193 u64 vinst; /* VRAM address */
194 u64 linst; /* VM address */
195
196 uint32_t engine;
197 uint32_t class;
198
199 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
200 void *priv;
201 };
202
203 struct nouveau_page_flip_state {
204 struct list_head head;
205 struct drm_pending_vblank_event *event;
206 int crtc, bpp, pitch, x, y;
207 uint64_t offset;
208 };
209
210 enum nouveau_channel_mutex_class {
211 NOUVEAU_UCHANNEL_MUTEX,
212 NOUVEAU_KCHANNEL_MUTEX
213 };
214
215 struct nouveau_channel {
216 struct drm_device *dev;
217 struct list_head list;
218 int id;
219
220 /* references to the channel data structure */
221 struct kref ref;
222 /* users of the hardware channel resources, the hardware
223 * context will be kicked off when it reaches zero. */
224 atomic_t users;
225 struct mutex mutex;
226
227 /* owner of this fifo */
228 struct drm_file *file_priv;
229 /* mapping of the fifo itself */
230 struct drm_local_map *map;
231
232 /* mapping of the regs controlling the fifo */
233 void __iomem *user;
234 uint32_t user_get;
235 uint32_t user_get_hi;
236 uint32_t user_put;
237
238 /* Fencing */
239 struct {
240 /* lock protects the pending list only */
241 spinlock_t lock;
242 struct list_head pending;
243 uint32_t sequence;
244 uint32_t sequence_ack;
245 atomic_t last_sequence_irq;
246 struct nouveau_vma vma;
247 } fence;
248
249 /* DMA push buffer */
250 struct nouveau_gpuobj *pushbuf;
251 struct nouveau_bo *pushbuf_bo;
252 struct nouveau_vma pushbuf_vma;
253 uint64_t pushbuf_base;
254
255 /* Notifier memory */
256 struct nouveau_bo *notifier_bo;
257 struct nouveau_vma notifier_vma;
258 struct drm_mm notifier_heap;
259
260 /* PFIFO context */
261 struct nouveau_gpuobj *ramfc;
262 struct nouveau_gpuobj *cache;
263 void *fifo_priv;
264
265 /* Execution engine contexts */
266 void *engctx[NVOBJ_ENGINE_NR];
267
268 /* NV50 VM */
269 struct nouveau_vm *vm;
270 struct nouveau_gpuobj *vm_pd;
271
272 /* Objects */
273 struct nouveau_gpuobj *ramin; /* Private instmem */
274 struct drm_mm ramin_heap; /* Private PRAMIN heap */
275 struct nouveau_ramht *ramht; /* Hash table */
276
277 /* GPU object info for stuff used in-kernel (mm_enabled) */
278 uint32_t m2mf_ntfy;
279 uint32_t vram_handle;
280 uint32_t gart_handle;
281 bool accel_done;
282
283 /* Push buffer state (only for drm's channel on !mm_enabled) */
284 struct {
285 int max;
286 int free;
287 int cur;
288 int put;
289 /* access via pushbuf_bo */
290
291 int ib_base;
292 int ib_max;
293 int ib_free;
294 int ib_put;
295 } dma;
296
297 uint32_t sw_subchannel[8];
298
299 struct nouveau_vma dispc_vma[2];
300 struct {
301 struct nouveau_gpuobj *vblsem;
302 uint32_t vblsem_head;
303 uint32_t vblsem_offset;
304 uint32_t vblsem_rval;
305 struct list_head vbl_wait;
306 struct list_head flip;
307 } nvsw;
308
309 struct {
310 bool active;
311 char name[32];
312 struct drm_info_list info;
313 } debugfs;
314 };
315
316 struct nouveau_exec_engine {
317 void (*destroy)(struct drm_device *, int engine);
318 int (*init)(struct drm_device *, int engine);
319 int (*fini)(struct drm_device *, int engine, bool suspend);
320 int (*context_new)(struct nouveau_channel *, int engine);
321 void (*context_del)(struct nouveau_channel *, int engine);
322 int (*object_new)(struct nouveau_channel *, int engine,
323 u32 handle, u16 class);
324 void (*set_tile_region)(struct drm_device *dev, int i);
325 void (*tlb_flush)(struct drm_device *, int engine);
326 };
327
328 struct nouveau_instmem_engine {
329 void *priv;
330
331 int (*init)(struct drm_device *dev);
332 void (*takedown)(struct drm_device *dev);
333 int (*suspend)(struct drm_device *dev);
334 void (*resume)(struct drm_device *dev);
335
336 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *,
337 u32 size, u32 align);
338 void (*put)(struct nouveau_gpuobj *);
339 int (*map)(struct nouveau_gpuobj *);
340 void (*unmap)(struct nouveau_gpuobj *);
341
342 void (*flush)(struct drm_device *);
343 };
344
345 struct nouveau_mc_engine {
346 int (*init)(struct drm_device *dev);
347 void (*takedown)(struct drm_device *dev);
348 };
349
350 struct nouveau_timer_engine {
351 int (*init)(struct drm_device *dev);
352 void (*takedown)(struct drm_device *dev);
353 uint64_t (*read)(struct drm_device *dev);
354 };
355
356 struct nouveau_fb_engine {
357 int num_tiles;
358 struct drm_mm tag_heap;
359 void *priv;
360
361 int (*init)(struct drm_device *dev);
362 void (*takedown)(struct drm_device *dev);
363
364 void (*init_tile_region)(struct drm_device *dev, int i,
365 uint32_t addr, uint32_t size,
366 uint32_t pitch, uint32_t flags);
367 void (*set_tile_region)(struct drm_device *dev, int i);
368 void (*free_tile_region)(struct drm_device *dev, int i);
369 };
370
371 struct nouveau_fifo_engine {
372 void *priv;
373 int channels;
374
375 struct nouveau_gpuobj *playlist[2];
376 int cur_playlist;
377
378 int (*init)(struct drm_device *);
379 void (*takedown)(struct drm_device *);
380
381 void (*disable)(struct drm_device *);
382 void (*enable)(struct drm_device *);
383 bool (*reassign)(struct drm_device *, bool enable);
384 bool (*cache_pull)(struct drm_device *dev, bool enable);
385
386 int (*channel_id)(struct drm_device *);
387
388 int (*create_context)(struct nouveau_channel *);
389 void (*destroy_context)(struct nouveau_channel *);
390 int (*load_context)(struct nouveau_channel *);
391 int (*unload_context)(struct drm_device *);
392 void (*tlb_flush)(struct drm_device *dev);
393 };
394
395 struct nouveau_display_engine {
396 void *priv;
397 int (*early_init)(struct drm_device *);
398 void (*late_takedown)(struct drm_device *);
399 int (*create)(struct drm_device *);
400 void (*destroy)(struct drm_device *);
401 int (*init)(struct drm_device *);
402 void (*fini)(struct drm_device *);
403
404 struct drm_property *dithering_mode;
405 struct drm_property *dithering_depth;
406 struct drm_property *underscan_property;
407 struct drm_property *underscan_hborder_property;
408 struct drm_property *underscan_vborder_property;
409 };
410
411 struct nouveau_gpio_engine {
412 spinlock_t lock;
413 struct list_head isr;
414 int (*init)(struct drm_device *);
415 void (*fini)(struct drm_device *);
416 int (*drive)(struct drm_device *, int line, int dir, int out);
417 int (*sense)(struct drm_device *, int line);
418 void (*irq_enable)(struct drm_device *, int line, bool);
419 };
420
421 struct nouveau_pm_voltage_level {
422 u32 voltage; /* microvolts */
423 u8 vid;
424 };
425
426 struct nouveau_pm_voltage {
427 bool supported;
428 u8 version;
429 u8 vid_mask;
430
431 struct nouveau_pm_voltage_level *level;
432 int nr_level;
433 };
434
435 struct nouveau_pm_memtiming {
436 int id;
437 u32 reg_0; /* 0x10f290 on Fermi, 0x100220 for older */
438 u32 reg_1;
439 u32 reg_2;
440 u32 reg_3;
441 u32 reg_4;
442 u32 reg_5;
443 u32 reg_6;
444 u32 reg_7;
445 u32 reg_8;
446 /* To be written to 0x1002c0 */
447 u8 CL;
448 u8 WR;
449 };
450
451 struct nouveau_pm_tbl_header{
452 u8 version;
453 u8 header_len;
454 u8 entry_cnt;
455 u8 entry_len;
456 };
457
458 struct nouveau_pm_tbl_entry{
459 u8 tWR;
460 u8 tUNK_1;
461 u8 tCL;
462 u8 tRP; /* Byte 3 */
463 u8 empty_4;
464 u8 tRAS; /* Byte 5 */
465 u8 empty_6;
466 u8 tRFC; /* Byte 7 */
467 u8 empty_8;
468 u8 tRC; /* Byte 9 */
469 u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14;
470 u8 empty_15,empty_16,empty_17;
471 u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21;
472 };
473
474 /* nouveau_mem.c */
475 void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr,
476 struct nouveau_pm_tbl_entry *e, uint8_t magic_number,
477 struct nouveau_pm_memtiming *timing);
478
479 #define NOUVEAU_PM_MAX_LEVEL 8
480 struct nouveau_pm_level {
481 struct device_attribute dev_attr;
482 char name[32];
483 int id;
484
485 u32 core;
486 u32 memory;
487 u32 shader;
488 u32 rop;
489 u32 copy;
490 u32 daemon;
491 u32 vdec;
492 u32 dom6;
493 u32 unka0; /* nva3:nvc0 */
494 u32 hub01; /* nvc0- */
495 u32 hub06; /* nvc0- */
496 u32 hub07; /* nvc0- */
497
498 u32 volt_min; /* microvolts */
499 u32 volt_max;
500 u8 fanspeed;
501
502 u16 memscript;
503 struct nouveau_pm_memtiming *timing;
504 };
505
506 struct nouveau_pm_temp_sensor_constants {
507 u16 offset_constant;
508 s16 offset_mult;
509 s16 offset_div;
510 s16 slope_mult;
511 s16 slope_div;
512 };
513
514 struct nouveau_pm_threshold_temp {
515 s16 critical;
516 s16 down_clock;
517 s16 fan_boost;
518 };
519
520 struct nouveau_pm_memtimings {
521 bool supported;
522 struct nouveau_pm_memtiming *timing;
523 int nr_timing;
524 };
525
526 struct nouveau_pm_fan {
527 u32 min_duty;
528 u32 max_duty;
529 u32 pwm_freq;
530 };
531
532 struct nouveau_pm_engine {
533 struct nouveau_pm_voltage voltage;
534 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
535 int nr_perflvl;
536 struct nouveau_pm_memtimings memtimings;
537 struct nouveau_pm_temp_sensor_constants sensor_constants;
538 struct nouveau_pm_threshold_temp threshold_temp;
539 struct nouveau_pm_fan fan;
540 u32 pwm_divisor;
541
542 struct nouveau_pm_level boot;
543 struct nouveau_pm_level *cur;
544
545 struct device *hwmon;
546 struct notifier_block acpi_nb;
547
548 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *);
549 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *);
550 int (*clocks_set)(struct drm_device *, void *);
551
552 int (*voltage_get)(struct drm_device *);
553 int (*voltage_set)(struct drm_device *, int voltage);
554 int (*pwm_get)(struct drm_device *, int line, u32*, u32*);
555 int (*pwm_set)(struct drm_device *, int line, u32, u32);
556 int (*temp_get)(struct drm_device *);
557 };
558
559 struct nouveau_vram_engine {
560 struct nouveau_mm mm;
561
562 int (*init)(struct drm_device *);
563 void (*takedown)(struct drm_device *dev);
564 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc,
565 u32 type, struct nouveau_mem **);
566 void (*put)(struct drm_device *, struct nouveau_mem **);
567
568 bool (*flags_valid)(struct drm_device *, u32 tile_flags);
569 };
570
571 struct nouveau_engine {
572 struct nouveau_instmem_engine instmem;
573 struct nouveau_mc_engine mc;
574 struct nouveau_timer_engine timer;
575 struct nouveau_fb_engine fb;
576 struct nouveau_fifo_engine fifo;
577 struct nouveau_display_engine display;
578 struct nouveau_gpio_engine gpio;
579 struct nouveau_pm_engine pm;
580 struct nouveau_vram_engine vram;
581 };
582
583 struct nouveau_pll_vals {
584 union {
585 struct {
586 #ifdef __BIG_ENDIAN
587 uint8_t N1, M1, N2, M2;
588 #else
589 uint8_t M1, N1, M2, N2;
590 #endif
591 };
592 struct {
593 uint16_t NM1, NM2;
594 } __attribute__((packed));
595 };
596 int log2P;
597
598 int refclk;
599 };
600
601 enum nv04_fp_display_regs {
602 FP_DISPLAY_END,
603 FP_TOTAL,
604 FP_CRTC,
605 FP_SYNC_START,
606 FP_SYNC_END,
607 FP_VALID_START,
608 FP_VALID_END
609 };
610
611 struct nv04_crtc_reg {
612 unsigned char MiscOutReg;
613 uint8_t CRTC[0xa0];
614 uint8_t CR58[0x10];
615 uint8_t Sequencer[5];
616 uint8_t Graphics[9];
617 uint8_t Attribute[21];
618 unsigned char DAC[768];
619
620 /* PCRTC regs */
621 uint32_t fb_start;
622 uint32_t crtc_cfg;
623 uint32_t cursor_cfg;
624 uint32_t gpio_ext;
625 uint32_t crtc_830;
626 uint32_t crtc_834;
627 uint32_t crtc_850;
628 uint32_t crtc_eng_ctrl;
629
630 /* PRAMDAC regs */
631 uint32_t nv10_cursync;
632 struct nouveau_pll_vals pllvals;
633 uint32_t ramdac_gen_ctrl;
634 uint32_t ramdac_630;
635 uint32_t ramdac_634;
636 uint32_t tv_setup;
637 uint32_t tv_vtotal;
638 uint32_t tv_vskew;
639 uint32_t tv_vsync_delay;
640 uint32_t tv_htotal;
641 uint32_t tv_hskew;
642 uint32_t tv_hsync_delay;
643 uint32_t tv_hsync_delay2;
644 uint32_t fp_horiz_regs[7];
645 uint32_t fp_vert_regs[7];
646 uint32_t dither;
647 uint32_t fp_control;
648 uint32_t dither_regs[6];
649 uint32_t fp_debug_0;
650 uint32_t fp_debug_1;
651 uint32_t fp_debug_2;
652 uint32_t fp_margin_color;
653 uint32_t ramdac_8c0;
654 uint32_t ramdac_a20;
655 uint32_t ramdac_a24;
656 uint32_t ramdac_a34;
657 uint32_t ctv_regs[38];
658 };
659
660 struct nv04_output_reg {
661 uint32_t output;
662 int head;
663 };
664
665 struct nv04_mode_state {
666 struct nv04_crtc_reg crtc_reg[2];
667 uint32_t pllsel;
668 uint32_t sel_clk;
669 };
670
671 enum nouveau_card_type {
672 NV_04 = 0x00,
673 NV_10 = 0x10,
674 NV_20 = 0x20,
675 NV_30 = 0x30,
676 NV_40 = 0x40,
677 NV_50 = 0x50,
678 NV_C0 = 0xc0,
679 NV_D0 = 0xd0
680 };
681
682 struct drm_nouveau_private {
683 struct drm_device *dev;
684 bool noaccel;
685
686 /* the card type, takes NV_* as values */
687 enum nouveau_card_type card_type;
688 /* exact chipset, derived from NV_PMC_BOOT_0 */
689 int chipset;
690 int flags;
691 u32 crystal;
692
693 void __iomem *mmio;
694
695 spinlock_t ramin_lock;
696 void __iomem *ramin;
697 u32 ramin_size;
698 u32 ramin_base;
699 bool ramin_available;
700 struct drm_mm ramin_heap;
701 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR];
702 struct list_head gpuobj_list;
703 struct list_head classes;
704
705 struct nouveau_bo *vga_ram;
706
707 /* interrupt handling */
708 void (*irq_handler[32])(struct drm_device *);
709 bool msi_enabled;
710
711 struct list_head vbl_waiting;
712
713 struct {
714 struct drm_global_reference mem_global_ref;
715 struct ttm_bo_global_ref bo_global_ref;
716 struct ttm_bo_device bdev;
717 atomic_t validate_sequence;
718 } ttm;
719
720 struct {
721 spinlock_t lock;
722 struct drm_mm heap;
723 struct nouveau_bo *bo;
724 } fence;
725
726 struct {
727 spinlock_t lock;
728 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
729 } channels;
730
731 struct nouveau_engine engine;
732 struct nouveau_channel *channel;
733
734 /* For PFIFO and PGRAPH. */
735 spinlock_t context_switch_lock;
736
737 /* VM/PRAMIN flush, legacy PRAMIN aperture */
738 spinlock_t vm_lock;
739
740 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
741 struct nouveau_ramht *ramht;
742 struct nouveau_gpuobj *ramfc;
743 struct nouveau_gpuobj *ramro;
744
745 uint32_t ramin_rsvd_vram;
746
747 struct {
748 enum {
749 NOUVEAU_GART_NONE = 0,
750 NOUVEAU_GART_AGP, /* AGP */
751 NOUVEAU_GART_PDMA, /* paged dma object */
752 NOUVEAU_GART_HW /* on-chip gart/vm */
753 } type;
754 uint64_t aper_base;
755 uint64_t aper_size;
756 uint64_t aper_free;
757
758 struct ttm_backend_func *func;
759
760 struct {
761 struct page *page;
762 dma_addr_t addr;
763 } dummy;
764
765 struct nouveau_gpuobj *sg_ctxdma;
766 } gart_info;
767
768 /* nv10-nv40 tiling regions */
769 struct {
770 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
771 spinlock_t lock;
772 } tile;
773
774 /* VRAM/fb configuration */
775 uint64_t vram_size;
776 uint64_t vram_sys_base;
777
778 uint64_t fb_available_size;
779 uint64_t fb_mappable_pages;
780 uint64_t fb_aper_free;
781 int fb_mtrr;
782
783 /* BAR control (NV50-) */
784 struct nouveau_vm *bar1_vm;
785 struct nouveau_vm *bar3_vm;
786
787 /* G8x/G9x virtual address space */
788 struct nouveau_vm *chan_vm;
789
790 struct nvbios vbios;
791 u8 *mxms;
792 struct list_head i2c_ports;
793
794 struct nv04_mode_state mode_reg;
795 struct nv04_mode_state saved_reg;
796 uint32_t saved_vga_font[4][16384];
797 uint32_t crtc_owner;
798 uint32_t dac_users[4];
799
800 struct backlight_device *backlight;
801
802 struct {
803 struct dentry *channel_root;
804 } debugfs;
805
806 struct nouveau_fbdev *nfbdev;
807 struct apertures_struct *apertures;
808 };
809
810 static inline struct drm_nouveau_private *
811 nouveau_private(struct drm_device *dev)
812 {
813 return dev->dev_private;
814 }
815
816 static inline struct drm_nouveau_private *
817 nouveau_bdev(struct ttm_bo_device *bd)
818 {
819 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
820 }
821
822 static inline int
823 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
824 {
825 struct nouveau_bo *prev;
826
827 if (!pnvbo)
828 return -EINVAL;
829 prev = *pnvbo;
830
831 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
832 if (prev) {
833 struct ttm_buffer_object *bo = &prev->bo;
834
835 ttm_bo_unref(&bo);
836 }
837
838 return 0;
839 }
840
841 /* nouveau_drv.c */
842 extern int nouveau_modeset;
843 extern int nouveau_agpmode;
844 extern int nouveau_duallink;
845 extern int nouveau_uscript_lvds;
846 extern int nouveau_uscript_tmds;
847 extern int nouveau_vram_pushbuf;
848 extern int nouveau_vram_notify;
849 extern int nouveau_fbpercrtc;
850 extern int nouveau_tv_disable;
851 extern char *nouveau_tv_norm;
852 extern int nouveau_reg_debug;
853 extern char *nouveau_vbios;
854 extern int nouveau_ignorelid;
855 extern int nouveau_nofbaccel;
856 extern int nouveau_noaccel;
857 extern int nouveau_force_post;
858 extern int nouveau_override_conntype;
859 extern char *nouveau_perflvl;
860 extern int nouveau_perflvl_wr;
861 extern int nouveau_msi;
862 extern int nouveau_ctxfw;
863 extern int nouveau_mxmdcb;
864
865 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
866 extern int nouveau_pci_resume(struct pci_dev *pdev);
867
868 /* nouveau_state.c */
869 extern int nouveau_open(struct drm_device *, struct drm_file *);
870 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
871 extern void nouveau_postclose(struct drm_device *, struct drm_file *);
872 extern int nouveau_load(struct drm_device *, unsigned long flags);
873 extern int nouveau_firstopen(struct drm_device *);
874 extern void nouveau_lastclose(struct drm_device *);
875 extern int nouveau_unload(struct drm_device *);
876 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
877 struct drm_file *);
878 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
879 struct drm_file *);
880 extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout,
881 uint32_t reg, uint32_t mask, uint32_t val);
882 extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout,
883 uint32_t reg, uint32_t mask, uint32_t val);
884 extern bool nouveau_wait_cb(struct drm_device *, u64 timeout,
885 bool (*cond)(void *), void *);
886 extern bool nouveau_wait_for_idle(struct drm_device *);
887 extern int nouveau_card_init(struct drm_device *);
888
889 /* nouveau_mem.c */
890 extern int nouveau_mem_vram_init(struct drm_device *);
891 extern void nouveau_mem_vram_fini(struct drm_device *);
892 extern int nouveau_mem_gart_init(struct drm_device *);
893 extern void nouveau_mem_gart_fini(struct drm_device *);
894 extern int nouveau_mem_init_agp(struct drm_device *);
895 extern int nouveau_mem_reset_agp(struct drm_device *);
896 extern void nouveau_mem_close(struct drm_device *);
897 extern int nouveau_mem_detect(struct drm_device *);
898 extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags);
899 extern struct nouveau_tile_reg *nv10_mem_set_tiling(
900 struct drm_device *dev, uint32_t addr, uint32_t size,
901 uint32_t pitch, uint32_t flags);
902 extern void nv10_mem_put_tile_region(struct drm_device *dev,
903 struct nouveau_tile_reg *tile,
904 struct nouveau_fence *fence);
905 extern const struct ttm_mem_type_manager_func nouveau_vram_manager;
906 extern const struct ttm_mem_type_manager_func nouveau_gart_manager;
907
908 /* nouveau_notifier.c */
909 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
910 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
911 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
912 int cout, uint32_t start, uint32_t end,
913 uint32_t *offset);
914 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
915 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
916 struct drm_file *);
917 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
918 struct drm_file *);
919
920 /* nouveau_channel.c */
921 extern struct drm_ioctl_desc nouveau_ioctls[];
922 extern int nouveau_max_ioctl;
923 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
924 extern int nouveau_channel_alloc(struct drm_device *dev,
925 struct nouveau_channel **chan,
926 struct drm_file *file_priv,
927 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
928 extern struct nouveau_channel *
929 nouveau_channel_get_unlocked(struct nouveau_channel *);
930 extern struct nouveau_channel *
931 nouveau_channel_get(struct drm_file *, int id);
932 extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
933 extern void nouveau_channel_put(struct nouveau_channel **);
934 extern void nouveau_channel_ref(struct nouveau_channel *chan,
935 struct nouveau_channel **pchan);
936 extern void nouveau_channel_idle(struct nouveau_channel *chan);
937
938 /* nouveau_object.c */
939 #define NVOBJ_ENGINE_ADD(d, e, p) do { \
940 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
941 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \
942 } while (0)
943
944 #define NVOBJ_ENGINE_DEL(d, e) do { \
945 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
946 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \
947 } while (0)
948
949 #define NVOBJ_CLASS(d, c, e) do { \
950 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
951 if (ret) \
952 return ret; \
953 } while (0)
954
955 #define NVOBJ_MTHD(d, c, m, e) do { \
956 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
957 if (ret) \
958 return ret; \
959 } while (0)
960
961 extern int nouveau_gpuobj_early_init(struct drm_device *);
962 extern int nouveau_gpuobj_init(struct drm_device *);
963 extern void nouveau_gpuobj_takedown(struct drm_device *);
964 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
965 extern void nouveau_gpuobj_resume(struct drm_device *dev);
966 extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
967 extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
968 int (*exec)(struct nouveau_channel *,
969 u32 class, u32 mthd, u32 data));
970 extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
971 extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32);
972 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
973 uint32_t vram_h, uint32_t tt_h);
974 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
975 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
976 uint32_t size, int align, uint32_t flags,
977 struct nouveau_gpuobj **);
978 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
979 struct nouveau_gpuobj **);
980 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
981 u32 size, u32 flags,
982 struct nouveau_gpuobj **);
983 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
984 uint64_t offset, uint64_t size, int access,
985 int target, struct nouveau_gpuobj **);
986 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class);
987 extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base,
988 u64 size, int target, int access, u32 type,
989 u32 comp, struct nouveau_gpuobj **pobj);
990 extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset,
991 int class, u64 base, u64 size, int target,
992 int access, u32 type, u32 comp);
993 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
994 struct drm_file *);
995 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
996 struct drm_file *);
997
998 /* nouveau_irq.c */
999 extern int nouveau_irq_init(struct drm_device *);
1000 extern void nouveau_irq_fini(struct drm_device *);
1001 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
1002 extern void nouveau_irq_register(struct drm_device *, int status_bit,
1003 void (*)(struct drm_device *));
1004 extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
1005 extern void nouveau_irq_preinstall(struct drm_device *);
1006 extern int nouveau_irq_postinstall(struct drm_device *);
1007 extern void nouveau_irq_uninstall(struct drm_device *);
1008
1009 /* nouveau_sgdma.c */
1010 extern int nouveau_sgdma_init(struct drm_device *);
1011 extern void nouveau_sgdma_takedown(struct drm_device *);
1012 extern uint32_t nouveau_sgdma_get_physical(struct drm_device *,
1013 uint32_t offset);
1014 extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev,
1015 unsigned long size,
1016 uint32_t page_flags,
1017 struct page *dummy_read_page);
1018
1019 /* nouveau_debugfs.c */
1020 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
1021 extern int nouveau_debugfs_init(struct drm_minor *);
1022 extern void nouveau_debugfs_takedown(struct drm_minor *);
1023 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
1024 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
1025 #else
1026 static inline int
1027 nouveau_debugfs_init(struct drm_minor *minor)
1028 {
1029 return 0;
1030 }
1031
1032 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
1033 {
1034 }
1035
1036 static inline int
1037 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
1038 {
1039 return 0;
1040 }
1041
1042 static inline void
1043 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
1044 {
1045 }
1046 #endif
1047
1048 /* nouveau_dma.c */
1049 extern void nouveau_dma_pre_init(struct nouveau_channel *);
1050 extern int nouveau_dma_init(struct nouveau_channel *);
1051 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
1052
1053 /* nouveau_acpi.c */
1054 #define ROM_BIOS_PAGE 4096
1055 #if defined(CONFIG_ACPI)
1056 void nouveau_register_dsm_handler(void);
1057 void nouveau_unregister_dsm_handler(void);
1058 void nouveau_switcheroo_optimus_dsm(void);
1059 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
1060 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
1061 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
1062 #else
1063 static inline void nouveau_register_dsm_handler(void) {}
1064 static inline void nouveau_unregister_dsm_handler(void) {}
1065 static inline void nouveau_switcheroo_optimus_dsm(void) {}
1066 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
1067 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
1068 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
1069 #endif
1070
1071 /* nouveau_backlight.c */
1072 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1073 extern int nouveau_backlight_init(struct drm_device *);
1074 extern void nouveau_backlight_exit(struct drm_device *);
1075 #else
1076 static inline int nouveau_backlight_init(struct drm_device *dev)
1077 {
1078 return 0;
1079 }
1080
1081 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
1082 #endif
1083
1084 /* nouveau_bios.c */
1085 extern int nouveau_bios_init(struct drm_device *);
1086 extern void nouveau_bios_takedown(struct drm_device *dev);
1087 extern int nouveau_run_vbios_init(struct drm_device *);
1088 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
1089 struct dcb_entry *, int crtc);
1090 extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table);
1091 extern struct dcb_connector_table_entry *
1092 nouveau_bios_connector_entry(struct drm_device *, int index);
1093 extern u32 get_pll_register(struct drm_device *, enum pll_types);
1094 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
1095 struct pll_lims *);
1096 extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk,
1097 struct dcb_entry *, int crtc);
1098 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
1099 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
1100 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
1101 bool *dl, bool *if_is_24bit);
1102 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
1103 int head, int pxclk);
1104 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
1105 enum LVDS_script, int pxclk);
1106 bool bios_encoder_match(struct dcb_entry *, u32 hash);
1107
1108 /* nouveau_mxm.c */
1109 int nouveau_mxm_init(struct drm_device *dev);
1110 void nouveau_mxm_fini(struct drm_device *dev);
1111
1112 /* nouveau_ttm.c */
1113 int nouveau_ttm_global_init(struct drm_nouveau_private *);
1114 void nouveau_ttm_global_release(struct drm_nouveau_private *);
1115 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
1116
1117 /* nouveau_hdmi.c */
1118 void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *);
1119
1120 /* nouveau_dp.c */
1121 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
1122 uint8_t *data, int data_nr);
1123 bool nouveau_dp_detect(struct drm_encoder *);
1124 bool nouveau_dp_link_train(struct drm_encoder *, u32 datarate);
1125 void nouveau_dp_tu_update(struct drm_device *, int, int, u32, u32);
1126 u8 *nouveau_dp_bios_data(struct drm_device *, struct dcb_entry *, u8 **);
1127
1128 /* nv04_fb.c */
1129 extern int nv04_fb_init(struct drm_device *);
1130 extern void nv04_fb_takedown(struct drm_device *);
1131
1132 /* nv10_fb.c */
1133 extern int nv10_fb_init(struct drm_device *);
1134 extern void nv10_fb_takedown(struct drm_device *);
1135 extern void nv10_fb_init_tile_region(struct drm_device *dev, int i,
1136 uint32_t addr, uint32_t size,
1137 uint32_t pitch, uint32_t flags);
1138 extern void nv10_fb_set_tile_region(struct drm_device *dev, int i);
1139 extern void nv10_fb_free_tile_region(struct drm_device *dev, int i);
1140
1141 /* nv30_fb.c */
1142 extern int nv30_fb_init(struct drm_device *);
1143 extern void nv30_fb_takedown(struct drm_device *);
1144 extern void nv30_fb_init_tile_region(struct drm_device *dev, int i,
1145 uint32_t addr, uint32_t size,
1146 uint32_t pitch, uint32_t flags);
1147 extern void nv30_fb_free_tile_region(struct drm_device *dev, int i);
1148
1149 /* nv40_fb.c */
1150 extern int nv40_fb_init(struct drm_device *);
1151 extern void nv40_fb_takedown(struct drm_device *);
1152 extern void nv40_fb_set_tile_region(struct drm_device *dev, int i);
1153
1154 /* nv50_fb.c */
1155 extern int nv50_fb_init(struct drm_device *);
1156 extern void nv50_fb_takedown(struct drm_device *);
1157 extern void nv50_fb_vm_trap(struct drm_device *, int display);
1158
1159 /* nvc0_fb.c */
1160 extern int nvc0_fb_init(struct drm_device *);
1161 extern void nvc0_fb_takedown(struct drm_device *);
1162
1163 /* nv04_fifo.c */
1164 extern int nv04_fifo_init(struct drm_device *);
1165 extern void nv04_fifo_fini(struct drm_device *);
1166 extern void nv04_fifo_disable(struct drm_device *);
1167 extern void nv04_fifo_enable(struct drm_device *);
1168 extern bool nv04_fifo_reassign(struct drm_device *, bool);
1169 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
1170 extern int nv04_fifo_channel_id(struct drm_device *);
1171 extern int nv04_fifo_create_context(struct nouveau_channel *);
1172 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1173 extern int nv04_fifo_load_context(struct nouveau_channel *);
1174 extern int nv04_fifo_unload_context(struct drm_device *);
1175 extern void nv04_fifo_isr(struct drm_device *);
1176
1177 /* nv10_fifo.c */
1178 extern int nv10_fifo_init(struct drm_device *);
1179 extern int nv10_fifo_channel_id(struct drm_device *);
1180 extern int nv10_fifo_create_context(struct nouveau_channel *);
1181 extern int nv10_fifo_load_context(struct nouveau_channel *);
1182 extern int nv10_fifo_unload_context(struct drm_device *);
1183
1184 /* nv40_fifo.c */
1185 extern int nv40_fifo_init(struct drm_device *);
1186 extern int nv40_fifo_create_context(struct nouveau_channel *);
1187 extern int nv40_fifo_load_context(struct nouveau_channel *);
1188 extern int nv40_fifo_unload_context(struct drm_device *);
1189
1190 /* nv50_fifo.c */
1191 extern int nv50_fifo_init(struct drm_device *);
1192 extern void nv50_fifo_takedown(struct drm_device *);
1193 extern int nv50_fifo_channel_id(struct drm_device *);
1194 extern int nv50_fifo_create_context(struct nouveau_channel *);
1195 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1196 extern int nv50_fifo_load_context(struct nouveau_channel *);
1197 extern int nv50_fifo_unload_context(struct drm_device *);
1198 extern void nv50_fifo_tlb_flush(struct drm_device *dev);
1199
1200 /* nvc0_fifo.c */
1201 extern int nvc0_fifo_init(struct drm_device *);
1202 extern void nvc0_fifo_takedown(struct drm_device *);
1203 extern void nvc0_fifo_disable(struct drm_device *);
1204 extern void nvc0_fifo_enable(struct drm_device *);
1205 extern bool nvc0_fifo_reassign(struct drm_device *, bool);
1206 extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1207 extern int nvc0_fifo_channel_id(struct drm_device *);
1208 extern int nvc0_fifo_create_context(struct nouveau_channel *);
1209 extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1210 extern int nvc0_fifo_load_context(struct nouveau_channel *);
1211 extern int nvc0_fifo_unload_context(struct drm_device *);
1212
1213 /* nv04_graph.c */
1214 extern int nv04_graph_create(struct drm_device *);
1215 extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16);
1216 extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
1217 u32 class, u32 mthd, u32 data);
1218 extern struct nouveau_bitfield nv04_graph_nsource[];
1219
1220 /* nv10_graph.c */
1221 extern int nv10_graph_create(struct drm_device *);
1222 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1223 extern struct nouveau_bitfield nv10_graph_intr[];
1224 extern struct nouveau_bitfield nv10_graph_nstatus[];
1225
1226 /* nv20_graph.c */
1227 extern int nv20_graph_create(struct drm_device *);
1228
1229 /* nv40_graph.c */
1230 extern int nv40_graph_create(struct drm_device *);
1231 extern void nv40_grctx_init(struct nouveau_grctx *);
1232
1233 /* nv50_graph.c */
1234 extern int nv50_graph_create(struct drm_device *);
1235 extern int nv50_grctx_init(struct nouveau_grctx *);
1236 extern struct nouveau_enum nv50_data_error_names[];
1237 extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst);
1238
1239 /* nvc0_graph.c */
1240 extern int nvc0_graph_create(struct drm_device *);
1241 extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst);
1242
1243 /* nv84_crypt.c */
1244 extern int nv84_crypt_create(struct drm_device *);
1245
1246 /* nv98_crypt.c */
1247 extern int nv98_crypt_create(struct drm_device *dev);
1248
1249 /* nva3_copy.c */
1250 extern int nva3_copy_create(struct drm_device *dev);
1251
1252 /* nvc0_copy.c */
1253 extern int nvc0_copy_create(struct drm_device *dev, int engine);
1254
1255 /* nv31_mpeg.c */
1256 extern int nv31_mpeg_create(struct drm_device *dev);
1257
1258 /* nv50_mpeg.c */
1259 extern int nv50_mpeg_create(struct drm_device *dev);
1260
1261 /* nv84_bsp.c */
1262 /* nv98_bsp.c */
1263 extern int nv84_bsp_create(struct drm_device *dev);
1264
1265 /* nv84_vp.c */
1266 /* nv98_vp.c */
1267 extern int nv84_vp_create(struct drm_device *dev);
1268
1269 /* nv98_ppp.c */
1270 extern int nv98_ppp_create(struct drm_device *dev);
1271
1272 /* nv04_instmem.c */
1273 extern int nv04_instmem_init(struct drm_device *);
1274 extern void nv04_instmem_takedown(struct drm_device *);
1275 extern int nv04_instmem_suspend(struct drm_device *);
1276 extern void nv04_instmem_resume(struct drm_device *);
1277 extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *,
1278 u32 size, u32 align);
1279 extern void nv04_instmem_put(struct nouveau_gpuobj *);
1280 extern int nv04_instmem_map(struct nouveau_gpuobj *);
1281 extern void nv04_instmem_unmap(struct nouveau_gpuobj *);
1282 extern void nv04_instmem_flush(struct drm_device *);
1283
1284 /* nv50_instmem.c */
1285 extern int nv50_instmem_init(struct drm_device *);
1286 extern void nv50_instmem_takedown(struct drm_device *);
1287 extern int nv50_instmem_suspend(struct drm_device *);
1288 extern void nv50_instmem_resume(struct drm_device *);
1289 extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *,
1290 u32 size, u32 align);
1291 extern void nv50_instmem_put(struct nouveau_gpuobj *);
1292 extern int nv50_instmem_map(struct nouveau_gpuobj *);
1293 extern void nv50_instmem_unmap(struct nouveau_gpuobj *);
1294 extern void nv50_instmem_flush(struct drm_device *);
1295 extern void nv84_instmem_flush(struct drm_device *);
1296
1297 /* nvc0_instmem.c */
1298 extern int nvc0_instmem_init(struct drm_device *);
1299 extern void nvc0_instmem_takedown(struct drm_device *);
1300 extern int nvc0_instmem_suspend(struct drm_device *);
1301 extern void nvc0_instmem_resume(struct drm_device *);
1302
1303 /* nv04_mc.c */
1304 extern int nv04_mc_init(struct drm_device *);
1305 extern void nv04_mc_takedown(struct drm_device *);
1306
1307 /* nv40_mc.c */
1308 extern int nv40_mc_init(struct drm_device *);
1309 extern void nv40_mc_takedown(struct drm_device *);
1310
1311 /* nv50_mc.c */
1312 extern int nv50_mc_init(struct drm_device *);
1313 extern void nv50_mc_takedown(struct drm_device *);
1314
1315 /* nv04_timer.c */
1316 extern int nv04_timer_init(struct drm_device *);
1317 extern uint64_t nv04_timer_read(struct drm_device *);
1318 extern void nv04_timer_takedown(struct drm_device *);
1319
1320 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1321 unsigned long arg);
1322
1323 /* nv04_dac.c */
1324 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1325 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1326 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1327 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1328 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1329
1330 /* nv04_dfp.c */
1331 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1332 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1333 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1334 int head, bool dl);
1335 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1336 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1337
1338 /* nv04_tv.c */
1339 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1340 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1341
1342 /* nv17_tv.c */
1343 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1344
1345 /* nv04_display.c */
1346 extern int nv04_display_early_init(struct drm_device *);
1347 extern void nv04_display_late_takedown(struct drm_device *);
1348 extern int nv04_display_create(struct drm_device *);
1349 extern void nv04_display_destroy(struct drm_device *);
1350 extern int nv04_display_init(struct drm_device *);
1351 extern void nv04_display_fini(struct drm_device *);
1352
1353 /* nvd0_display.c */
1354 extern int nvd0_display_create(struct drm_device *);
1355 extern void nvd0_display_destroy(struct drm_device *);
1356 extern int nvd0_display_init(struct drm_device *);
1357 extern void nvd0_display_fini(struct drm_device *);
1358 struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int crtc);
1359 void nvd0_display_flip_stop(struct drm_crtc *);
1360 int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
1361 struct nouveau_channel *, u32 swap_interval);
1362
1363 /* nv04_crtc.c */
1364 extern int nv04_crtc_create(struct drm_device *, int index);
1365
1366 /* nouveau_bo.c */
1367 extern struct ttm_bo_driver nouveau_bo_driver;
1368 extern int nouveau_bo_new(struct drm_device *, int size, int align,
1369 uint32_t flags, uint32_t tile_mode,
1370 uint32_t tile_flags, struct nouveau_bo **);
1371 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1372 extern int nouveau_bo_unpin(struct nouveau_bo *);
1373 extern int nouveau_bo_map(struct nouveau_bo *);
1374 extern void nouveau_bo_unmap(struct nouveau_bo *);
1375 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1376 uint32_t busy);
1377 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1378 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1379 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1380 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1381 extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *);
1382 extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible,
1383 bool no_wait_reserve, bool no_wait_gpu);
1384
1385 extern struct nouveau_vma *
1386 nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *);
1387 extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *,
1388 struct nouveau_vma *);
1389 extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *);
1390
1391 /* nouveau_fence.c */
1392 struct nouveau_fence;
1393 extern int nouveau_fence_init(struct drm_device *);
1394 extern void nouveau_fence_fini(struct drm_device *);
1395 extern int nouveau_fence_channel_init(struct nouveau_channel *);
1396 extern void nouveau_fence_channel_fini(struct nouveau_channel *);
1397 extern void nouveau_fence_update(struct nouveau_channel *);
1398 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1399 bool emit);
1400 extern int nouveau_fence_emit(struct nouveau_fence *);
1401 extern void nouveau_fence_work(struct nouveau_fence *fence,
1402 void (*work)(void *priv, bool signalled),
1403 void *priv);
1404 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1405
1406 extern bool __nouveau_fence_signalled(void *obj, void *arg);
1407 extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1408 extern int __nouveau_fence_flush(void *obj, void *arg);
1409 extern void __nouveau_fence_unref(void **obj);
1410 extern void *__nouveau_fence_ref(void *obj);
1411
1412 static inline bool nouveau_fence_signalled(struct nouveau_fence *obj)
1413 {
1414 return __nouveau_fence_signalled(obj, NULL);
1415 }
1416 static inline int
1417 nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr)
1418 {
1419 return __nouveau_fence_wait(obj, NULL, lazy, intr);
1420 }
1421 extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
1422 static inline int nouveau_fence_flush(struct nouveau_fence *obj)
1423 {
1424 return __nouveau_fence_flush(obj, NULL);
1425 }
1426 static inline void nouveau_fence_unref(struct nouveau_fence **obj)
1427 {
1428 __nouveau_fence_unref((void **)obj);
1429 }
1430 static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj)
1431 {
1432 return __nouveau_fence_ref(obj);
1433 }
1434
1435 /* nouveau_gem.c */
1436 extern int nouveau_gem_new(struct drm_device *, int size, int align,
1437 uint32_t domain, uint32_t tile_mode,
1438 uint32_t tile_flags, struct nouveau_bo **);
1439 extern int nouveau_gem_object_new(struct drm_gem_object *);
1440 extern void nouveau_gem_object_del(struct drm_gem_object *);
1441 extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *);
1442 extern void nouveau_gem_object_close(struct drm_gem_object *,
1443 struct drm_file *);
1444 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1445 struct drm_file *);
1446 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1447 struct drm_file *);
1448 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1449 struct drm_file *);
1450 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1451 struct drm_file *);
1452 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1453 struct drm_file *);
1454
1455 /* nouveau_display.c */
1456 int nouveau_display_create(struct drm_device *dev);
1457 void nouveau_display_destroy(struct drm_device *dev);
1458 int nouveau_display_init(struct drm_device *dev);
1459 void nouveau_display_fini(struct drm_device *dev);
1460 int nouveau_vblank_enable(struct drm_device *dev, int crtc);
1461 void nouveau_vblank_disable(struct drm_device *dev, int crtc);
1462 int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1463 struct drm_pending_vblank_event *event);
1464 int nouveau_finish_page_flip(struct nouveau_channel *,
1465 struct nouveau_page_flip_state *);
1466 int nouveau_display_dumb_create(struct drm_file *, struct drm_device *,
1467 struct drm_mode_create_dumb *args);
1468 int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *,
1469 uint32_t handle, uint64_t *offset);
1470 int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *,
1471 uint32_t handle);
1472
1473 /* nv10_gpio.c */
1474 int nv10_gpio_init(struct drm_device *dev);
1475 void nv10_gpio_fini(struct drm_device *dev);
1476 int nv10_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1477 int nv10_gpio_sense(struct drm_device *dev, int line);
1478 void nv10_gpio_irq_enable(struct drm_device *, int line, bool on);
1479
1480 /* nv50_gpio.c */
1481 int nv50_gpio_init(struct drm_device *dev);
1482 void nv50_gpio_fini(struct drm_device *dev);
1483 int nv50_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1484 int nv50_gpio_sense(struct drm_device *dev, int line);
1485 void nv50_gpio_irq_enable(struct drm_device *, int line, bool on);
1486 int nvd0_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1487 int nvd0_gpio_sense(struct drm_device *dev, int line);
1488
1489 /* nv50_calc.c */
1490 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1491 int *N1, int *M1, int *N2, int *M2, int *P);
1492 int nva3_calc_pll(struct drm_device *, struct pll_lims *,
1493 int clk, int *N, int *fN, int *M, int *P);
1494
1495 #ifndef ioread32_native
1496 #ifdef __BIG_ENDIAN
1497 #define ioread16_native ioread16be
1498 #define iowrite16_native iowrite16be
1499 #define ioread32_native ioread32be
1500 #define iowrite32_native iowrite32be
1501 #else /* def __BIG_ENDIAN */
1502 #define ioread16_native ioread16
1503 #define iowrite16_native iowrite16
1504 #define ioread32_native ioread32
1505 #define iowrite32_native iowrite32
1506 #endif /* def __BIG_ENDIAN else */
1507 #endif /* !ioread32_native */
1508
1509 /* channel control reg access */
1510 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1511 {
1512 return ioread32_native(chan->user + reg);
1513 }
1514
1515 static inline void nvchan_wr32(struct nouveau_channel *chan,
1516 unsigned reg, u32 val)
1517 {
1518 iowrite32_native(val, chan->user + reg);
1519 }
1520
1521 /* register access */
1522 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1523 {
1524 struct drm_nouveau_private *dev_priv = dev->dev_private;
1525 return ioread32_native(dev_priv->mmio + reg);
1526 }
1527
1528 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1529 {
1530 struct drm_nouveau_private *dev_priv = dev->dev_private;
1531 iowrite32_native(val, dev_priv->mmio + reg);
1532 }
1533
1534 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1535 {
1536 u32 tmp = nv_rd32(dev, reg);
1537 nv_wr32(dev, reg, (tmp & ~mask) | val);
1538 return tmp;
1539 }
1540
1541 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1542 {
1543 struct drm_nouveau_private *dev_priv = dev->dev_private;
1544 return ioread8(dev_priv->mmio + reg);
1545 }
1546
1547 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1548 {
1549 struct drm_nouveau_private *dev_priv = dev->dev_private;
1550 iowrite8(val, dev_priv->mmio + reg);
1551 }
1552
1553 #define nv_wait(dev, reg, mask, val) \
1554 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val))
1555 #define nv_wait_ne(dev, reg, mask, val) \
1556 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val))
1557 #define nv_wait_cb(dev, func, data) \
1558 nouveau_wait_cb(dev, 2000000000ULL, (func), (data))
1559
1560 /* PRAMIN access */
1561 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1562 {
1563 struct drm_nouveau_private *dev_priv = dev->dev_private;
1564 return ioread32_native(dev_priv->ramin + offset);
1565 }
1566
1567 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1568 {
1569 struct drm_nouveau_private *dev_priv = dev->dev_private;
1570 iowrite32_native(val, dev_priv->ramin + offset);
1571 }
1572
1573 /* object access */
1574 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1575 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
1576
1577 /*
1578 * Logging
1579 * Argument d is (struct drm_device *).
1580 */
1581 #define NV_PRINTK(level, d, fmt, arg...) \
1582 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1583 pci_name(d->pdev), ##arg)
1584 #ifndef NV_DEBUG_NOTRACE
1585 #define NV_DEBUG(d, fmt, arg...) do { \
1586 if (drm_debug & DRM_UT_DRIVER) { \
1587 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1588 __LINE__, ##arg); \
1589 } \
1590 } while (0)
1591 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1592 if (drm_debug & DRM_UT_KMS) { \
1593 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1594 __LINE__, ##arg); \
1595 } \
1596 } while (0)
1597 #else
1598 #define NV_DEBUG(d, fmt, arg...) do { \
1599 if (drm_debug & DRM_UT_DRIVER) \
1600 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1601 } while (0)
1602 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1603 if (drm_debug & DRM_UT_KMS) \
1604 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1605 } while (0)
1606 #endif
1607 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1608 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1609 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1610 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1611 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1612 #define NV_WARNONCE(d, fmt, arg...) do { \
1613 static int _warned = 0; \
1614 if (!_warned) { \
1615 NV_WARN(d, fmt, ##arg); \
1616 _warned = 1; \
1617 } \
1618 } while(0)
1619
1620 /* nouveau_reg_debug bitmask */
1621 enum {
1622 NOUVEAU_REG_DEBUG_MC = 0x1,
1623 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1624 NOUVEAU_REG_DEBUG_FB = 0x4,
1625 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1626 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1627 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1628 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1629 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1630 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1631 NOUVEAU_REG_DEBUG_EVO = 0x200,
1632 NOUVEAU_REG_DEBUG_AUXCH = 0x400
1633 };
1634
1635 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1636 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1637 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1638 } while (0)
1639
1640 static inline bool
1641 nv_two_heads(struct drm_device *dev)
1642 {
1643 struct drm_nouveau_private *dev_priv = dev->dev_private;
1644 const int impl = dev->pci_device & 0x0ff0;
1645
1646 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1647 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1648 return true;
1649
1650 return false;
1651 }
1652
1653 static inline bool
1654 nv_gf4_disp_arch(struct drm_device *dev)
1655 {
1656 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1657 }
1658
1659 static inline bool
1660 nv_two_reg_pll(struct drm_device *dev)
1661 {
1662 struct drm_nouveau_private *dev_priv = dev->dev_private;
1663 const int impl = dev->pci_device & 0x0ff0;
1664
1665 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1666 return true;
1667 return false;
1668 }
1669
1670 static inline bool
1671 nv_match_device(struct drm_device *dev, unsigned device,
1672 unsigned sub_vendor, unsigned sub_device)
1673 {
1674 return dev->pdev->device == device &&
1675 dev->pdev->subsystem_vendor == sub_vendor &&
1676 dev->pdev->subsystem_device == sub_device;
1677 }
1678
1679 static inline void *
1680 nv_engine(struct drm_device *dev, int engine)
1681 {
1682 struct drm_nouveau_private *dev_priv = dev->dev_private;
1683 return (void *)dev_priv->eng[engine];
1684 }
1685
1686 /* returns 1 if device is one of the nv4x using the 0x4497 object class,
1687 * helpful to determine a number of other hardware features
1688 */
1689 static inline int
1690 nv44_graph_class(struct drm_device *dev)
1691 {
1692 struct drm_nouveau_private *dev_priv = dev->dev_private;
1693
1694 if ((dev_priv->chipset & 0xf0) == 0x60)
1695 return 1;
1696
1697 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f)));
1698 }
1699
1700 /* memory type/access flags, do not match hardware values */
1701 #define NV_MEM_ACCESS_RO 1
1702 #define NV_MEM_ACCESS_WO 2
1703 #define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO)
1704 #define NV_MEM_ACCESS_SYS 4
1705 #define NV_MEM_ACCESS_VM 8
1706
1707 #define NV_MEM_TARGET_VRAM 0
1708 #define NV_MEM_TARGET_PCI 1
1709 #define NV_MEM_TARGET_PCI_NOSNOOP 2
1710 #define NV_MEM_TARGET_VM 3
1711 #define NV_MEM_TARGET_GART 4
1712
1713 #define NV_MEM_TYPE_VM 0x7f
1714 #define NV_MEM_COMP_VM 0x03
1715
1716 /* NV_SW object class */
1717 #define NV_SW 0x0000506e
1718 #define NV_SW_DMA_SEMAPHORE 0x00000060
1719 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1720 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1721 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1722 #define NV_SW_YIELD 0x00000080
1723 #define NV_SW_DMA_VBLSEM 0x0000018c
1724 #define NV_SW_VBLSEM_OFFSET 0x00000400
1725 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1726 #define NV_SW_VBLSEM_RELEASE 0x00000408
1727 #define NV_SW_PAGE_FLIP 0x00000500
1728
1729 #endif /* __NOUVEAU_DRV_H__ */