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OMAPDSS: VENC: fix NULL pointer dereference in DSS2 VENC sysfs debug attr on OMAP4
[zen-stable.git] / drivers / gpu / drm / radeon / radeon_atombios.c
blob73541373bf56fc628ea448afceb728c5f49a738d
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include "atom-bits.h"
32
33 /* from radeon_encoder.c */
34 extern uint32_t
35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
38 extern void
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
40 uint32_t supported_device, u16 caps);
41
42 /* from radeon_connector.c */
43 extern void
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
53
54 /* from radeon_legacy_encoder.c */
55 extern void
56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
57 uint32_t supported_device);
58
59 union atom_supported_devices {
60 struct _ATOM_SUPPORTED_DEVICES_INFO info;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
63 };
64
65 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
66 ATOM_GPIO_I2C_ASSIGMENT *gpio,
67 u8 index)
68 {
69 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
70 if ((rdev->family == CHIP_R420) ||
71 (rdev->family == CHIP_R423) ||
72 (rdev->family == CHIP_RV410)) {
73 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
74 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
75 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
76 gpio->ucClkMaskShift = 0x19;
77 gpio->ucDataMaskShift = 0x18;
78 }
79 }
80
81 /* some evergreen boards have bad data for this entry */
82 if (ASIC_IS_DCE4(rdev)) {
83 if ((index == 7) &&
84 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
85 (gpio->sucI2cId.ucAccess == 0)) {
86 gpio->sucI2cId.ucAccess = 0x97;
87 gpio->ucDataMaskShift = 8;
88 gpio->ucDataEnShift = 8;
89 gpio->ucDataY_Shift = 8;
90 gpio->ucDataA_Shift = 8;
91 }
92 }
93
94 /* some DCE3 boards have bad data for this entry */
95 if (ASIC_IS_DCE3(rdev)) {
96 if ((index == 4) &&
97 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
98 (gpio->sucI2cId.ucAccess == 0x94))
99 gpio->sucI2cId.ucAccess = 0x14;
100 }
101 }
102
103 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
104 {
105 struct radeon_i2c_bus_rec i2c;
106
107 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
108
109 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
110 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
111 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
112 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
113 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
114 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
115 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
116 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
117 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
118 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
119 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
120 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
121 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
122 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
123 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
124 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
125
126 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
127 i2c.hw_capable = true;
128 else
129 i2c.hw_capable = false;
130
131 if (gpio->sucI2cId.ucAccess == 0xa0)
132 i2c.mm_i2c = true;
133 else
134 i2c.mm_i2c = false;
135
136 i2c.i2c_id = gpio->sucI2cId.ucAccess;
137
138 if (i2c.mask_clk_reg)
139 i2c.valid = true;
140 else
141 i2c.valid = false;
142
143 return i2c;
144 }
145
146 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
147 uint8_t id)
148 {
149 struct atom_context *ctx = rdev->mode_info.atom_context;
150 ATOM_GPIO_I2C_ASSIGMENT *gpio;
151 struct radeon_i2c_bus_rec i2c;
152 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
153 struct _ATOM_GPIO_I2C_INFO *i2c_info;
154 uint16_t data_offset, size;
155 int i, num_indices;
156
157 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
158 i2c.valid = false;
159
160 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
161 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
162
163 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
164 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
165
166 for (i = 0; i < num_indices; i++) {
167 gpio = &i2c_info->asGPIO_Info[i];
168
169 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
170
171 if (gpio->sucI2cId.ucAccess == id) {
172 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
173 break;
174 }
175 }
176 }
177
178 return i2c;
179 }
180
181 void radeon_atombios_i2c_init(struct radeon_device *rdev)
182 {
183 struct atom_context *ctx = rdev->mode_info.atom_context;
184 ATOM_GPIO_I2C_ASSIGMENT *gpio;
185 struct radeon_i2c_bus_rec i2c;
186 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
187 struct _ATOM_GPIO_I2C_INFO *i2c_info;
188 uint16_t data_offset, size;
189 int i, num_indices;
190 char stmp[32];
191
192 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
193 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
194
195 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
196 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
197
198 for (i = 0; i < num_indices; i++) {
199 gpio = &i2c_info->asGPIO_Info[i];
200
201 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
202
203 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
204
205 if (i2c.valid) {
206 sprintf(stmp, "0x%x", i2c.i2c_id);
207 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
208 }
209 }
210 }
211 }
212
213 static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
214 u8 id)
215 {
216 struct atom_context *ctx = rdev->mode_info.atom_context;
217 struct radeon_gpio_rec gpio;
218 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
219 struct _ATOM_GPIO_PIN_LUT *gpio_info;
220 ATOM_GPIO_PIN_ASSIGNMENT *pin;
221 u16 data_offset, size;
222 int i, num_indices;
223
224 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
225 gpio.valid = false;
226
227 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
228 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
229
230 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
231 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
232
233 for (i = 0; i < num_indices; i++) {
234 pin = &gpio_info->asGPIO_Pin[i];
235 if (id == pin->ucGPIO_ID) {
236 gpio.id = pin->ucGPIO_ID;
237 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
238 gpio.mask = (1 << pin->ucGpioPinBitShift);
239 gpio.valid = true;
240 break;
241 }
242 }
243 }
244
245 return gpio;
246 }
247
248 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
249 struct radeon_gpio_rec *gpio)
250 {
251 struct radeon_hpd hpd;
252 u32 reg;
253
254 memset(&hpd, 0, sizeof(struct radeon_hpd));
255
256 if (ASIC_IS_DCE4(rdev))
257 reg = EVERGREEN_DC_GPIO_HPD_A;
258 else
259 reg = AVIVO_DC_GPIO_HPD_A;
260
261 hpd.gpio = *gpio;
262 if (gpio->reg == reg) {
263 switch(gpio->mask) {
264 case (1 << 0):
265 hpd.hpd = RADEON_HPD_1;
266 break;
267 case (1 << 8):
268 hpd.hpd = RADEON_HPD_2;
269 break;
270 case (1 << 16):
271 hpd.hpd = RADEON_HPD_3;
272 break;
273 case (1 << 24):
274 hpd.hpd = RADEON_HPD_4;
275 break;
276 case (1 << 26):
277 hpd.hpd = RADEON_HPD_5;
278 break;
279 case (1 << 28):
280 hpd.hpd = RADEON_HPD_6;
281 break;
282 default:
283 hpd.hpd = RADEON_HPD_NONE;
284 break;
285 }
286 } else
287 hpd.hpd = RADEON_HPD_NONE;
288 return hpd;
289 }
290
291 static bool radeon_atom_apply_quirks(struct drm_device *dev,
292 uint32_t supported_device,
293 int *connector_type,
294 struct radeon_i2c_bus_rec *i2c_bus,
295 uint16_t *line_mux,
296 struct radeon_hpd *hpd)
297 {
298
299 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
300 if ((dev->pdev->device == 0x791e) &&
301 (dev->pdev->subsystem_vendor == 0x1043) &&
302 (dev->pdev->subsystem_device == 0x826d)) {
303 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
304 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
305 *connector_type = DRM_MODE_CONNECTOR_DVID;
306 }
307
308 /* Asrock RS600 board lists the DVI port as HDMI */
309 if ((dev->pdev->device == 0x7941) &&
310 (dev->pdev->subsystem_vendor == 0x1849) &&
311 (dev->pdev->subsystem_device == 0x7941)) {
312 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
313 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
314 *connector_type = DRM_MODE_CONNECTOR_DVID;
315 }
316
317 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
318 if ((dev->pdev->device == 0x796e) &&
319 (dev->pdev->subsystem_vendor == 0x1462) &&
320 (dev->pdev->subsystem_device == 0x7302)) {
321 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
322 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
323 return false;
324 }
325
326 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
327 if ((dev->pdev->device == 0x7941) &&
328 (dev->pdev->subsystem_vendor == 0x147b) &&
329 (dev->pdev->subsystem_device == 0x2412)) {
330 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
331 return false;
332 }
333
334 /* Falcon NW laptop lists vga ddc line for LVDS */
335 if ((dev->pdev->device == 0x5653) &&
336 (dev->pdev->subsystem_vendor == 0x1462) &&
337 (dev->pdev->subsystem_device == 0x0291)) {
338 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
339 i2c_bus->valid = false;
340 *line_mux = 53;
341 }
342 }
343
344 /* HIS X1300 is DVI+VGA, not DVI+DVI */
345 if ((dev->pdev->device == 0x7146) &&
346 (dev->pdev->subsystem_vendor == 0x17af) &&
347 (dev->pdev->subsystem_device == 0x2058)) {
348 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
349 return false;
350 }
351
352 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
353 if ((dev->pdev->device == 0x7142) &&
354 (dev->pdev->subsystem_vendor == 0x1458) &&
355 (dev->pdev->subsystem_device == 0x2134)) {
356 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
357 return false;
358 }
359
360
361 /* Funky macbooks */
362 if ((dev->pdev->device == 0x71C5) &&
363 (dev->pdev->subsystem_vendor == 0x106b) &&
364 (dev->pdev->subsystem_device == 0x0080)) {
365 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
366 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
367 return false;
368 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
369 *line_mux = 0x90;
370 }
371
372 /* mac rv630, rv730, others */
373 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
374 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
375 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
376 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
377 }
378
379 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
380 if ((dev->pdev->device == 0x9598) &&
381 (dev->pdev->subsystem_vendor == 0x1043) &&
382 (dev->pdev->subsystem_device == 0x01da)) {
383 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
384 *connector_type = DRM_MODE_CONNECTOR_DVII;
385 }
386 }
387
388 /* ASUS HD 3600 board lists the DVI port as HDMI */
389 if ((dev->pdev->device == 0x9598) &&
390 (dev->pdev->subsystem_vendor == 0x1043) &&
391 (dev->pdev->subsystem_device == 0x01e4)) {
392 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
393 *connector_type = DRM_MODE_CONNECTOR_DVII;
394 }
395 }
396
397 /* ASUS HD 3450 board lists the DVI port as HDMI */
398 if ((dev->pdev->device == 0x95C5) &&
399 (dev->pdev->subsystem_vendor == 0x1043) &&
400 (dev->pdev->subsystem_device == 0x01e2)) {
401 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
402 *connector_type = DRM_MODE_CONNECTOR_DVII;
403 }
404 }
405
406 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
407 * HDMI + VGA reporting as HDMI
408 */
409 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
410 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
411 *connector_type = DRM_MODE_CONNECTOR_VGA;
412 *line_mux = 0;
413 }
414 }
415
416 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
417 * on the laptop and a DVI port on the docking station and
418 * both share the same encoder, hpd pin, and ddc line.
419 * So while the bios table is technically correct,
420 * we drop the DVI port here since xrandr has no concept of
421 * encoders and will try and drive both connectors
422 * with different crtcs which isn't possible on the hardware
423 * side and leaves no crtcs for LVDS or VGA.
424 */
425 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
426 (dev->pdev->subsystem_vendor == 0x1025) &&
427 (dev->pdev->subsystem_device == 0x013c)) {
428 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
429 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
430 /* actually it's a DVI-D port not DVI-I */
431 *connector_type = DRM_MODE_CONNECTOR_DVID;
432 return false;
433 }
434 }
435
436 /* XFX Pine Group device rv730 reports no VGA DDC lines
437 * even though they are wired up to record 0x93
438 */
439 if ((dev->pdev->device == 0x9498) &&
440 (dev->pdev->subsystem_vendor == 0x1682) &&
441 (dev->pdev->subsystem_device == 0x2452)) {
442 struct radeon_device *rdev = dev->dev_private;
443 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
444 }
445
446 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
447 if ((dev->pdev->device == 0x9802) &&
448 (dev->pdev->subsystem_vendor == 0x1734) &&
449 (dev->pdev->subsystem_device == 0x11bd)) {
450 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
451 *connector_type = DRM_MODE_CONNECTOR_DVII;
452 *line_mux = 0x3103;
453 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
454 *connector_type = DRM_MODE_CONNECTOR_DVII;
455 }
456 }
457
458
459 return true;
460 }
461
462 const int supported_devices_connector_convert[] = {
463 DRM_MODE_CONNECTOR_Unknown,
464 DRM_MODE_CONNECTOR_VGA,
465 DRM_MODE_CONNECTOR_DVII,
466 DRM_MODE_CONNECTOR_DVID,
467 DRM_MODE_CONNECTOR_DVIA,
468 DRM_MODE_CONNECTOR_SVIDEO,
469 DRM_MODE_CONNECTOR_Composite,
470 DRM_MODE_CONNECTOR_LVDS,
471 DRM_MODE_CONNECTOR_Unknown,
472 DRM_MODE_CONNECTOR_Unknown,
473 DRM_MODE_CONNECTOR_HDMIA,
474 DRM_MODE_CONNECTOR_HDMIB,
475 DRM_MODE_CONNECTOR_Unknown,
476 DRM_MODE_CONNECTOR_Unknown,
477 DRM_MODE_CONNECTOR_9PinDIN,
478 DRM_MODE_CONNECTOR_DisplayPort
479 };
480
481 const uint16_t supported_devices_connector_object_id_convert[] = {
482 CONNECTOR_OBJECT_ID_NONE,
483 CONNECTOR_OBJECT_ID_VGA,
484 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
485 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
486 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
487 CONNECTOR_OBJECT_ID_COMPOSITE,
488 CONNECTOR_OBJECT_ID_SVIDEO,
489 CONNECTOR_OBJECT_ID_LVDS,
490 CONNECTOR_OBJECT_ID_9PIN_DIN,
491 CONNECTOR_OBJECT_ID_9PIN_DIN,
492 CONNECTOR_OBJECT_ID_DISPLAYPORT,
493 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
494 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
495 CONNECTOR_OBJECT_ID_SVIDEO
496 };
497
498 const int object_connector_convert[] = {
499 DRM_MODE_CONNECTOR_Unknown,
500 DRM_MODE_CONNECTOR_DVII,
501 DRM_MODE_CONNECTOR_DVII,
502 DRM_MODE_CONNECTOR_DVID,
503 DRM_MODE_CONNECTOR_DVID,
504 DRM_MODE_CONNECTOR_VGA,
505 DRM_MODE_CONNECTOR_Composite,
506 DRM_MODE_CONNECTOR_SVIDEO,
507 DRM_MODE_CONNECTOR_Unknown,
508 DRM_MODE_CONNECTOR_Unknown,
509 DRM_MODE_CONNECTOR_9PinDIN,
510 DRM_MODE_CONNECTOR_Unknown,
511 DRM_MODE_CONNECTOR_HDMIA,
512 DRM_MODE_CONNECTOR_HDMIB,
513 DRM_MODE_CONNECTOR_LVDS,
514 DRM_MODE_CONNECTOR_9PinDIN,
515 DRM_MODE_CONNECTOR_Unknown,
516 DRM_MODE_CONNECTOR_Unknown,
517 DRM_MODE_CONNECTOR_Unknown,
518 DRM_MODE_CONNECTOR_DisplayPort,
519 DRM_MODE_CONNECTOR_eDP,
520 DRM_MODE_CONNECTOR_Unknown
521 };
522
523 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
524 {
525 struct radeon_device *rdev = dev->dev_private;
526 struct radeon_mode_info *mode_info = &rdev->mode_info;
527 struct atom_context *ctx = mode_info->atom_context;
528 int index = GetIndexIntoMasterTable(DATA, Object_Header);
529 u16 size, data_offset;
530 u8 frev, crev;
531 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
532 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
533 ATOM_OBJECT_TABLE *router_obj;
534 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
535 ATOM_OBJECT_HEADER *obj_header;
536 int i, j, k, path_size, device_support;
537 int connector_type;
538 u16 igp_lane_info, conn_id, connector_object_id;
539 struct radeon_i2c_bus_rec ddc_bus;
540 struct radeon_router router;
541 struct radeon_gpio_rec gpio;
542 struct radeon_hpd hpd;
543
544 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
545 return false;
546
547 if (crev < 2)
548 return false;
549
550 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
551 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
552 (ctx->bios + data_offset +
553 le16_to_cpu(obj_header->usDisplayPathTableOffset));
554 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
555 (ctx->bios + data_offset +
556 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
557 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
558 (ctx->bios + data_offset +
559 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
560 router_obj = (ATOM_OBJECT_TABLE *)
561 (ctx->bios + data_offset +
562 le16_to_cpu(obj_header->usRouterObjectTableOffset));
563 device_support = le16_to_cpu(obj_header->usDeviceSupport);
564
565 path_size = 0;
566 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
567 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
568 ATOM_DISPLAY_OBJECT_PATH *path;
569 addr += path_size;
570 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
571 path_size += le16_to_cpu(path->usSize);
572
573 if (device_support & le16_to_cpu(path->usDeviceTag)) {
574 uint8_t con_obj_id, con_obj_num, con_obj_type;
575
576 con_obj_id =
577 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
578 >> OBJECT_ID_SHIFT;
579 con_obj_num =
580 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
581 >> ENUM_ID_SHIFT;
582 con_obj_type =
583 (le16_to_cpu(path->usConnObjectId) &
584 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
585
586 /* TODO CV support */
587 if (le16_to_cpu(path->usDeviceTag) ==
588 ATOM_DEVICE_CV_SUPPORT)
589 continue;
590
591 /* IGP chips */
592 if ((rdev->flags & RADEON_IS_IGP) &&
593 (con_obj_id ==
594 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
595 uint16_t igp_offset = 0;
596 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
597
598 index =
599 GetIndexIntoMasterTable(DATA,
600 IntegratedSystemInfo);
601
602 if (atom_parse_data_header(ctx, index, &size, &frev,
603 &crev, &igp_offset)) {
604
605 if (crev >= 2) {
606 igp_obj =
607 (ATOM_INTEGRATED_SYSTEM_INFO_V2
608 *) (ctx->bios + igp_offset);
609
610 if (igp_obj) {
611 uint32_t slot_config, ct;
612
613 if (con_obj_num == 1)
614 slot_config =
615 igp_obj->
616 ulDDISlot1Config;
617 else
618 slot_config =
619 igp_obj->
620 ulDDISlot2Config;
621
622 ct = (slot_config >> 16) & 0xff;
623 connector_type =
624 object_connector_convert
625 [ct];
626 connector_object_id = ct;
627 igp_lane_info =
628 slot_config & 0xffff;
629 } else
630 continue;
631 } else
632 continue;
633 } else {
634 igp_lane_info = 0;
635 connector_type =
636 object_connector_convert[con_obj_id];
637 connector_object_id = con_obj_id;
638 }
639 } else {
640 igp_lane_info = 0;
641 connector_type =
642 object_connector_convert[con_obj_id];
643 connector_object_id = con_obj_id;
644 }
645
646 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
647 continue;
648
649 router.ddc_valid = false;
650 router.cd_valid = false;
651 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
652 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
653
654 grph_obj_id =
655 (le16_to_cpu(path->usGraphicObjIds[j]) &
656 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
657 grph_obj_num =
658 (le16_to_cpu(path->usGraphicObjIds[j]) &
659 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
660 grph_obj_type =
661 (le16_to_cpu(path->usGraphicObjIds[j]) &
662 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
663
664 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
665 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
666 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
667 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
668 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
669 (ctx->bios + data_offset +
670 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
671 ATOM_ENCODER_CAP_RECORD *cap_record;
672 u16 caps = 0;
673
674 while (record->ucRecordSize > 0 &&
675 record->ucRecordType > 0 &&
676 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
677 switch (record->ucRecordType) {
678 case ATOM_ENCODER_CAP_RECORD_TYPE:
679 cap_record =(ATOM_ENCODER_CAP_RECORD *)
680 record;
681 caps = le16_to_cpu(cap_record->usEncoderCap);
682 break;
683 }
684 record = (ATOM_COMMON_RECORD_HEADER *)
685 ((char *)record + record->ucRecordSize);
686 }
687 radeon_add_atom_encoder(dev,
688 encoder_obj,
689 le16_to_cpu
690 (path->
691 usDeviceTag),
692 caps);
693 }
694 }
695 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
696 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
697 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
698 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
699 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
700 (ctx->bios + data_offset +
701 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
702 ATOM_I2C_RECORD *i2c_record;
703 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
704 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
705 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
706 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
707 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
708 (ctx->bios + data_offset +
709 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
710 int enum_id;
711
712 router.router_id = router_obj_id;
713 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
714 enum_id++) {
715 if (le16_to_cpu(path->usConnObjectId) ==
716 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
717 break;
718 }
719
720 while (record->ucRecordSize > 0 &&
721 record->ucRecordType > 0 &&
722 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
723 switch (record->ucRecordType) {
724 case ATOM_I2C_RECORD_TYPE:
725 i2c_record =
726 (ATOM_I2C_RECORD *)
727 record;
728 i2c_config =
729 (ATOM_I2C_ID_CONFIG_ACCESS *)
730 &i2c_record->sucI2cId;
731 router.i2c_info =
732 radeon_lookup_i2c_gpio(rdev,
733 i2c_config->
734 ucAccess);
735 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
736 break;
737 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
738 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
739 record;
740 router.ddc_valid = true;
741 router.ddc_mux_type = ddc_path->ucMuxType;
742 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
743 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
744 break;
745 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
746 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
747 record;
748 router.cd_valid = true;
749 router.cd_mux_type = cd_path->ucMuxType;
750 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
751 router.cd_mux_state = cd_path->ucMuxState[enum_id];
752 break;
753 }
754 record = (ATOM_COMMON_RECORD_HEADER *)
755 ((char *)record + record->ucRecordSize);
756 }
757 }
758 }
759 }
760 }
761
762 /* look up gpio for ddc, hpd */
763 ddc_bus.valid = false;
764 hpd.hpd = RADEON_HPD_NONE;
765 if ((le16_to_cpu(path->usDeviceTag) &
766 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
767 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
768 if (le16_to_cpu(path->usConnObjectId) ==
769 le16_to_cpu(con_obj->asObjects[j].
770 usObjectID)) {
771 ATOM_COMMON_RECORD_HEADER
772 *record =
773 (ATOM_COMMON_RECORD_HEADER
774 *)
775 (ctx->bios + data_offset +
776 le16_to_cpu(con_obj->
777 asObjects[j].
778 usRecordOffset));
779 ATOM_I2C_RECORD *i2c_record;
780 ATOM_HPD_INT_RECORD *hpd_record;
781 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
782
783 while (record->ucRecordSize > 0 &&
784 record->ucRecordType > 0 &&
785 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
786 switch (record->ucRecordType) {
787 case ATOM_I2C_RECORD_TYPE:
788 i2c_record =
789 (ATOM_I2C_RECORD *)
790 record;
791 i2c_config =
792 (ATOM_I2C_ID_CONFIG_ACCESS *)
793 &i2c_record->sucI2cId;
794 ddc_bus = radeon_lookup_i2c_gpio(rdev,
795 i2c_config->
796 ucAccess);
797 break;
798 case ATOM_HPD_INT_RECORD_TYPE:
799 hpd_record =
800 (ATOM_HPD_INT_RECORD *)
801 record;
802 gpio = radeon_lookup_gpio(rdev,
803 hpd_record->ucHPDIntGPIOID);
804 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
805 hpd.plugged_state = hpd_record->ucPlugged_PinState;
806 break;
807 }
808 record =
809 (ATOM_COMMON_RECORD_HEADER
810 *) ((char *)record
811 +
812 record->
813 ucRecordSize);
814 }
815 break;
816 }
817 }
818 }
819
820 /* needed for aux chan transactions */
821 ddc_bus.hpd = hpd.hpd;
822
823 conn_id = le16_to_cpu(path->usConnObjectId);
824
825 if (!radeon_atom_apply_quirks
826 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
827 &ddc_bus, &conn_id, &hpd))
828 continue;
829
830 radeon_add_atom_connector(dev,
831 conn_id,
832 le16_to_cpu(path->
833 usDeviceTag),
834 connector_type, &ddc_bus,
835 igp_lane_info,
836 connector_object_id,
837 &hpd,
838 &router);
839
840 }
841 }
842
843 radeon_link_encoder_connector(dev);
844
845 return true;
846 }
847
848 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
849 int connector_type,
850 uint16_t devices)
851 {
852 struct radeon_device *rdev = dev->dev_private;
853
854 if (rdev->flags & RADEON_IS_IGP) {
855 return supported_devices_connector_object_id_convert
856 [connector_type];
857 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
858 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
859 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
860 struct radeon_mode_info *mode_info = &rdev->mode_info;
861 struct atom_context *ctx = mode_info->atom_context;
862 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
863 uint16_t size, data_offset;
864 uint8_t frev, crev;
865 ATOM_XTMDS_INFO *xtmds;
866
867 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
868 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
869
870 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
871 if (connector_type == DRM_MODE_CONNECTOR_DVII)
872 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
873 else
874 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
875 } else {
876 if (connector_type == DRM_MODE_CONNECTOR_DVII)
877 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
878 else
879 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
880 }
881 } else
882 return supported_devices_connector_object_id_convert
883 [connector_type];
884 } else {
885 return supported_devices_connector_object_id_convert
886 [connector_type];
887 }
888 }
889
890 struct bios_connector {
891 bool valid;
892 uint16_t line_mux;
893 uint16_t devices;
894 int connector_type;
895 struct radeon_i2c_bus_rec ddc_bus;
896 struct radeon_hpd hpd;
897 };
898
899 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
900 drm_device
901 *dev)
902 {
903 struct radeon_device *rdev = dev->dev_private;
904 struct radeon_mode_info *mode_info = &rdev->mode_info;
905 struct atom_context *ctx = mode_info->atom_context;
906 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
907 uint16_t size, data_offset;
908 uint8_t frev, crev;
909 uint16_t device_support;
910 uint8_t dac;
911 union atom_supported_devices *supported_devices;
912 int i, j, max_device;
913 struct bios_connector *bios_connectors;
914 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
915 struct radeon_router router;
916
917 router.ddc_valid = false;
918 router.cd_valid = false;
919
920 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
921 if (!bios_connectors)
922 return false;
923
924 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
925 &data_offset)) {
926 kfree(bios_connectors);
927 return false;
928 }
929
930 supported_devices =
931 (union atom_supported_devices *)(ctx->bios + data_offset);
932
933 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
934
935 if (frev > 1)
936 max_device = ATOM_MAX_SUPPORTED_DEVICE;
937 else
938 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
939
940 for (i = 0; i < max_device; i++) {
941 ATOM_CONNECTOR_INFO_I2C ci =
942 supported_devices->info.asConnInfo[i];
943
944 bios_connectors[i].valid = false;
945
946 if (!(device_support & (1 << i))) {
947 continue;
948 }
949
950 if (i == ATOM_DEVICE_CV_INDEX) {
951 DRM_DEBUG_KMS("Skipping Component Video\n");
952 continue;
953 }
954
955 bios_connectors[i].connector_type =
956 supported_devices_connector_convert[ci.sucConnectorInfo.
957 sbfAccess.
958 bfConnectorType];
959
960 if (bios_connectors[i].connector_type ==
961 DRM_MODE_CONNECTOR_Unknown)
962 continue;
963
964 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
965
966 bios_connectors[i].line_mux =
967 ci.sucI2cId.ucAccess;
968
969 /* give tv unique connector ids */
970 if (i == ATOM_DEVICE_TV1_INDEX) {
971 bios_connectors[i].ddc_bus.valid = false;
972 bios_connectors[i].line_mux = 50;
973 } else if (i == ATOM_DEVICE_TV2_INDEX) {
974 bios_connectors[i].ddc_bus.valid = false;
975 bios_connectors[i].line_mux = 51;
976 } else if (i == ATOM_DEVICE_CV_INDEX) {
977 bios_connectors[i].ddc_bus.valid = false;
978 bios_connectors[i].line_mux = 52;
979 } else
980 bios_connectors[i].ddc_bus =
981 radeon_lookup_i2c_gpio(rdev,
982 bios_connectors[i].line_mux);
983
984 if ((crev > 1) && (frev > 1)) {
985 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
986 switch (isb) {
987 case 0x4:
988 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
989 break;
990 case 0xa:
991 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
992 break;
993 default:
994 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
995 break;
996 }
997 } else {
998 if (i == ATOM_DEVICE_DFP1_INDEX)
999 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1000 else if (i == ATOM_DEVICE_DFP2_INDEX)
1001 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1002 else
1003 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1004 }
1005
1006 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1007 * shared with a DVI port, we'll pick up the DVI connector when we
1008 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1009 */
1010 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1011 bios_connectors[i].connector_type =
1012 DRM_MODE_CONNECTOR_VGA;
1013
1014 if (!radeon_atom_apply_quirks
1015 (dev, (1 << i), &bios_connectors[i].connector_type,
1016 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1017 &bios_connectors[i].hpd))
1018 continue;
1019
1020 bios_connectors[i].valid = true;
1021 bios_connectors[i].devices = (1 << i);
1022
1023 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1024 radeon_add_atom_encoder(dev,
1025 radeon_get_encoder_enum(dev,
1026 (1 << i),
1027 dac),
1028 (1 << i),
1029 0);
1030 else
1031 radeon_add_legacy_encoder(dev,
1032 radeon_get_encoder_enum(dev,
1033 (1 << i),
1034 dac),
1035 (1 << i));
1036 }
1037
1038 /* combine shared connectors */
1039 for (i = 0; i < max_device; i++) {
1040 if (bios_connectors[i].valid) {
1041 for (j = 0; j < max_device; j++) {
1042 if (bios_connectors[j].valid && (i != j)) {
1043 if (bios_connectors[i].line_mux ==
1044 bios_connectors[j].line_mux) {
1045 /* make sure not to combine LVDS */
1046 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1047 bios_connectors[i].line_mux = 53;
1048 bios_connectors[i].ddc_bus.valid = false;
1049 continue;
1050 }
1051 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1052 bios_connectors[j].line_mux = 53;
1053 bios_connectors[j].ddc_bus.valid = false;
1054 continue;
1055 }
1056 /* combine analog and digital for DVI-I */
1057 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1058 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1059 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1060 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1061 bios_connectors[i].devices |=
1062 bios_connectors[j].devices;
1063 bios_connectors[i].connector_type =
1064 DRM_MODE_CONNECTOR_DVII;
1065 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1066 bios_connectors[i].hpd =
1067 bios_connectors[j].hpd;
1068 bios_connectors[j].valid = false;
1069 }
1070 }
1071 }
1072 }
1073 }
1074 }
1075
1076 /* add the connectors */
1077 for (i = 0; i < max_device; i++) {
1078 if (bios_connectors[i].valid) {
1079 uint16_t connector_object_id =
1080 atombios_get_connector_object_id(dev,
1081 bios_connectors[i].connector_type,
1082 bios_connectors[i].devices);
1083 radeon_add_atom_connector(dev,
1084 bios_connectors[i].line_mux,
1085 bios_connectors[i].devices,
1086 bios_connectors[i].
1087 connector_type,
1088 &bios_connectors[i].ddc_bus,
1089 0,
1090 connector_object_id,
1091 &bios_connectors[i].hpd,
1092 &router);
1093 }
1094 }
1095
1096 radeon_link_encoder_connector(dev);
1097
1098 kfree(bios_connectors);
1099 return true;
1100 }
1101
1102 union firmware_info {
1103 ATOM_FIRMWARE_INFO info;
1104 ATOM_FIRMWARE_INFO_V1_2 info_12;
1105 ATOM_FIRMWARE_INFO_V1_3 info_13;
1106 ATOM_FIRMWARE_INFO_V1_4 info_14;
1107 ATOM_FIRMWARE_INFO_V2_1 info_21;
1108 ATOM_FIRMWARE_INFO_V2_2 info_22;
1109 };
1110
1111 bool radeon_atom_get_clock_info(struct drm_device *dev)
1112 {
1113 struct radeon_device *rdev = dev->dev_private;
1114 struct radeon_mode_info *mode_info = &rdev->mode_info;
1115 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1116 union firmware_info *firmware_info;
1117 uint8_t frev, crev;
1118 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1119 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1120 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1121 struct radeon_pll *spll = &rdev->clock.spll;
1122 struct radeon_pll *mpll = &rdev->clock.mpll;
1123 uint16_t data_offset;
1124
1125 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1126 &frev, &crev, &data_offset)) {
1127 firmware_info =
1128 (union firmware_info *)(mode_info->atom_context->bios +
1129 data_offset);
1130 /* pixel clocks */
1131 p1pll->reference_freq =
1132 le16_to_cpu(firmware_info->info.usReferenceClock);
1133 p1pll->reference_div = 0;
1134
1135 if (crev < 2)
1136 p1pll->pll_out_min =
1137 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1138 else
1139 p1pll->pll_out_min =
1140 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1141 p1pll->pll_out_max =
1142 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1143
1144 if (crev >= 4) {
1145 p1pll->lcd_pll_out_min =
1146 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1147 if (p1pll->lcd_pll_out_min == 0)
1148 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1149 p1pll->lcd_pll_out_max =
1150 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1151 if (p1pll->lcd_pll_out_max == 0)
1152 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1153 } else {
1154 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1155 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1156 }
1157
1158 if (p1pll->pll_out_min == 0) {
1159 if (ASIC_IS_AVIVO(rdev))
1160 p1pll->pll_out_min = 64800;
1161 else
1162 p1pll->pll_out_min = 20000;
1163 }
1164
1165 p1pll->pll_in_min =
1166 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1167 p1pll->pll_in_max =
1168 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1169
1170 *p2pll = *p1pll;
1171
1172 /* system clock */
1173 if (ASIC_IS_DCE4(rdev))
1174 spll->reference_freq =
1175 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1176 else
1177 spll->reference_freq =
1178 le16_to_cpu(firmware_info->info.usReferenceClock);
1179 spll->reference_div = 0;
1180
1181 spll->pll_out_min =
1182 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1183 spll->pll_out_max =
1184 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1185
1186 /* ??? */
1187 if (spll->pll_out_min == 0) {
1188 if (ASIC_IS_AVIVO(rdev))
1189 spll->pll_out_min = 64800;
1190 else
1191 spll->pll_out_min = 20000;
1192 }
1193
1194 spll->pll_in_min =
1195 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1196 spll->pll_in_max =
1197 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1198
1199 /* memory clock */
1200 if (ASIC_IS_DCE4(rdev))
1201 mpll->reference_freq =
1202 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1203 else
1204 mpll->reference_freq =
1205 le16_to_cpu(firmware_info->info.usReferenceClock);
1206 mpll->reference_div = 0;
1207
1208 mpll->pll_out_min =
1209 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1210 mpll->pll_out_max =
1211 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1212
1213 /* ??? */
1214 if (mpll->pll_out_min == 0) {
1215 if (ASIC_IS_AVIVO(rdev))
1216 mpll->pll_out_min = 64800;
1217 else
1218 mpll->pll_out_min = 20000;
1219 }
1220
1221 mpll->pll_in_min =
1222 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1223 mpll->pll_in_max =
1224 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1225
1226 rdev->clock.default_sclk =
1227 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1228 rdev->clock.default_mclk =
1229 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1230
1231 if (ASIC_IS_DCE4(rdev)) {
1232 rdev->clock.default_dispclk =
1233 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1234 if (rdev->clock.default_dispclk == 0) {
1235 if (ASIC_IS_DCE5(rdev))
1236 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1237 else
1238 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1239 }
1240 rdev->clock.dp_extclk =
1241 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1242 }
1243 *dcpll = *p1pll;
1244
1245 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1246 if (rdev->clock.max_pixel_clock == 0)
1247 rdev->clock.max_pixel_clock = 40000;
1248
1249 return true;
1250 }
1251
1252 return false;
1253 }
1254
1255 union igp_info {
1256 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1257 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1258 };
1259
1260 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1261 {
1262 struct radeon_mode_info *mode_info = &rdev->mode_info;
1263 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1264 union igp_info *igp_info;
1265 u8 frev, crev;
1266 u16 data_offset;
1267
1268 /* sideport is AMD only */
1269 if (rdev->family == CHIP_RS600)
1270 return false;
1271
1272 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1273 &frev, &crev, &data_offset)) {
1274 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1275 data_offset);
1276 switch (crev) {
1277 case 1:
1278 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1279 return true;
1280 break;
1281 case 2:
1282 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1283 return true;
1284 break;
1285 default:
1286 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1287 break;
1288 }
1289 }
1290 return false;
1291 }
1292
1293 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1294 struct radeon_encoder_int_tmds *tmds)
1295 {
1296 struct drm_device *dev = encoder->base.dev;
1297 struct radeon_device *rdev = dev->dev_private;
1298 struct radeon_mode_info *mode_info = &rdev->mode_info;
1299 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1300 uint16_t data_offset;
1301 struct _ATOM_TMDS_INFO *tmds_info;
1302 uint8_t frev, crev;
1303 uint16_t maxfreq;
1304 int i;
1305
1306 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1307 &frev, &crev, &data_offset)) {
1308 tmds_info =
1309 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1310 data_offset);
1311
1312 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1313 for (i = 0; i < 4; i++) {
1314 tmds->tmds_pll[i].freq =
1315 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1316 tmds->tmds_pll[i].value =
1317 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1318 tmds->tmds_pll[i].value |=
1319 (tmds_info->asMiscInfo[i].
1320 ucPLL_VCO_Gain & 0x3f) << 6;
1321 tmds->tmds_pll[i].value |=
1322 (tmds_info->asMiscInfo[i].
1323 ucPLL_DutyCycle & 0xf) << 12;
1324 tmds->tmds_pll[i].value |=
1325 (tmds_info->asMiscInfo[i].
1326 ucPLL_VoltageSwing & 0xf) << 16;
1327
1328 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1329 tmds->tmds_pll[i].freq,
1330 tmds->tmds_pll[i].value);
1331
1332 if (maxfreq == tmds->tmds_pll[i].freq) {
1333 tmds->tmds_pll[i].freq = 0xffffffff;
1334 break;
1335 }
1336 }
1337 return true;
1338 }
1339 return false;
1340 }
1341
1342 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1343 struct radeon_atom_ss *ss,
1344 int id)
1345 {
1346 struct radeon_mode_info *mode_info = &rdev->mode_info;
1347 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1348 uint16_t data_offset, size;
1349 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1350 uint8_t frev, crev;
1351 int i, num_indices;
1352
1353 memset(ss, 0, sizeof(struct radeon_atom_ss));
1354 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1355 &frev, &crev, &data_offset)) {
1356 ss_info =
1357 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1358
1359 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1360 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1361
1362 for (i = 0; i < num_indices; i++) {
1363 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1364 ss->percentage =
1365 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1366 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1367 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1368 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1369 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1370 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1371 return true;
1372 }
1373 }
1374 }
1375 return false;
1376 }
1377
1378 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1379 struct radeon_atom_ss *ss,
1380 int id)
1381 {
1382 struct radeon_mode_info *mode_info = &rdev->mode_info;
1383 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1384 u16 data_offset, size;
1385 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1386 u8 frev, crev;
1387 u16 percentage = 0, rate = 0;
1388
1389 /* get any igp specific overrides */
1390 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1391 &frev, &crev, &data_offset)) {
1392 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1393 (mode_info->atom_context->bios + data_offset);
1394 switch (id) {
1395 case ASIC_INTERNAL_SS_ON_TMDS:
1396 percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1397 rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1398 break;
1399 case ASIC_INTERNAL_SS_ON_HDMI:
1400 percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1401 rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1402 break;
1403 case ASIC_INTERNAL_SS_ON_LVDS:
1404 percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1405 rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1406 break;
1407 }
1408 if (percentage)
1409 ss->percentage = percentage;
1410 if (rate)
1411 ss->rate = rate;
1412 }
1413 }
1414
1415 union asic_ss_info {
1416 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1417 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1418 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1419 };
1420
1421 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1422 struct radeon_atom_ss *ss,
1423 int id, u32 clock)
1424 {
1425 struct radeon_mode_info *mode_info = &rdev->mode_info;
1426 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1427 uint16_t data_offset, size;
1428 union asic_ss_info *ss_info;
1429 uint8_t frev, crev;
1430 int i, num_indices;
1431
1432 memset(ss, 0, sizeof(struct radeon_atom_ss));
1433 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1434 &frev, &crev, &data_offset)) {
1435
1436 ss_info =
1437 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1438
1439 switch (frev) {
1440 case 1:
1441 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1442 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1443
1444 for (i = 0; i < num_indices; i++) {
1445 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1446 (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
1447 ss->percentage =
1448 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1449 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1450 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1451 return true;
1452 }
1453 }
1454 break;
1455 case 2:
1456 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1457 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1458 for (i = 0; i < num_indices; i++) {
1459 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1460 (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
1461 ss->percentage =
1462 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1463 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1464 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1465 return true;
1466 }
1467 }
1468 break;
1469 case 3:
1470 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1471 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1472 for (i = 0; i < num_indices; i++) {
1473 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1474 (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
1475 ss->percentage =
1476 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1477 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1478 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1479 if (rdev->flags & RADEON_IS_IGP)
1480 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1481 return true;
1482 }
1483 }
1484 break;
1485 default:
1486 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1487 break;
1488 }
1489
1490 }
1491 return false;
1492 }
1493
1494 union lvds_info {
1495 struct _ATOM_LVDS_INFO info;
1496 struct _ATOM_LVDS_INFO_V12 info_12;
1497 };
1498
1499 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1500 radeon_encoder
1501 *encoder)
1502 {
1503 struct drm_device *dev = encoder->base.dev;
1504 struct radeon_device *rdev = dev->dev_private;
1505 struct radeon_mode_info *mode_info = &rdev->mode_info;
1506 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1507 uint16_t data_offset, misc;
1508 union lvds_info *lvds_info;
1509 uint8_t frev, crev;
1510 struct radeon_encoder_atom_dig *lvds = NULL;
1511 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1512
1513 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1514 &frev, &crev, &data_offset)) {
1515 lvds_info =
1516 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1517 lvds =
1518 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1519
1520 if (!lvds)
1521 return NULL;
1522
1523 lvds->native_mode.clock =
1524 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1525 lvds->native_mode.hdisplay =
1526 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1527 lvds->native_mode.vdisplay =
1528 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1529 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1530 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1531 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1532 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1533 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1534 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1535 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1536 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1537 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1538 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1539 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1540 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1541 lvds->panel_pwr_delay =
1542 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1543 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1544
1545 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1546 if (misc & ATOM_VSYNC_POLARITY)
1547 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1548 if (misc & ATOM_HSYNC_POLARITY)
1549 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1550 if (misc & ATOM_COMPOSITESYNC)
1551 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1552 if (misc & ATOM_INTERLACE)
1553 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1554 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1555 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1556
1557 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1558 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1559
1560 /* set crtc values */
1561 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1562
1563 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1564
1565 encoder->native_mode = lvds->native_mode;
1566
1567 if (encoder_enum == 2)
1568 lvds->linkb = true;
1569 else
1570 lvds->linkb = false;
1571
1572 /* parse the lcd record table */
1573 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1574 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1575 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1576 bool bad_record = false;
1577 u8 *record;
1578
1579 if ((frev == 1) && (crev < 2))
1580 /* absolute */
1581 record = (u8 *)(mode_info->atom_context->bios +
1582 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1583 else
1584 /* relative */
1585 record = (u8 *)(mode_info->atom_context->bios +
1586 data_offset +
1587 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1588 while (*record != ATOM_RECORD_END_TYPE) {
1589 switch (*record) {
1590 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1591 record += sizeof(ATOM_PATCH_RECORD_MODE);
1592 break;
1593 case LCD_RTS_RECORD_TYPE:
1594 record += sizeof(ATOM_LCD_RTS_RECORD);
1595 break;
1596 case LCD_CAP_RECORD_TYPE:
1597 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1598 break;
1599 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1600 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1601 if (fake_edid_record->ucFakeEDIDLength) {
1602 struct edid *edid;
1603 int edid_size =
1604 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1605 edid = kmalloc(edid_size, GFP_KERNEL);
1606 if (edid) {
1607 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1608 fake_edid_record->ucFakeEDIDLength);
1609
1610 if (drm_edid_is_valid(edid)) {
1611 rdev->mode_info.bios_hardcoded_edid = edid;
1612 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1613 } else
1614 kfree(edid);
1615 }
1616 }
1617 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1618 break;
1619 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1620 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1621 lvds->native_mode.width_mm = panel_res_record->usHSize;
1622 lvds->native_mode.height_mm = panel_res_record->usVSize;
1623 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1624 break;
1625 default:
1626 DRM_ERROR("Bad LCD record %d\n", *record);
1627 bad_record = true;
1628 break;
1629 }
1630 if (bad_record)
1631 break;
1632 }
1633 }
1634 }
1635 return lvds;
1636 }
1637
1638 struct radeon_encoder_primary_dac *
1639 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1640 {
1641 struct drm_device *dev = encoder->base.dev;
1642 struct radeon_device *rdev = dev->dev_private;
1643 struct radeon_mode_info *mode_info = &rdev->mode_info;
1644 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1645 uint16_t data_offset;
1646 struct _COMPASSIONATE_DATA *dac_info;
1647 uint8_t frev, crev;
1648 uint8_t bg, dac;
1649 struct radeon_encoder_primary_dac *p_dac = NULL;
1650
1651 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1652 &frev, &crev, &data_offset)) {
1653 dac_info = (struct _COMPASSIONATE_DATA *)
1654 (mode_info->atom_context->bios + data_offset);
1655
1656 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1657
1658 if (!p_dac)
1659 return NULL;
1660
1661 bg = dac_info->ucDAC1_BG_Adjustment;
1662 dac = dac_info->ucDAC1_DAC_Adjustment;
1663 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1664
1665 }
1666 return p_dac;
1667 }
1668
1669 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1670 struct drm_display_mode *mode)
1671 {
1672 struct radeon_mode_info *mode_info = &rdev->mode_info;
1673 ATOM_ANALOG_TV_INFO *tv_info;
1674 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1675 ATOM_DTD_FORMAT *dtd_timings;
1676 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1677 u8 frev, crev;
1678 u16 data_offset, misc;
1679
1680 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1681 &frev, &crev, &data_offset))
1682 return false;
1683
1684 switch (crev) {
1685 case 1:
1686 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1687 if (index >= MAX_SUPPORTED_TV_TIMING)
1688 return false;
1689
1690 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1691 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1692 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1693 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1694 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1695
1696 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1697 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1698 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1699 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1700 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1701
1702 mode->flags = 0;
1703 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1704 if (misc & ATOM_VSYNC_POLARITY)
1705 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1706 if (misc & ATOM_HSYNC_POLARITY)
1707 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1708 if (misc & ATOM_COMPOSITESYNC)
1709 mode->flags |= DRM_MODE_FLAG_CSYNC;
1710 if (misc & ATOM_INTERLACE)
1711 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1712 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1713 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1714
1715 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1716
1717 if (index == 1) {
1718 /* PAL timings appear to have wrong values for totals */
1719 mode->crtc_htotal -= 1;
1720 mode->crtc_vtotal -= 1;
1721 }
1722 break;
1723 case 2:
1724 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1725 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1726 return false;
1727
1728 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1729 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1730 le16_to_cpu(dtd_timings->usHBlanking_Time);
1731 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1732 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1733 le16_to_cpu(dtd_timings->usHSyncOffset);
1734 mode->crtc_hsync_end = mode->crtc_hsync_start +
1735 le16_to_cpu(dtd_timings->usHSyncWidth);
1736
1737 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1738 le16_to_cpu(dtd_timings->usVBlanking_Time);
1739 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1740 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1741 le16_to_cpu(dtd_timings->usVSyncOffset);
1742 mode->crtc_vsync_end = mode->crtc_vsync_start +
1743 le16_to_cpu(dtd_timings->usVSyncWidth);
1744
1745 mode->flags = 0;
1746 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1747 if (misc & ATOM_VSYNC_POLARITY)
1748 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1749 if (misc & ATOM_HSYNC_POLARITY)
1750 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1751 if (misc & ATOM_COMPOSITESYNC)
1752 mode->flags |= DRM_MODE_FLAG_CSYNC;
1753 if (misc & ATOM_INTERLACE)
1754 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1755 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1756 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1757
1758 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1759 break;
1760 }
1761 return true;
1762 }
1763
1764 enum radeon_tv_std
1765 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1766 {
1767 struct radeon_mode_info *mode_info = &rdev->mode_info;
1768 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1769 uint16_t data_offset;
1770 uint8_t frev, crev;
1771 struct _ATOM_ANALOG_TV_INFO *tv_info;
1772 enum radeon_tv_std tv_std = TV_STD_NTSC;
1773
1774 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1775 &frev, &crev, &data_offset)) {
1776
1777 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1778 (mode_info->atom_context->bios + data_offset);
1779
1780 switch (tv_info->ucTV_BootUpDefaultStandard) {
1781 case ATOM_TV_NTSC:
1782 tv_std = TV_STD_NTSC;
1783 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1784 break;
1785 case ATOM_TV_NTSCJ:
1786 tv_std = TV_STD_NTSC_J;
1787 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1788 break;
1789 case ATOM_TV_PAL:
1790 tv_std = TV_STD_PAL;
1791 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1792 break;
1793 case ATOM_TV_PALM:
1794 tv_std = TV_STD_PAL_M;
1795 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1796 break;
1797 case ATOM_TV_PALN:
1798 tv_std = TV_STD_PAL_N;
1799 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1800 break;
1801 case ATOM_TV_PALCN:
1802 tv_std = TV_STD_PAL_CN;
1803 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1804 break;
1805 case ATOM_TV_PAL60:
1806 tv_std = TV_STD_PAL_60;
1807 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1808 break;
1809 case ATOM_TV_SECAM:
1810 tv_std = TV_STD_SECAM;
1811 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1812 break;
1813 default:
1814 tv_std = TV_STD_NTSC;
1815 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1816 break;
1817 }
1818 }
1819 return tv_std;
1820 }
1821
1822 struct radeon_encoder_tv_dac *
1823 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1824 {
1825 struct drm_device *dev = encoder->base.dev;
1826 struct radeon_device *rdev = dev->dev_private;
1827 struct radeon_mode_info *mode_info = &rdev->mode_info;
1828 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1829 uint16_t data_offset;
1830 struct _COMPASSIONATE_DATA *dac_info;
1831 uint8_t frev, crev;
1832 uint8_t bg, dac;
1833 struct radeon_encoder_tv_dac *tv_dac = NULL;
1834
1835 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1836 &frev, &crev, &data_offset)) {
1837
1838 dac_info = (struct _COMPASSIONATE_DATA *)
1839 (mode_info->atom_context->bios + data_offset);
1840
1841 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1842
1843 if (!tv_dac)
1844 return NULL;
1845
1846 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1847 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1848 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1849
1850 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1851 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1852 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1853
1854 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1855 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1856 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1857
1858 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1859 }
1860 return tv_dac;
1861 }
1862
1863 static const char *thermal_controller_names[] = {
1864 "NONE",
1865 "lm63",
1866 "adm1032",
1867 "adm1030",
1868 "max6649",
1869 "lm64",
1870 "f75375",
1871 "asc7xxx",
1872 };
1873
1874 static const char *pp_lib_thermal_controller_names[] = {
1875 "NONE",
1876 "lm63",
1877 "adm1032",
1878 "adm1030",
1879 "max6649",
1880 "lm64",
1881 "f75375",
1882 "RV6xx",
1883 "RV770",
1884 "adt7473",
1885 "NONE",
1886 "External GPIO",
1887 "Evergreen",
1888 "emc2103",
1889 "Sumo",
1890 "Northern Islands",
1891 };
1892
1893 union power_info {
1894 struct _ATOM_POWERPLAY_INFO info;
1895 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1896 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1897 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1898 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1899 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1900 };
1901
1902 union pplib_clock_info {
1903 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1904 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1905 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1906 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1907 };
1908
1909 union pplib_power_state {
1910 struct _ATOM_PPLIB_STATE v1;
1911 struct _ATOM_PPLIB_STATE_V2 v2;
1912 };
1913
1914 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1915 int state_index,
1916 u32 misc, u32 misc2)
1917 {
1918 rdev->pm.power_state[state_index].misc = misc;
1919 rdev->pm.power_state[state_index].misc2 = misc2;
1920 /* order matters! */
1921 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1922 rdev->pm.power_state[state_index].type =
1923 POWER_STATE_TYPE_POWERSAVE;
1924 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1925 rdev->pm.power_state[state_index].type =
1926 POWER_STATE_TYPE_BATTERY;
1927 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1928 rdev->pm.power_state[state_index].type =
1929 POWER_STATE_TYPE_BATTERY;
1930 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1931 rdev->pm.power_state[state_index].type =
1932 POWER_STATE_TYPE_BALANCED;
1933 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1934 rdev->pm.power_state[state_index].type =
1935 POWER_STATE_TYPE_PERFORMANCE;
1936 rdev->pm.power_state[state_index].flags &=
1937 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1938 }
1939 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1940 rdev->pm.power_state[state_index].type =
1941 POWER_STATE_TYPE_BALANCED;
1942 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1943 rdev->pm.power_state[state_index].type =
1944 POWER_STATE_TYPE_DEFAULT;
1945 rdev->pm.default_power_state_index = state_index;
1946 rdev->pm.power_state[state_index].default_clock_mode =
1947 &rdev->pm.power_state[state_index].clock_info[0];
1948 } else if (state_index == 0) {
1949 rdev->pm.power_state[state_index].clock_info[0].flags |=
1950 RADEON_PM_MODE_NO_DISPLAY;
1951 }
1952 }
1953
1954 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
1955 {
1956 struct radeon_mode_info *mode_info = &rdev->mode_info;
1957 u32 misc, misc2 = 0;
1958 int num_modes = 0, i;
1959 int state_index = 0;
1960 struct radeon_i2c_bus_rec i2c_bus;
1961 union power_info *power_info;
1962 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1963 u16 data_offset;
1964 u8 frev, crev;
1965
1966 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1967 &frev, &crev, &data_offset))
1968 return state_index;
1969 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1970
1971 /* add the i2c bus for thermal/fan chip */
1972 if (power_info->info.ucOverdriveThermalController > 0) {
1973 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1974 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1975 power_info->info.ucOverdriveControllerAddress >> 1);
1976 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1977 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1978 if (rdev->pm.i2c_bus) {
1979 struct i2c_board_info info = { };
1980 const char *name = thermal_controller_names[power_info->info.
1981 ucOverdriveThermalController];
1982 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1983 strlcpy(info.type, name, sizeof(info.type));
1984 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1985 }
1986 }
1987 num_modes = power_info->info.ucNumOfPowerModeEntries;
1988 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1989 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1990 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
1991 if (!rdev->pm.power_state)
1992 return state_index;
1993 /* last mode is usually default, array is low to high */
1994 for (i = 0; i < num_modes; i++) {
1995 rdev->pm.power_state[state_index].clock_info =
1996 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
1997 if (!rdev->pm.power_state[state_index].clock_info)
1998 return state_index;
1999 rdev->pm.power_state[state_index].num_clock_modes = 1;
2000 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2001 switch (frev) {
2002 case 1:
2003 rdev->pm.power_state[state_index].clock_info[0].mclk =
2004 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2005 rdev->pm.power_state[state_index].clock_info[0].sclk =
2006 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2007 /* skip invalid modes */
2008 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2009 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2010 continue;
2011 rdev->pm.power_state[state_index].pcie_lanes =
2012 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2013 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2014 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2015 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2016 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2017 VOLTAGE_GPIO;
2018 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2019 radeon_lookup_gpio(rdev,
2020 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2021 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2022 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2023 true;
2024 else
2025 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2026 false;
2027 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2028 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2029 VOLTAGE_VDDC;
2030 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2031 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2032 }
2033 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2034 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2035 state_index++;
2036 break;
2037 case 2:
2038 rdev->pm.power_state[state_index].clock_info[0].mclk =
2039 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2040 rdev->pm.power_state[state_index].clock_info[0].sclk =
2041 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2042 /* skip invalid modes */
2043 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2044 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2045 continue;
2046 rdev->pm.power_state[state_index].pcie_lanes =
2047 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2048 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2049 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2050 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2051 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2052 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2053 VOLTAGE_GPIO;
2054 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2055 radeon_lookup_gpio(rdev,
2056 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2057 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2058 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2059 true;
2060 else
2061 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2062 false;
2063 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2064 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2065 VOLTAGE_VDDC;
2066 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2067 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2068 }
2069 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2070 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2071 state_index++;
2072 break;
2073 case 3:
2074 rdev->pm.power_state[state_index].clock_info[0].mclk =
2075 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2076 rdev->pm.power_state[state_index].clock_info[0].sclk =
2077 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2078 /* skip invalid modes */
2079 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2080 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2081 continue;
2082 rdev->pm.power_state[state_index].pcie_lanes =
2083 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2084 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2085 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2086 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2087 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2088 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2089 VOLTAGE_GPIO;
2090 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2091 radeon_lookup_gpio(rdev,
2092 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2093 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2094 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2095 true;
2096 else
2097 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2098 false;
2099 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2100 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2101 VOLTAGE_VDDC;
2102 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2103 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2104 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2105 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2106 true;
2107 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2108 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2109 }
2110 }
2111 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2112 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2113 state_index++;
2114 break;
2115 }
2116 }
2117 /* last mode is usually default */
2118 if (rdev->pm.default_power_state_index == -1) {
2119 rdev->pm.power_state[state_index - 1].type =
2120 POWER_STATE_TYPE_DEFAULT;
2121 rdev->pm.default_power_state_index = state_index - 1;
2122 rdev->pm.power_state[state_index - 1].default_clock_mode =
2123 &rdev->pm.power_state[state_index - 1].clock_info[0];
2124 rdev->pm.power_state[state_index].flags &=
2125 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2126 rdev->pm.power_state[state_index].misc = 0;
2127 rdev->pm.power_state[state_index].misc2 = 0;
2128 }
2129 return state_index;
2130 }
2131
2132 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2133 ATOM_PPLIB_THERMALCONTROLLER *controller)
2134 {
2135 struct radeon_i2c_bus_rec i2c_bus;
2136
2137 /* add the i2c bus for thermal/fan chip */
2138 if (controller->ucType > 0) {
2139 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2140 DRM_INFO("Internal thermal controller %s fan control\n",
2141 (controller->ucFanParameters &
2142 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2143 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2144 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2145 DRM_INFO("Internal thermal controller %s fan control\n",
2146 (controller->ucFanParameters &
2147 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2148 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2149 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2150 DRM_INFO("Internal thermal controller %s fan control\n",
2151 (controller->ucFanParameters &
2152 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2153 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2154 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2155 DRM_INFO("Internal thermal controller %s fan control\n",
2156 (controller->ucFanParameters &
2157 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2158 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2159 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2160 DRM_INFO("Internal thermal controller %s fan control\n",
2161 (controller->ucFanParameters &
2162 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2163 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2164 } else if ((controller->ucType ==
2165 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2166 (controller->ucType ==
2167 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2168 (controller->ucType ==
2169 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2170 DRM_INFO("Special thermal controller config\n");
2171 } else {
2172 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2173 pp_lib_thermal_controller_names[controller->ucType],
2174 controller->ucI2cAddress >> 1,
2175 (controller->ucFanParameters &
2176 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2177 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2178 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2179 if (rdev->pm.i2c_bus) {
2180 struct i2c_board_info info = { };
2181 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2182 info.addr = controller->ucI2cAddress >> 1;
2183 strlcpy(info.type, name, sizeof(info.type));
2184 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2185 }
2186 }
2187 }
2188 }
2189
2190 static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2191 u16 *vddc, u16 *vddci)
2192 {
2193 struct radeon_mode_info *mode_info = &rdev->mode_info;
2194 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2195 u8 frev, crev;
2196 u16 data_offset;
2197 union firmware_info *firmware_info;
2198
2199 *vddc = 0;
2200 *vddci = 0;
2201
2202 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2203 &frev, &crev, &data_offset)) {
2204 firmware_info =
2205 (union firmware_info *)(mode_info->atom_context->bios +
2206 data_offset);
2207 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2208 if ((frev == 2) && (crev >= 2))
2209 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2210 }
2211 }
2212
2213 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2214 int state_index, int mode_index,
2215 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2216 {
2217 int j;
2218 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2219 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2220 u16 vddc, vddci;
2221
2222 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
2223
2224 rdev->pm.power_state[state_index].misc = misc;
2225 rdev->pm.power_state[state_index].misc2 = misc2;
2226 rdev->pm.power_state[state_index].pcie_lanes =
2227 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2228 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2229 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2230 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2231 rdev->pm.power_state[state_index].type =
2232 POWER_STATE_TYPE_BATTERY;
2233 break;
2234 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2235 rdev->pm.power_state[state_index].type =
2236 POWER_STATE_TYPE_BALANCED;
2237 break;
2238 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2239 rdev->pm.power_state[state_index].type =
2240 POWER_STATE_TYPE_PERFORMANCE;
2241 break;
2242 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2243 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2244 rdev->pm.power_state[state_index].type =
2245 POWER_STATE_TYPE_PERFORMANCE;
2246 break;
2247 }
2248 rdev->pm.power_state[state_index].flags = 0;
2249 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2250 rdev->pm.power_state[state_index].flags |=
2251 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2252 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2253 rdev->pm.power_state[state_index].type =
2254 POWER_STATE_TYPE_DEFAULT;
2255 rdev->pm.default_power_state_index = state_index;
2256 rdev->pm.power_state[state_index].default_clock_mode =
2257 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2258 if (ASIC_IS_DCE5(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2259 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2260 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2261 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2262 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2263 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2264 } else {
2265 /* patch the table values with the default slck/mclk from firmware info */
2266 for (j = 0; j < mode_index; j++) {
2267 rdev->pm.power_state[state_index].clock_info[j].mclk =
2268 rdev->clock.default_mclk;
2269 rdev->pm.power_state[state_index].clock_info[j].sclk =
2270 rdev->clock.default_sclk;
2271 if (vddc)
2272 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2273 vddc;
2274 }
2275 }
2276 }
2277 }
2278
2279 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2280 int state_index, int mode_index,
2281 union pplib_clock_info *clock_info)
2282 {
2283 u32 sclk, mclk;
2284
2285 if (rdev->flags & RADEON_IS_IGP) {
2286 if (rdev->family >= CHIP_PALM) {
2287 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2288 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2289 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2290 } else {
2291 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2292 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2293 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2294 }
2295 } else if (ASIC_IS_DCE4(rdev)) {
2296 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2297 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2298 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2299 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2300 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2301 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2302 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2303 VOLTAGE_SW;
2304 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2305 le16_to_cpu(clock_info->evergreen.usVDDC);
2306 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2307 le16_to_cpu(clock_info->evergreen.usVDDCI);
2308 } else {
2309 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2310 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2311 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2312 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2313 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2314 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2315 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2316 VOLTAGE_SW;
2317 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2318 le16_to_cpu(clock_info->r600.usVDDC);
2319 }
2320
2321 /* patch up vddc if necessary */
2322 if (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage == 0xff01) {
2323 u16 vddc;
2324
2325 if (radeon_atom_get_max_vddc(rdev, &vddc) == 0)
2326 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2327 }
2328
2329 if (rdev->flags & RADEON_IS_IGP) {
2330 /* skip invalid modes */
2331 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2332 return false;
2333 } else {
2334 /* skip invalid modes */
2335 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2336 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2337 return false;
2338 }
2339 return true;
2340 }
2341
2342 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2343 {
2344 struct radeon_mode_info *mode_info = &rdev->mode_info;
2345 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2346 union pplib_power_state *power_state;
2347 int i, j;
2348 int state_index = 0, mode_index = 0;
2349 union pplib_clock_info *clock_info;
2350 bool valid;
2351 union power_info *power_info;
2352 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2353 u16 data_offset;
2354 u8 frev, crev;
2355
2356 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2357 &frev, &crev, &data_offset))
2358 return state_index;
2359 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2360
2361 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2362 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2363 power_info->pplib.ucNumStates, GFP_KERNEL);
2364 if (!rdev->pm.power_state)
2365 return state_index;
2366 /* first mode is usually default, followed by low to high */
2367 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2368 mode_index = 0;
2369 power_state = (union pplib_power_state *)
2370 (mode_info->atom_context->bios + data_offset +
2371 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2372 i * power_info->pplib.ucStateEntrySize);
2373 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2374 (mode_info->atom_context->bios + data_offset +
2375 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2376 (power_state->v1.ucNonClockStateIndex *
2377 power_info->pplib.ucNonClockSize));
2378 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2379 ((power_info->pplib.ucStateEntrySize - 1) ?
2380 (power_info->pplib.ucStateEntrySize - 1) : 1),
2381 GFP_KERNEL);
2382 if (!rdev->pm.power_state[i].clock_info)
2383 return state_index;
2384 if (power_info->pplib.ucStateEntrySize - 1) {
2385 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2386 clock_info = (union pplib_clock_info *)
2387 (mode_info->atom_context->bios + data_offset +
2388 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2389 (power_state->v1.ucClockStateIndices[j] *
2390 power_info->pplib.ucClockInfoSize));
2391 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2392 state_index, mode_index,
2393 clock_info);
2394 if (valid)
2395 mode_index++;
2396 }
2397 } else {
2398 rdev->pm.power_state[state_index].clock_info[0].mclk =
2399 rdev->clock.default_mclk;
2400 rdev->pm.power_state[state_index].clock_info[0].sclk =
2401 rdev->clock.default_sclk;
2402 mode_index++;
2403 }
2404 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2405 if (mode_index) {
2406 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2407 non_clock_info);
2408 state_index++;
2409 }
2410 }
2411 /* if multiple clock modes, mark the lowest as no display */
2412 for (i = 0; i < state_index; i++) {
2413 if (rdev->pm.power_state[i].num_clock_modes > 1)
2414 rdev->pm.power_state[i].clock_info[0].flags |=
2415 RADEON_PM_MODE_NO_DISPLAY;
2416 }
2417 /* first mode is usually default */
2418 if (rdev->pm.default_power_state_index == -1) {
2419 rdev->pm.power_state[0].type =
2420 POWER_STATE_TYPE_DEFAULT;
2421 rdev->pm.default_power_state_index = 0;
2422 rdev->pm.power_state[0].default_clock_mode =
2423 &rdev->pm.power_state[0].clock_info[0];
2424 }
2425 return state_index;
2426 }
2427
2428 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2429 {
2430 struct radeon_mode_info *mode_info = &rdev->mode_info;
2431 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2432 union pplib_power_state *power_state;
2433 int i, j, non_clock_array_index, clock_array_index;
2434 int state_index = 0, mode_index = 0;
2435 union pplib_clock_info *clock_info;
2436 struct StateArray *state_array;
2437 struct ClockInfoArray *clock_info_array;
2438 struct NonClockInfoArray *non_clock_info_array;
2439 bool valid;
2440 union power_info *power_info;
2441 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2442 u16 data_offset;
2443 u8 frev, crev;
2444
2445 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2446 &frev, &crev, &data_offset))
2447 return state_index;
2448 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2449
2450 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2451 state_array = (struct StateArray *)
2452 (mode_info->atom_context->bios + data_offset +
2453 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2454 clock_info_array = (struct ClockInfoArray *)
2455 (mode_info->atom_context->bios + data_offset +
2456 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2457 non_clock_info_array = (struct NonClockInfoArray *)
2458 (mode_info->atom_context->bios + data_offset +
2459 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2460 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2461 state_array->ucNumEntries, GFP_KERNEL);
2462 if (!rdev->pm.power_state)
2463 return state_index;
2464 for (i = 0; i < state_array->ucNumEntries; i++) {
2465 mode_index = 0;
2466 power_state = (union pplib_power_state *)&state_array->states[i];
2467 /* XXX this might be an inagua bug... */
2468 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2469 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2470 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2471 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2472 (power_state->v2.ucNumDPMLevels ?
2473 power_state->v2.ucNumDPMLevels : 1),
2474 GFP_KERNEL);
2475 if (!rdev->pm.power_state[i].clock_info)
2476 return state_index;
2477 if (power_state->v2.ucNumDPMLevels) {
2478 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2479 clock_array_index = power_state->v2.clockInfoIndex[j];
2480 /* XXX this might be an inagua bug... */
2481 if (clock_array_index >= clock_info_array->ucNumEntries)
2482 continue;
2483 clock_info = (union pplib_clock_info *)
2484 &clock_info_array->clockInfo[clock_array_index];
2485 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2486 state_index, mode_index,
2487 clock_info);
2488 if (valid)
2489 mode_index++;
2490 }
2491 } else {
2492 rdev->pm.power_state[state_index].clock_info[0].mclk =
2493 rdev->clock.default_mclk;
2494 rdev->pm.power_state[state_index].clock_info[0].sclk =
2495 rdev->clock.default_sclk;
2496 mode_index++;
2497 }
2498 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2499 if (mode_index) {
2500 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2501 non_clock_info);
2502 state_index++;
2503 }
2504 }
2505 /* if multiple clock modes, mark the lowest as no display */
2506 for (i = 0; i < state_index; i++) {
2507 if (rdev->pm.power_state[i].num_clock_modes > 1)
2508 rdev->pm.power_state[i].clock_info[0].flags |=
2509 RADEON_PM_MODE_NO_DISPLAY;
2510 }
2511 /* first mode is usually default */
2512 if (rdev->pm.default_power_state_index == -1) {
2513 rdev->pm.power_state[0].type =
2514 POWER_STATE_TYPE_DEFAULT;
2515 rdev->pm.default_power_state_index = 0;
2516 rdev->pm.power_state[0].default_clock_mode =
2517 &rdev->pm.power_state[0].clock_info[0];
2518 }
2519 return state_index;
2520 }
2521
2522 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2523 {
2524 struct radeon_mode_info *mode_info = &rdev->mode_info;
2525 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2526 u16 data_offset;
2527 u8 frev, crev;
2528 int state_index = 0;
2529
2530 rdev->pm.default_power_state_index = -1;
2531
2532 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2533 &frev, &crev, &data_offset)) {
2534 switch (frev) {
2535 case 1:
2536 case 2:
2537 case 3:
2538 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2539 break;
2540 case 4:
2541 case 5:
2542 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2543 break;
2544 case 6:
2545 state_index = radeon_atombios_parse_power_table_6(rdev);
2546 break;
2547 default:
2548 break;
2549 }
2550 } else {
2551 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2552 if (rdev->pm.power_state) {
2553 rdev->pm.power_state[0].clock_info =
2554 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2555 if (rdev->pm.power_state[0].clock_info) {
2556 /* add the default mode */
2557 rdev->pm.power_state[state_index].type =
2558 POWER_STATE_TYPE_DEFAULT;
2559 rdev->pm.power_state[state_index].num_clock_modes = 1;
2560 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2561 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2562 rdev->pm.power_state[state_index].default_clock_mode =
2563 &rdev->pm.power_state[state_index].clock_info[0];
2564 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2565 rdev->pm.power_state[state_index].pcie_lanes = 16;
2566 rdev->pm.default_power_state_index = state_index;
2567 rdev->pm.power_state[state_index].flags = 0;
2568 state_index++;
2569 }
2570 }
2571 }
2572
2573 rdev->pm.num_power_states = state_index;
2574
2575 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2576 rdev->pm.current_clock_mode_index = 0;
2577 if (rdev->pm.default_power_state_index >= 0)
2578 rdev->pm.current_vddc =
2579 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2580 else
2581 rdev->pm.current_vddc = 0;
2582 }
2583
2584 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2585 {
2586 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2587 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2588
2589 args.ucEnable = enable;
2590
2591 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2592 }
2593
2594 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2595 {
2596 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2597 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2598
2599 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2600 return le32_to_cpu(args.ulReturnEngineClock);
2601 }
2602
2603 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2604 {
2605 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2606 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2607
2608 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2609 return le32_to_cpu(args.ulReturnMemoryClock);
2610 }
2611
2612 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2613 uint32_t eng_clock)
2614 {
2615 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2616 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2617
2618 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
2619
2620 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2621 }
2622
2623 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2624 uint32_t mem_clock)
2625 {
2626 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2627 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2628
2629 if (rdev->flags & RADEON_IS_IGP)
2630 return;
2631
2632 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
2633
2634 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2635 }
2636
2637 union set_voltage {
2638 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2639 struct _SET_VOLTAGE_PARAMETERS v1;
2640 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2641 };
2642
2643 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
2644 {
2645 union set_voltage args;
2646 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2647 u8 frev, crev, volt_index = voltage_level;
2648
2649 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2650 return;
2651
2652 /* 0xff01 is a flag rather then an actual voltage */
2653 if (voltage_level == 0xff01)
2654 return;
2655
2656 switch (crev) {
2657 case 1:
2658 args.v1.ucVoltageType = voltage_type;
2659 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2660 args.v1.ucVoltageIndex = volt_index;
2661 break;
2662 case 2:
2663 args.v2.ucVoltageType = voltage_type;
2664 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2665 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
2666 break;
2667 default:
2668 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2669 return;
2670 }
2671
2672 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2673 }
2674
2675 int radeon_atom_get_max_vddc(struct radeon_device *rdev,
2676 u16 *voltage)
2677 {
2678 union set_voltage args;
2679 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2680 u8 frev, crev;
2681
2682 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2683 return -EINVAL;
2684
2685 switch (crev) {
2686 case 1:
2687 return -EINVAL;
2688 case 2:
2689 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
2690 args.v2.ucVoltageMode = 0;
2691 args.v2.usVoltageLevel = 0;
2692
2693 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2694
2695 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
2696 break;
2697 default:
2698 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2699 return -EINVAL;
2700 }
2701
2702 return 0;
2703 }
2704
2705 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2706 {
2707 struct radeon_device *rdev = dev->dev_private;
2708 uint32_t bios_2_scratch, bios_6_scratch;
2709
2710 if (rdev->family >= CHIP_R600) {
2711 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2712 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2713 } else {
2714 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2715 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2716 }
2717
2718 /* let the bios control the backlight */
2719 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2720
2721 /* tell the bios not to handle mode switching */
2722 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
2723
2724 if (rdev->family >= CHIP_R600) {
2725 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2726 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2727 } else {
2728 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2729 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2730 }
2731
2732 }
2733
2734 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2735 {
2736 uint32_t scratch_reg;
2737 int i;
2738
2739 if (rdev->family >= CHIP_R600)
2740 scratch_reg = R600_BIOS_0_SCRATCH;
2741 else
2742 scratch_reg = RADEON_BIOS_0_SCRATCH;
2743
2744 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2745 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2746 }
2747
2748 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2749 {
2750 uint32_t scratch_reg;
2751 int i;
2752
2753 if (rdev->family >= CHIP_R600)
2754 scratch_reg = R600_BIOS_0_SCRATCH;
2755 else
2756 scratch_reg = RADEON_BIOS_0_SCRATCH;
2757
2758 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2759 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2760 }
2761
2762 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2763 {
2764 struct drm_device *dev = encoder->dev;
2765 struct radeon_device *rdev = dev->dev_private;
2766 uint32_t bios_6_scratch;
2767
2768 if (rdev->family >= CHIP_R600)
2769 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2770 else
2771 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2772
2773 if (lock) {
2774 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2775 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
2776 } else {
2777 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2778 bios_6_scratch |= ATOM_S6_ACC_MODE;
2779 }
2780
2781 if (rdev->family >= CHIP_R600)
2782 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2783 else
2784 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2785 }
2786
2787 /* at some point we may want to break this out into individual functions */
2788 void
2789 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2790 struct drm_encoder *encoder,
2791 bool connected)
2792 {
2793 struct drm_device *dev = connector->dev;
2794 struct radeon_device *rdev = dev->dev_private;
2795 struct radeon_connector *radeon_connector =
2796 to_radeon_connector(connector);
2797 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2798 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2799
2800 if (rdev->family >= CHIP_R600) {
2801 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2802 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2803 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2804 } else {
2805 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2806 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2807 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2808 }
2809
2810 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2811 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2812 if (connected) {
2813 DRM_DEBUG_KMS("TV1 connected\n");
2814 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2815 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2816 } else {
2817 DRM_DEBUG_KMS("TV1 disconnected\n");
2818 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2819 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2820 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2821 }
2822 }
2823 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2824 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2825 if (connected) {
2826 DRM_DEBUG_KMS("CV connected\n");
2827 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2828 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2829 } else {
2830 DRM_DEBUG_KMS("CV disconnected\n");
2831 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2832 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2833 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2834 }
2835 }
2836 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2837 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2838 if (connected) {
2839 DRM_DEBUG_KMS("LCD1 connected\n");
2840 bios_0_scratch |= ATOM_S0_LCD1;
2841 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2842 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2843 } else {
2844 DRM_DEBUG_KMS("LCD1 disconnected\n");
2845 bios_0_scratch &= ~ATOM_S0_LCD1;
2846 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2847 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2848 }
2849 }
2850 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2851 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2852 if (connected) {
2853 DRM_DEBUG_KMS("CRT1 connected\n");
2854 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2855 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2856 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2857 } else {
2858 DRM_DEBUG_KMS("CRT1 disconnected\n");
2859 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2860 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2861 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2862 }
2863 }
2864 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2865 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2866 if (connected) {
2867 DRM_DEBUG_KMS("CRT2 connected\n");
2868 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2869 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2870 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2871 } else {
2872 DRM_DEBUG_KMS("CRT2 disconnected\n");
2873 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2874 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2875 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2876 }
2877 }
2878 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2879 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2880 if (connected) {
2881 DRM_DEBUG_KMS("DFP1 connected\n");
2882 bios_0_scratch |= ATOM_S0_DFP1;
2883 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2884 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2885 } else {
2886 DRM_DEBUG_KMS("DFP1 disconnected\n");
2887 bios_0_scratch &= ~ATOM_S0_DFP1;
2888 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2889 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2890 }
2891 }
2892 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2893 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2894 if (connected) {
2895 DRM_DEBUG_KMS("DFP2 connected\n");
2896 bios_0_scratch |= ATOM_S0_DFP2;
2897 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2898 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2899 } else {
2900 DRM_DEBUG_KMS("DFP2 disconnected\n");
2901 bios_0_scratch &= ~ATOM_S0_DFP2;
2902 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2903 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2904 }
2905 }
2906 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2907 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2908 if (connected) {
2909 DRM_DEBUG_KMS("DFP3 connected\n");
2910 bios_0_scratch |= ATOM_S0_DFP3;
2911 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2912 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2913 } else {
2914 DRM_DEBUG_KMS("DFP3 disconnected\n");
2915 bios_0_scratch &= ~ATOM_S0_DFP3;
2916 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2917 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2918 }
2919 }
2920 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2921 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2922 if (connected) {
2923 DRM_DEBUG_KMS("DFP4 connected\n");
2924 bios_0_scratch |= ATOM_S0_DFP4;
2925 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2926 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2927 } else {
2928 DRM_DEBUG_KMS("DFP4 disconnected\n");
2929 bios_0_scratch &= ~ATOM_S0_DFP4;
2930 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2931 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2932 }
2933 }
2934 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2935 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2936 if (connected) {
2937 DRM_DEBUG_KMS("DFP5 connected\n");
2938 bios_0_scratch |= ATOM_S0_DFP5;
2939 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2940 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2941 } else {
2942 DRM_DEBUG_KMS("DFP5 disconnected\n");
2943 bios_0_scratch &= ~ATOM_S0_DFP5;
2944 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2945 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2946 }
2947 }
2948 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
2949 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
2950 if (connected) {
2951 DRM_DEBUG_KMS("DFP6 connected\n");
2952 bios_0_scratch |= ATOM_S0_DFP6;
2953 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
2954 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
2955 } else {
2956 DRM_DEBUG_KMS("DFP6 disconnected\n");
2957 bios_0_scratch &= ~ATOM_S0_DFP6;
2958 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
2959 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
2960 }
2961 }
2962
2963 if (rdev->family >= CHIP_R600) {
2964 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2965 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2966 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2967 } else {
2968 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2969 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2970 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2971 }
2972 }
2973
2974 void
2975 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2976 {
2977 struct drm_device *dev = encoder->dev;
2978 struct radeon_device *rdev = dev->dev_private;
2979 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2980 uint32_t bios_3_scratch;
2981
2982 if (ASIC_IS_DCE4(rdev))
2983 return;
2984
2985 if (rdev->family >= CHIP_R600)
2986 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2987 else
2988 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2989
2990 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2991 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2992 bios_3_scratch |= (crtc << 18);
2993 }
2994 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2995 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2996 bios_3_scratch |= (crtc << 24);
2997 }
2998 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2999 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
3000 bios_3_scratch |= (crtc << 16);
3001 }
3002 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3003 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
3004 bios_3_scratch |= (crtc << 20);
3005 }
3006 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3007 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
3008 bios_3_scratch |= (crtc << 17);
3009 }
3010 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3011 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
3012 bios_3_scratch |= (crtc << 19);
3013 }
3014 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3015 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
3016 bios_3_scratch |= (crtc << 23);
3017 }
3018 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3019 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
3020 bios_3_scratch |= (crtc << 25);
3021 }
3022
3023 if (rdev->family >= CHIP_R600)
3024 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3025 else
3026 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3027 }
3028
3029 void
3030 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3031 {
3032 struct drm_device *dev = encoder->dev;
3033 struct radeon_device *rdev = dev->dev_private;
3034 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3035 uint32_t bios_2_scratch;
3036
3037 if (ASIC_IS_DCE4(rdev))
3038 return;
3039
3040 if (rdev->family >= CHIP_R600)
3041 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
3042 else
3043 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
3044
3045 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3046 if (on)
3047 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
3048 else
3049 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
3050 }
3051 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3052 if (on)
3053 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
3054 else
3055 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
3056 }
3057 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3058 if (on)
3059 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
3060 else
3061 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
3062 }
3063 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3064 if (on)
3065 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
3066 else
3067 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
3068 }
3069 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3070 if (on)
3071 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
3072 else
3073 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
3074 }
3075 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3076 if (on)
3077 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
3078 else
3079 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
3080 }
3081 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3082 if (on)
3083 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
3084 else
3085 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
3086 }
3087 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3088 if (on)
3089 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
3090 else
3091 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
3092 }
3093 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
3094 if (on)
3095 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
3096 else
3097 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
3098 }
3099 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
3100 if (on)
3101 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
3102 else
3103 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
3104 }
3105
3106 if (rdev->family >= CHIP_R600)
3107 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3108 else
3109 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
3110 }