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OMAPDSS: VENC: fix NULL pointer dereference in DSS2 VENC sysfs debug attr on OMAP4
[zen-stable.git] / drivers / gpu / drm / radeon / radeon_i2c.c
blob43e444393d02de1d43c650fb79ca6e636d4fada6
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <linux/export.h>
27
28 #include "drmP.h"
29 #include "radeon_drm.h"
30 #include "radeon.h"
31 #include "atom.h"
32
33 /**
34 * radeon_ddc_probe
35 *
36 */
37 bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
38 {
39 u8 out = 0x0;
40 u8 buf[8];
41 int ret;
42 struct i2c_msg msgs[] = {
43 {
44 .addr = 0x50,
45 .flags = 0,
46 .len = 1,
47 .buf = &out,
48 },
49 {
50 .addr = 0x50,
51 .flags = I2C_M_RD,
52 .len = 8,
53 .buf = buf,
54 }
55 };
56
57 /* on hw with routers, select right port */
58 if (radeon_connector->router.ddc_valid)
59 radeon_router_select_ddc_port(radeon_connector);
60
61 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
62 if (ret != 2)
63 /* Couldn't find an accessible DDC on this connector */
64 return false;
65 /* Probe also for valid EDID header
66 * EDID header starts with:
67 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
68 * Only the first 6 bytes must be valid as
69 * drm_edid_block_valid() can fix the last 2 bytes */
70 if (drm_edid_header_is_valid(buf) < 6) {
71 /* Couldn't find an accessible EDID on this
72 * connector */
73 return false;
74 }
75 return true;
76 }
77
78 /* bit banging i2c */
79
80 static int pre_xfer(struct i2c_adapter *i2c_adap)
81 {
82 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
83 struct radeon_device *rdev = i2c->dev->dev_private;
84 struct radeon_i2c_bus_rec *rec = &i2c->rec;
85 uint32_t temp;
86
87 /* RV410 appears to have a bug where the hw i2c in reset
88 * holds the i2c port in a bad state - switch hw i2c away before
89 * doing DDC - do this for all r200s/r300s/r400s for safety sake
90 */
91 if (rec->hw_capable) {
92 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
93 u32 reg;
94
95 if (rdev->family >= CHIP_RV350)
96 reg = RADEON_GPIO_MONID;
97 else if ((rdev->family == CHIP_R300) ||
98 (rdev->family == CHIP_R350))
99 reg = RADEON_GPIO_DVI_DDC;
100 else
101 reg = RADEON_GPIO_CRT2_DDC;
102
103 mutex_lock(&rdev->dc_hw_i2c_mutex);
104 if (rec->a_clk_reg == reg) {
105 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
106 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
107 } else {
108 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
109 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
110 }
111 mutex_unlock(&rdev->dc_hw_i2c_mutex);
112 }
113 }
114
115 /* switch the pads to ddc mode */
116 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) {
117 temp = RREG32(rec->mask_clk_reg);
118 temp &= ~(1 << 16);
119 WREG32(rec->mask_clk_reg, temp);
120 }
121
122 /* clear the output pin values */
123 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
124 WREG32(rec->a_clk_reg, temp);
125
126 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
127 WREG32(rec->a_data_reg, temp);
128
129 /* set the pins to input */
130 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
131 WREG32(rec->en_clk_reg, temp);
132
133 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
134 WREG32(rec->en_data_reg, temp);
135
136 /* mask the gpio pins for software use */
137 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
138 WREG32(rec->mask_clk_reg, temp);
139 temp = RREG32(rec->mask_clk_reg);
140
141 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
142 WREG32(rec->mask_data_reg, temp);
143 temp = RREG32(rec->mask_data_reg);
144
145 return 0;
146 }
147
148 static void post_xfer(struct i2c_adapter *i2c_adap)
149 {
150 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
151 struct radeon_device *rdev = i2c->dev->dev_private;
152 struct radeon_i2c_bus_rec *rec = &i2c->rec;
153 uint32_t temp;
154
155 /* unmask the gpio pins for software use */
156 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
157 WREG32(rec->mask_clk_reg, temp);
158 temp = RREG32(rec->mask_clk_reg);
159
160 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
161 WREG32(rec->mask_data_reg, temp);
162 temp = RREG32(rec->mask_data_reg);
163 }
164
165 static int get_clock(void *i2c_priv)
166 {
167 struct radeon_i2c_chan *i2c = i2c_priv;
168 struct radeon_device *rdev = i2c->dev->dev_private;
169 struct radeon_i2c_bus_rec *rec = &i2c->rec;
170 uint32_t val;
171
172 /* read the value off the pin */
173 val = RREG32(rec->y_clk_reg);
174 val &= rec->y_clk_mask;
175
176 return (val != 0);
177 }
178
179
180 static int get_data(void *i2c_priv)
181 {
182 struct radeon_i2c_chan *i2c = i2c_priv;
183 struct radeon_device *rdev = i2c->dev->dev_private;
184 struct radeon_i2c_bus_rec *rec = &i2c->rec;
185 uint32_t val;
186
187 /* read the value off the pin */
188 val = RREG32(rec->y_data_reg);
189 val &= rec->y_data_mask;
190
191 return (val != 0);
192 }
193
194 static void set_clock(void *i2c_priv, int clock)
195 {
196 struct radeon_i2c_chan *i2c = i2c_priv;
197 struct radeon_device *rdev = i2c->dev->dev_private;
198 struct radeon_i2c_bus_rec *rec = &i2c->rec;
199 uint32_t val;
200
201 /* set pin direction */
202 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
203 val |= clock ? 0 : rec->en_clk_mask;
204 WREG32(rec->en_clk_reg, val);
205 }
206
207 static void set_data(void *i2c_priv, int data)
208 {
209 struct radeon_i2c_chan *i2c = i2c_priv;
210 struct radeon_device *rdev = i2c->dev->dev_private;
211 struct radeon_i2c_bus_rec *rec = &i2c->rec;
212 uint32_t val;
213
214 /* set pin direction */
215 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
216 val |= data ? 0 : rec->en_data_mask;
217 WREG32(rec->en_data_reg, val);
218 }
219
220 /* hw i2c */
221
222 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
223 {
224 u32 sclk = rdev->pm.current_sclk;
225 u32 prescale = 0;
226 u32 nm;
227 u8 n, m, loop;
228 int i2c_clock;
229
230 switch (rdev->family) {
231 case CHIP_R100:
232 case CHIP_RV100:
233 case CHIP_RS100:
234 case CHIP_RV200:
235 case CHIP_RS200:
236 case CHIP_R200:
237 case CHIP_RV250:
238 case CHIP_RS300:
239 case CHIP_RV280:
240 case CHIP_R300:
241 case CHIP_R350:
242 case CHIP_RV350:
243 i2c_clock = 60;
244 nm = (sclk * 10) / (i2c_clock * 4);
245 for (loop = 1; loop < 255; loop++) {
246 if ((nm / loop) < loop)
247 break;
248 }
249 n = loop - 1;
250 m = loop - 2;
251 prescale = m | (n << 8);
252 break;
253 case CHIP_RV380:
254 case CHIP_RS400:
255 case CHIP_RS480:
256 case CHIP_R420:
257 case CHIP_R423:
258 case CHIP_RV410:
259 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
260 break;
261 case CHIP_RS600:
262 case CHIP_RS690:
263 case CHIP_RS740:
264 /* todo */
265 break;
266 case CHIP_RV515:
267 case CHIP_R520:
268 case CHIP_RV530:
269 case CHIP_RV560:
270 case CHIP_RV570:
271 case CHIP_R580:
272 i2c_clock = 50;
273 if (rdev->family == CHIP_R520)
274 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
275 else
276 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
277 break;
278 case CHIP_R600:
279 case CHIP_RV610:
280 case CHIP_RV630:
281 case CHIP_RV670:
282 /* todo */
283 break;
284 case CHIP_RV620:
285 case CHIP_RV635:
286 case CHIP_RS780:
287 case CHIP_RS880:
288 case CHIP_RV770:
289 case CHIP_RV730:
290 case CHIP_RV710:
291 case CHIP_RV740:
292 /* todo */
293 break;
294 case CHIP_CEDAR:
295 case CHIP_REDWOOD:
296 case CHIP_JUNIPER:
297 case CHIP_CYPRESS:
298 case CHIP_HEMLOCK:
299 /* todo */
300 break;
301 default:
302 DRM_ERROR("i2c: unhandled radeon chip\n");
303 break;
304 }
305 return prescale;
306 }
307
308
309 /* hw i2c engine for r1xx-4xx hardware
310 * hw can buffer up to 15 bytes
311 */
312 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
313 struct i2c_msg *msgs, int num)
314 {
315 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
316 struct radeon_device *rdev = i2c->dev->dev_private;
317 struct radeon_i2c_bus_rec *rec = &i2c->rec;
318 struct i2c_msg *p;
319 int i, j, k, ret = num;
320 u32 prescale;
321 u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
322 u32 tmp, reg;
323
324 mutex_lock(&rdev->dc_hw_i2c_mutex);
325 /* take the pm lock since we need a constant sclk */
326 mutex_lock(&rdev->pm.mutex);
327
328 prescale = radeon_get_i2c_prescale(rdev);
329
330 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
331 RADEON_I2C_DRIVE_EN |
332 RADEON_I2C_START |
333 RADEON_I2C_STOP |
334 RADEON_I2C_GO);
335
336 if (rdev->is_atom_bios) {
337 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
338 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
339 }
340
341 if (rec->mm_i2c) {
342 i2c_cntl_0 = RADEON_I2C_CNTL_0;
343 i2c_cntl_1 = RADEON_I2C_CNTL_1;
344 i2c_data = RADEON_I2C_DATA;
345 } else {
346 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
347 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
348 i2c_data = RADEON_DVI_I2C_DATA;
349
350 switch (rdev->family) {
351 case CHIP_R100:
352 case CHIP_RV100:
353 case CHIP_RS100:
354 case CHIP_RV200:
355 case CHIP_RS200:
356 case CHIP_RS300:
357 switch (rec->mask_clk_reg) {
358 case RADEON_GPIO_DVI_DDC:
359 /* no gpio select bit */
360 break;
361 default:
362 DRM_ERROR("gpio not supported with hw i2c\n");
363 ret = -EINVAL;
364 goto done;
365 }
366 break;
367 case CHIP_R200:
368 /* only bit 4 on r200 */
369 switch (rec->mask_clk_reg) {
370 case RADEON_GPIO_DVI_DDC:
371 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
372 break;
373 case RADEON_GPIO_MONID:
374 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
375 break;
376 default:
377 DRM_ERROR("gpio not supported with hw i2c\n");
378 ret = -EINVAL;
379 goto done;
380 }
381 break;
382 case CHIP_RV250:
383 case CHIP_RV280:
384 /* bits 3 and 4 */
385 switch (rec->mask_clk_reg) {
386 case RADEON_GPIO_DVI_DDC:
387 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
388 break;
389 case RADEON_GPIO_VGA_DDC:
390 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
391 break;
392 case RADEON_GPIO_CRT2_DDC:
393 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
394 break;
395 default:
396 DRM_ERROR("gpio not supported with hw i2c\n");
397 ret = -EINVAL;
398 goto done;
399 }
400 break;
401 case CHIP_R300:
402 case CHIP_R350:
403 /* only bit 4 on r300/r350 */
404 switch (rec->mask_clk_reg) {
405 case RADEON_GPIO_VGA_DDC:
406 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
407 break;
408 case RADEON_GPIO_DVI_DDC:
409 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
410 break;
411 default:
412 DRM_ERROR("gpio not supported with hw i2c\n");
413 ret = -EINVAL;
414 goto done;
415 }
416 break;
417 case CHIP_RV350:
418 case CHIP_RV380:
419 case CHIP_R420:
420 case CHIP_R423:
421 case CHIP_RV410:
422 case CHIP_RS400:
423 case CHIP_RS480:
424 /* bits 3 and 4 */
425 switch (rec->mask_clk_reg) {
426 case RADEON_GPIO_VGA_DDC:
427 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
428 break;
429 case RADEON_GPIO_DVI_DDC:
430 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
431 break;
432 case RADEON_GPIO_MONID:
433 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
434 break;
435 default:
436 DRM_ERROR("gpio not supported with hw i2c\n");
437 ret = -EINVAL;
438 goto done;
439 }
440 break;
441 default:
442 DRM_ERROR("unsupported asic\n");
443 ret = -EINVAL;
444 goto done;
445 break;
446 }
447 }
448
449 /* check for bus probe */
450 p = &msgs[0];
451 if ((num == 1) && (p->len == 0)) {
452 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
453 RADEON_I2C_NACK |
454 RADEON_I2C_HALT |
455 RADEON_I2C_SOFT_RST));
456 WREG32(i2c_data, (p->addr << 1) & 0xff);
457 WREG32(i2c_data, 0);
458 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
459 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
460 RADEON_I2C_EN |
461 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
462 WREG32(i2c_cntl_0, reg);
463 for (k = 0; k < 32; k++) {
464 udelay(10);
465 tmp = RREG32(i2c_cntl_0);
466 if (tmp & RADEON_I2C_GO)
467 continue;
468 tmp = RREG32(i2c_cntl_0);
469 if (tmp & RADEON_I2C_DONE)
470 break;
471 else {
472 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
473 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
474 ret = -EIO;
475 goto done;
476 }
477 }
478 goto done;
479 }
480
481 for (i = 0; i < num; i++) {
482 p = &msgs[i];
483 for (j = 0; j < p->len; j++) {
484 if (p->flags & I2C_M_RD) {
485 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
486 RADEON_I2C_NACK |
487 RADEON_I2C_HALT |
488 RADEON_I2C_SOFT_RST));
489 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
490 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
491 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
492 RADEON_I2C_EN |
493 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
494 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
495 for (k = 0; k < 32; k++) {
496 udelay(10);
497 tmp = RREG32(i2c_cntl_0);
498 if (tmp & RADEON_I2C_GO)
499 continue;
500 tmp = RREG32(i2c_cntl_0);
501 if (tmp & RADEON_I2C_DONE)
502 break;
503 else {
504 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
505 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
506 ret = -EIO;
507 goto done;
508 }
509 }
510 p->buf[j] = RREG32(i2c_data) & 0xff;
511 } else {
512 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
513 RADEON_I2C_NACK |
514 RADEON_I2C_HALT |
515 RADEON_I2C_SOFT_RST));
516 WREG32(i2c_data, (p->addr << 1) & 0xff);
517 WREG32(i2c_data, p->buf[j]);
518 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
519 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
520 RADEON_I2C_EN |
521 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
522 WREG32(i2c_cntl_0, reg);
523 for (k = 0; k < 32; k++) {
524 udelay(10);
525 tmp = RREG32(i2c_cntl_0);
526 if (tmp & RADEON_I2C_GO)
527 continue;
528 tmp = RREG32(i2c_cntl_0);
529 if (tmp & RADEON_I2C_DONE)
530 break;
531 else {
532 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
533 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
534 ret = -EIO;
535 goto done;
536 }
537 }
538 }
539 }
540 }
541
542 done:
543 WREG32(i2c_cntl_0, 0);
544 WREG32(i2c_cntl_1, 0);
545 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
546 RADEON_I2C_NACK |
547 RADEON_I2C_HALT |
548 RADEON_I2C_SOFT_RST));
549
550 if (rdev->is_atom_bios) {
551 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
552 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
553 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
554 }
555
556 mutex_unlock(&rdev->pm.mutex);
557 mutex_unlock(&rdev->dc_hw_i2c_mutex);
558
559 return ret;
560 }
561
562 /* hw i2c engine for r5xx hardware
563 * hw can buffer up to 15 bytes
564 */
565 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
566 struct i2c_msg *msgs, int num)
567 {
568 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
569 struct radeon_device *rdev = i2c->dev->dev_private;
570 struct radeon_i2c_bus_rec *rec = &i2c->rec;
571 struct i2c_msg *p;
572 int i, j, remaining, current_count, buffer_offset, ret = num;
573 u32 prescale;
574 u32 tmp, reg;
575 u32 saved1, saved2;
576
577 mutex_lock(&rdev->dc_hw_i2c_mutex);
578 /* take the pm lock since we need a constant sclk */
579 mutex_lock(&rdev->pm.mutex);
580
581 prescale = radeon_get_i2c_prescale(rdev);
582
583 /* clear gpio mask bits */
584 tmp = RREG32(rec->mask_clk_reg);
585 tmp &= ~rec->mask_clk_mask;
586 WREG32(rec->mask_clk_reg, tmp);
587 tmp = RREG32(rec->mask_clk_reg);
588
589 tmp = RREG32(rec->mask_data_reg);
590 tmp &= ~rec->mask_data_mask;
591 WREG32(rec->mask_data_reg, tmp);
592 tmp = RREG32(rec->mask_data_reg);
593
594 /* clear pin values */
595 tmp = RREG32(rec->a_clk_reg);
596 tmp &= ~rec->a_clk_mask;
597 WREG32(rec->a_clk_reg, tmp);
598 tmp = RREG32(rec->a_clk_reg);
599
600 tmp = RREG32(rec->a_data_reg);
601 tmp &= ~rec->a_data_mask;
602 WREG32(rec->a_data_reg, tmp);
603 tmp = RREG32(rec->a_data_reg);
604
605 /* set the pins to input */
606 tmp = RREG32(rec->en_clk_reg);
607 tmp &= ~rec->en_clk_mask;
608 WREG32(rec->en_clk_reg, tmp);
609 tmp = RREG32(rec->en_clk_reg);
610
611 tmp = RREG32(rec->en_data_reg);
612 tmp &= ~rec->en_data_mask;
613 WREG32(rec->en_data_reg, tmp);
614 tmp = RREG32(rec->en_data_reg);
615
616 /* */
617 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
618 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
619 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
620 saved2 = RREG32(0x494);
621 WREG32(0x494, saved2 | 0x1);
622
623 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
624 for (i = 0; i < 50; i++) {
625 udelay(1);
626 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
627 break;
628 }
629 if (i == 50) {
630 DRM_ERROR("failed to get i2c bus\n");
631 ret = -EBUSY;
632 goto done;
633 }
634
635 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
636 switch (rec->mask_clk_reg) {
637 case AVIVO_DC_GPIO_DDC1_MASK:
638 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
639 break;
640 case AVIVO_DC_GPIO_DDC2_MASK:
641 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
642 break;
643 case AVIVO_DC_GPIO_DDC3_MASK:
644 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
645 break;
646 default:
647 DRM_ERROR("gpio not supported with hw i2c\n");
648 ret = -EINVAL;
649 goto done;
650 }
651
652 /* check for bus probe */
653 p = &msgs[0];
654 if ((num == 1) && (p->len == 0)) {
655 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
656 AVIVO_DC_I2C_NACK |
657 AVIVO_DC_I2C_HALT));
658 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
659 udelay(1);
660 WREG32(AVIVO_DC_I2C_RESET, 0);
661
662 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
663 WREG32(AVIVO_DC_I2C_DATA, 0);
664
665 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
666 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
667 AVIVO_DC_I2C_DATA_COUNT(1) |
668 (prescale << 16)));
669 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
670 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
671 for (j = 0; j < 200; j++) {
672 udelay(50);
673 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
674 if (tmp & AVIVO_DC_I2C_GO)
675 continue;
676 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
677 if (tmp & AVIVO_DC_I2C_DONE)
678 break;
679 else {
680 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
681 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
682 ret = -EIO;
683 goto done;
684 }
685 }
686 goto done;
687 }
688
689 for (i = 0; i < num; i++) {
690 p = &msgs[i];
691 remaining = p->len;
692 buffer_offset = 0;
693 if (p->flags & I2C_M_RD) {
694 while (remaining) {
695 if (remaining > 15)
696 current_count = 15;
697 else
698 current_count = remaining;
699 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
700 AVIVO_DC_I2C_NACK |
701 AVIVO_DC_I2C_HALT));
702 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
703 udelay(1);
704 WREG32(AVIVO_DC_I2C_RESET, 0);
705
706 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
707 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
708 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
709 AVIVO_DC_I2C_DATA_COUNT(current_count) |
710 (prescale << 16)));
711 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
712 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
713 for (j = 0; j < 200; j++) {
714 udelay(50);
715 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
716 if (tmp & AVIVO_DC_I2C_GO)
717 continue;
718 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
719 if (tmp & AVIVO_DC_I2C_DONE)
720 break;
721 else {
722 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
723 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
724 ret = -EIO;
725 goto done;
726 }
727 }
728 for (j = 0; j < current_count; j++)
729 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
730 remaining -= current_count;
731 buffer_offset += current_count;
732 }
733 } else {
734 while (remaining) {
735 if (remaining > 15)
736 current_count = 15;
737 else
738 current_count = remaining;
739 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
740 AVIVO_DC_I2C_NACK |
741 AVIVO_DC_I2C_HALT));
742 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
743 udelay(1);
744 WREG32(AVIVO_DC_I2C_RESET, 0);
745
746 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
747 for (j = 0; j < current_count; j++)
748 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
749
750 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
751 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
752 AVIVO_DC_I2C_DATA_COUNT(current_count) |
753 (prescale << 16)));
754 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
755 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
756 for (j = 0; j < 200; j++) {
757 udelay(50);
758 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
759 if (tmp & AVIVO_DC_I2C_GO)
760 continue;
761 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
762 if (tmp & AVIVO_DC_I2C_DONE)
763 break;
764 else {
765 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
766 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
767 ret = -EIO;
768 goto done;
769 }
770 }
771 remaining -= current_count;
772 buffer_offset += current_count;
773 }
774 }
775 }
776
777 done:
778 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
779 AVIVO_DC_I2C_NACK |
780 AVIVO_DC_I2C_HALT));
781 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
782 udelay(1);
783 WREG32(AVIVO_DC_I2C_RESET, 0);
784
785 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
786 WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
787 WREG32(0x494, saved2);
788 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
789 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
790 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
791
792 mutex_unlock(&rdev->pm.mutex);
793 mutex_unlock(&rdev->dc_hw_i2c_mutex);
794
795 return ret;
796 }
797
798 static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
799 struct i2c_msg *msgs, int num)
800 {
801 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
802 struct radeon_device *rdev = i2c->dev->dev_private;
803 struct radeon_i2c_bus_rec *rec = &i2c->rec;
804 int ret = 0;
805
806 switch (rdev->family) {
807 case CHIP_R100:
808 case CHIP_RV100:
809 case CHIP_RS100:
810 case CHIP_RV200:
811 case CHIP_RS200:
812 case CHIP_R200:
813 case CHIP_RV250:
814 case CHIP_RS300:
815 case CHIP_RV280:
816 case CHIP_R300:
817 case CHIP_R350:
818 case CHIP_RV350:
819 case CHIP_RV380:
820 case CHIP_R420:
821 case CHIP_R423:
822 case CHIP_RV410:
823 case CHIP_RS400:
824 case CHIP_RS480:
825 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
826 break;
827 case CHIP_RS600:
828 case CHIP_RS690:
829 case CHIP_RS740:
830 /* XXX fill in hw i2c implementation */
831 break;
832 case CHIP_RV515:
833 case CHIP_R520:
834 case CHIP_RV530:
835 case CHIP_RV560:
836 case CHIP_RV570:
837 case CHIP_R580:
838 if (rec->mm_i2c)
839 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
840 else
841 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
842 break;
843 case CHIP_R600:
844 case CHIP_RV610:
845 case CHIP_RV630:
846 case CHIP_RV670:
847 /* XXX fill in hw i2c implementation */
848 break;
849 case CHIP_RV620:
850 case CHIP_RV635:
851 case CHIP_RS780:
852 case CHIP_RS880:
853 case CHIP_RV770:
854 case CHIP_RV730:
855 case CHIP_RV710:
856 case CHIP_RV740:
857 /* XXX fill in hw i2c implementation */
858 break;
859 case CHIP_CEDAR:
860 case CHIP_REDWOOD:
861 case CHIP_JUNIPER:
862 case CHIP_CYPRESS:
863 case CHIP_HEMLOCK:
864 /* XXX fill in hw i2c implementation */
865 break;
866 default:
867 DRM_ERROR("i2c: unhandled radeon chip\n");
868 ret = -EIO;
869 break;
870 }
871
872 return ret;
873 }
874
875 static u32 radeon_hw_i2c_func(struct i2c_adapter *adap)
876 {
877 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
878 }
879
880 static const struct i2c_algorithm radeon_i2c_algo = {
881 .master_xfer = radeon_hw_i2c_xfer,
882 .functionality = radeon_hw_i2c_func,
883 };
884
885 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
886 struct radeon_i2c_bus_rec *rec,
887 const char *name)
888 {
889 struct radeon_device *rdev = dev->dev_private;
890 struct radeon_i2c_chan *i2c;
891 int ret;
892
893 /* don't add the mm_i2c bus unless hw_i2c is enabled */
894 if (rec->mm_i2c && (radeon_hw_i2c == 0))
895 return NULL;
896
897 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
898 if (i2c == NULL)
899 return NULL;
900
901 i2c->rec = *rec;
902 i2c->adapter.owner = THIS_MODULE;
903 i2c->adapter.class = I2C_CLASS_DDC;
904 i2c->adapter.dev.parent = &dev->pdev->dev;
905 i2c->dev = dev;
906 i2c_set_adapdata(&i2c->adapter, i2c);
907 if (rec->mm_i2c ||
908 (rec->hw_capable &&
909 radeon_hw_i2c &&
910 ((rdev->family <= CHIP_RS480) ||
911 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) {
912 /* set the radeon hw i2c adapter */
913 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
914 "Radeon i2c hw bus %s", name);
915 i2c->adapter.algo = &radeon_i2c_algo;
916 ret = i2c_add_adapter(&i2c->adapter);
917 if (ret) {
918 DRM_ERROR("Failed to register hw i2c %s\n", name);
919 goto out_free;
920 }
921 } else {
922 /* set the radeon bit adapter */
923 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
924 "Radeon i2c bit bus %s", name);
925 i2c->adapter.algo_data = &i2c->algo.bit;
926 i2c->algo.bit.pre_xfer = pre_xfer;
927 i2c->algo.bit.post_xfer = post_xfer;
928 i2c->algo.bit.setsda = set_data;
929 i2c->algo.bit.setscl = set_clock;
930 i2c->algo.bit.getsda = get_data;
931 i2c->algo.bit.getscl = get_clock;
932 i2c->algo.bit.udelay = 20;
933 /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always
934 * make this, 2 jiffies is a lot more reliable */
935 i2c->algo.bit.timeout = 2;
936 i2c->algo.bit.data = i2c;
937 ret = i2c_bit_add_bus(&i2c->adapter);
938 if (ret) {
939 DRM_ERROR("Failed to register bit i2c %s\n", name);
940 goto out_free;
941 }
942 }
943
944 return i2c;
945 out_free:
946 kfree(i2c);
947 return NULL;
948
949 }
950
951 struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
952 struct radeon_i2c_bus_rec *rec,
953 const char *name)
954 {
955 struct radeon_i2c_chan *i2c;
956 int ret;
957
958 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
959 if (i2c == NULL)
960 return NULL;
961
962 i2c->rec = *rec;
963 i2c->adapter.owner = THIS_MODULE;
964 i2c->adapter.class = I2C_CLASS_DDC;
965 i2c->adapter.dev.parent = &dev->pdev->dev;
966 i2c->dev = dev;
967 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
968 "Radeon aux bus %s", name);
969 i2c_set_adapdata(&i2c->adapter, i2c);
970 i2c->adapter.algo_data = &i2c->algo.dp;
971 i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch;
972 i2c->algo.dp.address = 0;
973 ret = i2c_dp_aux_add_bus(&i2c->adapter);
974 if (ret) {
975 DRM_INFO("Failed to register i2c %s\n", name);
976 goto out_free;
977 }
978
979 return i2c;
980 out_free:
981 kfree(i2c);
982 return NULL;
983
984 }
985
986 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
987 {
988 if (!i2c)
989 return;
990 i2c_del_adapter(&i2c->adapter);
991 kfree(i2c);
992 }
993
994 /* Add the default buses */
995 void radeon_i2c_init(struct radeon_device *rdev)
996 {
997 if (rdev->is_atom_bios)
998 radeon_atombios_i2c_init(rdev);
999 else
1000 radeon_combios_i2c_init(rdev);
1001 }
1002
1003 /* remove all the buses */
1004 void radeon_i2c_fini(struct radeon_device *rdev)
1005 {
1006 int i;
1007
1008 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1009 if (rdev->i2c_bus[i]) {
1010 radeon_i2c_destroy(rdev->i2c_bus[i]);
1011 rdev->i2c_bus[i] = NULL;
1012 }
1013 }
1014 }
1015
1016 /* Add additional buses */
1017 void radeon_i2c_add(struct radeon_device *rdev,
1018 struct radeon_i2c_bus_rec *rec,
1019 const char *name)
1020 {
1021 struct drm_device *dev = rdev->ddev;
1022 int i;
1023
1024 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1025 if (!rdev->i2c_bus[i]) {
1026 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name);
1027 return;
1028 }
1029 }
1030 }
1031
1032 /* looks up bus based on id */
1033 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
1034 struct radeon_i2c_bus_rec *i2c_bus)
1035 {
1036 int i;
1037
1038 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1039 if (rdev->i2c_bus[i] &&
1040 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
1041 return rdev->i2c_bus[i];
1042 }
1043 }
1044 return NULL;
1045 }
1046
1047 struct drm_encoder *radeon_best_encoder(struct drm_connector *connector)
1048 {
1049 return NULL;
1050 }
1051
1052 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
1053 u8 slave_addr,
1054 u8 addr,
1055 u8 *val)
1056 {
1057 u8 out_buf[2];
1058 u8 in_buf[2];
1059 struct i2c_msg msgs[] = {
1060 {
1061 .addr = slave_addr,
1062 .flags = 0,
1063 .len = 1,
1064 .buf = out_buf,
1065 },
1066 {
1067 .addr = slave_addr,
1068 .flags = I2C_M_RD,
1069 .len = 1,
1070 .buf = in_buf,
1071 }
1072 };
1073
1074 out_buf[0] = addr;
1075 out_buf[1] = 0;
1076
1077 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
1078 *val = in_buf[0];
1079 DRM_DEBUG("val = 0x%02x\n", *val);
1080 } else {
1081 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
1082 addr, *val);
1083 }
1084 }
1085
1086 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1087 u8 slave_addr,
1088 u8 addr,
1089 u8 val)
1090 {
1091 uint8_t out_buf[2];
1092 struct i2c_msg msg = {
1093 .addr = slave_addr,
1094 .flags = 0,
1095 .len = 2,
1096 .buf = out_buf,
1097 };
1098
1099 out_buf[0] = addr;
1100 out_buf[1] = val;
1101
1102 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
1103 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",
1104 addr, val);
1105 }
1106
1107 /* ddc router switching */
1108 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector)
1109 {
1110 u8 val;
1111
1112 if (!radeon_connector->router.ddc_valid)
1113 return;
1114
1115 if (!radeon_connector->router_bus)
1116 return;
1117
1118 radeon_i2c_get_byte(radeon_connector->router_bus,
1119 radeon_connector->router.i2c_addr,
1120 0x3, &val);
1121 val &= ~radeon_connector->router.ddc_mux_control_pin;
1122 radeon_i2c_put_byte(radeon_connector->router_bus,
1123 radeon_connector->router.i2c_addr,
1124 0x3, val);
1125 radeon_i2c_get_byte(radeon_connector->router_bus,
1126 radeon_connector->router.i2c_addr,
1127 0x1, &val);
1128 val &= ~radeon_connector->router.ddc_mux_control_pin;
1129 val |= radeon_connector->router.ddc_mux_state;
1130 radeon_i2c_put_byte(radeon_connector->router_bus,
1131 radeon_connector->router.i2c_addr,
1132 0x1, val);
1133 }
1134
1135 /* clock/data router switching */
1136 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector)
1137 {
1138 u8 val;
1139
1140 if (!radeon_connector->router.cd_valid)
1141 return;
1142
1143 if (!radeon_connector->router_bus)
1144 return;
1145
1146 radeon_i2c_get_byte(radeon_connector->router_bus,
1147 radeon_connector->router.i2c_addr,
1148 0x3, &val);
1149 val &= ~radeon_connector->router.cd_mux_control_pin;
1150 radeon_i2c_put_byte(radeon_connector->router_bus,
1151 radeon_connector->router.i2c_addr,
1152 0x3, val);
1153 radeon_i2c_get_byte(radeon_connector->router_bus,
1154 radeon_connector->router.i2c_addr,
1155 0x1, &val);
1156 val &= ~radeon_connector->router.cd_mux_control_pin;
1157 val |= radeon_connector->router.cd_mux_state;
1158 radeon_i2c_put_byte(radeon_connector->router_bus,
1159 radeon_connector->router.i2c_addr,
1160 0x1, val);
1161 }
1162