drivers/misc/hpilo.h

   1 /*
   2  * linux/drivers/char/hpilo.h
   3  *
   4  * Copyright (C) 2008 Hewlett-Packard Development Company, L.P.
   5  *      David Altobelli <david.altobelli@hp.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #ifndef __HPILO_H
  12 #define __HPILO_H
  13
  14 #define ILO_NAME "hpilo"
  15
  16 /* max number of open channel control blocks per device, hw limited to 32 */
  17 #define MAX_CCB         8
  18 /* max number of supported devices */
  19 #define MAX_ILO_DEV     1
  20 /* max number of files */
  21 #define MAX_OPEN        (MAX_CCB * MAX_ILO_DEV)
  22 /* total wait time in usec */
  23 #define MAX_WAIT_TIME   10000
  24 /* per spin wait time in usec */
  25 #define WAIT_TIME       10
  26 /* spin counter for open/close delay */
  27 #define MAX_WAIT        (MAX_WAIT_TIME / WAIT_TIME)
  28
  29 /*
  30  * Per device, used to track global memory allocations.
  31  */
  32 struct ilo_hwinfo {
  33         /* mmio registers on device */
  34         char __iomem *mmio_vaddr;
  35
  36         /* doorbell registers on device */
  37         char __iomem *db_vaddr;
  38
  39         /* shared memory on device used for channel control blocks */
  40         char __iomem *ram_vaddr;
  41
  42         /* files corresponding to this device */
  43         struct ccb_data *ccb_alloc[MAX_CCB];
  44
  45         struct pci_dev *ilo_dev;
  46
  47         /*
  48          * open_lock      serializes ccb_cnt during open and close
  49          * [ irq disabled ]
  50          * -> alloc_lock  used when adding/removing/searching ccb_alloc,
  51          *                which represents all ccbs open on the device
  52          * --> fifo_lock  controls access to fifo queues shared with hw
  53          *
  54          * Locks must be taken in this order, but open_lock and alloc_lock
  55          * are optional, they do not need to be held in order to take a
  56          * lower level lock.
  57          */
  58         spinlock_t open_lock;
  59         spinlock_t alloc_lock;
  60         spinlock_t fifo_lock;
  61
  62         struct cdev cdev;
  63 };
  64
  65 /* offset from mmio_vaddr for enabling doorbell interrupts */
  66 #define DB_IRQ          0xB2
  67 /* offset from mmio_vaddr for outbound communications */
  68 #define DB_OUT          0xD4
  69 /* DB_OUT reset bit */
  70 #define DB_RESET        26
  71
  72 /*
  73  * Channel control block. Used to manage hardware queues.
  74  * The format must match hw's version.  The hw ccb is 128 bytes,
  75  * but the context area shouldn't be touched by the driver.
  76  */
  77 #define ILOSW_CCB_SZ    64
  78 #define ILOHW_CCB_SZ    128
  79 struct ccb {
  80         union {
  81                 char *send_fifobar;
  82                 u64 send_fifobar_pa;
  83         } ccb_u1;
  84         union {
  85                 char *send_desc;
  86                 u64 send_desc_pa;
  87         } ccb_u2;
  88         u64 send_ctrl;
  89
  90         union {
  91                 char *recv_fifobar;
  92                 u64 recv_fifobar_pa;
  93         } ccb_u3;
  94         union {
  95                 char *recv_desc;
  96                 u64 recv_desc_pa;
  97         } ccb_u4;
  98         u64 recv_ctrl;
  99
 100         union {
 101                 char __iomem *db_base;
 102                 u64 padding5;
 103         } ccb_u5;
 104
 105         u64 channel;
 106
 107         /* unused context area (64 bytes) */
 108 };
 109
 110 /* ccb queue parameters */
 111 #define SENDQ           1
 112 #define RECVQ           2
 113 #define NR_QENTRY       4
 114 #define L2_QENTRY_SZ    12
 115
 116 /* ccb ctrl bitfields */
 117 #define CTRL_BITPOS_L2SZ             0
 118 #define CTRL_BITPOS_FIFOINDEXMASK    4
 119 #define CTRL_BITPOS_DESCLIMIT        18
 120 #define CTRL_BITPOS_A                30
 121 #define CTRL_BITPOS_G                31
 122
 123 /* ccb doorbell macros */
 124 #define L2_DB_SIZE              14
 125 #define ONE_DB_SIZE             (1 << L2_DB_SIZE)
 126
 127 /*
 128  * Per fd structure used to track the ccb allocated to that dev file.
 129  */
 130 struct ccb_data {
 131         /* software version of ccb, using virtual addrs */
 132         struct ccb  driver_ccb;
 133
 134         /* hardware version of ccb, using physical addrs */
 135         struct ccb  ilo_ccb;
 136
 137         /* hardware ccb is written to this shared mapped device memory */
 138         struct ccb __iomem *mapped_ccb;
 139
 140         /* dma'able memory used for send/recv queues */
 141         void       *dma_va;
 142         dma_addr_t  dma_pa;
 143         size_t      dma_size;
 144
 145         /* pointer to hardware device info */
 146         struct ilo_hwinfo *ilo_hw;
 147
 148         /* queue for this ccb to wait for recv data */
 149         wait_queue_head_t ccb_waitq;
 150
 151         /* usage count, to allow for shared ccb's */
 152         int         ccb_cnt;
 153
 154         /* open wanted exclusive access to this ccb */
 155         int         ccb_excl;
 156 };
 157
 158 /*
 159  * FIFO queue structure, shared with hw.
 160  */
 161 #define ILO_START_ALIGN 4096
 162 #define ILO_CACHE_SZ     128
 163 struct fifo {
 164     u64 nrents; /* user requested number of fifo entries */
 165     u64 imask;  /* mask to extract valid fifo index */
 166     u64 merge;  /*  O/C bits to merge in during enqueue operation */
 167     u64 reset;  /* set to non-zero when the target device resets */
 168     u8  pad_0[ILO_CACHE_SZ - (sizeof(u64) * 4)];
 169
 170     u64 head;
 171     u8  pad_1[ILO_CACHE_SZ - (sizeof(u64))];
 172
 173     u64 tail;
 174     u8  pad_2[ILO_CACHE_SZ - (sizeof(u64))];
 175
 176     u64 fifobar[1];
 177 };
 178
 179 /* convert between struct fifo, and the fifobar, which is saved in the ccb */
 180 #define FIFOHANDLESIZE (sizeof(struct fifo) - sizeof(u64))
 181 #define FIFOBARTOHANDLE(_fifo) \
 182         ((struct fifo *)(((char *)(_fifo)) - FIFOHANDLESIZE))
 183
 184 /* the number of qwords to consume from the entry descriptor */
 185 #define ENTRY_BITPOS_QWORDS      0
 186 /* descriptor index number (within a specified queue) */
 187 #define ENTRY_BITPOS_DESCRIPTOR  10
 188 /* state bit, fifo entry consumed by consumer */
 189 #define ENTRY_BITPOS_C           22
 190 /* state bit, fifo entry is occupied */
 191 #define ENTRY_BITPOS_O           23
 192
 193 #define ENTRY_BITS_QWORDS        10
 194 #define ENTRY_BITS_DESCRIPTOR    12
 195 #define ENTRY_BITS_C             1
 196 #define ENTRY_BITS_O             1
 197 #define ENTRY_BITS_TOTAL        \
 198         (ENTRY_BITS_C + ENTRY_BITS_O + \
 199          ENTRY_BITS_QWORDS + ENTRY_BITS_DESCRIPTOR)
 200
 201 /* extract various entry fields */
 202 #define ENTRY_MASK ((1 << ENTRY_BITS_TOTAL) - 1)
 203 #define ENTRY_MASK_C (((1 << ENTRY_BITS_C) - 1) << ENTRY_BITPOS_C)
 204 #define ENTRY_MASK_O (((1 << ENTRY_BITS_O) - 1) << ENTRY_BITPOS_O)
 205 #define ENTRY_MASK_QWORDS \
 206         (((1 << ENTRY_BITS_QWORDS) - 1) << ENTRY_BITPOS_QWORDS)
 207 #define ENTRY_MASK_DESCRIPTOR \
 208         (((1 << ENTRY_BITS_DESCRIPTOR) - 1) << ENTRY_BITPOS_DESCRIPTOR)
 209
 210 #define ENTRY_MASK_NOSTATE (ENTRY_MASK >> (ENTRY_BITS_C + ENTRY_BITS_O))
 211
 212 #endif /* __HPILO_H */