2 * CAN bus driver for the alone generic (as possible as) MSCAN controller.
4 * Copyright (C) 2005-2006 Andrey Volkov <avolkov@varma-el.com>,
6 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
7 * Copyright (C) 2008-2009 Pengutronix <kernel@pengutronix.de>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the version 2 of the GNU General Public License
11 * as published by the Free Software Foundation
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/netdevice.h>
28 #include <linux/if_arp.h>
29 #include <linux/if_ether.h>
30 #include <linux/list.h>
31 #include <linux/can/dev.h>
32 #include <linux/can/error.h>
37 static struct can_bittiming_const mscan_bittiming_const
= {
55 static enum can_state state_map
[] = {
56 CAN_STATE_ERROR_ACTIVE
,
57 CAN_STATE_ERROR_WARNING
,
58 CAN_STATE_ERROR_PASSIVE
,
62 static int mscan_set_mode(struct net_device
*dev
, u8 mode
)
64 struct mscan_priv
*priv
= netdev_priv(dev
);
65 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
70 if (mode
!= MSCAN_NORMAL_MODE
) {
71 if (priv
->tx_active
) {
72 /* Abort transfers before going to sleep */#
73 out_8(®s
->cantarq
, priv
->tx_active
);
74 /* Suppress TX done interrupts */
75 out_8(®s
->cantier
, 0);
78 canctl1
= in_8(®s
->canctl1
);
79 if ((mode
& MSCAN_SLPRQ
) && !(canctl1
& MSCAN_SLPAK
)) {
80 setbits8(®s
->canctl0
, MSCAN_SLPRQ
);
81 for (i
= 0; i
< MSCAN_SET_MODE_RETRIES
; i
++) {
82 if (in_8(®s
->canctl1
) & MSCAN_SLPAK
)
87 * The mscan controller will fail to enter sleep mode,
88 * while there are irregular activities on bus, like
89 * somebody keeps retransmitting. This behavior is
90 * undocumented and seems to differ between mscan built
91 * in mpc5200b and mpc5200. We proceed in that case,
92 * since otherwise the slprq will be kept set and the
93 * controller will get stuck. NOTE: INITRQ or CSWAI
94 * will abort all active transmit actions, if still
97 if (i
>= MSCAN_SET_MODE_RETRIES
)
98 dev_dbg(dev
->dev
.parent
,
99 "device failed to enter sleep mode. "
100 "We proceed anyhow.\n");
102 priv
->can
.state
= CAN_STATE_SLEEPING
;
105 if ((mode
& MSCAN_INITRQ
) && !(canctl1
& MSCAN_INITAK
)) {
106 setbits8(®s
->canctl0
, MSCAN_INITRQ
);
107 for (i
= 0; i
< MSCAN_SET_MODE_RETRIES
; i
++) {
108 if (in_8(®s
->canctl1
) & MSCAN_INITAK
)
111 if (i
>= MSCAN_SET_MODE_RETRIES
)
115 priv
->can
.state
= CAN_STATE_STOPPED
;
117 if (mode
& MSCAN_CSWAI
)
118 setbits8(®s
->canctl0
, MSCAN_CSWAI
);
121 canctl1
= in_8(®s
->canctl1
);
122 if (canctl1
& (MSCAN_SLPAK
| MSCAN_INITAK
)) {
123 clrbits8(®s
->canctl0
, MSCAN_SLPRQ
| MSCAN_INITRQ
);
124 for (i
= 0; i
< MSCAN_SET_MODE_RETRIES
; i
++) {
125 canctl1
= in_8(®s
->canctl1
);
126 if (!(canctl1
& (MSCAN_INITAK
| MSCAN_SLPAK
)))
129 if (i
>= MSCAN_SET_MODE_RETRIES
)
132 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
138 static int mscan_start(struct net_device
*dev
)
140 struct mscan_priv
*priv
= netdev_priv(dev
);
141 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
145 out_8(®s
->canrier
, 0);
147 INIT_LIST_HEAD(&priv
->tx_head
);
148 priv
->prev_buf_id
= 0;
151 priv
->shadow_canrier
= 0;
154 if (priv
->type
== MSCAN_TYPE_MPC5121
) {
155 /* Clear pending bus-off condition */
156 if (in_8(®s
->canmisc
) & MSCAN_BOHOLD
)
157 out_8(®s
->canmisc
, MSCAN_BOHOLD
);
160 err
= mscan_set_mode(dev
, MSCAN_NORMAL_MODE
);
164 canrflg
= in_8(®s
->canrflg
);
165 priv
->shadow_statflg
= canrflg
& MSCAN_STAT_MSK
;
166 priv
->can
.state
= state_map
[max(MSCAN_STATE_RX(canrflg
),
167 MSCAN_STATE_TX(canrflg
))];
168 out_8(®s
->cantier
, 0);
170 /* Enable receive interrupts. */
171 out_8(®s
->canrier
, MSCAN_RX_INTS_ENABLE
);
176 static int mscan_restart(struct net_device
*dev
)
178 struct mscan_priv
*priv
= netdev_priv(dev
);
180 if (priv
->type
== MSCAN_TYPE_MPC5121
) {
181 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
183 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
184 WARN(!(in_8(®s
->canmisc
) & MSCAN_BOHOLD
),
185 "bus-off state expected\n");
186 out_8(®s
->canmisc
, MSCAN_BOHOLD
);
187 /* Re-enable receive interrupts. */
188 out_8(®s
->canrier
, MSCAN_RX_INTS_ENABLE
);
190 if (priv
->can
.state
<= CAN_STATE_BUS_OFF
)
191 mscan_set_mode(dev
, MSCAN_INIT_MODE
);
192 return mscan_start(dev
);
198 static netdev_tx_t
mscan_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
200 struct can_frame
*frame
= (struct can_frame
*)skb
->data
;
201 struct mscan_priv
*priv
= netdev_priv(dev
);
202 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
206 if (can_dropped_invalid_skb(dev
, skb
))
209 out_8(®s
->cantier
, 0);
211 i
= ~priv
->tx_active
& MSCAN_TXE
;
213 switch (hweight8(i
)) {
215 netif_stop_queue(dev
);
216 dev_err(dev
->dev
.parent
, "Tx Ring full when queue awake!\n");
217 return NETDEV_TX_BUSY
;
220 * if buf_id < 3, then current frame will be send out of order,
221 * since buffer with lower id have higher priority (hell..)
223 netif_stop_queue(dev
);
225 if (buf_id
< priv
->prev_buf_id
) {
227 if (priv
->cur_pri
== 0xff) {
228 set_bit(F_TX_WAIT_ALL
, &priv
->flags
);
229 netif_stop_queue(dev
);
232 set_bit(F_TX_PROGRESS
, &priv
->flags
);
235 priv
->prev_buf_id
= buf_id
;
236 out_8(®s
->cantbsel
, i
);
238 rtr
= frame
->can_id
& CAN_RTR_FLAG
;
240 /* RTR is always the lowest bit of interest, then IDs follow */
241 if (frame
->can_id
& CAN_EFF_FLAG
) {
242 can_id
= (frame
->can_id
& CAN_EFF_MASK
)
243 << (MSCAN_EFF_RTR_SHIFT
+ 1);
245 can_id
|= 1 << MSCAN_EFF_RTR_SHIFT
;
246 out_be16(®s
->tx
.idr3_2
, can_id
);
249 /* EFF_FLAGS are between the IDs :( */
250 can_id
= (can_id
& 0x7) | ((can_id
<< 2) & 0xffe0)
253 can_id
= (frame
->can_id
& CAN_SFF_MASK
)
254 << (MSCAN_SFF_RTR_SHIFT
+ 1);
256 can_id
|= 1 << MSCAN_SFF_RTR_SHIFT
;
258 out_be16(®s
->tx
.idr1_0
, can_id
);
261 void __iomem
*data
= ®s
->tx
.dsr1_0
;
262 u16
*payload
= (u16
*)frame
->data
;
264 for (i
= 0; i
< frame
->can_dlc
/ 2; i
++) {
265 out_be16(data
, *payload
++);
266 data
+= 2 + _MSCAN_RESERVED_DSR_SIZE
;
268 /* write remaining byte if necessary */
269 if (frame
->can_dlc
& 1)
270 out_8(data
, frame
->data
[frame
->can_dlc
- 1]);
273 out_8(®s
->tx
.dlr
, frame
->can_dlc
);
274 out_8(®s
->tx
.tbpr
, priv
->cur_pri
);
276 /* Start transmission. */
277 out_8(®s
->cantflg
, 1 << buf_id
);
279 if (!test_bit(F_TX_PROGRESS
, &priv
->flags
))
280 dev
->trans_start
= jiffies
;
282 list_add_tail(&priv
->tx_queue
[buf_id
].list
, &priv
->tx_head
);
284 can_put_echo_skb(skb
, dev
, buf_id
);
286 /* Enable interrupt. */
287 priv
->tx_active
|= 1 << buf_id
;
288 out_8(®s
->cantier
, priv
->tx_active
);
293 /* This function returns the old state to see where we came from */
294 static enum can_state
check_set_state(struct net_device
*dev
, u8 canrflg
)
296 struct mscan_priv
*priv
= netdev_priv(dev
);
297 enum can_state state
, old_state
= priv
->can
.state
;
299 if (canrflg
& MSCAN_CSCIF
&& old_state
<= CAN_STATE_BUS_OFF
) {
300 state
= state_map
[max(MSCAN_STATE_RX(canrflg
),
301 MSCAN_STATE_TX(canrflg
))];
302 priv
->can
.state
= state
;
307 static void mscan_get_rx_frame(struct net_device
*dev
, struct can_frame
*frame
)
309 struct mscan_priv
*priv
= netdev_priv(dev
);
310 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
314 can_id
= in_be16(®s
->rx
.idr1_0
);
315 if (can_id
& (1 << 3)) {
316 frame
->can_id
= CAN_EFF_FLAG
;
317 can_id
= ((can_id
<< 16) | in_be16(®s
->rx
.idr3_2
));
318 can_id
= ((can_id
& 0xffe00000) |
319 ((can_id
& 0x7ffff) << 2)) >> 2;
325 frame
->can_id
|= can_id
>> 1;
327 frame
->can_id
|= CAN_RTR_FLAG
;
329 frame
->can_dlc
= get_can_dlc(in_8(®s
->rx
.dlr
) & 0xf);
331 if (!(frame
->can_id
& CAN_RTR_FLAG
)) {
332 void __iomem
*data
= ®s
->rx
.dsr1_0
;
333 u16
*payload
= (u16
*)frame
->data
;
335 for (i
= 0; i
< frame
->can_dlc
/ 2; i
++) {
336 *payload
++ = in_be16(data
);
337 data
+= 2 + _MSCAN_RESERVED_DSR_SIZE
;
339 /* read remaining byte if necessary */
340 if (frame
->can_dlc
& 1)
341 frame
->data
[frame
->can_dlc
- 1] = in_8(data
);
344 out_8(®s
->canrflg
, MSCAN_RXF
);
347 static void mscan_get_err_frame(struct net_device
*dev
, struct can_frame
*frame
,
350 struct mscan_priv
*priv
= netdev_priv(dev
);
351 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
352 struct net_device_stats
*stats
= &dev
->stats
;
353 enum can_state old_state
;
355 dev_dbg(dev
->dev
.parent
, "error interrupt (canrflg=%#x)\n", canrflg
);
356 frame
->can_id
= CAN_ERR_FLAG
;
358 if (canrflg
& MSCAN_OVRIF
) {
359 frame
->can_id
|= CAN_ERR_CRTL
;
360 frame
->data
[1] = CAN_ERR_CRTL_RX_OVERFLOW
;
361 stats
->rx_over_errors
++;
367 old_state
= check_set_state(dev
, canrflg
);
369 if (old_state
!= priv
->can
.state
) {
370 switch (priv
->can
.state
) {
371 case CAN_STATE_ERROR_WARNING
:
372 frame
->can_id
|= CAN_ERR_CRTL
;
373 priv
->can
.can_stats
.error_warning
++;
374 if ((priv
->shadow_statflg
& MSCAN_RSTAT_MSK
) <
375 (canrflg
& MSCAN_RSTAT_MSK
))
376 frame
->data
[1] |= CAN_ERR_CRTL_RX_WARNING
;
377 if ((priv
->shadow_statflg
& MSCAN_TSTAT_MSK
) <
378 (canrflg
& MSCAN_TSTAT_MSK
))
379 frame
->data
[1] |= CAN_ERR_CRTL_TX_WARNING
;
381 case CAN_STATE_ERROR_PASSIVE
:
382 frame
->can_id
|= CAN_ERR_CRTL
;
383 priv
->can
.can_stats
.error_passive
++;
384 frame
->data
[1] |= CAN_ERR_CRTL_RX_PASSIVE
;
386 case CAN_STATE_BUS_OFF
:
387 frame
->can_id
|= CAN_ERR_BUSOFF
;
389 * The MSCAN on the MPC5200 does recover from bus-off
390 * automatically. To avoid that we stop the chip doing
391 * a light-weight stop (we are in irq-context).
393 if (priv
->type
!= MSCAN_TYPE_MPC5121
) {
394 out_8(®s
->cantier
, 0);
395 out_8(®s
->canrier
, 0);
396 setbits8(®s
->canctl0
,
397 MSCAN_SLPRQ
| MSCAN_INITRQ
);
405 priv
->shadow_statflg
= canrflg
& MSCAN_STAT_MSK
;
406 frame
->can_dlc
= CAN_ERR_DLC
;
407 out_8(®s
->canrflg
, MSCAN_ERR_IF
);
410 static int mscan_rx_poll(struct napi_struct
*napi
, int quota
)
412 struct mscan_priv
*priv
= container_of(napi
, struct mscan_priv
, napi
);
413 struct net_device
*dev
= napi
->dev
;
414 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
415 struct net_device_stats
*stats
= &dev
->stats
;
419 struct can_frame
*frame
;
422 while (npackets
< quota
) {
423 canrflg
= in_8(®s
->canrflg
);
424 if (!(canrflg
& (MSCAN_RXF
| MSCAN_ERR_IF
)))
427 skb
= alloc_can_skb(dev
, &frame
);
429 if (printk_ratelimit())
430 dev_notice(dev
->dev
.parent
, "packet dropped\n");
432 out_8(®s
->canrflg
, canrflg
);
436 if (canrflg
& MSCAN_RXF
)
437 mscan_get_rx_frame(dev
, frame
);
438 else if (canrflg
& MSCAN_ERR_IF
)
439 mscan_get_err_frame(dev
, frame
, canrflg
);
442 stats
->rx_bytes
+= frame
->can_dlc
;
444 netif_receive_skb(skb
);
447 if (!(in_8(®s
->canrflg
) & (MSCAN_RXF
| MSCAN_ERR_IF
))) {
448 napi_complete(&priv
->napi
);
449 clear_bit(F_RX_PROGRESS
, &priv
->flags
);
450 if (priv
->can
.state
< CAN_STATE_BUS_OFF
)
451 out_8(®s
->canrier
, priv
->shadow_canrier
);
457 static irqreturn_t
mscan_isr(int irq
, void *dev_id
)
459 struct net_device
*dev
= (struct net_device
*)dev_id
;
460 struct mscan_priv
*priv
= netdev_priv(dev
);
461 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
462 struct net_device_stats
*stats
= &dev
->stats
;
463 u8 cantier
, cantflg
, canrflg
;
464 irqreturn_t ret
= IRQ_NONE
;
466 cantier
= in_8(®s
->cantier
) & MSCAN_TXE
;
467 cantflg
= in_8(®s
->cantflg
) & cantier
;
469 if (cantier
&& cantflg
) {
470 struct list_head
*tmp
, *pos
;
472 list_for_each_safe(pos
, tmp
, &priv
->tx_head
) {
473 struct tx_queue_entry
*entry
=
474 list_entry(pos
, struct tx_queue_entry
, list
);
475 u8 mask
= entry
->mask
;
477 if (!(cantflg
& mask
))
480 out_8(®s
->cantbsel
, mask
);
481 stats
->tx_bytes
+= in_8(®s
->tx
.dlr
);
483 can_get_echo_skb(dev
, entry
->id
);
484 priv
->tx_active
&= ~mask
;
488 if (list_empty(&priv
->tx_head
)) {
489 clear_bit(F_TX_WAIT_ALL
, &priv
->flags
);
490 clear_bit(F_TX_PROGRESS
, &priv
->flags
);
493 dev
->trans_start
= jiffies
;
496 if (!test_bit(F_TX_WAIT_ALL
, &priv
->flags
))
497 netif_wake_queue(dev
);
499 out_8(®s
->cantier
, priv
->tx_active
);
503 canrflg
= in_8(®s
->canrflg
);
504 if ((canrflg
& ~MSCAN_STAT_MSK
) &&
505 !test_and_set_bit(F_RX_PROGRESS
, &priv
->flags
)) {
506 if (canrflg
& ~MSCAN_STAT_MSK
) {
507 priv
->shadow_canrier
= in_8(®s
->canrier
);
508 out_8(®s
->canrier
, 0);
509 napi_schedule(&priv
->napi
);
512 clear_bit(F_RX_PROGRESS
, &priv
->flags
);
518 static int mscan_do_set_mode(struct net_device
*dev
, enum can_mode mode
)
520 struct mscan_priv
*priv
= netdev_priv(dev
);
523 if (!priv
->open_time
)
528 ret
= mscan_restart(dev
);
531 if (netif_queue_stopped(dev
))
532 netif_wake_queue(dev
);
542 static int mscan_do_set_bittiming(struct net_device
*dev
)
544 struct mscan_priv
*priv
= netdev_priv(dev
);
545 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
546 struct can_bittiming
*bt
= &priv
->can
.bittiming
;
549 btr0
= BTR0_SET_BRP(bt
->brp
) | BTR0_SET_SJW(bt
->sjw
);
550 btr1
= (BTR1_SET_TSEG1(bt
->prop_seg
+ bt
->phase_seg1
) |
551 BTR1_SET_TSEG2(bt
->phase_seg2
) |
552 BTR1_SET_SAM(priv
->can
.ctrlmode
& CAN_CTRLMODE_3_SAMPLES
));
554 dev_info(dev
->dev
.parent
, "setting BTR0=0x%02x BTR1=0x%02x\n",
557 out_8(®s
->canbtr0
, btr0
);
558 out_8(®s
->canbtr1
, btr1
);
563 static int mscan_open(struct net_device
*dev
)
566 struct mscan_priv
*priv
= netdev_priv(dev
);
567 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
570 ret
= open_candev(dev
);
574 napi_enable(&priv
->napi
);
576 ret
= request_irq(dev
->irq
, mscan_isr
, 0, dev
->name
, dev
);
578 dev_err(dev
->dev
.parent
, "failed to attach interrupt\n");
579 goto exit_napi_disable
;
582 priv
->open_time
= jiffies
;
584 if (priv
->can
.ctrlmode
& CAN_CTRLMODE_LISTENONLY
)
585 setbits8(®s
->canctl1
, MSCAN_LISTEN
);
587 clrbits8(®s
->canctl1
, MSCAN_LISTEN
);
589 ret
= mscan_start(dev
);
593 netif_start_queue(dev
);
599 free_irq(dev
->irq
, dev
);
601 napi_disable(&priv
->napi
);
606 static int mscan_close(struct net_device
*dev
)
608 struct mscan_priv
*priv
= netdev_priv(dev
);
609 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
611 netif_stop_queue(dev
);
612 napi_disable(&priv
->napi
);
614 out_8(®s
->cantier
, 0);
615 out_8(®s
->canrier
, 0);
616 mscan_set_mode(dev
, MSCAN_INIT_MODE
);
618 free_irq(dev
->irq
, dev
);
624 static const struct net_device_ops mscan_netdev_ops
= {
625 .ndo_open
= mscan_open
,
626 .ndo_stop
= mscan_close
,
627 .ndo_start_xmit
= mscan_start_xmit
,
630 int register_mscandev(struct net_device
*dev
, int mscan_clksrc
)
632 struct mscan_priv
*priv
= netdev_priv(dev
);
633 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
636 ctl1
= in_8(®s
->canctl1
);
638 ctl1
|= MSCAN_CLKSRC
;
640 ctl1
&= ~MSCAN_CLKSRC
;
642 if (priv
->type
== MSCAN_TYPE_MPC5121
)
643 ctl1
|= MSCAN_BORM
; /* bus-off recovery upon request */
646 out_8(®s
->canctl1
, ctl1
);
649 /* acceptance mask/acceptance code (accept everything) */
650 out_be16(®s
->canidar1_0
, 0);
651 out_be16(®s
->canidar3_2
, 0);
652 out_be16(®s
->canidar5_4
, 0);
653 out_be16(®s
->canidar7_6
, 0);
655 out_be16(®s
->canidmr1_0
, 0xffff);
656 out_be16(®s
->canidmr3_2
, 0xffff);
657 out_be16(®s
->canidmr5_4
, 0xffff);
658 out_be16(®s
->canidmr7_6
, 0xffff);
659 /* Two 32 bit Acceptance Filters */
660 out_8(®s
->canidac
, MSCAN_AF_32BIT
);
662 mscan_set_mode(dev
, MSCAN_INIT_MODE
);
664 return register_candev(dev
);
667 void unregister_mscandev(struct net_device
*dev
)
669 struct mscan_priv
*priv
= netdev_priv(dev
);
670 struct mscan_regs __iomem
*regs
= priv
->reg_base
;
671 mscan_set_mode(dev
, MSCAN_INIT_MODE
);
672 clrbits8(®s
->canctl1
, MSCAN_CANE
);
673 unregister_candev(dev
);
676 struct net_device
*alloc_mscandev(void)
678 struct net_device
*dev
;
679 struct mscan_priv
*priv
;
682 dev
= alloc_candev(sizeof(struct mscan_priv
), MSCAN_ECHO_SKB_MAX
);
685 priv
= netdev_priv(dev
);
687 dev
->netdev_ops
= &mscan_netdev_ops
;
689 dev
->flags
|= IFF_ECHO
; /* we support local echo */
691 netif_napi_add(dev
, &priv
->napi
, mscan_rx_poll
, 8);
693 priv
->can
.bittiming_const
= &mscan_bittiming_const
;
694 priv
->can
.do_set_bittiming
= mscan_do_set_bittiming
;
695 priv
->can
.do_set_mode
= mscan_do_set_mode
;
696 priv
->can
.ctrlmode_supported
= CAN_CTRLMODE_3_SAMPLES
|
697 CAN_CTRLMODE_LISTENONLY
;
699 for (i
= 0; i
< TX_QUEUE_SIZE
; i
++) {
700 priv
->tx_queue
[i
].id
= i
;
701 priv
->tx_queue
[i
].mask
= 1 << i
;
707 MODULE_AUTHOR("Andrey Volkov <avolkov@varma-el.com>");
708 MODULE_LICENSE("GPL v2");
709 MODULE_DESCRIPTION("CAN port driver for a MSCAN based chips");