2 * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
3 * Copyright (c) 2008-2009 Marvell Semiconductor
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
11 #include <linux/list.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/phy.h>
17 #define REG_PORT(p) (8 + (p))
18 #define REG_GLOBAL 0x0f
20 static int reg_read(struct dsa_switch
*ds
, int addr
, int reg
)
22 return mdiobus_read(ds
->master_mii_bus
, ds
->pd
->sw_addr
+ addr
, reg
);
25 #define REG_READ(addr, reg) \
29 __ret = reg_read(ds, addr, reg); \
36 static int reg_write(struct dsa_switch
*ds
, int addr
, int reg
, u16 val
)
38 return mdiobus_write(ds
->master_mii_bus
, ds
->pd
->sw_addr
+ addr
,
42 #define REG_WRITE(addr, reg, val) \
46 __ret = reg_write(ds, addr, reg, val); \
51 static char *mv88e6060_probe(struct mii_bus
*bus
, int sw_addr
)
55 ret
= mdiobus_read(bus
, sw_addr
+ REG_PORT(0), 0x03);
59 return "Marvell 88E6060";
65 static int mv88e6060_switch_reset(struct dsa_switch
*ds
)
71 * Set all ports to the disabled state.
73 for (i
= 0; i
< 6; i
++) {
74 ret
= REG_READ(REG_PORT(i
), 0x04);
75 REG_WRITE(REG_PORT(i
), 0x04, ret
& 0xfffc);
79 * Wait for transmit queues to drain.
86 REG_WRITE(REG_GLOBAL
, 0x0a, 0xa130);
89 * Wait up to one second for reset to complete.
91 for (i
= 0; i
< 1000; i
++) {
92 ret
= REG_READ(REG_GLOBAL
, 0x00);
93 if ((ret
& 0x8000) == 0x0000)
104 static int mv88e6060_setup_global(struct dsa_switch
*ds
)
107 * Disable discarding of frames with excessive collisions,
108 * set the maximum frame size to 1536 bytes, and mask all
111 REG_WRITE(REG_GLOBAL
, 0x04, 0x0800);
114 * Enable automatic address learning, set the address
115 * database size to 1024 entries, and set the default aging
118 REG_WRITE(REG_GLOBAL
, 0x0a, 0x2130);
123 static int mv88e6060_setup_port(struct dsa_switch
*ds
, int p
)
125 int addr
= REG_PORT(p
);
128 * Do not force flow control, disable Ingress and Egress
129 * Header tagging, disable VLAN tunneling, and set the port
130 * state to Forwarding. Additionally, if this is the CPU
131 * port, enable Ingress and Egress Trailer tagging mode.
133 REG_WRITE(addr
, 0x04, dsa_is_cpu_port(ds
, p
) ? 0x4103 : 0x0003);
136 * Port based VLAN map: give each port its own address
137 * database, allow the CPU port to talk to each of the 'real'
138 * ports, and allow each of the 'real' ports to only talk to
141 REG_WRITE(addr
, 0x06,
143 (dsa_is_cpu_port(ds
, p
) ?
145 (1 << ds
->dst
->cpu_port
)));
148 * Port Association Vector: when learning source addresses
149 * of packets, add the address to the address database using
150 * a port bitmap that has only the bit for this port set and
151 * the other bits clear.
153 REG_WRITE(addr
, 0x0b, 1 << p
);
158 static int mv88e6060_setup(struct dsa_switch
*ds
)
163 ret
= mv88e6060_switch_reset(ds
);
167 /* @@@ initialise atu */
169 ret
= mv88e6060_setup_global(ds
);
173 for (i
= 0; i
< 6; i
++) {
174 ret
= mv88e6060_setup_port(ds
, i
);
182 static int mv88e6060_set_addr(struct dsa_switch
*ds
, u8
*addr
)
184 REG_WRITE(REG_GLOBAL
, 0x01, (addr
[0] << 8) | addr
[1]);
185 REG_WRITE(REG_GLOBAL
, 0x02, (addr
[2] << 8) | addr
[3]);
186 REG_WRITE(REG_GLOBAL
, 0x03, (addr
[4] << 8) | addr
[5]);
191 static int mv88e6060_port_to_phy_addr(int port
)
193 if (port
>= 0 && port
<= 5)
198 static int mv88e6060_phy_read(struct dsa_switch
*ds
, int port
, int regnum
)
202 addr
= mv88e6060_port_to_phy_addr(port
);
206 return reg_read(ds
, addr
, regnum
);
210 mv88e6060_phy_write(struct dsa_switch
*ds
, int port
, int regnum
, u16 val
)
214 addr
= mv88e6060_port_to_phy_addr(port
);
218 return reg_write(ds
, addr
, regnum
, val
);
221 static void mv88e6060_poll_link(struct dsa_switch
*ds
)
225 for (i
= 0; i
< DSA_MAX_PORTS
; i
++) {
226 struct net_device
*dev
;
227 int uninitialized_var(port_status
);
238 if (dev
->flags
& IFF_UP
) {
239 port_status
= reg_read(ds
, REG_PORT(i
), 0x00);
243 link
= !!(port_status
& 0x1000);
247 if (netif_carrier_ok(dev
)) {
248 printk(KERN_INFO
"%s: link down\n", dev
->name
);
249 netif_carrier_off(dev
);
254 speed
= (port_status
& 0x0100) ? 100 : 10;
255 duplex
= (port_status
& 0x0200) ? 1 : 0;
256 fc
= ((port_status
& 0xc000) == 0xc000) ? 1 : 0;
258 if (!netif_carrier_ok(dev
)) {
259 printk(KERN_INFO
"%s: link up, %d Mb/s, %s duplex, "
260 "flow control %sabled\n", dev
->name
,
261 speed
, duplex
? "full" : "half",
263 netif_carrier_on(dev
);
268 static struct dsa_switch_driver mv88e6060_switch_driver
= {
269 .tag_protocol
= htons(ETH_P_TRAILER
),
270 .probe
= mv88e6060_probe
,
271 .setup
= mv88e6060_setup
,
272 .set_addr
= mv88e6060_set_addr
,
273 .phy_read
= mv88e6060_phy_read
,
274 .phy_write
= mv88e6060_phy_write
,
275 .poll_link
= mv88e6060_poll_link
,
278 static int __init
mv88e6060_init(void)
280 register_switch_driver(&mv88e6060_switch_driver
);
283 module_init(mv88e6060_init
);
285 static void __exit
mv88e6060_cleanup(void)
287 unregister_switch_driver(&mv88e6060_switch_driver
);
289 module_exit(mv88e6060_cleanup
);
291 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
292 MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
293 MODULE_LICENSE("GPL");
294 MODULE_ALIAS("platform:mv88e6060");