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OMAPDSS: VENC: fix NULL pointer dereference in DSS2 VENC sysfs debug attr on OMAP4
[zen-stable.git] / drivers / net / ethernet / 3com / typhoon.c
blob6d6bc754b1a8e9f3fd49255aaadfe5620c49d567
1 /* typhoon.c: A Linux Ethernet device driver for 3Com 3CR990 family of NICs */
2 /*
3 Written 2002-2004 by David Dillow <dave@thedillows.org>
4 Based on code written 1998-2000 by Donald Becker <becker@scyld.com> and
5 Linux 2.2.x driver by David P. McLean <davidpmclean@yahoo.com>.
6
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL.
13
14 This software is available on a public web site. It may enable
15 cryptographic capabilities of the 3Com hardware, and may be
16 exported from the United States under License Exception "TSU"
17 pursuant to 15 C.F.R. Section 740.13(e).
18
19 This work was funded by the National Library of Medicine under
20 the Department of Energy project number 0274DD06D1 and NLM project
21 number Y1-LM-2015-01.
22
23 This driver is designed for the 3Com 3CR990 Family of cards with the
24 3XP Processor. It has been tested on x86 and sparc64.
25
26 KNOWN ISSUES:
27 *) Cannot DMA Rx packets to a 2 byte aligned address. Also firmware
28 issue. Hopefully 3Com will fix it.
29 *) Waiting for a command response takes 8ms due to non-preemptable
30 polling. Only significant for getting stats and creating
31 SAs, but an ugly wart never the less.
32
33 TODO:
34 *) Doesn't do IPSEC offloading. Yet. Keep yer pants on, it's coming.
35 *) Add more support for ethtool (especially for NIC stats)
36 *) Allow disabling of RX checksum offloading
37 *) Fix MAC changing to work while the interface is up
38 (Need to put commands on the TX ring, which changes
39 the locking)
40 *) Add in FCS to {rx,tx}_bytes, since the hardware doesn't. See
41 http://oss.sgi.com/cgi-bin/mesg.cgi?a=netdev&i=20031215152211.7003fe8e.rddunlap%40osdl.org
42 */
43
44 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
45 * Setting to > 1518 effectively disables this feature.
46 */
47 static int rx_copybreak = 200;
48
49 /* Should we use MMIO or Port IO?
50 * 0: Port IO
51 * 1: MMIO
52 * 2: Try MMIO, fallback to Port IO
53 */
54 static unsigned int use_mmio = 2;
55
56 /* end user-configurable values */
57
58 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
59 */
60 static const int multicast_filter_limit = 32;
61
62 /* Operational parameters that are set at compile time. */
63
64 /* Keep the ring sizes a power of two for compile efficiency.
65 * The compiler will convert <unsigned>'%'<2^N> into a bit mask.
66 * Making the Tx ring too large decreases the effectiveness of channel
67 * bonding and packet priority.
68 * There are no ill effects from too-large receive rings.
69 *
70 * We don't currently use the Hi Tx ring so, don't make it very big.
71 *
72 * Beware that if we start using the Hi Tx ring, we will need to change
73 * typhoon_num_free_tx() and typhoon_tx_complete() to account for that.
74 */
75 #define TXHI_ENTRIES 2
76 #define TXLO_ENTRIES 128
77 #define RX_ENTRIES 32
78 #define COMMAND_ENTRIES 16
79 #define RESPONSE_ENTRIES 32
80
81 #define COMMAND_RING_SIZE (COMMAND_ENTRIES * sizeof(struct cmd_desc))
82 #define RESPONSE_RING_SIZE (RESPONSE_ENTRIES * sizeof(struct resp_desc))
83
84 /* The 3XP will preload and remove 64 entries from the free buffer
85 * list, and we need one entry to keep the ring from wrapping, so
86 * to keep this a power of two, we use 128 entries.
87 */
88 #define RXFREE_ENTRIES 128
89 #define RXENT_ENTRIES (RXFREE_ENTRIES - 1)
90
91 /* Operational parameters that usually are not changed. */
92
93 /* Time in jiffies before concluding the transmitter is hung. */
94 #define TX_TIMEOUT (2*HZ)
95
96 #define PKT_BUF_SZ 1536
97 #define FIRMWARE_NAME "3com/typhoon.bin"
98
99 #define pr_fmt(fmt) KBUILD_MODNAME " " fmt
100
101 #include <linux/module.h>
102 #include <linux/kernel.h>
103 #include <linux/sched.h>
104 #include <linux/string.h>
105 #include <linux/timer.h>
106 #include <linux/errno.h>
107 #include <linux/ioport.h>
108 #include <linux/interrupt.h>
109 #include <linux/pci.h>
110 #include <linux/netdevice.h>
111 #include <linux/etherdevice.h>
112 #include <linux/skbuff.h>
113 #include <linux/mm.h>
114 #include <linux/init.h>
115 #include <linux/delay.h>
116 #include <linux/ethtool.h>
117 #include <linux/if_vlan.h>
118 #include <linux/crc32.h>
119 #include <linux/bitops.h>
120 #include <asm/processor.h>
121 #include <asm/io.h>
122 #include <asm/uaccess.h>
123 #include <linux/in6.h>
124 #include <linux/dma-mapping.h>
125 #include <linux/firmware.h>
126
127 #include "typhoon.h"
128
129 MODULE_AUTHOR("David Dillow <dave@thedillows.org>");
130 MODULE_VERSION("1.0");
131 MODULE_LICENSE("GPL");
132 MODULE_FIRMWARE(FIRMWARE_NAME);
133 MODULE_DESCRIPTION("3Com Typhoon Family (3C990, 3CR990, and variants)");
134 MODULE_PARM_DESC(rx_copybreak, "Packets smaller than this are copied and "
135 "the buffer given back to the NIC. Default "
136 "is 200.");
137 MODULE_PARM_DESC(use_mmio, "Use MMIO (1) or PIO(0) to access the NIC. "
138 "Default is to try MMIO and fallback to PIO.");
139 module_param(rx_copybreak, int, 0);
140 module_param(use_mmio, int, 0);
141
142 #if defined(NETIF_F_TSO) && MAX_SKB_FRAGS > 32
143 #warning Typhoon only supports 32 entries in its SG list for TSO, disabling TSO
144 #undef NETIF_F_TSO
145 #endif
146
147 #if TXLO_ENTRIES <= (2 * MAX_SKB_FRAGS)
148 #error TX ring too small!
149 #endif
150
151 struct typhoon_card_info {
152 const char *name;
153 const int capabilities;
154 };
155
156 #define TYPHOON_CRYPTO_NONE 0x00
157 #define TYPHOON_CRYPTO_DES 0x01
158 #define TYPHOON_CRYPTO_3DES 0x02
159 #define TYPHOON_CRYPTO_VARIABLE 0x04
160 #define TYPHOON_FIBER 0x08
161 #define TYPHOON_WAKEUP_NEEDS_RESET 0x10
162
163 enum typhoon_cards {
164 TYPHOON_TX = 0, TYPHOON_TX95, TYPHOON_TX97, TYPHOON_SVR,
165 TYPHOON_SVR95, TYPHOON_SVR97, TYPHOON_TXM, TYPHOON_BSVR,
166 TYPHOON_FX95, TYPHOON_FX97, TYPHOON_FX95SVR, TYPHOON_FX97SVR,
167 TYPHOON_FXM,
168 };
169
170 /* directly indexed by enum typhoon_cards, above */
171 static struct typhoon_card_info typhoon_card_info[] __devinitdata = {
172 { "3Com Typhoon (3C990-TX)",
173 TYPHOON_CRYPTO_NONE},
174 { "3Com Typhoon (3CR990-TX-95)",
175 TYPHOON_CRYPTO_DES},
176 { "3Com Typhoon (3CR990-TX-97)",
177 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
178 { "3Com Typhoon (3C990SVR)",
179 TYPHOON_CRYPTO_NONE},
180 { "3Com Typhoon (3CR990SVR95)",
181 TYPHOON_CRYPTO_DES},
182 { "3Com Typhoon (3CR990SVR97)",
183 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
184 { "3Com Typhoon2 (3C990B-TX-M)",
185 TYPHOON_CRYPTO_VARIABLE},
186 { "3Com Typhoon2 (3C990BSVR)",
187 TYPHOON_CRYPTO_VARIABLE},
188 { "3Com Typhoon (3CR990-FX-95)",
189 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
190 { "3Com Typhoon (3CR990-FX-97)",
191 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
192 { "3Com Typhoon (3CR990-FX-95 Server)",
193 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
194 { "3Com Typhoon (3CR990-FX-97 Server)",
195 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
196 { "3Com Typhoon2 (3C990B-FX-97)",
197 TYPHOON_CRYPTO_VARIABLE | TYPHOON_FIBER},
198 };
199
200 /* Notes on the new subsystem numbering scheme:
201 * bits 0-1 indicate crypto capabilities: (0) variable, (1) DES, or (2) 3DES
202 * bit 4 indicates if this card has secured firmware (we don't support it)
203 * bit 8 indicates if this is a (0) copper or (1) fiber card
204 * bits 12-16 indicate card type: (0) client and (1) server
205 */
206 static DEFINE_PCI_DEVICE_TABLE(typhoon_pci_tbl) = {
207 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0,TYPHOON_TX },
209 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_95,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX95 },
211 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_97,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX97 },
213 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
214 PCI_ANY_ID, 0x1000, 0, 0, TYPHOON_TXM },
215 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
216 PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FXM },
217 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
218 PCI_ANY_ID, 0x2000, 0, 0, TYPHOON_BSVR },
219 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
220 PCI_ANY_ID, 0x1101, 0, 0, TYPHOON_FX95 },
221 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
222 PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FX97 },
223 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
224 PCI_ANY_ID, 0x2101, 0, 0, TYPHOON_FX95SVR },
225 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
226 PCI_ANY_ID, 0x2102, 0, 0, TYPHOON_FX97SVR },
227 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR95,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR95 },
229 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR97,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR97 },
231 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR },
233 { 0, }
234 };
235 MODULE_DEVICE_TABLE(pci, typhoon_pci_tbl);
236
237 /* Define the shared memory area
238 * Align everything the 3XP will normally be using.
239 * We'll need to move/align txHi if we start using that ring.
240 */
241 #define __3xp_aligned ____cacheline_aligned
242 struct typhoon_shared {
243 struct typhoon_interface iface;
244 struct typhoon_indexes indexes __3xp_aligned;
245 struct tx_desc txLo[TXLO_ENTRIES] __3xp_aligned;
246 struct rx_desc rxLo[RX_ENTRIES] __3xp_aligned;
247 struct rx_desc rxHi[RX_ENTRIES] __3xp_aligned;
248 struct cmd_desc cmd[COMMAND_ENTRIES] __3xp_aligned;
249 struct resp_desc resp[RESPONSE_ENTRIES] __3xp_aligned;
250 struct rx_free rxBuff[RXFREE_ENTRIES] __3xp_aligned;
251 u32 zeroWord;
252 struct tx_desc txHi[TXHI_ENTRIES];
253 } __packed;
254
255 struct rxbuff_ent {
256 struct sk_buff *skb;
257 dma_addr_t dma_addr;
258 };
259
260 struct typhoon {
261 /* Tx cache line section */
262 struct transmit_ring txLoRing ____cacheline_aligned;
263 struct pci_dev * tx_pdev;
264 void __iomem *tx_ioaddr;
265 u32 txlo_dma_addr;
266
267 /* Irq/Rx cache line section */
268 void __iomem *ioaddr ____cacheline_aligned;
269 struct typhoon_indexes *indexes;
270 u8 awaiting_resp;
271 u8 duplex;
272 u8 speed;
273 u8 card_state;
274 struct basic_ring rxLoRing;
275 struct pci_dev * pdev;
276 struct net_device * dev;
277 struct napi_struct napi;
278 struct basic_ring rxHiRing;
279 struct basic_ring rxBuffRing;
280 struct rxbuff_ent rxbuffers[RXENT_ENTRIES];
281
282 /* general section */
283 spinlock_t command_lock ____cacheline_aligned;
284 struct basic_ring cmdRing;
285 struct basic_ring respRing;
286 struct net_device_stats stats;
287 struct net_device_stats stats_saved;
288 struct typhoon_shared * shared;
289 dma_addr_t shared_dma;
290 __le16 xcvr_select;
291 __le16 wol_events;
292 __le32 offload;
293
294 /* unused stuff (future use) */
295 int capabilities;
296 struct transmit_ring txHiRing;
297 };
298
299 enum completion_wait_values {
300 NoWait = 0, WaitNoSleep, WaitSleep,
301 };
302
303 /* These are the values for the typhoon.card_state variable.
304 * These determine where the statistics will come from in get_stats().
305 * The sleep image does not support the statistics we need.
306 */
307 enum state_values {
308 Sleeping = 0, Running,
309 };
310
311 /* PCI writes are not guaranteed to be posted in order, but outstanding writes
312 * cannot pass a read, so this forces current writes to post.
313 */
314 #define typhoon_post_pci_writes(x) \
315 do { if(likely(use_mmio)) ioread32(x+TYPHOON_REG_HEARTBEAT); } while(0)
316
317 /* We'll wait up to six seconds for a reset, and half a second normally.
318 */
319 #define TYPHOON_UDELAY 50
320 #define TYPHOON_RESET_TIMEOUT_SLEEP (6 * HZ)
321 #define TYPHOON_RESET_TIMEOUT_NOSLEEP ((6 * 1000000) / TYPHOON_UDELAY)
322 #define TYPHOON_WAIT_TIMEOUT ((1000000 / 2) / TYPHOON_UDELAY)
323
324 #if defined(NETIF_F_TSO)
325 #define skb_tso_size(x) (skb_shinfo(x)->gso_size)
326 #define TSO_NUM_DESCRIPTORS 2
327 #define TSO_OFFLOAD_ON TYPHOON_OFFLOAD_TCP_SEGMENT
328 #else
329 #define NETIF_F_TSO 0
330 #define skb_tso_size(x) 0
331 #define TSO_NUM_DESCRIPTORS 0
332 #define TSO_OFFLOAD_ON 0
333 #endif
334
335 static inline void
336 typhoon_inc_index(u32 *index, const int count, const int num_entries)
337 {
338 /* Increment a ring index -- we can use this for all rings execept
339 * the Rx rings, as they use different size descriptors
340 * otherwise, everything is the same size as a cmd_desc
341 */
342 *index += count * sizeof(struct cmd_desc);
343 *index %= num_entries * sizeof(struct cmd_desc);
344 }
345
346 static inline void
347 typhoon_inc_cmd_index(u32 *index, const int count)
348 {
349 typhoon_inc_index(index, count, COMMAND_ENTRIES);
350 }
351
352 static inline void
353 typhoon_inc_resp_index(u32 *index, const int count)
354 {
355 typhoon_inc_index(index, count, RESPONSE_ENTRIES);
356 }
357
358 static inline void
359 typhoon_inc_rxfree_index(u32 *index, const int count)
360 {
361 typhoon_inc_index(index, count, RXFREE_ENTRIES);
362 }
363
364 static inline void
365 typhoon_inc_tx_index(u32 *index, const int count)
366 {
367 /* if we start using the Hi Tx ring, this needs updateing */
368 typhoon_inc_index(index, count, TXLO_ENTRIES);
369 }
370
371 static inline void
372 typhoon_inc_rx_index(u32 *index, const int count)
373 {
374 /* sizeof(struct rx_desc) != sizeof(struct cmd_desc) */
375 *index += count * sizeof(struct rx_desc);
376 *index %= RX_ENTRIES * sizeof(struct rx_desc);
377 }
378
379 static int
380 typhoon_reset(void __iomem *ioaddr, int wait_type)
381 {
382 int i, err = 0;
383 int timeout;
384
385 if(wait_type == WaitNoSleep)
386 timeout = TYPHOON_RESET_TIMEOUT_NOSLEEP;
387 else
388 timeout = TYPHOON_RESET_TIMEOUT_SLEEP;
389
390 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
391 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
392
393 iowrite32(TYPHOON_RESET_ALL, ioaddr + TYPHOON_REG_SOFT_RESET);
394 typhoon_post_pci_writes(ioaddr);
395 udelay(1);
396 iowrite32(TYPHOON_RESET_NONE, ioaddr + TYPHOON_REG_SOFT_RESET);
397
398 if(wait_type != NoWait) {
399 for(i = 0; i < timeout; i++) {
400 if(ioread32(ioaddr + TYPHOON_REG_STATUS) ==
401 TYPHOON_STATUS_WAITING_FOR_HOST)
402 goto out;
403
404 if(wait_type == WaitSleep)
405 schedule_timeout_uninterruptible(1);
406 else
407 udelay(TYPHOON_UDELAY);
408 }
409
410 err = -ETIMEDOUT;
411 }
412
413 out:
414 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
415 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
416
417 /* The 3XP seems to need a little extra time to complete the load
418 * of the sleep image before we can reliably boot it. Failure to
419 * do this occasionally results in a hung adapter after boot in
420 * typhoon_init_one() while trying to read the MAC address or
421 * putting the card to sleep. 3Com's driver waits 5ms, but
422 * that seems to be overkill. However, if we can sleep, we might
423 * as well give it that much time. Otherwise, we'll give it 500us,
424 * which should be enough (I've see it work well at 100us, but still
425 * saw occasional problems.)
426 */
427 if(wait_type == WaitSleep)
428 msleep(5);
429 else
430 udelay(500);
431 return err;
432 }
433
434 static int
435 typhoon_wait_status(void __iomem *ioaddr, u32 wait_value)
436 {
437 int i, err = 0;
438
439 for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
440 if(ioread32(ioaddr + TYPHOON_REG_STATUS) == wait_value)
441 goto out;
442 udelay(TYPHOON_UDELAY);
443 }
444
445 err = -ETIMEDOUT;
446
447 out:
448 return err;
449 }
450
451 static inline void
452 typhoon_media_status(struct net_device *dev, struct resp_desc *resp)
453 {
454 if(resp->parm1 & TYPHOON_MEDIA_STAT_NO_LINK)
455 netif_carrier_off(dev);
456 else
457 netif_carrier_on(dev);
458 }
459
460 static inline void
461 typhoon_hello(struct typhoon *tp)
462 {
463 struct basic_ring *ring = &tp->cmdRing;
464 struct cmd_desc *cmd;
465
466 /* We only get a hello request if we've not sent anything to the
467 * card in a long while. If the lock is held, then we're in the
468 * process of issuing a command, so we don't need to respond.
469 */
470 if(spin_trylock(&tp->command_lock)) {
471 cmd = (struct cmd_desc *)(ring->ringBase + ring->lastWrite);
472 typhoon_inc_cmd_index(&ring->lastWrite, 1);
473
474 INIT_COMMAND_NO_RESPONSE(cmd, TYPHOON_CMD_HELLO_RESP);
475 wmb();
476 iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
477 spin_unlock(&tp->command_lock);
478 }
479 }
480
481 static int
482 typhoon_process_response(struct typhoon *tp, int resp_size,
483 struct resp_desc *resp_save)
484 {
485 struct typhoon_indexes *indexes = tp->indexes;
486 struct resp_desc *resp;
487 u8 *base = tp->respRing.ringBase;
488 int count, len, wrap_len;
489 u32 cleared;
490 u32 ready;
491
492 cleared = le32_to_cpu(indexes->respCleared);
493 ready = le32_to_cpu(indexes->respReady);
494 while(cleared != ready) {
495 resp = (struct resp_desc *)(base + cleared);
496 count = resp->numDesc + 1;
497 if(resp_save && resp->seqNo) {
498 if(count > resp_size) {
499 resp_save->flags = TYPHOON_RESP_ERROR;
500 goto cleanup;
501 }
502
503 wrap_len = 0;
504 len = count * sizeof(*resp);
505 if(unlikely(cleared + len > RESPONSE_RING_SIZE)) {
506 wrap_len = cleared + len - RESPONSE_RING_SIZE;
507 len = RESPONSE_RING_SIZE - cleared;
508 }
509
510 memcpy(resp_save, resp, len);
511 if(unlikely(wrap_len)) {
512 resp_save += len / sizeof(*resp);
513 memcpy(resp_save, base, wrap_len);
514 }
515
516 resp_save = NULL;
517 } else if(resp->cmd == TYPHOON_CMD_READ_MEDIA_STATUS) {
518 typhoon_media_status(tp->dev, resp);
519 } else if(resp->cmd == TYPHOON_CMD_HELLO_RESP) {
520 typhoon_hello(tp);
521 } else {
522 netdev_err(tp->dev,
523 "dumping unexpected response 0x%04x:%d:0x%02x:0x%04x:%08x:%08x\n",
524 le16_to_cpu(resp->cmd),
525 resp->numDesc, resp->flags,
526 le16_to_cpu(resp->parm1),
527 le32_to_cpu(resp->parm2),
528 le32_to_cpu(resp->parm3));
529 }
530
531 cleanup:
532 typhoon_inc_resp_index(&cleared, count);
533 }
534
535 indexes->respCleared = cpu_to_le32(cleared);
536 wmb();
537 return resp_save == NULL;
538 }
539
540 static inline int
541 typhoon_num_free(int lastWrite, int lastRead, int ringSize)
542 {
543 /* this works for all descriptors but rx_desc, as they are a
544 * different size than the cmd_desc -- everyone else is the same
545 */
546 lastWrite /= sizeof(struct cmd_desc);
547 lastRead /= sizeof(struct cmd_desc);
548 return (ringSize + lastRead - lastWrite - 1) % ringSize;
549 }
550
551 static inline int
552 typhoon_num_free_cmd(struct typhoon *tp)
553 {
554 int lastWrite = tp->cmdRing.lastWrite;
555 int cmdCleared = le32_to_cpu(tp->indexes->cmdCleared);
556
557 return typhoon_num_free(lastWrite, cmdCleared, COMMAND_ENTRIES);
558 }
559
560 static inline int
561 typhoon_num_free_resp(struct typhoon *tp)
562 {
563 int respReady = le32_to_cpu(tp->indexes->respReady);
564 int respCleared = le32_to_cpu(tp->indexes->respCleared);
565
566 return typhoon_num_free(respReady, respCleared, RESPONSE_ENTRIES);
567 }
568
569 static inline int
570 typhoon_num_free_tx(struct transmit_ring *ring)
571 {
572 /* if we start using the Hi Tx ring, this needs updating */
573 return typhoon_num_free(ring->lastWrite, ring->lastRead, TXLO_ENTRIES);
574 }
575
576 static int
577 typhoon_issue_command(struct typhoon *tp, int num_cmd, struct cmd_desc *cmd,
578 int num_resp, struct resp_desc *resp)
579 {
580 struct typhoon_indexes *indexes = tp->indexes;
581 struct basic_ring *ring = &tp->cmdRing;
582 struct resp_desc local_resp;
583 int i, err = 0;
584 int got_resp;
585 int freeCmd, freeResp;
586 int len, wrap_len;
587
588 spin_lock(&tp->command_lock);
589
590 freeCmd = typhoon_num_free_cmd(tp);
591 freeResp = typhoon_num_free_resp(tp);
592
593 if(freeCmd < num_cmd || freeResp < num_resp) {
594 netdev_err(tp->dev, "no descs for cmd, had (needed) %d (%d) cmd, %d (%d) resp\n",
595 freeCmd, num_cmd, freeResp, num_resp);
596 err = -ENOMEM;
597 goto out;
598 }
599
600 if(cmd->flags & TYPHOON_CMD_RESPOND) {
601 /* If we're expecting a response, but the caller hasn't given
602 * us a place to put it, we'll provide one.
603 */
604 tp->awaiting_resp = 1;
605 if(resp == NULL) {
606 resp = &local_resp;
607 num_resp = 1;
608 }
609 }
610
611 wrap_len = 0;
612 len = num_cmd * sizeof(*cmd);
613 if(unlikely(ring->lastWrite + len > COMMAND_RING_SIZE)) {
614 wrap_len = ring->lastWrite + len - COMMAND_RING_SIZE;
615 len = COMMAND_RING_SIZE - ring->lastWrite;
616 }
617
618 memcpy(ring->ringBase + ring->lastWrite, cmd, len);
619 if(unlikely(wrap_len)) {
620 struct cmd_desc *wrap_ptr = cmd;
621 wrap_ptr += len / sizeof(*cmd);
622 memcpy(ring->ringBase, wrap_ptr, wrap_len);
623 }
624
625 typhoon_inc_cmd_index(&ring->lastWrite, num_cmd);
626
627 /* "I feel a presence... another warrior is on the mesa."
628 */
629 wmb();
630 iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
631 typhoon_post_pci_writes(tp->ioaddr);
632
633 if((cmd->flags & TYPHOON_CMD_RESPOND) == 0)
634 goto out;
635
636 /* Ugh. We'll be here about 8ms, spinning our thumbs, unable to
637 * preempt or do anything other than take interrupts. So, don't
638 * wait for a response unless you have to.
639 *
640 * I've thought about trying to sleep here, but we're called
641 * from many contexts that don't allow that. Also, given the way
642 * 3Com has implemented irq coalescing, we would likely timeout --
643 * this has been observed in real life!
644 *
645 * The big killer is we have to wait to get stats from the card,
646 * though we could go to a periodic refresh of those if we don't
647 * mind them getting somewhat stale. The rest of the waiting
648 * commands occur during open/close/suspend/resume, so they aren't
649 * time critical. Creating SAs in the future will also have to
650 * wait here.
651 */
652 got_resp = 0;
653 for(i = 0; i < TYPHOON_WAIT_TIMEOUT && !got_resp; i++) {
654 if(indexes->respCleared != indexes->respReady)
655 got_resp = typhoon_process_response(tp, num_resp,
656 resp);
657 udelay(TYPHOON_UDELAY);
658 }
659
660 if(!got_resp) {
661 err = -ETIMEDOUT;
662 goto out;
663 }
664
665 /* Collect the error response even if we don't care about the
666 * rest of the response
667 */
668 if(resp->flags & TYPHOON_RESP_ERROR)
669 err = -EIO;
670
671 out:
672 if(tp->awaiting_resp) {
673 tp->awaiting_resp = 0;
674 smp_wmb();
675
676 /* Ugh. If a response was added to the ring between
677 * the call to typhoon_process_response() and the clearing
678 * of tp->awaiting_resp, we could have missed the interrupt
679 * and it could hang in the ring an indeterminate amount of
680 * time. So, check for it, and interrupt ourselves if this
681 * is the case.
682 */
683 if(indexes->respCleared != indexes->respReady)
684 iowrite32(1, tp->ioaddr + TYPHOON_REG_SELF_INTERRUPT);
685 }
686
687 spin_unlock(&tp->command_lock);
688 return err;
689 }
690
691 static inline void
692 typhoon_tso_fill(struct sk_buff *skb, struct transmit_ring *txRing,
693 u32 ring_dma)
694 {
695 struct tcpopt_desc *tcpd;
696 u32 tcpd_offset = ring_dma;
697
698 tcpd = (struct tcpopt_desc *) (txRing->ringBase + txRing->lastWrite);
699 tcpd_offset += txRing->lastWrite;
700 tcpd_offset += offsetof(struct tcpopt_desc, bytesTx);
701 typhoon_inc_tx_index(&txRing->lastWrite, 1);
702
703 tcpd->flags = TYPHOON_OPT_DESC | TYPHOON_OPT_TCP_SEG;
704 tcpd->numDesc = 1;
705 tcpd->mss_flags = cpu_to_le16(skb_tso_size(skb));
706 tcpd->mss_flags |= TYPHOON_TSO_FIRST | TYPHOON_TSO_LAST;
707 tcpd->respAddrLo = cpu_to_le32(tcpd_offset);
708 tcpd->bytesTx = cpu_to_le32(skb->len);
709 tcpd->status = 0;
710 }
711
712 static netdev_tx_t
713 typhoon_start_tx(struct sk_buff *skb, struct net_device *dev)
714 {
715 struct typhoon *tp = netdev_priv(dev);
716 struct transmit_ring *txRing;
717 struct tx_desc *txd, *first_txd;
718 dma_addr_t skb_dma;
719 int numDesc;
720
721 /* we have two rings to choose from, but we only use txLo for now
722 * If we start using the Hi ring as well, we'll need to update
723 * typhoon_stop_runtime(), typhoon_interrupt(), typhoon_num_free_tx(),
724 * and TXHI_ENTRIES to match, as well as update the TSO code below
725 * to get the right DMA address
726 */
727 txRing = &tp->txLoRing;
728
729 /* We need one descriptor for each fragment of the sk_buff, plus the
730 * one for the ->data area of it.
731 *
732 * The docs say a maximum of 16 fragment descriptors per TCP option
733 * descriptor, then make a new packet descriptor and option descriptor
734 * for the next 16 fragments. The engineers say just an option
735 * descriptor is needed. I've tested up to 26 fragments with a single
736 * packet descriptor/option descriptor combo, so I use that for now.
737 *
738 * If problems develop with TSO, check this first.
739 */
740 numDesc = skb_shinfo(skb)->nr_frags + 1;
741 if (skb_is_gso(skb))
742 numDesc++;
743
744 /* When checking for free space in the ring, we need to also
745 * account for the initial Tx descriptor, and we always must leave
746 * at least one descriptor unused in the ring so that it doesn't
747 * wrap and look empty.
748 *
749 * The only time we should loop here is when we hit the race
750 * between marking the queue awake and updating the cleared index.
751 * Just loop and it will appear. This comes from the acenic driver.
752 */
753 while(unlikely(typhoon_num_free_tx(txRing) < (numDesc + 2)))
754 smp_rmb();
755
756 first_txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
757 typhoon_inc_tx_index(&txRing->lastWrite, 1);
758
759 first_txd->flags = TYPHOON_TX_DESC | TYPHOON_DESC_VALID;
760 first_txd->numDesc = 0;
761 first_txd->len = 0;
762 first_txd->tx_addr = (u64)((unsigned long) skb);
763 first_txd->processFlags = 0;
764
765 if(skb->ip_summed == CHECKSUM_PARTIAL) {
766 /* The 3XP will figure out if this is UDP/TCP */
767 first_txd->processFlags |= TYPHOON_TX_PF_TCP_CHKSUM;
768 first_txd->processFlags |= TYPHOON_TX_PF_UDP_CHKSUM;
769 first_txd->processFlags |= TYPHOON_TX_PF_IP_CHKSUM;
770 }
771
772 if(vlan_tx_tag_present(skb)) {
773 first_txd->processFlags |=
774 TYPHOON_TX_PF_INSERT_VLAN | TYPHOON_TX_PF_VLAN_PRIORITY;
775 first_txd->processFlags |=
776 cpu_to_le32(htons(vlan_tx_tag_get(skb)) <<
777 TYPHOON_TX_PF_VLAN_TAG_SHIFT);
778 }
779
780 if (skb_is_gso(skb)) {
781 first_txd->processFlags |= TYPHOON_TX_PF_TCP_SEGMENT;
782 first_txd->numDesc++;
783
784 typhoon_tso_fill(skb, txRing, tp->txlo_dma_addr);
785 }
786
787 txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
788 typhoon_inc_tx_index(&txRing->lastWrite, 1);
789
790 /* No need to worry about padding packet -- the firmware pads
791 * it with zeros to ETH_ZLEN for us.
792 */
793 if(skb_shinfo(skb)->nr_frags == 0) {
794 skb_dma = pci_map_single(tp->tx_pdev, skb->data, skb->len,
795 PCI_DMA_TODEVICE);
796 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
797 txd->len = cpu_to_le16(skb->len);
798 txd->frag.addr = cpu_to_le32(skb_dma);
799 txd->frag.addrHi = 0;
800 first_txd->numDesc++;
801 } else {
802 int i, len;
803
804 len = skb_headlen(skb);
805 skb_dma = pci_map_single(tp->tx_pdev, skb->data, len,
806 PCI_DMA_TODEVICE);
807 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
808 txd->len = cpu_to_le16(len);
809 txd->frag.addr = cpu_to_le32(skb_dma);
810 txd->frag.addrHi = 0;
811 first_txd->numDesc++;
812
813 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
814 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
815 void *frag_addr;
816
817 txd = (struct tx_desc *) (txRing->ringBase +
818 txRing->lastWrite);
819 typhoon_inc_tx_index(&txRing->lastWrite, 1);
820
821 len = skb_frag_size(frag);
822 frag_addr = skb_frag_address(frag);
823 skb_dma = pci_map_single(tp->tx_pdev, frag_addr, len,
824 PCI_DMA_TODEVICE);
825 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
826 txd->len = cpu_to_le16(len);
827 txd->frag.addr = cpu_to_le32(skb_dma);
828 txd->frag.addrHi = 0;
829 first_txd->numDesc++;
830 }
831 }
832
833 /* Kick the 3XP
834 */
835 wmb();
836 iowrite32(txRing->lastWrite, tp->tx_ioaddr + txRing->writeRegister);
837
838 /* If we don't have room to put the worst case packet on the
839 * queue, then we must stop the queue. We need 2 extra
840 * descriptors -- one to prevent ring wrap, and one for the
841 * Tx header.
842 */
843 numDesc = MAX_SKB_FRAGS + TSO_NUM_DESCRIPTORS + 1;
844
845 if(typhoon_num_free_tx(txRing) < (numDesc + 2)) {
846 netif_stop_queue(dev);
847
848 /* A Tx complete IRQ could have gotten between, making
849 * the ring free again. Only need to recheck here, since
850 * Tx is serialized.
851 */
852 if(typhoon_num_free_tx(txRing) >= (numDesc + 2))
853 netif_wake_queue(dev);
854 }
855
856 return NETDEV_TX_OK;
857 }
858
859 static void
860 typhoon_set_rx_mode(struct net_device *dev)
861 {
862 struct typhoon *tp = netdev_priv(dev);
863 struct cmd_desc xp_cmd;
864 u32 mc_filter[2];
865 __le16 filter;
866
867 filter = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
868 if(dev->flags & IFF_PROMISC) {
869 filter |= TYPHOON_RX_FILTER_PROMISCOUS;
870 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
871 (dev->flags & IFF_ALLMULTI)) {
872 /* Too many to match, or accept all multicasts. */
873 filter |= TYPHOON_RX_FILTER_ALL_MCAST;
874 } else if (!netdev_mc_empty(dev)) {
875 struct netdev_hw_addr *ha;
876
877 memset(mc_filter, 0, sizeof(mc_filter));
878 netdev_for_each_mc_addr(ha, dev) {
879 int bit = ether_crc(ETH_ALEN, ha->addr) & 0x3f;
880 mc_filter[bit >> 5] |= 1 << (bit & 0x1f);
881 }
882
883 INIT_COMMAND_NO_RESPONSE(&xp_cmd,
884 TYPHOON_CMD_SET_MULTICAST_HASH);
885 xp_cmd.parm1 = TYPHOON_MCAST_HASH_SET;
886 xp_cmd.parm2 = cpu_to_le32(mc_filter[0]);
887 xp_cmd.parm3 = cpu_to_le32(mc_filter[1]);
888 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
889
890 filter |= TYPHOON_RX_FILTER_MCAST_HASH;
891 }
892
893 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
894 xp_cmd.parm1 = filter;
895 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
896 }
897
898 static int
899 typhoon_do_get_stats(struct typhoon *tp)
900 {
901 struct net_device_stats *stats = &tp->stats;
902 struct net_device_stats *saved = &tp->stats_saved;
903 struct cmd_desc xp_cmd;
904 struct resp_desc xp_resp[7];
905 struct stats_resp *s = (struct stats_resp *) xp_resp;
906 int err;
907
908 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_STATS);
909 err = typhoon_issue_command(tp, 1, &xp_cmd, 7, xp_resp);
910 if(err < 0)
911 return err;
912
913 /* 3Com's Linux driver uses txMultipleCollisions as it's
914 * collisions value, but there is some other collision info as well...
915 *
916 * The extra status reported would be a good candidate for
917 * ethtool_ops->get_{strings,stats}()
918 */
919 stats->tx_packets = le32_to_cpu(s->txPackets) +
920 saved->tx_packets;
921 stats->tx_bytes = le64_to_cpu(s->txBytes) +
922 saved->tx_bytes;
923 stats->tx_errors = le32_to_cpu(s->txCarrierLost) +
924 saved->tx_errors;
925 stats->tx_carrier_errors = le32_to_cpu(s->txCarrierLost) +
926 saved->tx_carrier_errors;
927 stats->collisions = le32_to_cpu(s->txMultipleCollisions) +
928 saved->collisions;
929 stats->rx_packets = le32_to_cpu(s->rxPacketsGood) +
930 saved->rx_packets;
931 stats->rx_bytes = le64_to_cpu(s->rxBytesGood) +
932 saved->rx_bytes;
933 stats->rx_fifo_errors = le32_to_cpu(s->rxFifoOverruns) +
934 saved->rx_fifo_errors;
935 stats->rx_errors = le32_to_cpu(s->rxFifoOverruns) +
936 le32_to_cpu(s->BadSSD) + le32_to_cpu(s->rxCrcErrors) +
937 saved->rx_errors;
938 stats->rx_crc_errors = le32_to_cpu(s->rxCrcErrors) +
939 saved->rx_crc_errors;
940 stats->rx_length_errors = le32_to_cpu(s->rxOversized) +
941 saved->rx_length_errors;
942 tp->speed = (s->linkStatus & TYPHOON_LINK_100MBPS) ?
943 SPEED_100 : SPEED_10;
944 tp->duplex = (s->linkStatus & TYPHOON_LINK_FULL_DUPLEX) ?
945 DUPLEX_FULL : DUPLEX_HALF;
946
947 return 0;
948 }
949
950 static struct net_device_stats *
951 typhoon_get_stats(struct net_device *dev)
952 {
953 struct typhoon *tp = netdev_priv(dev);
954 struct net_device_stats *stats = &tp->stats;
955 struct net_device_stats *saved = &tp->stats_saved;
956
957 smp_rmb();
958 if(tp->card_state == Sleeping)
959 return saved;
960
961 if(typhoon_do_get_stats(tp) < 0) {
962 netdev_err(dev, "error getting stats\n");
963 return saved;
964 }
965
966 return stats;
967 }
968
969 static int
970 typhoon_set_mac_address(struct net_device *dev, void *addr)
971 {
972 struct sockaddr *saddr = (struct sockaddr *) addr;
973
974 if(netif_running(dev))
975 return -EBUSY;
976
977 memcpy(dev->dev_addr, saddr->sa_data, dev->addr_len);
978 return 0;
979 }
980
981 static void
982 typhoon_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
983 {
984 struct typhoon *tp = netdev_priv(dev);
985 struct pci_dev *pci_dev = tp->pdev;
986 struct cmd_desc xp_cmd;
987 struct resp_desc xp_resp[3];
988
989 smp_rmb();
990 if(tp->card_state == Sleeping) {
991 strlcpy(info->fw_version, "Sleep image",
992 sizeof(info->fw_version));
993 } else {
994 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
995 if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
996 strlcpy(info->fw_version, "Unknown runtime",
997 sizeof(info->fw_version));
998 } else {
999 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
1000 snprintf(info->fw_version, sizeof(info->fw_version),
1001 "%02x.%03x.%03x", sleep_ver >> 24,
1002 (sleep_ver >> 12) & 0xfff, sleep_ver & 0xfff);
1003 }
1004 }
1005
1006 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1007 strlcpy(info->bus_info, pci_name(pci_dev), sizeof(info->bus_info));
1008 }
1009
1010 static int
1011 typhoon_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1012 {
1013 struct typhoon *tp = netdev_priv(dev);
1014
1015 cmd->supported = SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1016 SUPPORTED_Autoneg;
1017
1018 switch (tp->xcvr_select) {
1019 case TYPHOON_XCVR_10HALF:
1020 cmd->advertising = ADVERTISED_10baseT_Half;
1021 break;
1022 case TYPHOON_XCVR_10FULL:
1023 cmd->advertising = ADVERTISED_10baseT_Full;
1024 break;
1025 case TYPHOON_XCVR_100HALF:
1026 cmd->advertising = ADVERTISED_100baseT_Half;
1027 break;
1028 case TYPHOON_XCVR_100FULL:
1029 cmd->advertising = ADVERTISED_100baseT_Full;
1030 break;
1031 case TYPHOON_XCVR_AUTONEG:
1032 cmd->advertising = ADVERTISED_10baseT_Half |
1033 ADVERTISED_10baseT_Full |
1034 ADVERTISED_100baseT_Half |
1035 ADVERTISED_100baseT_Full |
1036 ADVERTISED_Autoneg;
1037 break;
1038 }
1039
1040 if(tp->capabilities & TYPHOON_FIBER) {
1041 cmd->supported |= SUPPORTED_FIBRE;
1042 cmd->advertising |= ADVERTISED_FIBRE;
1043 cmd->port = PORT_FIBRE;
1044 } else {
1045 cmd->supported |= SUPPORTED_10baseT_Half |
1046 SUPPORTED_10baseT_Full |
1047 SUPPORTED_TP;
1048 cmd->advertising |= ADVERTISED_TP;
1049 cmd->port = PORT_TP;
1050 }
1051
1052 /* need to get stats to make these link speed/duplex valid */
1053 typhoon_do_get_stats(tp);
1054 ethtool_cmd_speed_set(cmd, tp->speed);
1055 cmd->duplex = tp->duplex;
1056 cmd->phy_address = 0;
1057 cmd->transceiver = XCVR_INTERNAL;
1058 if(tp->xcvr_select == TYPHOON_XCVR_AUTONEG)
1059 cmd->autoneg = AUTONEG_ENABLE;
1060 else
1061 cmd->autoneg = AUTONEG_DISABLE;
1062 cmd->maxtxpkt = 1;
1063 cmd->maxrxpkt = 1;
1064
1065 return 0;
1066 }
1067
1068 static int
1069 typhoon_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1070 {
1071 struct typhoon *tp = netdev_priv(dev);
1072 u32 speed = ethtool_cmd_speed(cmd);
1073 struct cmd_desc xp_cmd;
1074 __le16 xcvr;
1075 int err;
1076
1077 err = -EINVAL;
1078 if (cmd->autoneg == AUTONEG_ENABLE) {
1079 xcvr = TYPHOON_XCVR_AUTONEG;
1080 } else {
1081 if (cmd->duplex == DUPLEX_HALF) {
1082 if (speed == SPEED_10)
1083 xcvr = TYPHOON_XCVR_10HALF;
1084 else if (speed == SPEED_100)
1085 xcvr = TYPHOON_XCVR_100HALF;
1086 else
1087 goto out;
1088 } else if (cmd->duplex == DUPLEX_FULL) {
1089 if (speed == SPEED_10)
1090 xcvr = TYPHOON_XCVR_10FULL;
1091 else if (speed == SPEED_100)
1092 xcvr = TYPHOON_XCVR_100FULL;
1093 else
1094 goto out;
1095 } else
1096 goto out;
1097 }
1098
1099 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1100 xp_cmd.parm1 = xcvr;
1101 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1102 if(err < 0)
1103 goto out;
1104
1105 tp->xcvr_select = xcvr;
1106 if(cmd->autoneg == AUTONEG_ENABLE) {
1107 tp->speed = 0xff; /* invalid */
1108 tp->duplex = 0xff; /* invalid */
1109 } else {
1110 tp->speed = speed;
1111 tp->duplex = cmd->duplex;
1112 }
1113
1114 out:
1115 return err;
1116 }
1117
1118 static void
1119 typhoon_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1120 {
1121 struct typhoon *tp = netdev_priv(dev);
1122
1123 wol->supported = WAKE_PHY | WAKE_MAGIC;
1124 wol->wolopts = 0;
1125 if(tp->wol_events & TYPHOON_WAKE_LINK_EVENT)
1126 wol->wolopts |= WAKE_PHY;
1127 if(tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
1128 wol->wolopts |= WAKE_MAGIC;
1129 memset(&wol->sopass, 0, sizeof(wol->sopass));
1130 }
1131
1132 static int
1133 typhoon_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1134 {
1135 struct typhoon *tp = netdev_priv(dev);
1136
1137 if(wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
1138 return -EINVAL;
1139
1140 tp->wol_events = 0;
1141 if(wol->wolopts & WAKE_PHY)
1142 tp->wol_events |= TYPHOON_WAKE_LINK_EVENT;
1143 if(wol->wolopts & WAKE_MAGIC)
1144 tp->wol_events |= TYPHOON_WAKE_MAGIC_PKT;
1145
1146 return 0;
1147 }
1148
1149 static void
1150 typhoon_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
1151 {
1152 ering->rx_max_pending = RXENT_ENTRIES;
1153 ering->tx_max_pending = TXLO_ENTRIES - 1;
1154
1155 ering->rx_pending = RXENT_ENTRIES;
1156 ering->tx_pending = TXLO_ENTRIES - 1;
1157 }
1158
1159 static const struct ethtool_ops typhoon_ethtool_ops = {
1160 .get_settings = typhoon_get_settings,
1161 .set_settings = typhoon_set_settings,
1162 .get_drvinfo = typhoon_get_drvinfo,
1163 .get_wol = typhoon_get_wol,
1164 .set_wol = typhoon_set_wol,
1165 .get_link = ethtool_op_get_link,
1166 .get_ringparam = typhoon_get_ringparam,
1167 };
1168
1169 static int
1170 typhoon_wait_interrupt(void __iomem *ioaddr)
1171 {
1172 int i, err = 0;
1173
1174 for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
1175 if(ioread32(ioaddr + TYPHOON_REG_INTR_STATUS) &
1176 TYPHOON_INTR_BOOTCMD)
1177 goto out;
1178 udelay(TYPHOON_UDELAY);
1179 }
1180
1181 err = -ETIMEDOUT;
1182
1183 out:
1184 iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1185 return err;
1186 }
1187
1188 #define shared_offset(x) offsetof(struct typhoon_shared, x)
1189
1190 static void
1191 typhoon_init_interface(struct typhoon *tp)
1192 {
1193 struct typhoon_interface *iface = &tp->shared->iface;
1194 dma_addr_t shared_dma;
1195
1196 memset(tp->shared, 0, sizeof(struct typhoon_shared));
1197
1198 /* The *Hi members of iface are all init'd to zero by the memset().
1199 */
1200 shared_dma = tp->shared_dma + shared_offset(indexes);
1201 iface->ringIndex = cpu_to_le32(shared_dma);
1202
1203 shared_dma = tp->shared_dma + shared_offset(txLo);
1204 iface->txLoAddr = cpu_to_le32(shared_dma);
1205 iface->txLoSize = cpu_to_le32(TXLO_ENTRIES * sizeof(struct tx_desc));
1206
1207 shared_dma = tp->shared_dma + shared_offset(txHi);
1208 iface->txHiAddr = cpu_to_le32(shared_dma);
1209 iface->txHiSize = cpu_to_le32(TXHI_ENTRIES * sizeof(struct tx_desc));
1210
1211 shared_dma = tp->shared_dma + shared_offset(rxBuff);
1212 iface->rxBuffAddr = cpu_to_le32(shared_dma);
1213 iface->rxBuffSize = cpu_to_le32(RXFREE_ENTRIES *
1214 sizeof(struct rx_free));
1215
1216 shared_dma = tp->shared_dma + shared_offset(rxLo);
1217 iface->rxLoAddr = cpu_to_le32(shared_dma);
1218 iface->rxLoSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1219
1220 shared_dma = tp->shared_dma + shared_offset(rxHi);
1221 iface->rxHiAddr = cpu_to_le32(shared_dma);
1222 iface->rxHiSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1223
1224 shared_dma = tp->shared_dma + shared_offset(cmd);
1225 iface->cmdAddr = cpu_to_le32(shared_dma);
1226 iface->cmdSize = cpu_to_le32(COMMAND_RING_SIZE);
1227
1228 shared_dma = tp->shared_dma + shared_offset(resp);
1229 iface->respAddr = cpu_to_le32(shared_dma);
1230 iface->respSize = cpu_to_le32(RESPONSE_RING_SIZE);
1231
1232 shared_dma = tp->shared_dma + shared_offset(zeroWord);
1233 iface->zeroAddr = cpu_to_le32(shared_dma);
1234
1235 tp->indexes = &tp->shared->indexes;
1236 tp->txLoRing.ringBase = (u8 *) tp->shared->txLo;
1237 tp->txHiRing.ringBase = (u8 *) tp->shared->txHi;
1238 tp->rxLoRing.ringBase = (u8 *) tp->shared->rxLo;
1239 tp->rxHiRing.ringBase = (u8 *) tp->shared->rxHi;
1240 tp->rxBuffRing.ringBase = (u8 *) tp->shared->rxBuff;
1241 tp->cmdRing.ringBase = (u8 *) tp->shared->cmd;
1242 tp->respRing.ringBase = (u8 *) tp->shared->resp;
1243
1244 tp->txLoRing.writeRegister = TYPHOON_REG_TX_LO_READY;
1245 tp->txHiRing.writeRegister = TYPHOON_REG_TX_HI_READY;
1246
1247 tp->txlo_dma_addr = le32_to_cpu(iface->txLoAddr);
1248 tp->card_state = Sleeping;
1249
1250 tp->offload = TYPHOON_OFFLOAD_IP_CHKSUM | TYPHOON_OFFLOAD_TCP_CHKSUM;
1251 tp->offload |= TYPHOON_OFFLOAD_UDP_CHKSUM | TSO_OFFLOAD_ON;
1252 tp->offload |= TYPHOON_OFFLOAD_VLAN;
1253
1254 spin_lock_init(&tp->command_lock);
1255
1256 /* Force the writes to the shared memory area out before continuing. */
1257 wmb();
1258 }
1259
1260 static void
1261 typhoon_init_rings(struct typhoon *tp)
1262 {
1263 memset(tp->indexes, 0, sizeof(struct typhoon_indexes));
1264
1265 tp->txLoRing.lastWrite = 0;
1266 tp->txHiRing.lastWrite = 0;
1267 tp->rxLoRing.lastWrite = 0;
1268 tp->rxHiRing.lastWrite = 0;
1269 tp->rxBuffRing.lastWrite = 0;
1270 tp->cmdRing.lastWrite = 0;
1271 tp->respRing.lastWrite = 0;
1272
1273 tp->txLoRing.lastRead = 0;
1274 tp->txHiRing.lastRead = 0;
1275 }
1276
1277 static const struct firmware *typhoon_fw;
1278
1279 static int
1280 typhoon_request_firmware(struct typhoon *tp)
1281 {
1282 const struct typhoon_file_header *fHdr;
1283 const struct typhoon_section_header *sHdr;
1284 const u8 *image_data;
1285 u32 numSections;
1286 u32 section_len;
1287 u32 remaining;
1288 int err;
1289
1290 if (typhoon_fw)
1291 return 0;
1292
1293 err = request_firmware(&typhoon_fw, FIRMWARE_NAME, &tp->pdev->dev);
1294 if (err) {
1295 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
1296 FIRMWARE_NAME);
1297 return err;
1298 }
1299
1300 image_data = (u8 *) typhoon_fw->data;
1301 remaining = typhoon_fw->size;
1302 if (remaining < sizeof(struct typhoon_file_header))
1303 goto invalid_fw;
1304
1305 fHdr = (struct typhoon_file_header *) image_data;
1306 if (memcmp(fHdr->tag, "TYPHOON", 8))
1307 goto invalid_fw;
1308
1309 numSections = le32_to_cpu(fHdr->numSections);
1310 image_data += sizeof(struct typhoon_file_header);
1311 remaining -= sizeof(struct typhoon_file_header);
1312
1313 while (numSections--) {
1314 if (remaining < sizeof(struct typhoon_section_header))
1315 goto invalid_fw;
1316
1317 sHdr = (struct typhoon_section_header *) image_data;
1318 image_data += sizeof(struct typhoon_section_header);
1319 section_len = le32_to_cpu(sHdr->len);
1320
1321 if (remaining < section_len)
1322 goto invalid_fw;
1323
1324 image_data += section_len;
1325 remaining -= section_len;
1326 }
1327
1328 return 0;
1329
1330 invalid_fw:
1331 netdev_err(tp->dev, "Invalid firmware image\n");
1332 release_firmware(typhoon_fw);
1333 typhoon_fw = NULL;
1334 return -EINVAL;
1335 }
1336
1337 static int
1338 typhoon_download_firmware(struct typhoon *tp)
1339 {
1340 void __iomem *ioaddr = tp->ioaddr;
1341 struct pci_dev *pdev = tp->pdev;
1342 const struct typhoon_file_header *fHdr;
1343 const struct typhoon_section_header *sHdr;
1344 const u8 *image_data;
1345 void *dpage;
1346 dma_addr_t dpage_dma;
1347 __sum16 csum;
1348 u32 irqEnabled;
1349 u32 irqMasked;
1350 u32 numSections;
1351 u32 section_len;
1352 u32 len;
1353 u32 load_addr;
1354 u32 hmac;
1355 int i;
1356 int err;
1357
1358 image_data = (u8 *) typhoon_fw->data;
1359 fHdr = (struct typhoon_file_header *) image_data;
1360
1361 /* Cannot just map the firmware image using pci_map_single() as
1362 * the firmware is vmalloc()'d and may not be physically contiguous,
1363 * so we allocate some consistent memory to copy the sections into.
1364 */
1365 err = -ENOMEM;
1366 dpage = pci_alloc_consistent(pdev, PAGE_SIZE, &dpage_dma);
1367 if(!dpage) {
1368 netdev_err(tp->dev, "no DMA mem for firmware\n");
1369 goto err_out;
1370 }
1371
1372 irqEnabled = ioread32(ioaddr + TYPHOON_REG_INTR_ENABLE);
1373 iowrite32(irqEnabled | TYPHOON_INTR_BOOTCMD,
1374 ioaddr + TYPHOON_REG_INTR_ENABLE);
1375 irqMasked = ioread32(ioaddr + TYPHOON_REG_INTR_MASK);
1376 iowrite32(irqMasked | TYPHOON_INTR_BOOTCMD,
1377 ioaddr + TYPHOON_REG_INTR_MASK);
1378
1379 err = -ETIMEDOUT;
1380 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
1381 netdev_err(tp->dev, "card ready timeout\n");
1382 goto err_out_irq;
1383 }
1384
1385 numSections = le32_to_cpu(fHdr->numSections);
1386 load_addr = le32_to_cpu(fHdr->startAddr);
1387
1388 iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1389 iowrite32(load_addr, ioaddr + TYPHOON_REG_DOWNLOAD_BOOT_ADDR);
1390 hmac = le32_to_cpu(fHdr->hmacDigest[0]);
1391 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_0);
1392 hmac = le32_to_cpu(fHdr->hmacDigest[1]);
1393 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_1);
1394 hmac = le32_to_cpu(fHdr->hmacDigest[2]);
1395 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_2);
1396 hmac = le32_to_cpu(fHdr->hmacDigest[3]);
1397 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_3);
1398 hmac = le32_to_cpu(fHdr->hmacDigest[4]);
1399 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_4);
1400 typhoon_post_pci_writes(ioaddr);
1401 iowrite32(TYPHOON_BOOTCMD_RUNTIME_IMAGE, ioaddr + TYPHOON_REG_COMMAND);
1402
1403 image_data += sizeof(struct typhoon_file_header);
1404
1405 /* The ioread32() in typhoon_wait_interrupt() will force the
1406 * last write to the command register to post, so
1407 * we don't need a typhoon_post_pci_writes() after it.
1408 */
1409 for(i = 0; i < numSections; i++) {
1410 sHdr = (struct typhoon_section_header *) image_data;
1411 image_data += sizeof(struct typhoon_section_header);
1412 load_addr = le32_to_cpu(sHdr->startAddr);
1413 section_len = le32_to_cpu(sHdr->len);
1414
1415 while(section_len) {
1416 len = min_t(u32, section_len, PAGE_SIZE);
1417
1418 if(typhoon_wait_interrupt(ioaddr) < 0 ||
1419 ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1420 TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1421 netdev_err(tp->dev, "segment ready timeout\n");
1422 goto err_out_irq;
1423 }
1424
1425 /* Do an pseudo IPv4 checksum on the data -- first
1426 * need to convert each u16 to cpu order before
1427 * summing. Fortunately, due to the properties of
1428 * the checksum, we can do this once, at the end.
1429 */
1430 csum = csum_fold(csum_partial_copy_nocheck(image_data,
1431 dpage, len,
1432 0));
1433
1434 iowrite32(len, ioaddr + TYPHOON_REG_BOOT_LENGTH);
1435 iowrite32(le16_to_cpu((__force __le16)csum),
1436 ioaddr + TYPHOON_REG_BOOT_CHECKSUM);
1437 iowrite32(load_addr,
1438 ioaddr + TYPHOON_REG_BOOT_DEST_ADDR);
1439 iowrite32(0, ioaddr + TYPHOON_REG_BOOT_DATA_HI);
1440 iowrite32(dpage_dma, ioaddr + TYPHOON_REG_BOOT_DATA_LO);
1441 typhoon_post_pci_writes(ioaddr);
1442 iowrite32(TYPHOON_BOOTCMD_SEG_AVAILABLE,
1443 ioaddr + TYPHOON_REG_COMMAND);
1444
1445 image_data += len;
1446 load_addr += len;
1447 section_len -= len;
1448 }
1449 }
1450
1451 if(typhoon_wait_interrupt(ioaddr) < 0 ||
1452 ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1453 TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1454 netdev_err(tp->dev, "final segment ready timeout\n");
1455 goto err_out_irq;
1456 }
1457
1458 iowrite32(TYPHOON_BOOTCMD_DNLD_COMPLETE, ioaddr + TYPHOON_REG_COMMAND);
1459
1460 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1461 netdev_err(tp->dev, "boot ready timeout, status 0x%0x\n",
1462 ioread32(ioaddr + TYPHOON_REG_STATUS));
1463 goto err_out_irq;
1464 }
1465
1466 err = 0;
1467
1468 err_out_irq:
1469 iowrite32(irqMasked, ioaddr + TYPHOON_REG_INTR_MASK);
1470 iowrite32(irqEnabled, ioaddr + TYPHOON_REG_INTR_ENABLE);
1471
1472 pci_free_consistent(pdev, PAGE_SIZE, dpage, dpage_dma);
1473
1474 err_out:
1475 return err;
1476 }
1477
1478 static int
1479 typhoon_boot_3XP(struct typhoon *tp, u32 initial_status)
1480 {
1481 void __iomem *ioaddr = tp->ioaddr;
1482
1483 if(typhoon_wait_status(ioaddr, initial_status) < 0) {
1484 netdev_err(tp->dev, "boot ready timeout\n");
1485 goto out_timeout;
1486 }
1487
1488 iowrite32(0, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_HI);
1489 iowrite32(tp->shared_dma, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_LO);
1490 typhoon_post_pci_writes(ioaddr);
1491 iowrite32(TYPHOON_BOOTCMD_REG_BOOT_RECORD,
1492 ioaddr + TYPHOON_REG_COMMAND);
1493
1494 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_RUNNING) < 0) {
1495 netdev_err(tp->dev, "boot finish timeout (status 0x%x)\n",
1496 ioread32(ioaddr + TYPHOON_REG_STATUS));
1497 goto out_timeout;
1498 }
1499
1500 /* Clear the Transmit and Command ready registers
1501 */
1502 iowrite32(0, ioaddr + TYPHOON_REG_TX_HI_READY);
1503 iowrite32(0, ioaddr + TYPHOON_REG_CMD_READY);
1504 iowrite32(0, ioaddr + TYPHOON_REG_TX_LO_READY);
1505 typhoon_post_pci_writes(ioaddr);
1506 iowrite32(TYPHOON_BOOTCMD_BOOT, ioaddr + TYPHOON_REG_COMMAND);
1507
1508 return 0;
1509
1510 out_timeout:
1511 return -ETIMEDOUT;
1512 }
1513
1514 static u32
1515 typhoon_clean_tx(struct typhoon *tp, struct transmit_ring *txRing,
1516 volatile __le32 * index)
1517 {
1518 u32 lastRead = txRing->lastRead;
1519 struct tx_desc *tx;
1520 dma_addr_t skb_dma;
1521 int dma_len;
1522 int type;
1523
1524 while(lastRead != le32_to_cpu(*index)) {
1525 tx = (struct tx_desc *) (txRing->ringBase + lastRead);
1526 type = tx->flags & TYPHOON_TYPE_MASK;
1527
1528 if(type == TYPHOON_TX_DESC) {
1529 /* This tx_desc describes a packet.
1530 */
1531 unsigned long ptr = tx->tx_addr;
1532 struct sk_buff *skb = (struct sk_buff *) ptr;
1533 dev_kfree_skb_irq(skb);
1534 } else if(type == TYPHOON_FRAG_DESC) {
1535 /* This tx_desc describes a memory mapping. Free it.
1536 */
1537 skb_dma = (dma_addr_t) le32_to_cpu(tx->frag.addr);
1538 dma_len = le16_to_cpu(tx->len);
1539 pci_unmap_single(tp->pdev, skb_dma, dma_len,
1540 PCI_DMA_TODEVICE);
1541 }
1542
1543 tx->flags = 0;
1544 typhoon_inc_tx_index(&lastRead, 1);
1545 }
1546
1547 return lastRead;
1548 }
1549
1550 static void
1551 typhoon_tx_complete(struct typhoon *tp, struct transmit_ring *txRing,
1552 volatile __le32 * index)
1553 {
1554 u32 lastRead;
1555 int numDesc = MAX_SKB_FRAGS + 1;
1556
1557 /* This will need changing if we start to use the Hi Tx ring. */
1558 lastRead = typhoon_clean_tx(tp, txRing, index);
1559 if(netif_queue_stopped(tp->dev) && typhoon_num_free(txRing->lastWrite,
1560 lastRead, TXLO_ENTRIES) > (numDesc + 2))
1561 netif_wake_queue(tp->dev);
1562
1563 txRing->lastRead = lastRead;
1564 smp_wmb();
1565 }
1566
1567 static void
1568 typhoon_recycle_rx_skb(struct typhoon *tp, u32 idx)
1569 {
1570 struct typhoon_indexes *indexes = tp->indexes;
1571 struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1572 struct basic_ring *ring = &tp->rxBuffRing;
1573 struct rx_free *r;
1574
1575 if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1576 le32_to_cpu(indexes->rxBuffCleared)) {
1577 /* no room in ring, just drop the skb
1578 */
1579 dev_kfree_skb_any(rxb->skb);
1580 rxb->skb = NULL;
1581 return;
1582 }
1583
1584 r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1585 typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1586 r->virtAddr = idx;
1587 r->physAddr = cpu_to_le32(rxb->dma_addr);
1588
1589 /* Tell the card about it */
1590 wmb();
1591 indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1592 }
1593
1594 static int
1595 typhoon_alloc_rx_skb(struct typhoon *tp, u32 idx)
1596 {
1597 struct typhoon_indexes *indexes = tp->indexes;
1598 struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1599 struct basic_ring *ring = &tp->rxBuffRing;
1600 struct rx_free *r;
1601 struct sk_buff *skb;
1602 dma_addr_t dma_addr;
1603
1604 rxb->skb = NULL;
1605
1606 if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1607 le32_to_cpu(indexes->rxBuffCleared))
1608 return -ENOMEM;
1609
1610 skb = dev_alloc_skb(PKT_BUF_SZ);
1611 if(!skb)
1612 return -ENOMEM;
1613
1614 #if 0
1615 /* Please, 3com, fix the firmware to allow DMA to a unaligned
1616 * address! Pretty please?
1617 */
1618 skb_reserve(skb, 2);
1619 #endif
1620
1621 skb->dev = tp->dev;
1622 dma_addr = pci_map_single(tp->pdev, skb->data,
1623 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
1624
1625 /* Since no card does 64 bit DAC, the high bits will never
1626 * change from zero.
1627 */
1628 r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1629 typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1630 r->virtAddr = idx;
1631 r->physAddr = cpu_to_le32(dma_addr);
1632 rxb->skb = skb;
1633 rxb->dma_addr = dma_addr;
1634
1635 /* Tell the card about it */
1636 wmb();
1637 indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1638 return 0;
1639 }
1640
1641 static int
1642 typhoon_rx(struct typhoon *tp, struct basic_ring *rxRing, volatile __le32 * ready,
1643 volatile __le32 * cleared, int budget)
1644 {
1645 struct rx_desc *rx;
1646 struct sk_buff *skb, *new_skb;
1647 struct rxbuff_ent *rxb;
1648 dma_addr_t dma_addr;
1649 u32 local_ready;
1650 u32 rxaddr;
1651 int pkt_len;
1652 u32 idx;
1653 __le32 csum_bits;
1654 int received;
1655
1656 received = 0;
1657 local_ready = le32_to_cpu(*ready);
1658 rxaddr = le32_to_cpu(*cleared);
1659 while(rxaddr != local_ready && budget > 0) {
1660 rx = (struct rx_desc *) (rxRing->ringBase + rxaddr);
1661 idx = rx->addr;
1662 rxb = &tp->rxbuffers[idx];
1663 skb = rxb->skb;
1664 dma_addr = rxb->dma_addr;
1665
1666 typhoon_inc_rx_index(&rxaddr, 1);
1667
1668 if(rx->flags & TYPHOON_RX_ERROR) {
1669 typhoon_recycle_rx_skb(tp, idx);
1670 continue;
1671 }
1672
1673 pkt_len = le16_to_cpu(rx->frameLen);
1674
1675 if(pkt_len < rx_copybreak &&
1676 (new_skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1677 skb_reserve(new_skb, 2);
1678 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr,
1679 PKT_BUF_SZ,
1680 PCI_DMA_FROMDEVICE);
1681 skb_copy_to_linear_data(new_skb, skb->data, pkt_len);
1682 pci_dma_sync_single_for_device(tp->pdev, dma_addr,
1683 PKT_BUF_SZ,
1684 PCI_DMA_FROMDEVICE);
1685 skb_put(new_skb, pkt_len);
1686 typhoon_recycle_rx_skb(tp, idx);
1687 } else {
1688 new_skb = skb;
1689 skb_put(new_skb, pkt_len);
1690 pci_unmap_single(tp->pdev, dma_addr, PKT_BUF_SZ,
1691 PCI_DMA_FROMDEVICE);
1692 typhoon_alloc_rx_skb(tp, idx);
1693 }
1694 new_skb->protocol = eth_type_trans(new_skb, tp->dev);
1695 csum_bits = rx->rxStatus & (TYPHOON_RX_IP_CHK_GOOD |
1696 TYPHOON_RX_UDP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD);
1697 if(csum_bits ==
1698 (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD) ||
1699 csum_bits ==
1700 (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_UDP_CHK_GOOD)) {
1701 new_skb->ip_summed = CHECKSUM_UNNECESSARY;
1702 } else
1703 skb_checksum_none_assert(new_skb);
1704
1705 if (rx->rxStatus & TYPHOON_RX_VLAN)
1706 __vlan_hwaccel_put_tag(new_skb,
1707 ntohl(rx->vlanTag) & 0xffff);
1708 netif_receive_skb(new_skb);
1709
1710 received++;
1711 budget--;
1712 }
1713 *cleared = cpu_to_le32(rxaddr);
1714
1715 return received;
1716 }
1717
1718 static void
1719 typhoon_fill_free_ring(struct typhoon *tp)
1720 {
1721 u32 i;
1722
1723 for(i = 0; i < RXENT_ENTRIES; i++) {
1724 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1725 if(rxb->skb)
1726 continue;
1727 if(typhoon_alloc_rx_skb(tp, i) < 0)
1728 break;
1729 }
1730 }
1731
1732 static int
1733 typhoon_poll(struct napi_struct *napi, int budget)
1734 {
1735 struct typhoon *tp = container_of(napi, struct typhoon, napi);
1736 struct typhoon_indexes *indexes = tp->indexes;
1737 int work_done;
1738
1739 rmb();
1740 if(!tp->awaiting_resp && indexes->respReady != indexes->respCleared)
1741 typhoon_process_response(tp, 0, NULL);
1742
1743 if(le32_to_cpu(indexes->txLoCleared) != tp->txLoRing.lastRead)
1744 typhoon_tx_complete(tp, &tp->txLoRing, &indexes->txLoCleared);
1745
1746 work_done = 0;
1747
1748 if(indexes->rxHiCleared != indexes->rxHiReady) {
1749 work_done += typhoon_rx(tp, &tp->rxHiRing, &indexes->rxHiReady,
1750 &indexes->rxHiCleared, budget);
1751 }
1752
1753 if(indexes->rxLoCleared != indexes->rxLoReady) {
1754 work_done += typhoon_rx(tp, &tp->rxLoRing, &indexes->rxLoReady,
1755 &indexes->rxLoCleared, budget - work_done);
1756 }
1757
1758 if(le32_to_cpu(indexes->rxBuffCleared) == tp->rxBuffRing.lastWrite) {
1759 /* rxBuff ring is empty, try to fill it. */
1760 typhoon_fill_free_ring(tp);
1761 }
1762
1763 if (work_done < budget) {
1764 napi_complete(napi);
1765 iowrite32(TYPHOON_INTR_NONE,
1766 tp->ioaddr + TYPHOON_REG_INTR_MASK);
1767 typhoon_post_pci_writes(tp->ioaddr);
1768 }
1769
1770 return work_done;
1771 }
1772
1773 static irqreturn_t
1774 typhoon_interrupt(int irq, void *dev_instance)
1775 {
1776 struct net_device *dev = dev_instance;
1777 struct typhoon *tp = netdev_priv(dev);
1778 void __iomem *ioaddr = tp->ioaddr;
1779 u32 intr_status;
1780
1781 intr_status = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
1782 if(!(intr_status & TYPHOON_INTR_HOST_INT))
1783 return IRQ_NONE;
1784
1785 iowrite32(intr_status, ioaddr + TYPHOON_REG_INTR_STATUS);
1786
1787 if (napi_schedule_prep(&tp->napi)) {
1788 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
1789 typhoon_post_pci_writes(ioaddr);
1790 __napi_schedule(&tp->napi);
1791 } else {
1792 netdev_err(dev, "Error, poll already scheduled\n");
1793 }
1794 return IRQ_HANDLED;
1795 }
1796
1797 static void
1798 typhoon_free_rx_rings(struct typhoon *tp)
1799 {
1800 u32 i;
1801
1802 for(i = 0; i < RXENT_ENTRIES; i++) {
1803 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1804 if(rxb->skb) {
1805 pci_unmap_single(tp->pdev, rxb->dma_addr, PKT_BUF_SZ,
1806 PCI_DMA_FROMDEVICE);
1807 dev_kfree_skb(rxb->skb);
1808 rxb->skb = NULL;
1809 }
1810 }
1811 }
1812
1813 static int
1814 typhoon_sleep(struct typhoon *tp, pci_power_t state, __le16 events)
1815 {
1816 struct pci_dev *pdev = tp->pdev;
1817 void __iomem *ioaddr = tp->ioaddr;
1818 struct cmd_desc xp_cmd;
1819 int err;
1820
1821 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_ENABLE_WAKE_EVENTS);
1822 xp_cmd.parm1 = events;
1823 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1824 if(err < 0) {
1825 netdev_err(tp->dev, "typhoon_sleep(): wake events cmd err %d\n",
1826 err);
1827 return err;
1828 }
1829
1830 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_GOTO_SLEEP);
1831 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1832 if(err < 0) {
1833 netdev_err(tp->dev, "typhoon_sleep(): sleep cmd err %d\n", err);
1834 return err;
1835 }
1836
1837 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_SLEEPING) < 0)
1838 return -ETIMEDOUT;
1839
1840 /* Since we cannot monitor the status of the link while sleeping,
1841 * tell the world it went away.
1842 */
1843 netif_carrier_off(tp->dev);
1844
1845 pci_enable_wake(tp->pdev, state, 1);
1846 pci_disable_device(pdev);
1847 return pci_set_power_state(pdev, state);
1848 }
1849
1850 static int
1851 typhoon_wakeup(struct typhoon *tp, int wait_type)
1852 {
1853 struct pci_dev *pdev = tp->pdev;
1854 void __iomem *ioaddr = tp->ioaddr;
1855
1856 pci_set_power_state(pdev, PCI_D0);
1857 pci_restore_state(pdev);
1858
1859 /* Post 2.x.x versions of the Sleep Image require a reset before
1860 * we can download the Runtime Image. But let's not make users of
1861 * the old firmware pay for the reset.
1862 */
1863 iowrite32(TYPHOON_BOOTCMD_WAKEUP, ioaddr + TYPHOON_REG_COMMAND);
1864 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0 ||
1865 (tp->capabilities & TYPHOON_WAKEUP_NEEDS_RESET))
1866 return typhoon_reset(ioaddr, wait_type);
1867
1868 return 0;
1869 }
1870
1871 static int
1872 typhoon_start_runtime(struct typhoon *tp)
1873 {
1874 struct net_device *dev = tp->dev;
1875 void __iomem *ioaddr = tp->ioaddr;
1876 struct cmd_desc xp_cmd;
1877 int err;
1878
1879 typhoon_init_rings(tp);
1880 typhoon_fill_free_ring(tp);
1881
1882 err = typhoon_download_firmware(tp);
1883 if(err < 0) {
1884 netdev_err(tp->dev, "cannot load runtime on 3XP\n");
1885 goto error_out;
1886 }
1887
1888 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1889 netdev_err(tp->dev, "cannot boot 3XP\n");
1890 err = -EIO;
1891 goto error_out;
1892 }
1893
1894 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAX_PKT_SIZE);
1895 xp_cmd.parm1 = cpu_to_le16(PKT_BUF_SZ);
1896 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1897 if(err < 0)
1898 goto error_out;
1899
1900 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
1901 xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
1902 xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
1903 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1904 if(err < 0)
1905 goto error_out;
1906
1907 /* Disable IRQ coalescing -- we can reenable it when 3Com gives
1908 * us some more information on how to control it.
1909 */
1910 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_IRQ_COALESCE_CTRL);
1911 xp_cmd.parm1 = 0;
1912 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1913 if(err < 0)
1914 goto error_out;
1915
1916 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1917 xp_cmd.parm1 = tp->xcvr_select;
1918 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1919 if(err < 0)
1920 goto error_out;
1921
1922 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_VLAN_TYPE_WRITE);
1923 xp_cmd.parm1 = cpu_to_le16(ETH_P_8021Q);
1924 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1925 if(err < 0)
1926 goto error_out;
1927
1928 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_OFFLOAD_TASKS);
1929 xp_cmd.parm2 = tp->offload;
1930 xp_cmd.parm3 = tp->offload;
1931 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1932 if(err < 0)
1933 goto error_out;
1934
1935 typhoon_set_rx_mode(dev);
1936
1937 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_ENABLE);
1938 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1939 if(err < 0)
1940 goto error_out;
1941
1942 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_ENABLE);
1943 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1944 if(err < 0)
1945 goto error_out;
1946
1947 tp->card_state = Running;
1948 smp_wmb();
1949
1950 iowrite32(TYPHOON_INTR_ENABLE_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
1951 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_MASK);
1952 typhoon_post_pci_writes(ioaddr);
1953
1954 return 0;
1955
1956 error_out:
1957 typhoon_reset(ioaddr, WaitNoSleep);
1958 typhoon_free_rx_rings(tp);
1959 typhoon_init_rings(tp);
1960 return err;
1961 }
1962
1963 static int
1964 typhoon_stop_runtime(struct typhoon *tp, int wait_type)
1965 {
1966 struct typhoon_indexes *indexes = tp->indexes;
1967 struct transmit_ring *txLo = &tp->txLoRing;
1968 void __iomem *ioaddr = tp->ioaddr;
1969 struct cmd_desc xp_cmd;
1970 int i;
1971
1972 /* Disable interrupts early, since we can't schedule a poll
1973 * when called with !netif_running(). This will be posted
1974 * when we force the posting of the command.
1975 */
1976 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
1977
1978 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_DISABLE);
1979 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1980
1981 /* Wait 1/2 sec for any outstanding transmits to occur
1982 * We'll cleanup after the reset if this times out.
1983 */
1984 for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
1985 if(indexes->txLoCleared == cpu_to_le32(txLo->lastWrite))
1986 break;
1987 udelay(TYPHOON_UDELAY);
1988 }
1989
1990 if(i == TYPHOON_WAIT_TIMEOUT)
1991 netdev_err(tp->dev, "halt timed out waiting for Tx to complete\n");
1992
1993 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_DISABLE);
1994 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1995
1996 /* save the statistics so when we bring the interface up again,
1997 * the values reported to userspace are correct.
1998 */
1999 tp->card_state = Sleeping;
2000 smp_wmb();
2001 typhoon_do_get_stats(tp);
2002 memcpy(&tp->stats_saved, &tp->stats, sizeof(struct net_device_stats));
2003
2004 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_HALT);
2005 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2006
2007 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_HALTED) < 0)
2008 netdev_err(tp->dev, "timed out waiting for 3XP to halt\n");
2009
2010 if(typhoon_reset(ioaddr, wait_type) < 0) {
2011 netdev_err(tp->dev, "unable to reset 3XP\n");
2012 return -ETIMEDOUT;
2013 }
2014
2015 /* cleanup any outstanding Tx packets */
2016 if(indexes->txLoCleared != cpu_to_le32(txLo->lastWrite)) {
2017 indexes->txLoCleared = cpu_to_le32(txLo->lastWrite);
2018 typhoon_clean_tx(tp, &tp->txLoRing, &indexes->txLoCleared);
2019 }
2020
2021 return 0;
2022 }
2023
2024 static void
2025 typhoon_tx_timeout(struct net_device *dev)
2026 {
2027 struct typhoon *tp = netdev_priv(dev);
2028
2029 if(typhoon_reset(tp->ioaddr, WaitNoSleep) < 0) {
2030 netdev_warn(dev, "could not reset in tx timeout\n");
2031 goto truly_dead;
2032 }
2033
2034 /* If we ever start using the Hi ring, it will need cleaning too */
2035 typhoon_clean_tx(tp, &tp->txLoRing, &tp->indexes->txLoCleared);
2036 typhoon_free_rx_rings(tp);
2037
2038 if(typhoon_start_runtime(tp) < 0) {
2039 netdev_err(dev, "could not start runtime in tx timeout\n");
2040 goto truly_dead;
2041 }
2042
2043 netif_wake_queue(dev);
2044 return;
2045
2046 truly_dead:
2047 /* Reset the hardware, and turn off carrier to avoid more timeouts */
2048 typhoon_reset(tp->ioaddr, NoWait);
2049 netif_carrier_off(dev);
2050 }
2051
2052 static int
2053 typhoon_open(struct net_device *dev)
2054 {
2055 struct typhoon *tp = netdev_priv(dev);
2056 int err;
2057
2058 err = typhoon_request_firmware(tp);
2059 if (err)
2060 goto out;
2061
2062 err = typhoon_wakeup(tp, WaitSleep);
2063 if(err < 0) {
2064 netdev_err(dev, "unable to wakeup device\n");
2065 goto out_sleep;
2066 }
2067
2068 err = request_irq(dev->irq, typhoon_interrupt, IRQF_SHARED,
2069 dev->name, dev);
2070 if(err < 0)
2071 goto out_sleep;
2072
2073 napi_enable(&tp->napi);
2074
2075 err = typhoon_start_runtime(tp);
2076 if(err < 0) {
2077 napi_disable(&tp->napi);
2078 goto out_irq;
2079 }
2080
2081 netif_start_queue(dev);
2082 return 0;
2083
2084 out_irq:
2085 free_irq(dev->irq, dev);
2086
2087 out_sleep:
2088 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2089 netdev_err(dev, "unable to reboot into sleep img\n");
2090 typhoon_reset(tp->ioaddr, NoWait);
2091 goto out;
2092 }
2093
2094 if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2095 netdev_err(dev, "unable to go back to sleep\n");
2096
2097 out:
2098 return err;
2099 }
2100
2101 static int
2102 typhoon_close(struct net_device *dev)
2103 {
2104 struct typhoon *tp = netdev_priv(dev);
2105
2106 netif_stop_queue(dev);
2107 napi_disable(&tp->napi);
2108
2109 if(typhoon_stop_runtime(tp, WaitSleep) < 0)
2110 netdev_err(dev, "unable to stop runtime\n");
2111
2112 /* Make sure there is no irq handler running on a different CPU. */
2113 free_irq(dev->irq, dev);
2114
2115 typhoon_free_rx_rings(tp);
2116 typhoon_init_rings(tp);
2117
2118 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0)
2119 netdev_err(dev, "unable to boot sleep image\n");
2120
2121 if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2122 netdev_err(dev, "unable to put card to sleep\n");
2123
2124 return 0;
2125 }
2126
2127 #ifdef CONFIG_PM
2128 static int
2129 typhoon_resume(struct pci_dev *pdev)
2130 {
2131 struct net_device *dev = pci_get_drvdata(pdev);
2132 struct typhoon *tp = netdev_priv(dev);
2133
2134 /* If we're down, resume when we are upped.
2135 */
2136 if(!netif_running(dev))
2137 return 0;
2138
2139 if(typhoon_wakeup(tp, WaitNoSleep) < 0) {
2140 netdev_err(dev, "critical: could not wake up in resume\n");
2141 goto reset;
2142 }
2143
2144 if(typhoon_start_runtime(tp) < 0) {
2145 netdev_err(dev, "critical: could not start runtime in resume\n");
2146 goto reset;
2147 }
2148
2149 netif_device_attach(dev);
2150 return 0;
2151
2152 reset:
2153 typhoon_reset(tp->ioaddr, NoWait);
2154 return -EBUSY;
2155 }
2156
2157 static int
2158 typhoon_suspend(struct pci_dev *pdev, pm_message_t state)
2159 {
2160 struct net_device *dev = pci_get_drvdata(pdev);
2161 struct typhoon *tp = netdev_priv(dev);
2162 struct cmd_desc xp_cmd;
2163
2164 /* If we're down, we're already suspended.
2165 */
2166 if(!netif_running(dev))
2167 return 0;
2168
2169 /* TYPHOON_OFFLOAD_VLAN is always on now, so this doesn't work */
2170 if(tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
2171 netdev_warn(dev, "cannot do WAKE_MAGIC with VLAN offloading\n");
2172
2173 netif_device_detach(dev);
2174
2175 if(typhoon_stop_runtime(tp, WaitNoSleep) < 0) {
2176 netdev_err(dev, "unable to stop runtime\n");
2177 goto need_resume;
2178 }
2179
2180 typhoon_free_rx_rings(tp);
2181 typhoon_init_rings(tp);
2182
2183 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2184 netdev_err(dev, "unable to boot sleep image\n");
2185 goto need_resume;
2186 }
2187
2188 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
2189 xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
2190 xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
2191 if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2192 netdev_err(dev, "unable to set mac address in suspend\n");
2193 goto need_resume;
2194 }
2195
2196 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
2197 xp_cmd.parm1 = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
2198 if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2199 netdev_err(dev, "unable to set rx filter in suspend\n");
2200 goto need_resume;
2201 }
2202
2203 if(typhoon_sleep(tp, pci_choose_state(pdev, state), tp->wol_events) < 0) {
2204 netdev_err(dev, "unable to put card to sleep\n");
2205 goto need_resume;
2206 }
2207
2208 return 0;
2209
2210 need_resume:
2211 typhoon_resume(pdev);
2212 return -EBUSY;
2213 }
2214 #endif
2215
2216 static int __devinit
2217 typhoon_test_mmio(struct pci_dev *pdev)
2218 {
2219 void __iomem *ioaddr = pci_iomap(pdev, 1, 128);
2220 int mode = 0;
2221 u32 val;
2222
2223 if(!ioaddr)
2224 goto out;
2225
2226 if(ioread32(ioaddr + TYPHOON_REG_STATUS) !=
2227 TYPHOON_STATUS_WAITING_FOR_HOST)
2228 goto out_unmap;
2229
2230 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2231 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2232 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
2233
2234 /* Ok, see if we can change our interrupt status register by
2235 * sending ourselves an interrupt. If so, then MMIO works.
2236 * The 50usec delay is arbitrary -- it could probably be smaller.
2237 */
2238 val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2239 if((val & TYPHOON_INTR_SELF) == 0) {
2240 iowrite32(1, ioaddr + TYPHOON_REG_SELF_INTERRUPT);
2241 ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2242 udelay(50);
2243 val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2244 if(val & TYPHOON_INTR_SELF)
2245 mode = 1;
2246 }
2247
2248 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2249 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2250 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2251 ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2252
2253 out_unmap:
2254 pci_iounmap(pdev, ioaddr);
2255
2256 out:
2257 if(!mode)
2258 pr_info("%s: falling back to port IO\n", pci_name(pdev));
2259 return mode;
2260 }
2261
2262 static const struct net_device_ops typhoon_netdev_ops = {
2263 .ndo_open = typhoon_open,
2264 .ndo_stop = typhoon_close,
2265 .ndo_start_xmit = typhoon_start_tx,
2266 .ndo_set_rx_mode = typhoon_set_rx_mode,
2267 .ndo_tx_timeout = typhoon_tx_timeout,
2268 .ndo_get_stats = typhoon_get_stats,
2269 .ndo_validate_addr = eth_validate_addr,
2270 .ndo_set_mac_address = typhoon_set_mac_address,
2271 .ndo_change_mtu = eth_change_mtu,
2272 };
2273
2274 static int __devinit
2275 typhoon_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2276 {
2277 struct net_device *dev;
2278 struct typhoon *tp;
2279 int card_id = (int) ent->driver_data;
2280 void __iomem *ioaddr;
2281 void *shared;
2282 dma_addr_t shared_dma;
2283 struct cmd_desc xp_cmd;
2284 struct resp_desc xp_resp[3];
2285 int err = 0;
2286 const char *err_msg;
2287
2288 dev = alloc_etherdev(sizeof(*tp));
2289 if(dev == NULL) {
2290 err_msg = "unable to alloc new net device";
2291 err = -ENOMEM;
2292 goto error_out;
2293 }
2294 SET_NETDEV_DEV(dev, &pdev->dev);
2295
2296 err = pci_enable_device(pdev);
2297 if(err < 0) {
2298 err_msg = "unable to enable device";
2299 goto error_out_dev;
2300 }
2301
2302 err = pci_set_mwi(pdev);
2303 if(err < 0) {
2304 err_msg = "unable to set MWI";
2305 goto error_out_disable;
2306 }
2307
2308 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2309 if(err < 0) {
2310 err_msg = "No usable DMA configuration";
2311 goto error_out_mwi;
2312 }
2313
2314 /* sanity checks on IO and MMIO BARs
2315 */
2316 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
2317 err_msg = "region #1 not a PCI IO resource, aborting";
2318 err = -ENODEV;
2319 goto error_out_mwi;
2320 }
2321 if(pci_resource_len(pdev, 0) < 128) {
2322 err_msg = "Invalid PCI IO region size, aborting";
2323 err = -ENODEV;
2324 goto error_out_mwi;
2325 }
2326 if(!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
2327 err_msg = "region #1 not a PCI MMIO resource, aborting";
2328 err = -ENODEV;
2329 goto error_out_mwi;
2330 }
2331 if(pci_resource_len(pdev, 1) < 128) {
2332 err_msg = "Invalid PCI MMIO region size, aborting";
2333 err = -ENODEV;
2334 goto error_out_mwi;
2335 }
2336
2337 err = pci_request_regions(pdev, KBUILD_MODNAME);
2338 if(err < 0) {
2339 err_msg = "could not request regions";
2340 goto error_out_mwi;
2341 }
2342
2343 /* map our registers
2344 */
2345 if(use_mmio != 0 && use_mmio != 1)
2346 use_mmio = typhoon_test_mmio(pdev);
2347
2348 ioaddr = pci_iomap(pdev, use_mmio, 128);
2349 if (!ioaddr) {
2350 err_msg = "cannot remap registers, aborting";
2351 err = -EIO;
2352 goto error_out_regions;
2353 }
2354
2355 /* allocate pci dma space for rx and tx descriptor rings
2356 */
2357 shared = pci_alloc_consistent(pdev, sizeof(struct typhoon_shared),
2358 &shared_dma);
2359 if(!shared) {
2360 err_msg = "could not allocate DMA memory";
2361 err = -ENOMEM;
2362 goto error_out_remap;
2363 }
2364
2365 dev->irq = pdev->irq;
2366 tp = netdev_priv(dev);
2367 tp->shared = shared;
2368 tp->shared_dma = shared_dma;
2369 tp->pdev = pdev;
2370 tp->tx_pdev = pdev;
2371 tp->ioaddr = ioaddr;
2372 tp->tx_ioaddr = ioaddr;
2373 tp->dev = dev;
2374
2375 /* Init sequence:
2376 * 1) Reset the adapter to clear any bad juju
2377 * 2) Reload the sleep image
2378 * 3) Boot the sleep image
2379 * 4) Get the hardware address.
2380 * 5) Put the card to sleep.
2381 */
2382 if (typhoon_reset(ioaddr, WaitSleep) < 0) {
2383 err_msg = "could not reset 3XP";
2384 err = -EIO;
2385 goto error_out_dma;
2386 }
2387
2388 /* Now that we've reset the 3XP and are sure it's not going to
2389 * write all over memory, enable bus mastering, and save our
2390 * state for resuming after a suspend.
2391 */
2392 pci_set_master(pdev);
2393 pci_save_state(pdev);
2394
2395 typhoon_init_interface(tp);
2396 typhoon_init_rings(tp);
2397
2398 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2399 err_msg = "cannot boot 3XP sleep image";
2400 err = -EIO;
2401 goto error_out_reset;
2402 }
2403
2404 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_MAC_ADDRESS);
2405 if(typhoon_issue_command(tp, 1, &xp_cmd, 1, xp_resp) < 0) {
2406 err_msg = "cannot read MAC address";
2407 err = -EIO;
2408 goto error_out_reset;
2409 }
2410
2411 *(__be16 *)&dev->dev_addr[0] = htons(le16_to_cpu(xp_resp[0].parm1));
2412 *(__be32 *)&dev->dev_addr[2] = htonl(le32_to_cpu(xp_resp[0].parm2));
2413
2414 if(!is_valid_ether_addr(dev->dev_addr)) {
2415 err_msg = "Could not obtain valid ethernet address, aborting";
2416 goto error_out_reset;
2417 }
2418
2419 /* Read the Sleep Image version last, so the response is valid
2420 * later when we print out the version reported.
2421 */
2422 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
2423 if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
2424 err_msg = "Could not get Sleep Image version";
2425 goto error_out_reset;
2426 }
2427
2428 tp->capabilities = typhoon_card_info[card_id].capabilities;
2429 tp->xcvr_select = TYPHOON_XCVR_AUTONEG;
2430
2431 /* Typhoon 1.0 Sleep Images return one response descriptor to the
2432 * READ_VERSIONS command. Those versions are OK after waking up
2433 * from sleep without needing a reset. Typhoon 1.1+ Sleep Images
2434 * seem to need a little extra help to get started. Since we don't
2435 * know how to nudge it along, just kick it.
2436 */
2437 if(xp_resp[0].numDesc != 0)
2438 tp->capabilities |= TYPHOON_WAKEUP_NEEDS_RESET;
2439
2440 if(typhoon_sleep(tp, PCI_D3hot, 0) < 0) {
2441 err_msg = "cannot put adapter to sleep";
2442 err = -EIO;
2443 goto error_out_reset;
2444 }
2445
2446 /* The chip-specific entries in the device structure. */
2447 dev->netdev_ops = &typhoon_netdev_ops;
2448 netif_napi_add(dev, &tp->napi, typhoon_poll, 16);
2449 dev->watchdog_timeo = TX_TIMEOUT;
2450
2451 SET_ETHTOOL_OPS(dev, &typhoon_ethtool_ops);
2452
2453 /* We can handle scatter gather, up to 16 entries, and
2454 * we can do IP checksumming (only version 4, doh...)
2455 *
2456 * There's no way to turn off the RX VLAN offloading and stripping
2457 * on the current 3XP firmware -- it does not respect the offload
2458 * settings -- so we only allow the user to toggle the TX processing.
2459 */
2460 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
2461 NETIF_F_HW_VLAN_TX;
2462 dev->features = dev->hw_features |
2463 NETIF_F_HW_VLAN_RX | NETIF_F_RXCSUM;
2464
2465 if(register_netdev(dev) < 0) {
2466 err_msg = "unable to register netdev";
2467 goto error_out_reset;
2468 }
2469
2470 pci_set_drvdata(pdev, dev);
2471
2472 netdev_info(dev, "%s at %s 0x%llx, %pM\n",
2473 typhoon_card_info[card_id].name,
2474 use_mmio ? "MMIO" : "IO",
2475 (unsigned long long)pci_resource_start(pdev, use_mmio),
2476 dev->dev_addr);
2477
2478 /* xp_resp still contains the response to the READ_VERSIONS command.
2479 * For debugging, let the user know what version he has.
2480 */
2481 if(xp_resp[0].numDesc == 0) {
2482 /* This is the Typhoon 1.0 type Sleep Image, last 16 bits
2483 * of version is Month/Day of build.
2484 */
2485 u16 monthday = le32_to_cpu(xp_resp[0].parm2) & 0xffff;
2486 netdev_info(dev, "Typhoon 1.0 Sleep Image built %02u/%02u/2000\n",
2487 monthday >> 8, monthday & 0xff);
2488 } else if(xp_resp[0].numDesc == 2) {
2489 /* This is the Typhoon 1.1+ type Sleep Image
2490 */
2491 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
2492 u8 *ver_string = (u8 *) &xp_resp[1];
2493 ver_string[25] = 0;
2494 netdev_info(dev, "Typhoon 1.1+ Sleep Image version %02x.%03x.%03x %s\n",
2495 sleep_ver >> 24, (sleep_ver >> 12) & 0xfff,
2496 sleep_ver & 0xfff, ver_string);
2497 } else {
2498 netdev_warn(dev, "Unknown Sleep Image version (%u:%04x)\n",
2499 xp_resp[0].numDesc, le32_to_cpu(xp_resp[0].parm2));
2500 }
2501
2502 return 0;
2503
2504 error_out_reset:
2505 typhoon_reset(ioaddr, NoWait);
2506
2507 error_out_dma:
2508 pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2509 shared, shared_dma);
2510 error_out_remap:
2511 pci_iounmap(pdev, ioaddr);
2512 error_out_regions:
2513 pci_release_regions(pdev);
2514 error_out_mwi:
2515 pci_clear_mwi(pdev);
2516 error_out_disable:
2517 pci_disable_device(pdev);
2518 error_out_dev:
2519 free_netdev(dev);
2520 error_out:
2521 pr_err("%s: %s\n", pci_name(pdev), err_msg);
2522 return err;
2523 }
2524
2525 static void __devexit
2526 typhoon_remove_one(struct pci_dev *pdev)
2527 {
2528 struct net_device *dev = pci_get_drvdata(pdev);
2529 struct typhoon *tp = netdev_priv(dev);
2530
2531 unregister_netdev(dev);
2532 pci_set_power_state(pdev, PCI_D0);
2533 pci_restore_state(pdev);
2534 typhoon_reset(tp->ioaddr, NoWait);
2535 pci_iounmap(pdev, tp->ioaddr);
2536 pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2537 tp->shared, tp->shared_dma);
2538 pci_release_regions(pdev);
2539 pci_clear_mwi(pdev);
2540 pci_disable_device(pdev);
2541 pci_set_drvdata(pdev, NULL);
2542 free_netdev(dev);
2543 }
2544
2545 static struct pci_driver typhoon_driver = {
2546 .name = KBUILD_MODNAME,
2547 .id_table = typhoon_pci_tbl,
2548 .probe = typhoon_init_one,
2549 .remove = __devexit_p(typhoon_remove_one),
2550 #ifdef CONFIG_PM
2551 .suspend = typhoon_suspend,
2552 .resume = typhoon_resume,
2553 #endif
2554 };
2555
2556 static int __init
2557 typhoon_init(void)
2558 {
2559 return pci_register_driver(&typhoon_driver);
2560 }
2561
2562 static void __exit
2563 typhoon_cleanup(void)
2564 {
2565 if (typhoon_fw)
2566 release_firmware(typhoon_fw);
2567 pci_unregister_driver(&typhoon_driver);
2568 }
2569
2570 module_init(typhoon_init);
2571 module_exit(typhoon_cleanup);