drivers/net/ethernet/amd/nmclan_cs.c

   1 /* ----------------------------------------------------------------------------
   2 Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
   3   nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
   4
   5   The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
   6   Access Controller for Ethernet (MACE).  It is essentially the Am2150
   7   PCMCIA Ethernet card contained in the Am2150 Demo Kit.
   8
   9 Written by Roger C. Pao <rpao@paonet.org>
  10   Copyright 1995 Roger C. Pao
  11   Linux 2.5 cleanups Copyright Red Hat 2003
  12
  13   This software may be used and distributed according to the terms of
  14   the GNU General Public License.
  15
  16 Ported to Linux 1.3.* network driver environment by
  17   Matti Aarnio <mea@utu.fi>
  18
  19 References
  20
  21   Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
  22   Am79C940 (MACE) Data Sheet, 1994
  23   Am79C90 (C-LANCE) Data Sheet, 1994
  24   Linux PCMCIA Programmer's Guide v1.17
  25   /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
  26
  27   Eric Mears, New Media Corporation
  28   Tom Pollard, New Media Corporation
  29   Dean Siasoyco, New Media Corporation
  30   Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
  31   Donald Becker <becker@scyld.com>
  32   David Hinds <dahinds@users.sourceforge.net>
  33
  34   The Linux client driver is based on the 3c589_cs.c client driver by
  35   David Hinds.
  36
  37   The Linux network driver outline is based on the 3c589_cs.c driver,
  38   the 8390.c driver, and the example skeleton.c kernel code, which are
  39   by Donald Becker.
  40
  41   The Am2150 network driver hardware interface code is based on the
  42   OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
  43
  44   Special thanks for testing and help in debugging this driver goes
  45   to Ken Lesniak.
  46
  47 -------------------------------------------------------------------------------
  48 Driver Notes and Issues
  49 -------------------------------------------------------------------------------
  50
  51 1. Developed on a Dell 320SLi
  52    PCMCIA Card Services 2.6.2
  53    Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
  54
  55 2. rc.pcmcia may require loading pcmcia_core with io_speed=300:
  56    'insmod pcmcia_core.o io_speed=300'.
  57    This will avoid problems with fast systems which causes rx_framecnt
  58    to return random values.
  59
  60 3. If hot extraction does not work for you, use 'ifconfig eth0 down'
  61    before extraction.
  62
  63 4. There is a bad slow-down problem in this driver.
  64
  65 5. Future: Multicast processing.  In the meantime, do _not_ compile your
  66    kernel with multicast ip enabled.
  67
  68 -------------------------------------------------------------------------------
  69 History
  70 -------------------------------------------------------------------------------
  71 Log: nmclan_cs.c,v
  72  * 2.5.75-ac1 2003/07/11 Alan Cox <alan@lxorguk.ukuu.org.uk>
  73  * Fixed hang on card eject as we probe it
  74  * Cleaned up to use new style locking.
  75  *
  76  * Revision 0.16  1995/07/01  06:42:17  rpao
  77  * Bug fix: nmclan_reset() called CardServices incorrectly.
  78  *
  79  * Revision 0.15  1995/05/24  08:09:47  rpao
  80  * Re-implement MULTI_TX dev->tbusy handling.
  81  *
  82  * Revision 0.14  1995/05/23  03:19:30  rpao
  83  * Added, in nmclan_config(), "tuple.Attributes = 0;".
  84  * Modified MACE ID check to ignore chip revision level.
  85  * Avoid tx_free_frames race condition between _start_xmit and _interrupt.
  86  *
  87  * Revision 0.13  1995/05/18  05:56:34  rpao
  88  * Statistics changes.
  89  * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
  90  * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT.  Fixes driver lockup.
  91  *
  92  * Revision 0.12  1995/05/14  00:12:23  rpao
  93  * Statistics overhaul.
  94  *
  95
  96 95/05/13 rpao   V0.10a
  97                 Bug fix: MACE statistics counters used wrong I/O ports.
  98                 Bug fix: mace_interrupt() needed to allow statistics to be
  99                 processed without RX or TX interrupts pending.
 100 95/05/11 rpao   V0.10
 101                 Multiple transmit request processing.
 102                 Modified statistics to use MACE counters where possible.
 103 95/05/10 rpao   V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
 104                 *Released
 105 95/05/10 rpao   V0.08
 106                 Bug fix: Make all non-exported functions private by using
 107                 static keyword.
 108                 Bug fix: Test IntrCnt _before_ reading MACE_IR.
 109 95/05/10 rpao   V0.07 Statistics.
 110 95/05/09 rpao   V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
 111
 112 ---------------------------------------------------------------------------- */
 113
 114 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 115
 116 #define DRV_NAME        "nmclan_cs"
 117 #define DRV_VERSION     "0.16"
 118
 119
 120 /* ----------------------------------------------------------------------------
 121 Conditional Compilation Options
 122 ---------------------------------------------------------------------------- */
 123
 124 #define MULTI_TX                        0
 125 #define RESET_ON_TIMEOUT                1
 126 #define TX_INTERRUPTABLE                1
 127 #define RESET_XILINX                    0
 128
 129 /* ----------------------------------------------------------------------------
 130 Include Files
 131 ---------------------------------------------------------------------------- */
 132
 133 #include <linux/module.h>
 134 #include <linux/kernel.h>
 135 #include <linux/init.h>
 136 #include <linux/ptrace.h>
 137 #include <linux/slab.h>
 138 #include <linux/string.h>
 139 #include <linux/timer.h>
 140 #include <linux/interrupt.h>
 141 #include <linux/in.h>
 142 #include <linux/delay.h>
 143 #include <linux/ethtool.h>
 144 #include <linux/netdevice.h>
 145 #include <linux/etherdevice.h>
 146 #include <linux/skbuff.h>
 147 #include <linux/if_arp.h>
 148 #include <linux/ioport.h>
 149 #include <linux/bitops.h>
 150
 151 #include <pcmcia/cisreg.h>
 152 #include <pcmcia/cistpl.h>
 153 #include <pcmcia/ds.h>
 154
 155 #include <asm/uaccess.h>
 156 #include <asm/io.h>
 157 #include <asm/system.h>
 158
 159 /* ----------------------------------------------------------------------------
 160 Defines
 161 ---------------------------------------------------------------------------- */
 162
 163 #define MACE_LADRF_LEN                  8
 164                                         /* 8 bytes in Logical Address Filter */
 165
 166 /* Loop Control Defines */
 167 #define MACE_MAX_IR_ITERATIONS          10
 168 #define MACE_MAX_RX_ITERATIONS          12
 169         /*
 170         TBD: Dean brought this up, and I assumed the hardware would
 171         handle it:
 172
 173         If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
 174         non-zero when the isr exits.  We may not get another interrupt
 175         to process the remaining packets for some time.
 176         */
 177
 178 /*
 179 The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
 180 which manages the interface between the MACE and the PCMCIA bus.  It
 181 also includes buffer management for the 32K x 8 SRAM to control up to
 182 four transmit and 12 receive frames at a time.
 183 */
 184 #define AM2150_MAX_TX_FRAMES            4
 185 #define AM2150_MAX_RX_FRAMES            12
 186
 187 /* Am2150 Ethernet Card I/O Mapping */
 188 #define AM2150_RCV                      0x00
 189 #define AM2150_XMT                      0x04
 190 #define AM2150_XMT_SKIP                 0x09
 191 #define AM2150_RCV_NEXT                 0x0A
 192 #define AM2150_RCV_FRAME_COUNT          0x0B
 193 #define AM2150_MACE_BANK                0x0C
 194 #define AM2150_MACE_BASE                0x10
 195
 196 /* MACE Registers */
 197 #define MACE_RCVFIFO                    0
 198 #define MACE_XMTFIFO                    1
 199 #define MACE_XMTFC                      2
 200 #define MACE_XMTFS                      3
 201 #define MACE_XMTRC                      4
 202 #define MACE_RCVFC                      5
 203 #define MACE_RCVFS                      6
 204 #define MACE_FIFOFC                     7
 205 #define MACE_IR                         8
 206 #define MACE_IMR                        9
 207 #define MACE_PR                         10
 208 #define MACE_BIUCC                      11
 209 #define MACE_FIFOCC                     12
 210 #define MACE_MACCC                      13
 211 #define MACE_PLSCC                      14
 212 #define MACE_PHYCC                      15
 213 #define MACE_CHIPIDL                    16
 214 #define MACE_CHIPIDH                    17
 215 #define MACE_IAC                        18
 216 /* Reserved */
 217 #define MACE_LADRF                      20
 218 #define MACE_PADR                       21
 219 /* Reserved */
 220 /* Reserved */
 221 #define MACE_MPC                        24
 222 /* Reserved */
 223 #define MACE_RNTPC                      26
 224 #define MACE_RCVCC                      27
 225 /* Reserved */
 226 #define MACE_UTR                        29
 227 #define MACE_RTR1                       30
 228 #define MACE_RTR2                       31
 229
 230 /* MACE Bit Masks */
 231 #define MACE_XMTRC_EXDEF                0x80
 232 #define MACE_XMTRC_XMTRC                0x0F
 233
 234 #define MACE_XMTFS_XMTSV                0x80
 235 #define MACE_XMTFS_UFLO                 0x40
 236 #define MACE_XMTFS_LCOL                 0x20
 237 #define MACE_XMTFS_MORE                 0x10
 238 #define MACE_XMTFS_ONE                  0x08
 239 #define MACE_XMTFS_DEFER                0x04
 240 #define MACE_XMTFS_LCAR                 0x02
 241 #define MACE_XMTFS_RTRY                 0x01
 242
 243 #define MACE_RCVFS_RCVSTS               0xF000
 244 #define MACE_RCVFS_OFLO                 0x8000
 245 #define MACE_RCVFS_CLSN                 0x4000
 246 #define MACE_RCVFS_FRAM                 0x2000
 247 #define MACE_RCVFS_FCS                  0x1000
 248
 249 #define MACE_FIFOFC_RCVFC               0xF0
 250 #define MACE_FIFOFC_XMTFC               0x0F
 251
 252 #define MACE_IR_JAB                     0x80
 253 #define MACE_IR_BABL                    0x40
 254 #define MACE_IR_CERR                    0x20
 255 #define MACE_IR_RCVCCO                  0x10
 256 #define MACE_IR_RNTPCO                  0x08
 257 #define MACE_IR_MPCO                    0x04
 258 #define MACE_IR_RCVINT                  0x02
 259 #define MACE_IR_XMTINT                  0x01
 260
 261 #define MACE_MACCC_PROM                 0x80
 262 #define MACE_MACCC_DXMT2PD              0x40
 263 #define MACE_MACCC_EMBA                 0x20
 264 #define MACE_MACCC_RESERVED             0x10
 265 #define MACE_MACCC_DRCVPA               0x08
 266 #define MACE_MACCC_DRCVBC               0x04
 267 #define MACE_MACCC_ENXMT                0x02
 268 #define MACE_MACCC_ENRCV                0x01
 269
 270 #define MACE_PHYCC_LNKFL                0x80
 271 #define MACE_PHYCC_DLNKTST              0x40
 272 #define MACE_PHYCC_REVPOL               0x20
 273 #define MACE_PHYCC_DAPC                 0x10
 274 #define MACE_PHYCC_LRT                  0x08
 275 #define MACE_PHYCC_ASEL                 0x04
 276 #define MACE_PHYCC_RWAKE                0x02
 277 #define MACE_PHYCC_AWAKE                0x01
 278
 279 #define MACE_IAC_ADDRCHG                0x80
 280 #define MACE_IAC_PHYADDR                0x04
 281 #define MACE_IAC_LOGADDR                0x02
 282
 283 #define MACE_UTR_RTRE                   0x80
 284 #define MACE_UTR_RTRD                   0x40
 285 #define MACE_UTR_RPA                    0x20
 286 #define MACE_UTR_FCOLL                  0x10
 287 #define MACE_UTR_RCVFCSE                0x08
 288 #define MACE_UTR_LOOP_INCL_MENDEC       0x06
 289 #define MACE_UTR_LOOP_NO_MENDEC         0x04
 290 #define MACE_UTR_LOOP_EXTERNAL          0x02
 291 #define MACE_UTR_LOOP_NONE              0x00
 292 #define MACE_UTR_RESERVED               0x01
 293
 294 /* Switch MACE register bank (only 0 and 1 are valid) */
 295 #define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
 296
 297 #define MACE_IMR_DEFAULT \
 298   (0xFF - \
 299     ( \
 300       MACE_IR_CERR | \
 301       MACE_IR_RCVCCO | \
 302       MACE_IR_RNTPCO | \
 303       MACE_IR_MPCO | \
 304       MACE_IR_RCVINT | \
 305       MACE_IR_XMTINT \
 306     ) \
 307   )
 308 #undef MACE_IMR_DEFAULT
 309 #define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
 310
 311 #define TX_TIMEOUT              ((400*HZ)/1000)
 312
 313 /* ----------------------------------------------------------------------------
 314 Type Definitions
 315 ---------------------------------------------------------------------------- */
 316
 317 typedef struct _mace_statistics {
 318     /* MACE_XMTFS */
 319     int xmtsv;
 320     int uflo;
 321     int lcol;
 322     int more;
 323     int one;
 324     int defer;
 325     int lcar;
 326     int rtry;
 327
 328     /* MACE_XMTRC */
 329     int exdef;
 330     int xmtrc;
 331
 332     /* RFS1--Receive Status (RCVSTS) */
 333     int oflo;
 334     int clsn;
 335     int fram;
 336     int fcs;
 337
 338     /* RFS2--Runt Packet Count (RNTPC) */
 339     int rfs_rntpc;
 340
 341     /* RFS3--Receive Collision Count (RCVCC) */
 342     int rfs_rcvcc;
 343
 344     /* MACE_IR */
 345     int jab;
 346     int babl;
 347     int cerr;
 348     int rcvcco;
 349     int rntpco;
 350     int mpco;
 351
 352     /* MACE_MPC */
 353     int mpc;
 354
 355     /* MACE_RNTPC */
 356     int rntpc;
 357
 358     /* MACE_RCVCC */
 359     int rcvcc;
 360 } mace_statistics;
 361
 362 typedef struct _mace_private {
 363         struct pcmcia_device    *p_dev;
 364     struct net_device_stats linux_stats; /* Linux statistics counters */
 365     mace_statistics mace_stats; /* MACE chip statistics counters */
 366
 367     /* restore_multicast_list() state variables */
 368     int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
 369     int multicast_num_addrs;
 370
 371     char tx_free_frames; /* Number of free transmit frame buffers */
 372     char tx_irq_disabled; /* MACE TX interrupt disabled */
 373
 374     spinlock_t bank_lock; /* Must be held if you step off bank 0 */
 375 } mace_private;
 376
 377 /* ----------------------------------------------------------------------------
 378 Private Global Variables
 379 ---------------------------------------------------------------------------- */
 380
 381 static const char *if_names[]={
 382     "Auto", "10baseT", "BNC",
 383 };
 384
 385 /* ----------------------------------------------------------------------------
 386 Parameters
 387         These are the parameters that can be set during loading with
 388         'insmod'.
 389 ---------------------------------------------------------------------------- */
 390
 391 MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
 392 MODULE_LICENSE("GPL");
 393
 394 #define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
 395
 396 /* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
 397 INT_MODULE_PARM(if_port, 0);
 398
 399
 400 /* ----------------------------------------------------------------------------
 401 Function Prototypes
 402 ---------------------------------------------------------------------------- */
 403
 404 static int nmclan_config(struct pcmcia_device *link);
 405 static void nmclan_release(struct pcmcia_device *link);
 406
 407 static void nmclan_reset(struct net_device *dev);
 408 static int mace_config(struct net_device *dev, struct ifmap *map);
 409 static int mace_open(struct net_device *dev);
 410 static int mace_close(struct net_device *dev);
 411 static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
 412                                          struct net_device *dev);
 413 static void mace_tx_timeout(struct net_device *dev);
 414 static irqreturn_t mace_interrupt(int irq, void *dev_id);
 415 static struct net_device_stats *mace_get_stats(struct net_device *dev);
 416 static int mace_rx(struct net_device *dev, unsigned char RxCnt);
 417 static void restore_multicast_list(struct net_device *dev);
 418 static void set_multicast_list(struct net_device *dev);
 419 static const struct ethtool_ops netdev_ethtool_ops;
 420
 421
 422 static void nmclan_detach(struct pcmcia_device *p_dev);
 423
 424 static const struct net_device_ops mace_netdev_ops = {
 425         .ndo_open               = mace_open,
 426         .ndo_stop               = mace_close,
 427         .ndo_start_xmit         = mace_start_xmit,
 428         .ndo_tx_timeout         = mace_tx_timeout,
 429         .ndo_set_config         = mace_config,
 430         .ndo_get_stats          = mace_get_stats,
 431         .ndo_set_rx_mode        = set_multicast_list,
 432         .ndo_change_mtu         = eth_change_mtu,
 433         .ndo_set_mac_address    = eth_mac_addr,
 434         .ndo_validate_addr      = eth_validate_addr,
 435 };
 436
 437 static int nmclan_probe(struct pcmcia_device *link)
 438 {
 439     mace_private *lp;
 440     struct net_device *dev;
 441
 442     dev_dbg(&link->dev, "nmclan_attach()\n");
 443
 444     /* Create new ethernet device */
 445     dev = alloc_etherdev(sizeof(mace_private));
 446     if (!dev)
 447             return -ENOMEM;
 448     lp = netdev_priv(dev);
 449     lp->p_dev = link;
 450     link->priv = dev;
 451
 452     spin_lock_init(&lp->bank_lock);
 453     link->resource[0]->end = 32;
 454     link->resource[0]->flags |= IO_DATA_PATH_WIDTH_AUTO;
 455     link->config_flags |= CONF_ENABLE_IRQ;
 456     link->config_index = 1;
 457     link->config_regs = PRESENT_OPTION;
 458
 459     lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
 460
 461     dev->netdev_ops = &mace_netdev_ops;
 462     SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
 463     dev->watchdog_timeo = TX_TIMEOUT;
 464
 465     return nmclan_config(link);
 466 } /* nmclan_attach */
 467
 468 static void nmclan_detach(struct pcmcia_device *link)
 469 {
 470     struct net_device *dev = link->priv;
 471
 472     dev_dbg(&link->dev, "nmclan_detach\n");
 473
 474     unregister_netdev(dev);
 475
 476     nmclan_release(link);
 477
 478     free_netdev(dev);
 479 } /* nmclan_detach */
 480
 481 /* ----------------------------------------------------------------------------
 482 mace_read
 483         Reads a MACE register.  This is bank independent; however, the
 484         caller must ensure that this call is not interruptable.  We are
 485         assuming that during normal operation, the MACE is always in
 486         bank 0.
 487 ---------------------------------------------------------------------------- */
 488 static int mace_read(mace_private *lp, unsigned int ioaddr, int reg)
 489 {
 490   int data = 0xFF;
 491   unsigned long flags;
 492
 493   switch (reg >> 4) {
 494     case 0: /* register 0-15 */
 495       data = inb(ioaddr + AM2150_MACE_BASE + reg);
 496       break;
 497     case 1: /* register 16-31 */
 498       spin_lock_irqsave(&lp->bank_lock, flags);
 499       MACEBANK(1);
 500       data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
 501       MACEBANK(0);
 502       spin_unlock_irqrestore(&lp->bank_lock, flags);
 503       break;
 504   }
 505   return data & 0xFF;
 506 } /* mace_read */
 507
 508 /* ----------------------------------------------------------------------------
 509 mace_write
 510         Writes to a MACE register.  This is bank independent; however,
 511         the caller must ensure that this call is not interruptable.  We
 512         are assuming that during normal operation, the MACE is always in
 513         bank 0.
 514 ---------------------------------------------------------------------------- */
 515 static void mace_write(mace_private *lp, unsigned int ioaddr, int reg,
 516                        int data)
 517 {
 518   unsigned long flags;
 519
 520   switch (reg >> 4) {
 521     case 0: /* register 0-15 */
 522       outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
 523       break;
 524     case 1: /* register 16-31 */
 525       spin_lock_irqsave(&lp->bank_lock, flags);
 526       MACEBANK(1);
 527       outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
 528       MACEBANK(0);
 529       spin_unlock_irqrestore(&lp->bank_lock, flags);
 530       break;
 531   }
 532 } /* mace_write */
 533
 534 /* ----------------------------------------------------------------------------
 535 mace_init
 536         Resets the MACE chip.
 537 ---------------------------------------------------------------------------- */
 538 static int mace_init(mace_private *lp, unsigned int ioaddr, char *enet_addr)
 539 {
 540   int i;
 541   int ct = 0;
 542
 543   /* MACE Software reset */
 544   mace_write(lp, ioaddr, MACE_BIUCC, 1);
 545   while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
 546     /* Wait for reset bit to be cleared automatically after <= 200ns */;
 547     if(++ct > 500)
 548     {
 549         pr_err("reset failed, card removed?\n");
 550         return -1;
 551     }
 552     udelay(1);
 553   }
 554   mace_write(lp, ioaddr, MACE_BIUCC, 0);
 555
 556   /* The Am2150 requires that the MACE FIFOs operate in burst mode. */
 557   mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
 558
 559   mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
 560   mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
 561
 562   /*
 563    * Bit 2-1 PORTSEL[1-0] Port Select.
 564    * 00 AUI/10Base-2
 565    * 01 10Base-T
 566    * 10 DAI Port (reserved in Am2150)
 567    * 11 GPSI
 568    * For this card, only the first two are valid.
 569    * So, PLSCC should be set to
 570    * 0x00 for 10Base-2
 571    * 0x02 for 10Base-T
 572    * Or just set ASEL in PHYCC below!
 573    */
 574   switch (if_port) {
 575     case 1:
 576       mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
 577       break;
 578     case 2:
 579       mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
 580       break;
 581     default:
 582       mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
 583       /* ASEL Auto Select.  When set, the PORTSEL[1-0] bits are overridden,
 584          and the MACE device will automatically select the operating media
 585          interface port. */
 586       break;
 587   }
 588
 589   mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
 590   /* Poll ADDRCHG bit */
 591   ct = 0;
 592   while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
 593   {
 594         if(++ ct > 500)
 595         {
 596                 pr_err("ADDRCHG timeout, card removed?\n");
 597                 return -1;
 598         }
 599   }
 600   /* Set PADR register */
 601   for (i = 0; i < ETH_ALEN; i++)
 602     mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
 603
 604   /* MAC Configuration Control Register should be written last */
 605   /* Let set_multicast_list set this. */
 606   /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
 607   mace_write(lp, ioaddr, MACE_MACCC, 0x00);
 608   return 0;
 609 } /* mace_init */
 610
 611 static int nmclan_config(struct pcmcia_device *link)
 612 {
 613   struct net_device *dev = link->priv;
 614   mace_private *lp = netdev_priv(dev);
 615   u8 *buf;
 616   size_t len;
 617   int i, ret;
 618   unsigned int ioaddr;
 619
 620   dev_dbg(&link->dev, "nmclan_config\n");
 621
 622   link->io_lines = 5;
 623   ret = pcmcia_request_io(link);
 624   if (ret)
 625           goto failed;
 626   ret = pcmcia_request_exclusive_irq(link, mace_interrupt);
 627   if (ret)
 628           goto failed;
 629   ret = pcmcia_enable_device(link);
 630   if (ret)
 631           goto failed;
 632
 633   dev->irq = link->irq;
 634   dev->base_addr = link->resource[0]->start;
 635
 636   ioaddr = dev->base_addr;
 637
 638   /* Read the ethernet address from the CIS. */
 639   len = pcmcia_get_tuple(link, 0x80, &buf);
 640   if (!buf || len < ETH_ALEN) {
 641           kfree(buf);
 642           goto failed;
 643   }
 644   memcpy(dev->dev_addr, buf, ETH_ALEN);
 645   kfree(buf);
 646
 647   /* Verify configuration by reading the MACE ID. */
 648   {
 649     char sig[2];
 650
 651     sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);
 652     sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);
 653     if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
 654       dev_dbg(&link->dev, "nmclan_cs configured: mace id=%x %x\n",
 655             sig[0], sig[1]);
 656     } else {
 657       pr_notice("mace id not found: %x %x should be 0x40 0x?9\n",
 658                 sig[0], sig[1]);
 659       return -ENODEV;
 660     }
 661   }
 662
 663   if(mace_init(lp, ioaddr, dev->dev_addr) == -1)
 664         goto failed;
 665
 666   /* The if_port symbol can be set when the module is loaded */
 667   if (if_port <= 2)
 668     dev->if_port = if_port;
 669   else
 670     pr_notice("invalid if_port requested\n");
 671
 672   SET_NETDEV_DEV(dev, &link->dev);
 673
 674   i = register_netdev(dev);
 675   if (i != 0) {
 676     pr_notice("register_netdev() failed\n");
 677     goto failed;
 678   }
 679
 680   netdev_info(dev, "nmclan: port %#3lx, irq %d, %s port, hw_addr %pM\n",
 681               dev->base_addr, dev->irq, if_names[dev->if_port], dev->dev_addr);
 682   return 0;
 683
 684 failed:
 685         nmclan_release(link);
 686         return -ENODEV;
 687 } /* nmclan_config */
 688
 689 static void nmclan_release(struct pcmcia_device *link)
 690 {
 691         dev_dbg(&link->dev, "nmclan_release\n");
 692         pcmcia_disable_device(link);
 693 }
 694
 695 static int nmclan_suspend(struct pcmcia_device *link)
 696 {
 697         struct net_device *dev = link->priv;
 698
 699         if (link->open)
 700                 netif_device_detach(dev);
 701
 702         return 0;
 703 }
 704
 705 static int nmclan_resume(struct pcmcia_device *link)
 706 {
 707         struct net_device *dev = link->priv;
 708
 709         if (link->open) {
 710                 nmclan_reset(dev);
 711                 netif_device_attach(dev);
 712         }
 713
 714         return 0;
 715 }
 716
 717
 718 /* ----------------------------------------------------------------------------
 719 nmclan_reset
 720         Reset and restore all of the Xilinx and MACE registers.
 721 ---------------------------------------------------------------------------- */
 722 static void nmclan_reset(struct net_device *dev)
 723 {
 724   mace_private *lp = netdev_priv(dev);
 725
 726 #if RESET_XILINX
 727   struct pcmcia_device *link = &lp->link;
 728   u8 OrigCorValue;
 729
 730   /* Save original COR value */
 731   pcmcia_read_config_byte(link, CISREG_COR, &OrigCorValue);
 732
 733   /* Reset Xilinx */
 734   dev_dbg(&link->dev, "nmclan_reset: OrigCorValue=0x%x, resetting...\n",
 735         OrigCorValue);
 736   pcmcia_write_config_byte(link, CISREG_COR, COR_SOFT_RESET);
 737   /* Need to wait for 20 ms for PCMCIA to finish reset. */
 738
 739   /* Restore original COR configuration index */
 740   pcmcia_write_config_byte(link, CISREG_COR,
 741                           (COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK)));
 742   /* Xilinx is now completely reset along with the MACE chip. */
 743   lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
 744
 745 #endif /* #if RESET_XILINX */
 746
 747   /* Xilinx is now completely reset along with the MACE chip. */
 748   lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
 749
 750   /* Reinitialize the MACE chip for operation. */
 751   mace_init(lp, dev->base_addr, dev->dev_addr);
 752   mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
 753
 754   /* Restore the multicast list and enable TX and RX. */
 755   restore_multicast_list(dev);
 756 } /* nmclan_reset */
 757
 758 /* ----------------------------------------------------------------------------
 759 mace_config
 760         [Someone tell me what this is supposed to do?  Is if_port a defined
 761         standard?  If so, there should be defines to indicate 1=10Base-T,
 762         2=10Base-2, etc. including limited automatic detection.]
 763 ---------------------------------------------------------------------------- */
 764 static int mace_config(struct net_device *dev, struct ifmap *map)
 765 {
 766   if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
 767     if (map->port <= 2) {
 768       dev->if_port = map->port;
 769       netdev_info(dev, "switched to %s port\n", if_names[dev->if_port]);
 770     } else
 771       return -EINVAL;
 772   }
 773   return 0;
 774 } /* mace_config */
 775
 776 /* ----------------------------------------------------------------------------
 777 mace_open
 778         Open device driver.
 779 ---------------------------------------------------------------------------- */
 780 static int mace_open(struct net_device *dev)
 781 {
 782   unsigned int ioaddr = dev->base_addr;
 783   mace_private *lp = netdev_priv(dev);
 784   struct pcmcia_device *link = lp->p_dev;
 785
 786   if (!pcmcia_dev_present(link))
 787     return -ENODEV;
 788
 789   link->open++;
 790
 791   MACEBANK(0);
 792
 793   netif_start_queue(dev);
 794   nmclan_reset(dev);
 795
 796   return 0; /* Always succeed */
 797 } /* mace_open */
 798
 799 /* ----------------------------------------------------------------------------
 800 mace_close
 801         Closes device driver.
 802 ---------------------------------------------------------------------------- */
 803 static int mace_close(struct net_device *dev)
 804 {
 805   unsigned int ioaddr = dev->base_addr;
 806   mace_private *lp = netdev_priv(dev);
 807   struct pcmcia_device *link = lp->p_dev;
 808
 809   dev_dbg(&link->dev, "%s: shutting down ethercard.\n", dev->name);
 810
 811   /* Mask off all interrupts from the MACE chip. */
 812   outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
 813
 814   link->open--;
 815   netif_stop_queue(dev);
 816
 817   return 0;
 818 } /* mace_close */
 819
 820 static void netdev_get_drvinfo(struct net_device *dev,
 821                                struct ethtool_drvinfo *info)
 822 {
 823         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
 824         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
 825         snprintf(info->bus_info, sizeof(info->bus_info),
 826                 "PCMCIA 0x%lx", dev->base_addr);
 827 }
 828
 829 static const struct ethtool_ops netdev_ethtool_ops = {
 830         .get_drvinfo            = netdev_get_drvinfo,
 831 };
 832
 833 /* ----------------------------------------------------------------------------
 834 mace_start_xmit
 835         This routine begins the packet transmit function.  When completed,
 836         it will generate a transmit interrupt.
 837
 838         According to /usr/src/linux/net/inet/dev.c, if _start_xmit
 839         returns 0, the "packet is now solely the responsibility of the
 840         driver."  If _start_xmit returns non-zero, the "transmission
 841         failed, put skb back into a list."
 842 ---------------------------------------------------------------------------- */
 843
 844 static void mace_tx_timeout(struct net_device *dev)
 845 {
 846   mace_private *lp = netdev_priv(dev);
 847   struct pcmcia_device *link = lp->p_dev;
 848
 849   netdev_notice(dev, "transmit timed out -- ");
 850 #if RESET_ON_TIMEOUT
 851   pr_cont("resetting card\n");
 852   pcmcia_reset_card(link->socket);
 853 #else /* #if RESET_ON_TIMEOUT */
 854   pr_cont("NOT resetting card\n");
 855 #endif /* #if RESET_ON_TIMEOUT */
 856   dev->trans_start = jiffies; /* prevent tx timeout */
 857   netif_wake_queue(dev);
 858 }
 859
 860 static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
 861                                          struct net_device *dev)
 862 {
 863   mace_private *lp = netdev_priv(dev);
 864   unsigned int ioaddr = dev->base_addr;
 865
 866   netif_stop_queue(dev);
 867
 868   pr_debug("%s: mace_start_xmit(length = %ld) called.\n",
 869         dev->name, (long)skb->len);
 870
 871 #if (!TX_INTERRUPTABLE)
 872   /* Disable MACE TX interrupts. */
 873   outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
 874     ioaddr + AM2150_MACE_BASE + MACE_IMR);
 875   lp->tx_irq_disabled=1;
 876 #endif /* #if (!TX_INTERRUPTABLE) */
 877
 878   {
 879     /* This block must not be interrupted by another transmit request!
 880        mace_tx_timeout will take care of timer-based retransmissions from
 881        the upper layers.  The interrupt handler is guaranteed never to
 882        service a transmit interrupt while we are in here.
 883     */
 884
 885     lp->linux_stats.tx_bytes += skb->len;
 886     lp->tx_free_frames--;
 887
 888     /* WARNING: Write the _exact_ number of bytes written in the header! */
 889     /* Put out the word header [must be an outw()] . . . */
 890     outw(skb->len, ioaddr + AM2150_XMT);
 891     /* . . . and the packet [may be any combination of outw() and outb()] */
 892     outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
 893     if (skb->len & 1) {
 894       /* Odd byte transfer */
 895       outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
 896     }
 897
 898 #if MULTI_TX
 899     if (lp->tx_free_frames > 0)
 900       netif_start_queue(dev);
 901 #endif /* #if MULTI_TX */
 902   }
 903
 904 #if (!TX_INTERRUPTABLE)
 905   /* Re-enable MACE TX interrupts. */
 906   lp->tx_irq_disabled=0;
 907   outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
 908 #endif /* #if (!TX_INTERRUPTABLE) */
 909
 910   dev_kfree_skb(skb);
 911
 912   return NETDEV_TX_OK;
 913 } /* mace_start_xmit */
 914
 915 /* ----------------------------------------------------------------------------
 916 mace_interrupt
 917         The interrupt handler.
 918 ---------------------------------------------------------------------------- */
 919 static irqreturn_t mace_interrupt(int irq, void *dev_id)
 920 {
 921   struct net_device *dev = (struct net_device *) dev_id;
 922   mace_private *lp = netdev_priv(dev);
 923   unsigned int ioaddr;
 924   int status;
 925   int IntrCnt = MACE_MAX_IR_ITERATIONS;
 926
 927   if (dev == NULL) {
 928     pr_debug("mace_interrupt(): irq 0x%X for unknown device.\n",
 929           irq);
 930     return IRQ_NONE;
 931   }
 932
 933   ioaddr = dev->base_addr;
 934
 935   if (lp->tx_irq_disabled) {
 936     const char *msg;
 937     if (lp->tx_irq_disabled)
 938       msg = "Interrupt with tx_irq_disabled";
 939     else
 940       msg = "Re-entering the interrupt handler";
 941     netdev_notice(dev, "%s [isr=%02X, imr=%02X]\n",
 942                   msg,
 943                   inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
 944                   inb(ioaddr + AM2150_MACE_BASE + MACE_IMR));
 945     /* WARNING: MACE_IR has been read! */
 946     return IRQ_NONE;
 947   }
 948
 949   if (!netif_device_present(dev)) {
 950     netdev_dbg(dev, "interrupt from dead card\n");
 951     return IRQ_NONE;
 952   }
 953
 954   do {
 955     /* WARNING: MACE_IR is a READ/CLEAR port! */
 956     status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
 957
 958     pr_debug("mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
 959
 960     if (status & MACE_IR_RCVINT) {
 961       mace_rx(dev, MACE_MAX_RX_ITERATIONS);
 962     }
 963
 964     if (status & MACE_IR_XMTINT) {
 965       unsigned char fifofc;
 966       unsigned char xmtrc;
 967       unsigned char xmtfs;
 968
 969       fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
 970       if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
 971         lp->linux_stats.tx_errors++;
 972         outb(0xFF, ioaddr + AM2150_XMT_SKIP);
 973       }
 974
 975       /* Transmit Retry Count (XMTRC, reg 4) */
 976       xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
 977       if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
 978       lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
 979
 980       if (
 981         (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
 982         MACE_XMTFS_XMTSV /* Transmit Status Valid */
 983       ) {
 984         lp->mace_stats.xmtsv++;
 985
 986         if (xmtfs & ~MACE_XMTFS_XMTSV) {
 987           if (xmtfs & MACE_XMTFS_UFLO) {
 988             /* Underflow.  Indicates that the Transmit FIFO emptied before
 989                the end of frame was reached. */
 990             lp->mace_stats.uflo++;
 991           }
 992           if (xmtfs & MACE_XMTFS_LCOL) {
 993             /* Late Collision */
 994             lp->mace_stats.lcol++;
 995           }
 996           if (xmtfs & MACE_XMTFS_MORE) {
 997             /* MORE than one retry was needed */
 998             lp->mace_stats.more++;
 999           }
1000           if (xmtfs & MACE_XMTFS_ONE) {
1001             /* Exactly ONE retry occurred */
1002             lp->mace_stats.one++;
1003           }
1004           if (xmtfs & MACE_XMTFS_DEFER) {
1005             /* Transmission was defered */
1006             lp->mace_stats.defer++;
1007           }
1008           if (xmtfs & MACE_XMTFS_LCAR) {
1009             /* Loss of carrier */
1010             lp->mace_stats.lcar++;
1011           }
1012           if (xmtfs & MACE_XMTFS_RTRY) {
1013             /* Retry error: transmit aborted after 16 attempts */
1014             lp->mace_stats.rtry++;
1015           }
1016         } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1017
1018       } /* if (xmtfs & MACE_XMTFS_XMTSV) */
1019
1020       lp->linux_stats.tx_packets++;
1021       lp->tx_free_frames++;
1022       netif_wake_queue(dev);
1023     } /* if (status & MACE_IR_XMTINT) */
1024
1025     if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1026       if (status & MACE_IR_JAB) {
1027         /* Jabber Error.  Excessive transmit duration (20-150ms). */
1028         lp->mace_stats.jab++;
1029       }
1030       if (status & MACE_IR_BABL) {
1031         /* Babble Error.  >1518 bytes transmitted. */
1032         lp->mace_stats.babl++;
1033       }
1034       if (status & MACE_IR_CERR) {
1035         /* Collision Error.  CERR indicates the absence of the
1036            Signal Quality Error Test message after a packet
1037            transmission. */
1038         lp->mace_stats.cerr++;
1039       }
1040       if (status & MACE_IR_RCVCCO) {
1041         /* Receive Collision Count Overflow; */
1042         lp->mace_stats.rcvcco++;
1043       }
1044       if (status & MACE_IR_RNTPCO) {
1045         /* Runt Packet Count Overflow */
1046         lp->mace_stats.rntpco++;
1047       }
1048       if (status & MACE_IR_MPCO) {
1049         /* Missed Packet Count Overflow */
1050         lp->mace_stats.mpco++;
1051       }
1052     } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1053
1054   } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1055
1056   return IRQ_HANDLED;
1057 } /* mace_interrupt */
1058
1059 /* ----------------------------------------------------------------------------
1060 mace_rx
1061         Receives packets.
1062 ---------------------------------------------------------------------------- */
1063 static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1064 {
1065   mace_private *lp = netdev_priv(dev);
1066   unsigned int ioaddr = dev->base_addr;
1067   unsigned char rx_framecnt;
1068   unsigned short rx_status;
1069
1070   while (
1071     ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1072     (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1073     (RxCnt--)
1074   ) {
1075     rx_status = inw(ioaddr + AM2150_RCV);
1076
1077     pr_debug("%s: in mace_rx(), framecnt 0x%X, rx_status"
1078           " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1079
1080     if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1081       lp->linux_stats.rx_errors++;
1082       if (rx_status & MACE_RCVFS_OFLO) {
1083         lp->mace_stats.oflo++;
1084       }
1085       if (rx_status & MACE_RCVFS_CLSN) {
1086         lp->mace_stats.clsn++;
1087       }
1088       if (rx_status & MACE_RCVFS_FRAM) {
1089         lp->mace_stats.fram++;
1090       }
1091       if (rx_status & MACE_RCVFS_FCS) {
1092         lp->mace_stats.fcs++;
1093       }
1094     } else {
1095       short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1096         /* Auto Strip is off, always subtract 4 */
1097       struct sk_buff *skb;
1098
1099       lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1100         /* runt packet count */
1101       lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1102         /* rcv collision count */
1103
1104       pr_debug("    receiving packet size 0x%X rx_status"
1105             " 0x%X.\n", pkt_len, rx_status);
1106
1107       skb = dev_alloc_skb(pkt_len+2);
1108
1109       if (skb != NULL) {
1110         skb_reserve(skb, 2);
1111         insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1112         if (pkt_len & 1)
1113             *(skb_tail_pointer(skb) - 1) = inb(ioaddr + AM2150_RCV);
1114         skb->protocol = eth_type_trans(skb, dev);
1115
1116         netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1117
1118         lp->linux_stats.rx_packets++;
1119         lp->linux_stats.rx_bytes += pkt_len;
1120         outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1121         continue;
1122       } else {
1123         pr_debug("%s: couldn't allocate a sk_buff of size"
1124               " %d.\n", dev->name, pkt_len);
1125         lp->linux_stats.rx_dropped++;
1126       }
1127     }
1128     outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1129   } /* while */
1130
1131   return 0;
1132 } /* mace_rx */
1133
1134 /* ----------------------------------------------------------------------------
1135 pr_linux_stats
1136 ---------------------------------------------------------------------------- */
1137 static void pr_linux_stats(struct net_device_stats *pstats)
1138 {
1139   pr_debug("pr_linux_stats\n");
1140   pr_debug(" rx_packets=%-7ld        tx_packets=%ld\n",
1141         (long)pstats->rx_packets, (long)pstats->tx_packets);
1142   pr_debug(" rx_errors=%-7ld         tx_errors=%ld\n",
1143         (long)pstats->rx_errors, (long)pstats->tx_errors);
1144   pr_debug(" rx_dropped=%-7ld        tx_dropped=%ld\n",
1145         (long)pstats->rx_dropped, (long)pstats->tx_dropped);
1146   pr_debug(" multicast=%-7ld         collisions=%ld\n",
1147         (long)pstats->multicast, (long)pstats->collisions);
1148
1149   pr_debug(" rx_length_errors=%-7ld  rx_over_errors=%ld\n",
1150         (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
1151   pr_debug(" rx_crc_errors=%-7ld     rx_frame_errors=%ld\n",
1152         (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
1153   pr_debug(" rx_fifo_errors=%-7ld    rx_missed_errors=%ld\n",
1154         (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1155
1156   pr_debug(" tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1157         (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
1158   pr_debug(" tx_fifo_errors=%-7ld    tx_heartbeat_errors=%ld\n",
1159         (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
1160   pr_debug(" tx_window_errors=%ld\n",
1161         (long)pstats->tx_window_errors);
1162 } /* pr_linux_stats */
1163
1164 /* ----------------------------------------------------------------------------
1165 pr_mace_stats
1166 ---------------------------------------------------------------------------- */
1167 static void pr_mace_stats(mace_statistics *pstats)
1168 {
1169   pr_debug("pr_mace_stats\n");
1170
1171   pr_debug(" xmtsv=%-7d             uflo=%d\n",
1172         pstats->xmtsv, pstats->uflo);
1173   pr_debug(" lcol=%-7d              more=%d\n",
1174         pstats->lcol, pstats->more);
1175   pr_debug(" one=%-7d               defer=%d\n",
1176         pstats->one, pstats->defer);
1177   pr_debug(" lcar=%-7d              rtry=%d\n",
1178         pstats->lcar, pstats->rtry);
1179
1180   /* MACE_XMTRC */
1181   pr_debug(" exdef=%-7d             xmtrc=%d\n",
1182         pstats->exdef, pstats->xmtrc);
1183
1184   /* RFS1--Receive Status (RCVSTS) */
1185   pr_debug(" oflo=%-7d              clsn=%d\n",
1186         pstats->oflo, pstats->clsn);
1187   pr_debug(" fram=%-7d              fcs=%d\n",
1188         pstats->fram, pstats->fcs);
1189
1190   /* RFS2--Runt Packet Count (RNTPC) */
1191   /* RFS3--Receive Collision Count (RCVCC) */
1192   pr_debug(" rfs_rntpc=%-7d         rfs_rcvcc=%d\n",
1193         pstats->rfs_rntpc, pstats->rfs_rcvcc);
1194
1195   /* MACE_IR */
1196   pr_debug(" jab=%-7d               babl=%d\n",
1197         pstats->jab, pstats->babl);
1198   pr_debug(" cerr=%-7d              rcvcco=%d\n",
1199         pstats->cerr, pstats->rcvcco);
1200   pr_debug(" rntpco=%-7d            mpco=%d\n",
1201         pstats->rntpco, pstats->mpco);
1202
1203   /* MACE_MPC */
1204   pr_debug(" mpc=%d\n", pstats->mpc);
1205
1206   /* MACE_RNTPC */
1207   pr_debug(" rntpc=%d\n", pstats->rntpc);
1208
1209   /* MACE_RCVCC */
1210   pr_debug(" rcvcc=%d\n", pstats->rcvcc);
1211
1212 } /* pr_mace_stats */
1213
1214 /* ----------------------------------------------------------------------------
1215 update_stats
1216         Update statistics.  We change to register window 1, so this
1217         should be run single-threaded if the device is active. This is
1218         expected to be a rare operation, and it's simpler for the rest
1219         of the driver to assume that window 0 is always valid rather
1220         than use a special window-state variable.
1221
1222         oflo & uflo should _never_ occur since it would mean the Xilinx
1223         was not able to transfer data between the MACE FIFO and the
1224         card's SRAM fast enough.  If this happens, something is
1225         seriously wrong with the hardware.
1226 ---------------------------------------------------------------------------- */
1227 static void update_stats(unsigned int ioaddr, struct net_device *dev)
1228 {
1229   mace_private *lp = netdev_priv(dev);
1230
1231   lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
1232   lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
1233   lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC);
1234   /* At this point, mace_stats is fully updated for this call.
1235      We may now update the linux_stats. */
1236
1237   /* The MACE has no equivalent for linux_stats field which are commented
1238      out. */
1239
1240   /* lp->linux_stats.multicast; */
1241   lp->linux_stats.collisions =
1242     lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1243     /* Collision: The MACE may retry sending a packet 15 times
1244        before giving up.  The retry count is in XMTRC.
1245        Does each retry constitute a collision?
1246        If so, why doesn't the RCVCC record these collisions? */
1247
1248   /* detailed rx_errors: */
1249   lp->linux_stats.rx_length_errors =
1250     lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1251   /* lp->linux_stats.rx_over_errors */
1252   lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs;
1253   lp->linux_stats.rx_frame_errors = lp->mace_stats.fram;
1254   lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo;
1255   lp->linux_stats.rx_missed_errors =
1256     lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1257
1258   /* detailed tx_errors */
1259   lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry;
1260   lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar;
1261     /* LCAR usually results from bad cabling. */
1262   lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo;
1263   lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1264   /* lp->linux_stats.tx_window_errors; */
1265 } /* update_stats */
1266
1267 /* ----------------------------------------------------------------------------
1268 mace_get_stats
1269         Gathers ethernet statistics from the MACE chip.
1270 ---------------------------------------------------------------------------- */
1271 static struct net_device_stats *mace_get_stats(struct net_device *dev)
1272 {
1273   mace_private *lp = netdev_priv(dev);
1274
1275   update_stats(dev->base_addr, dev);
1276
1277   pr_debug("%s: updating the statistics.\n", dev->name);
1278   pr_linux_stats(&lp->linux_stats);
1279   pr_mace_stats(&lp->mace_stats);
1280
1281   return &lp->linux_stats;
1282 } /* net_device_stats */
1283
1284 /* ----------------------------------------------------------------------------
1285 updateCRC
1286         Modified from Am79C90 data sheet.
1287 ---------------------------------------------------------------------------- */
1288
1289 #ifdef BROKEN_MULTICAST
1290
1291 static void updateCRC(int *CRC, int bit)
1292 {
1293   static const int poly[]={
1294     1,1,1,0, 1,1,0,1,
1295     1,0,1,1, 1,0,0,0,
1296     1,0,0,0, 0,0,1,1,
1297     0,0,1,0, 0,0,0,0
1298   }; /* CRC polynomial.  poly[n] = coefficient of the x**n term of the
1299         CRC generator polynomial. */
1300
1301   int j;
1302
1303   /* shift CRC and control bit (CRC[32]) */
1304   for (j = 32; j > 0; j--)
1305     CRC[j] = CRC[j-1];
1306   CRC[0] = 0;
1307
1308   /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1309   if (bit ^ CRC[32])
1310     for (j = 0; j < 32; j++)
1311       CRC[j] ^= poly[j];
1312 } /* updateCRC */
1313
1314 /* ----------------------------------------------------------------------------
1315 BuildLAF
1316         Build logical address filter.
1317         Modified from Am79C90 data sheet.
1318
1319 Input
1320         ladrf: logical address filter (contents initialized to 0)
1321         adr: ethernet address
1322 ---------------------------------------------------------------------------- */
1323 static void BuildLAF(int *ladrf, int *adr)
1324 {
1325   int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1326
1327   int i, byte; /* temporary array indices */
1328   int hashcode; /* the output object */
1329
1330   CRC[32]=0;
1331
1332   for (byte = 0; byte < 6; byte++)
1333     for (i = 0; i < 8; i++)
1334       updateCRC(CRC, (adr[byte] >> i) & 1);
1335
1336   hashcode = 0;
1337   for (i = 0; i < 6; i++)
1338     hashcode = (hashcode << 1) + CRC[i];
1339
1340   byte = hashcode >> 3;
1341   ladrf[byte] |= (1 << (hashcode & 7));
1342
1343 #ifdef PCMCIA_DEBUG
1344   if (0)
1345     printk(KERN_DEBUG "    adr =%pM\n", adr);
1346   printk(KERN_DEBUG "    hashcode = %d(decimal), ladrf[0:63] =", hashcode);
1347   for (i = 0; i < 8; i++)
1348     pr_cont(" %02X", ladrf[i]);
1349   pr_cont("\n");
1350 #endif
1351 } /* BuildLAF */
1352
1353 /* ----------------------------------------------------------------------------
1354 restore_multicast_list
1355         Restores the multicast filter for MACE chip to the last
1356         set_multicast_list() call.
1357
1358 Input
1359         multicast_num_addrs
1360         multicast_ladrf[]
1361 ---------------------------------------------------------------------------- */
1362 static void restore_multicast_list(struct net_device *dev)
1363 {
1364   mace_private *lp = netdev_priv(dev);
1365   int num_addrs = lp->multicast_num_addrs;
1366   int *ladrf = lp->multicast_ladrf;
1367   unsigned int ioaddr = dev->base_addr;
1368   int i;
1369
1370   pr_debug("%s: restoring Rx mode to %d addresses.\n",
1371         dev->name, num_addrs);
1372
1373   if (num_addrs > 0) {
1374
1375     pr_debug("Attempt to restore multicast list detected.\n");
1376
1377     mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1378     /* Poll ADDRCHG bit */
1379     while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1380       ;
1381     /* Set LADRF register */
1382     for (i = 0; i < MACE_LADRF_LEN; i++)
1383       mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
1384
1385     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1386     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1387
1388   } else if (num_addrs < 0) {
1389
1390     /* Promiscuous mode: receive all packets */
1391     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1392     mace_write(lp, ioaddr, MACE_MACCC,
1393       MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1394     );
1395
1396   } else {
1397
1398     /* Normal mode */
1399     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1400     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1401
1402   }
1403 } /* restore_multicast_list */
1404
1405 /* ----------------------------------------------------------------------------
1406 set_multicast_list
1407         Set or clear the multicast filter for this adaptor.
1408
1409 Input
1410         num_addrs == -1 Promiscuous mode, receive all packets
1411         num_addrs == 0  Normal mode, clear multicast list
1412         num_addrs > 0   Multicast mode, receive normal and MC packets, and do
1413                         best-effort filtering.
1414 Output
1415         multicast_num_addrs
1416         multicast_ladrf[]
1417 ---------------------------------------------------------------------------- */
1418
1419 static void set_multicast_list(struct net_device *dev)
1420 {
1421   mace_private *lp = netdev_priv(dev);
1422   int adr[ETH_ALEN] = {0}; /* Ethernet address */
1423   struct netdev_hw_addr *ha;
1424
1425 #ifdef PCMCIA_DEBUG
1426   {
1427     static int old;
1428     if (netdev_mc_count(dev) != old) {
1429       old = netdev_mc_count(dev);
1430       pr_debug("%s: setting Rx mode to %d addresses.\n",
1431             dev->name, old);
1432     }
1433   }
1434 #endif
1435
1436   /* Set multicast_num_addrs. */
1437   lp->multicast_num_addrs = netdev_mc_count(dev);
1438
1439   /* Set multicast_ladrf. */
1440   if (num_addrs > 0) {
1441     /* Calculate multicast logical address filter */
1442     memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
1443     netdev_for_each_mc_addr(ha, dev) {
1444       memcpy(adr, ha->addr, ETH_ALEN);
1445       BuildLAF(lp->multicast_ladrf, adr);
1446     }
1447   }
1448
1449   restore_multicast_list(dev);
1450
1451 } /* set_multicast_list */
1452
1453 #endif /* BROKEN_MULTICAST */
1454
1455 static void restore_multicast_list(struct net_device *dev)
1456 {
1457   unsigned int ioaddr = dev->base_addr;
1458   mace_private *lp = netdev_priv(dev);
1459
1460   pr_debug("%s: restoring Rx mode to %d addresses.\n", dev->name,
1461         lp->multicast_num_addrs);
1462
1463   if (dev->flags & IFF_PROMISC) {
1464     /* Promiscuous mode: receive all packets */
1465     mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1466     mace_write(lp, ioaddr, MACE_MACCC,
1467       MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1468     );
1469   } else {
1470     /* Normal mode */
1471     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1472     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1473   }
1474 } /* restore_multicast_list */
1475
1476 static void set_multicast_list(struct net_device *dev)
1477 {
1478   mace_private *lp = netdev_priv(dev);
1479
1480 #ifdef PCMCIA_DEBUG
1481   {
1482     static int old;
1483     if (netdev_mc_count(dev) != old) {
1484       old = netdev_mc_count(dev);
1485       pr_debug("%s: setting Rx mode to %d addresses.\n",
1486             dev->name, old);
1487     }
1488   }
1489 #endif
1490
1491   lp->multicast_num_addrs = netdev_mc_count(dev);
1492   restore_multicast_list(dev);
1493
1494 } /* set_multicast_list */
1495
1496 static const struct pcmcia_device_id nmclan_ids[] = {
1497         PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941),
1498         PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf),
1499         PCMCIA_DEVICE_NULL,
1500 };
1501 MODULE_DEVICE_TABLE(pcmcia, nmclan_ids);
1502
1503 static struct pcmcia_driver nmclan_cs_driver = {
1504         .owner          = THIS_MODULE,
1505         .name           = "nmclan_cs",
1506         .probe          = nmclan_probe,
1507         .remove         = nmclan_detach,
1508         .id_table       = nmclan_ids,
1509         .suspend        = nmclan_suspend,
1510         .resume         = nmclan_resume,
1511 };
1512
1513 static int __init init_nmclan_cs(void)
1514 {
1515         return pcmcia_register_driver(&nmclan_cs_driver);
1516 }
1517
1518 static void __exit exit_nmclan_cs(void)
1519 {
1520         pcmcia_unregister_driver(&nmclan_cs_driver);
1521 }
1522
1523 module_init(init_nmclan_cs);
1524 module_exit(exit_nmclan_cs);