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OMAPDSS: VENC: fix NULL pointer dereference in DSS2 VENC sysfs debug attr on OMAP4
[zen-stable.git] / drivers / net / ethernet / dec / tulip / uli526x.c
blob48b0b6566eef2105399e3bc06ddae226e94cde0d
1 /*
2 This program is free software; you can redistribute it and/or
3 modify it under the terms of the GNU General Public License
4 as published by the Free Software Foundation; either version 2
5 of the License, or (at your option) any later version.
6
7 This program is distributed in the hope that it will be useful,
8 but WITHOUT ANY WARRANTY; without even the implied warranty of
9 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 GNU General Public License for more details.
11
12
13 */
14
15 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
17 #define DRV_NAME "uli526x"
18 #define DRV_VERSION "0.9.3"
19 #define DRV_RELDATE "2005-7-29"
20
21 #include <linux/module.h>
22
23 #include <linux/kernel.h>
24 #include <linux/string.h>
25 #include <linux/timer.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/skbuff.h>
35 #include <linux/delay.h>
36 #include <linux/spinlock.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/bitops.h>
39
40 #include <asm/processor.h>
41 #include <asm/io.h>
42 #include <asm/dma.h>
43 #include <asm/uaccess.h>
44
45
46 /* Board/System/Debug information/definition ---------------- */
47 #define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/
48 #define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/
49
50 #define ULI526X_IO_SIZE 0x100
51 #define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */
52 #define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */
53 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
54 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
55 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
56 #define TX_BUF_ALLOC 0x600
57 #define RX_ALLOC_SIZE 0x620
58 #define ULI526X_RESET 1
59 #define CR0_DEFAULT 0
60 #define CR6_DEFAULT 0x22200000
61 #define CR7_DEFAULT 0x180c1
62 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
63 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
64 #define MAX_PACKET_SIZE 1514
65 #define ULI5261_MAX_MULTICAST 14
66 #define RX_COPY_SIZE 100
67 #define MAX_CHECK_PACKET 0x8000
68
69 #define ULI526X_10MHF 0
70 #define ULI526X_100MHF 1
71 #define ULI526X_10MFD 4
72 #define ULI526X_100MFD 5
73 #define ULI526X_AUTO 8
74
75 #define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
76 #define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
77 #define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
78 #define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
79 #define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
80 #define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
81
82 #define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
83 #define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */
84 #define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */
85
86 #define ULI526X_DBUG(dbug_now, msg, value) \
87 do { \
88 if (uli526x_debug || (dbug_now)) \
89 pr_err("%s %lx\n", (msg), (long) (value)); \
90 } while (0)
91
92 #define SHOW_MEDIA_TYPE(mode) \
93 pr_err("Change Speed to %sMhz %s duplex\n", \
94 mode & 1 ? "100" : "10", \
95 mode & 4 ? "full" : "half");
96
97
98 /* CR9 definition: SROM/MII */
99 #define CR9_SROM_READ 0x4800
100 #define CR9_SRCS 0x1
101 #define CR9_SRCLK 0x2
102 #define CR9_CRDOUT 0x8
103 #define SROM_DATA_0 0x0
104 #define SROM_DATA_1 0x4
105 #define PHY_DATA_1 0x20000
106 #define PHY_DATA_0 0x00000
107 #define MDCLKH 0x10000
108
109 #define PHY_POWER_DOWN 0x800
110
111 #define SROM_V41_CODE 0x14
112
113 #define SROM_CLK_WRITE(data, ioaddr) \
114 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
115 udelay(5); \
116 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
117 udelay(5); \
118 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
119 udelay(5);
120
121 /* Structure/enum declaration ------------------------------- */
122 struct tx_desc {
123 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
124 char *tx_buf_ptr; /* Data for us */
125 struct tx_desc *next_tx_desc;
126 } __attribute__(( aligned(32) ));
127
128 struct rx_desc {
129 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
130 struct sk_buff *rx_skb_ptr; /* Data for us */
131 struct rx_desc *next_rx_desc;
132 } __attribute__(( aligned(32) ));
133
134 struct uli526x_board_info {
135 u32 chip_id; /* Chip vendor/Device ID */
136 struct net_device *next_dev; /* next device */
137 struct pci_dev *pdev; /* PCI device */
138 spinlock_t lock;
139
140 long ioaddr; /* I/O base address */
141 u32 cr0_data;
142 u32 cr5_data;
143 u32 cr6_data;
144 u32 cr7_data;
145 u32 cr15_data;
146
147 /* pointer for memory physical address */
148 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
149 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
150 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
151 dma_addr_t first_tx_desc_dma;
152 dma_addr_t first_rx_desc_dma;
153
154 /* descriptor pointer */
155 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
156 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
157 unsigned char *desc_pool_ptr; /* descriptor pool memory */
158 struct tx_desc *first_tx_desc;
159 struct tx_desc *tx_insert_ptr;
160 struct tx_desc *tx_remove_ptr;
161 struct rx_desc *first_rx_desc;
162 struct rx_desc *rx_insert_ptr;
163 struct rx_desc *rx_ready_ptr; /* packet come pointer */
164 unsigned long tx_packet_cnt; /* transmitted packet count */
165 unsigned long rx_avail_cnt; /* available rx descriptor count */
166 unsigned long interval_rx_cnt; /* rx packet count a callback time */
167
168 u16 dbug_cnt;
169 u16 NIC_capability; /* NIC media capability */
170 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
171
172 u8 media_mode; /* user specify media mode */
173 u8 op_mode; /* real work media mode */
174 u8 phy_addr;
175 u8 link_failed; /* Ever link failed */
176 u8 wait_reset; /* Hardware failed, need to reset */
177 struct timer_list timer;
178
179 /* Driver defined statistic counter */
180 unsigned long tx_fifo_underrun;
181 unsigned long tx_loss_carrier;
182 unsigned long tx_no_carrier;
183 unsigned long tx_late_collision;
184 unsigned long tx_excessive_collision;
185 unsigned long tx_jabber_timeout;
186 unsigned long reset_count;
187 unsigned long reset_cr8;
188 unsigned long reset_fatal;
189 unsigned long reset_TXtimeout;
190
191 /* NIC SROM data */
192 unsigned char srom[128];
193 u8 init;
194 };
195
196 enum uli526x_offsets {
197 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
198 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
199 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
200 DCR15 = 0x78
201 };
202
203 enum uli526x_CR6_bits {
204 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
205 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
206 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
207 };
208
209 /* Global variable declaration ----------------------------- */
210 static int __devinitdata printed_version;
211 static const char version[] __devinitconst =
212 "ULi M5261/M5263 net driver, version " DRV_VERSION " (" DRV_RELDATE ")";
213
214 static int uli526x_debug;
215 static unsigned char uli526x_media_mode = ULI526X_AUTO;
216 static u32 uli526x_cr6_user_set;
217
218 /* For module input parameter */
219 static int debug;
220 static u32 cr6set;
221 static int mode = 8;
222
223 /* function declaration ------------------------------------- */
224 static int uli526x_open(struct net_device *);
225 static netdev_tx_t uli526x_start_xmit(struct sk_buff *,
226 struct net_device *);
227 static int uli526x_stop(struct net_device *);
228 static void uli526x_set_filter_mode(struct net_device *);
229 static const struct ethtool_ops netdev_ethtool_ops;
230 static u16 read_srom_word(long, int);
231 static irqreturn_t uli526x_interrupt(int, void *);
232 #ifdef CONFIG_NET_POLL_CONTROLLER
233 static void uli526x_poll(struct net_device *dev);
234 #endif
235 static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
236 static void allocate_rx_buffer(struct uli526x_board_info *);
237 static void update_cr6(u32, unsigned long);
238 static void send_filter_frame(struct net_device *, int);
239 static u16 phy_read(unsigned long, u8, u8, u32);
240 static u16 phy_readby_cr10(unsigned long, u8, u8);
241 static void phy_write(unsigned long, u8, u8, u16, u32);
242 static void phy_writeby_cr10(unsigned long, u8, u8, u16);
243 static void phy_write_1bit(unsigned long, u32, u32);
244 static u16 phy_read_1bit(unsigned long, u32);
245 static u8 uli526x_sense_speed(struct uli526x_board_info *);
246 static void uli526x_process_mode(struct uli526x_board_info *);
247 static void uli526x_timer(unsigned long);
248 static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *);
249 static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *);
250 static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *);
251 static void uli526x_dynamic_reset(struct net_device *);
252 static void uli526x_free_rxbuffer(struct uli526x_board_info *);
253 static void uli526x_init(struct net_device *);
254 static void uli526x_set_phyxcer(struct uli526x_board_info *);
255
256 /* ULI526X network board routine ---------------------------- */
257
258 static const struct net_device_ops netdev_ops = {
259 .ndo_open = uli526x_open,
260 .ndo_stop = uli526x_stop,
261 .ndo_start_xmit = uli526x_start_xmit,
262 .ndo_set_rx_mode = uli526x_set_filter_mode,
263 .ndo_change_mtu = eth_change_mtu,
264 .ndo_set_mac_address = eth_mac_addr,
265 .ndo_validate_addr = eth_validate_addr,
266 #ifdef CONFIG_NET_POLL_CONTROLLER
267 .ndo_poll_controller = uli526x_poll,
268 #endif
269 };
270
271 /*
272 * Search ULI526X board, allocate space and register it
273 */
274
275 static int __devinit uli526x_init_one (struct pci_dev *pdev,
276 const struct pci_device_id *ent)
277 {
278 struct uli526x_board_info *db; /* board information structure */
279 struct net_device *dev;
280 int i, err;
281
282 ULI526X_DBUG(0, "uli526x_init_one()", 0);
283
284 if (!printed_version++)
285 pr_info("%s\n", version);
286
287 /* Init network device */
288 dev = alloc_etherdev(sizeof(*db));
289 if (dev == NULL)
290 return -ENOMEM;
291 SET_NETDEV_DEV(dev, &pdev->dev);
292
293 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
294 pr_warn("32-bit PCI DMA not available\n");
295 err = -ENODEV;
296 goto err_out_free;
297 }
298
299 /* Enable Master/IO access, Disable memory access */
300 err = pci_enable_device(pdev);
301 if (err)
302 goto err_out_free;
303
304 if (!pci_resource_start(pdev, 0)) {
305 pr_err("I/O base is zero\n");
306 err = -ENODEV;
307 goto err_out_disable;
308 }
309
310 if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) {
311 pr_err("Allocated I/O size too small\n");
312 err = -ENODEV;
313 goto err_out_disable;
314 }
315
316 if (pci_request_regions(pdev, DRV_NAME)) {
317 pr_err("Failed to request PCI regions\n");
318 err = -ENODEV;
319 goto err_out_disable;
320 }
321
322 /* Init system & device */
323 db = netdev_priv(dev);
324
325 /* Allocate Tx/Rx descriptor memory */
326 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
327 if(db->desc_pool_ptr == NULL)
328 {
329 err = -ENOMEM;
330 goto err_out_nomem;
331 }
332 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
333 if(db->buf_pool_ptr == NULL)
334 {
335 err = -ENOMEM;
336 goto err_out_nomem;
337 }
338
339 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
340 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
341 db->buf_pool_start = db->buf_pool_ptr;
342 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
343
344 db->chip_id = ent->driver_data;
345 db->ioaddr = pci_resource_start(pdev, 0);
346
347 db->pdev = pdev;
348 db->init = 1;
349
350 dev->base_addr = db->ioaddr;
351 dev->irq = pdev->irq;
352 pci_set_drvdata(pdev, dev);
353
354 /* Register some necessary functions */
355 dev->netdev_ops = &netdev_ops;
356 dev->ethtool_ops = &netdev_ethtool_ops;
357
358 spin_lock_init(&db->lock);
359
360
361 /* read 64 word srom data */
362 for (i = 0; i < 64; i++)
363 ((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i));
364
365 /* Set Node address */
366 if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) /* SROM absent, so read MAC address from ID Table */
367 {
368 outl(0x10000, db->ioaddr + DCR0); //Diagnosis mode
369 outl(0x1c0, db->ioaddr + DCR13); //Reset dianostic pointer port
370 outl(0, db->ioaddr + DCR14); //Clear reset port
371 outl(0x10, db->ioaddr + DCR14); //Reset ID Table pointer
372 outl(0, db->ioaddr + DCR14); //Clear reset port
373 outl(0, db->ioaddr + DCR13); //Clear CR13
374 outl(0x1b0, db->ioaddr + DCR13); //Select ID Table access port
375 //Read MAC address from CR14
376 for (i = 0; i < 6; i++)
377 dev->dev_addr[i] = inl(db->ioaddr + DCR14);
378 //Read end
379 outl(0, db->ioaddr + DCR13); //Clear CR13
380 outl(0, db->ioaddr + DCR0); //Clear CR0
381 udelay(10);
382 }
383 else /*Exist SROM*/
384 {
385 for (i = 0; i < 6; i++)
386 dev->dev_addr[i] = db->srom[20 + i];
387 }
388 err = register_netdev (dev);
389 if (err)
390 goto err_out_res;
391
392 netdev_info(dev, "ULi M%04lx at pci%s, %pM, irq %d\n",
393 ent->driver_data >> 16, pci_name(pdev),
394 dev->dev_addr, dev->irq);
395
396 pci_set_master(pdev);
397
398 return 0;
399
400 err_out_res:
401 pci_release_regions(pdev);
402 err_out_nomem:
403 if(db->desc_pool_ptr)
404 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
405 db->desc_pool_ptr, db->desc_pool_dma_ptr);
406
407 if(db->buf_pool_ptr != NULL)
408 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
409 db->buf_pool_ptr, db->buf_pool_dma_ptr);
410 err_out_disable:
411 pci_disable_device(pdev);
412 err_out_free:
413 pci_set_drvdata(pdev, NULL);
414 free_netdev(dev);
415
416 return err;
417 }
418
419
420 static void __devexit uli526x_remove_one (struct pci_dev *pdev)
421 {
422 struct net_device *dev = pci_get_drvdata(pdev);
423 struct uli526x_board_info *db = netdev_priv(dev);
424
425 ULI526X_DBUG(0, "uli526x_remove_one()", 0);
426
427 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
428 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
429 db->desc_pool_dma_ptr);
430 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
431 db->buf_pool_ptr, db->buf_pool_dma_ptr);
432 unregister_netdev(dev);
433 pci_release_regions(pdev);
434 free_netdev(dev); /* free board information */
435 pci_set_drvdata(pdev, NULL);
436 pci_disable_device(pdev);
437 ULI526X_DBUG(0, "uli526x_remove_one() exit", 0);
438 }
439
440
441 /*
442 * Open the interface.
443 * The interface is opened whenever "ifconfig" activates it.
444 */
445
446 static int uli526x_open(struct net_device *dev)
447 {
448 int ret;
449 struct uli526x_board_info *db = netdev_priv(dev);
450
451 ULI526X_DBUG(0, "uli526x_open", 0);
452
453 /* system variable init */
454 db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set;
455 db->tx_packet_cnt = 0;
456 db->rx_avail_cnt = 0;
457 db->link_failed = 1;
458 netif_carrier_off(dev);
459 db->wait_reset = 0;
460
461 db->NIC_capability = 0xf; /* All capability*/
462 db->PHY_reg4 = 0x1e0;
463
464 /* CR6 operation mode decision */
465 db->cr6_data |= ULI526X_TXTH_256;
466 db->cr0_data = CR0_DEFAULT;
467
468 /* Initialize ULI526X board */
469 uli526x_init(dev);
470
471 ret = request_irq(dev->irq, uli526x_interrupt, IRQF_SHARED, dev->name, dev);
472 if (ret)
473 return ret;
474
475 /* Active System Interface */
476 netif_wake_queue(dev);
477
478 /* set and active a timer process */
479 init_timer(&db->timer);
480 db->timer.expires = ULI526X_TIMER_WUT + HZ * 2;
481 db->timer.data = (unsigned long)dev;
482 db->timer.function = uli526x_timer;
483 add_timer(&db->timer);
484
485 return 0;
486 }
487
488
489 /* Initialize ULI526X board
490 * Reset ULI526X board
491 * Initialize TX/Rx descriptor chain structure
492 * Send the set-up frame
493 * Enable Tx/Rx machine
494 */
495
496 static void uli526x_init(struct net_device *dev)
497 {
498 struct uli526x_board_info *db = netdev_priv(dev);
499 unsigned long ioaddr = db->ioaddr;
500 u8 phy_tmp;
501 u8 timeout;
502 u16 phy_value;
503 u16 phy_reg_reset;
504
505
506 ULI526X_DBUG(0, "uli526x_init()", 0);
507
508 /* Reset M526x MAC controller */
509 outl(ULI526X_RESET, ioaddr + DCR0); /* RESET MAC */
510 udelay(100);
511 outl(db->cr0_data, ioaddr + DCR0);
512 udelay(5);
513
514 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
515 db->phy_addr = 1;
516 for(phy_tmp=0;phy_tmp<32;phy_tmp++)
517 {
518 phy_value=phy_read(db->ioaddr,phy_tmp,3,db->chip_id);//peer add
519 if(phy_value != 0xffff&&phy_value!=0)
520 {
521 db->phy_addr = phy_tmp;
522 break;
523 }
524 }
525 if(phy_tmp == 32)
526 pr_warn("Can not find the phy address!!!\n");
527 /* Parser SROM and media mode */
528 db->media_mode = uli526x_media_mode;
529
530 /* phyxcer capability setting */
531 phy_reg_reset = phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id);
532 phy_reg_reset = (phy_reg_reset | 0x8000);
533 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg_reset, db->chip_id);
534
535 /* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management
536 * functions") or phy data sheet for details on phy reset
537 */
538 udelay(500);
539 timeout = 10;
540 while (timeout-- &&
541 phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id) & 0x8000)
542 udelay(100);
543
544 /* Process Phyxcer Media Mode */
545 uli526x_set_phyxcer(db);
546
547 /* Media Mode Process */
548 if ( !(db->media_mode & ULI526X_AUTO) )
549 db->op_mode = db->media_mode; /* Force Mode */
550
551 /* Initialize Transmit/Receive decriptor and CR3/4 */
552 uli526x_descriptor_init(db, ioaddr);
553
554 /* Init CR6 to program M526X operation */
555 update_cr6(db->cr6_data, ioaddr);
556
557 /* Send setup frame */
558 send_filter_frame(dev, netdev_mc_count(dev)); /* M5261/M5263 */
559
560 /* Init CR7, interrupt active bit */
561 db->cr7_data = CR7_DEFAULT;
562 outl(db->cr7_data, ioaddr + DCR7);
563
564 /* Init CR15, Tx jabber and Rx watchdog timer */
565 outl(db->cr15_data, ioaddr + DCR15);
566
567 /* Enable ULI526X Tx/Rx function */
568 db->cr6_data |= CR6_RXSC | CR6_TXSC;
569 update_cr6(db->cr6_data, ioaddr);
570 }
571
572
573 /*
574 * Hardware start transmission.
575 * Send a packet to media from the upper layer.
576 */
577
578 static netdev_tx_t uli526x_start_xmit(struct sk_buff *skb,
579 struct net_device *dev)
580 {
581 struct uli526x_board_info *db = netdev_priv(dev);
582 struct tx_desc *txptr;
583 unsigned long flags;
584
585 ULI526X_DBUG(0, "uli526x_start_xmit", 0);
586
587 /* Resource flag check */
588 netif_stop_queue(dev);
589
590 /* Too large packet check */
591 if (skb->len > MAX_PACKET_SIZE) {
592 netdev_err(dev, "big packet = %d\n", (u16)skb->len);
593 dev_kfree_skb(skb);
594 return NETDEV_TX_OK;
595 }
596
597 spin_lock_irqsave(&db->lock, flags);
598
599 /* No Tx resource check, it never happen nromally */
600 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
601 spin_unlock_irqrestore(&db->lock, flags);
602 netdev_err(dev, "No Tx resource %ld\n", db->tx_packet_cnt);
603 return NETDEV_TX_BUSY;
604 }
605
606 /* Disable NIC interrupt */
607 outl(0, dev->base_addr + DCR7);
608
609 /* transmit this packet */
610 txptr = db->tx_insert_ptr;
611 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
612 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
613
614 /* Point to next transmit free descriptor */
615 db->tx_insert_ptr = txptr->next_tx_desc;
616
617 /* Transmit Packet Process */
618 if ( (db->tx_packet_cnt < TX_DESC_CNT) ) {
619 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
620 db->tx_packet_cnt++; /* Ready to send */
621 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
622 dev->trans_start = jiffies; /* saved time stamp */
623 }
624
625 /* Tx resource check */
626 if ( db->tx_packet_cnt < TX_FREE_DESC_CNT )
627 netif_wake_queue(dev);
628
629 /* Restore CR7 to enable interrupt */
630 spin_unlock_irqrestore(&db->lock, flags);
631 outl(db->cr7_data, dev->base_addr + DCR7);
632
633 /* free this SKB */
634 dev_kfree_skb(skb);
635
636 return NETDEV_TX_OK;
637 }
638
639
640 /*
641 * Stop the interface.
642 * The interface is stopped when it is brought.
643 */
644
645 static int uli526x_stop(struct net_device *dev)
646 {
647 struct uli526x_board_info *db = netdev_priv(dev);
648 unsigned long ioaddr = dev->base_addr;
649
650 ULI526X_DBUG(0, "uli526x_stop", 0);
651
652 /* disable system */
653 netif_stop_queue(dev);
654
655 /* deleted timer */
656 del_timer_sync(&db->timer);
657
658 /* Reset & stop ULI526X board */
659 outl(ULI526X_RESET, ioaddr + DCR0);
660 udelay(5);
661 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
662
663 /* free interrupt */
664 free_irq(dev->irq, dev);
665
666 /* free allocated rx buffer */
667 uli526x_free_rxbuffer(db);
668
669 return 0;
670 }
671
672
673 /*
674 * M5261/M5263 insterrupt handler
675 * receive the packet to upper layer, free the transmitted packet
676 */
677
678 static irqreturn_t uli526x_interrupt(int irq, void *dev_id)
679 {
680 struct net_device *dev = dev_id;
681 struct uli526x_board_info *db = netdev_priv(dev);
682 unsigned long ioaddr = dev->base_addr;
683 unsigned long flags;
684
685 spin_lock_irqsave(&db->lock, flags);
686 outl(0, ioaddr + DCR7);
687
688 /* Got ULI526X status */
689 db->cr5_data = inl(ioaddr + DCR5);
690 outl(db->cr5_data, ioaddr + DCR5);
691 if ( !(db->cr5_data & 0x180c1) ) {
692 /* Restore CR7 to enable interrupt mask */
693 outl(db->cr7_data, ioaddr + DCR7);
694 spin_unlock_irqrestore(&db->lock, flags);
695 return IRQ_HANDLED;
696 }
697
698 /* Check system status */
699 if (db->cr5_data & 0x2000) {
700 /* system bus error happen */
701 ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
702 db->reset_fatal++;
703 db->wait_reset = 1; /* Need to RESET */
704 spin_unlock_irqrestore(&db->lock, flags);
705 return IRQ_HANDLED;
706 }
707
708 /* Received the coming packet */
709 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
710 uli526x_rx_packet(dev, db);
711
712 /* reallocate rx descriptor buffer */
713 if (db->rx_avail_cnt<RX_DESC_CNT)
714 allocate_rx_buffer(db);
715
716 /* Free the transmitted descriptor */
717 if ( db->cr5_data & 0x01)
718 uli526x_free_tx_pkt(dev, db);
719
720 /* Restore CR7 to enable interrupt mask */
721 outl(db->cr7_data, ioaddr + DCR7);
722
723 spin_unlock_irqrestore(&db->lock, flags);
724 return IRQ_HANDLED;
725 }
726
727 #ifdef CONFIG_NET_POLL_CONTROLLER
728 static void uli526x_poll(struct net_device *dev)
729 {
730 /* ISR grabs the irqsave lock, so this should be safe */
731 uli526x_interrupt(dev->irq, dev);
732 }
733 #endif
734
735 /*
736 * Free TX resource after TX complete
737 */
738
739 static void uli526x_free_tx_pkt(struct net_device *dev,
740 struct uli526x_board_info * db)
741 {
742 struct tx_desc *txptr;
743 u32 tdes0;
744
745 txptr = db->tx_remove_ptr;
746 while(db->tx_packet_cnt) {
747 tdes0 = le32_to_cpu(txptr->tdes0);
748 if (tdes0 & 0x80000000)
749 break;
750
751 /* A packet sent completed */
752 db->tx_packet_cnt--;
753 dev->stats.tx_packets++;
754
755 /* Transmit statistic counter */
756 if ( tdes0 != 0x7fffffff ) {
757 dev->stats.collisions += (tdes0 >> 3) & 0xf;
758 dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
759 if (tdes0 & TDES0_ERR_MASK) {
760 dev->stats.tx_errors++;
761 if (tdes0 & 0x0002) { /* UnderRun */
762 db->tx_fifo_underrun++;
763 if ( !(db->cr6_data & CR6_SFT) ) {
764 db->cr6_data = db->cr6_data | CR6_SFT;
765 update_cr6(db->cr6_data, db->ioaddr);
766 }
767 }
768 if (tdes0 & 0x0100)
769 db->tx_excessive_collision++;
770 if (tdes0 & 0x0200)
771 db->tx_late_collision++;
772 if (tdes0 & 0x0400)
773 db->tx_no_carrier++;
774 if (tdes0 & 0x0800)
775 db->tx_loss_carrier++;
776 if (tdes0 & 0x4000)
777 db->tx_jabber_timeout++;
778 }
779 }
780
781 txptr = txptr->next_tx_desc;
782 }/* End of while */
783
784 /* Update TX remove pointer to next */
785 db->tx_remove_ptr = txptr;
786
787 /* Resource available check */
788 if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT )
789 netif_wake_queue(dev); /* Active upper layer, send again */
790 }
791
792
793 /*
794 * Receive the come packet and pass to upper layer
795 */
796
797 static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db)
798 {
799 struct rx_desc *rxptr;
800 struct sk_buff *skb;
801 int rxlen;
802 u32 rdes0;
803
804 rxptr = db->rx_ready_ptr;
805
806 while(db->rx_avail_cnt) {
807 rdes0 = le32_to_cpu(rxptr->rdes0);
808 if (rdes0 & 0x80000000) /* packet owner check */
809 {
810 break;
811 }
812
813 db->rx_avail_cnt--;
814 db->interval_rx_cnt++;
815
816 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
817 if ( (rdes0 & 0x300) != 0x300) {
818 /* A packet without First/Last flag */
819 /* reuse this SKB */
820 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
821 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
822 } else {
823 /* A packet with First/Last flag */
824 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
825
826 /* error summary bit check */
827 if (rdes0 & 0x8000) {
828 /* This is a error packet */
829 dev->stats.rx_errors++;
830 if (rdes0 & 1)
831 dev->stats.rx_fifo_errors++;
832 if (rdes0 & 2)
833 dev->stats.rx_crc_errors++;
834 if (rdes0 & 0x80)
835 dev->stats.rx_length_errors++;
836 }
837
838 if ( !(rdes0 & 0x8000) ||
839 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
840 struct sk_buff *new_skb = NULL;
841
842 skb = rxptr->rx_skb_ptr;
843
844 /* Good packet, send to upper layer */
845 /* Shorst packet used new SKB */
846 if ((rxlen < RX_COPY_SIZE) &&
847 (((new_skb = dev_alloc_skb(rxlen + 2)) != NULL))) {
848 skb = new_skb;
849 /* size less than COPY_SIZE, allocate a rxlen SKB */
850 skb_reserve(skb, 2); /* 16byte align */
851 memcpy(skb_put(skb, rxlen),
852 skb_tail_pointer(rxptr->rx_skb_ptr),
853 rxlen);
854 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
855 } else
856 skb_put(skb, rxlen);
857
858 skb->protocol = eth_type_trans(skb, dev);
859 netif_rx(skb);
860 dev->stats.rx_packets++;
861 dev->stats.rx_bytes += rxlen;
862
863 } else {
864 /* Reuse SKB buffer when the packet is error */
865 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
866 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
867 }
868 }
869
870 rxptr = rxptr->next_rx_desc;
871 }
872
873 db->rx_ready_ptr = rxptr;
874 }
875
876
877 /*
878 * Set ULI526X multicast address
879 */
880
881 static void uli526x_set_filter_mode(struct net_device * dev)
882 {
883 struct uli526x_board_info *db = netdev_priv(dev);
884 unsigned long flags;
885
886 ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
887 spin_lock_irqsave(&db->lock, flags);
888
889 if (dev->flags & IFF_PROMISC) {
890 ULI526X_DBUG(0, "Enable PROM Mode", 0);
891 db->cr6_data |= CR6_PM | CR6_PBF;
892 update_cr6(db->cr6_data, db->ioaddr);
893 spin_unlock_irqrestore(&db->lock, flags);
894 return;
895 }
896
897 if (dev->flags & IFF_ALLMULTI ||
898 netdev_mc_count(dev) > ULI5261_MAX_MULTICAST) {
899 ULI526X_DBUG(0, "Pass all multicast address",
900 netdev_mc_count(dev));
901 db->cr6_data &= ~(CR6_PM | CR6_PBF);
902 db->cr6_data |= CR6_PAM;
903 spin_unlock_irqrestore(&db->lock, flags);
904 return;
905 }
906
907 ULI526X_DBUG(0, "Set multicast address", netdev_mc_count(dev));
908 send_filter_frame(dev, netdev_mc_count(dev)); /* M5261/M5263 */
909 spin_unlock_irqrestore(&db->lock, flags);
910 }
911
912 static void
913 ULi_ethtool_gset(struct uli526x_board_info *db, struct ethtool_cmd *ecmd)
914 {
915 ecmd->supported = (SUPPORTED_10baseT_Half |
916 SUPPORTED_10baseT_Full |
917 SUPPORTED_100baseT_Half |
918 SUPPORTED_100baseT_Full |
919 SUPPORTED_Autoneg |
920 SUPPORTED_MII);
921
922 ecmd->advertising = (ADVERTISED_10baseT_Half |
923 ADVERTISED_10baseT_Full |
924 ADVERTISED_100baseT_Half |
925 ADVERTISED_100baseT_Full |
926 ADVERTISED_Autoneg |
927 ADVERTISED_MII);
928
929
930 ecmd->port = PORT_MII;
931 ecmd->phy_address = db->phy_addr;
932
933 ecmd->transceiver = XCVR_EXTERNAL;
934
935 ethtool_cmd_speed_set(ecmd, SPEED_10);
936 ecmd->duplex = DUPLEX_HALF;
937
938 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
939 {
940 ethtool_cmd_speed_set(ecmd, SPEED_100);
941 }
942 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
943 {
944 ecmd->duplex = DUPLEX_FULL;
945 }
946 if(db->link_failed)
947 {
948 ethtool_cmd_speed_set(ecmd, -1);
949 ecmd->duplex = -1;
950 }
951
952 if (db->media_mode & ULI526X_AUTO)
953 {
954 ecmd->autoneg = AUTONEG_ENABLE;
955 }
956 }
957
958 static void netdev_get_drvinfo(struct net_device *dev,
959 struct ethtool_drvinfo *info)
960 {
961 struct uli526x_board_info *np = netdev_priv(dev);
962
963 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
964 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
965 if (np->pdev)
966 strlcpy(info->bus_info, pci_name(np->pdev),
967 sizeof(info->bus_info));
968 else
969 sprintf(info->bus_info, "EISA 0x%lx %d",
970 dev->base_addr, dev->irq);
971 }
972
973 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) {
974 struct uli526x_board_info *np = netdev_priv(dev);
975
976 ULi_ethtool_gset(np, cmd);
977
978 return 0;
979 }
980
981 static u32 netdev_get_link(struct net_device *dev) {
982 struct uli526x_board_info *np = netdev_priv(dev);
983
984 if(np->link_failed)
985 return 0;
986 else
987 return 1;
988 }
989
990 static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
991 {
992 wol->supported = WAKE_PHY | WAKE_MAGIC;
993 wol->wolopts = 0;
994 }
995
996 static const struct ethtool_ops netdev_ethtool_ops = {
997 .get_drvinfo = netdev_get_drvinfo,
998 .get_settings = netdev_get_settings,
999 .get_link = netdev_get_link,
1000 .get_wol = uli526x_get_wol,
1001 };
1002
1003 /*
1004 * A periodic timer routine
1005 * Dynamic media sense, allocate Rx buffer...
1006 */
1007
1008 static void uli526x_timer(unsigned long data)
1009 {
1010 u32 tmp_cr8;
1011 unsigned char tmp_cr12=0;
1012 struct net_device *dev = (struct net_device *) data;
1013 struct uli526x_board_info *db = netdev_priv(dev);
1014 unsigned long flags;
1015
1016 //ULI526X_DBUG(0, "uli526x_timer()", 0);
1017 spin_lock_irqsave(&db->lock, flags);
1018
1019
1020 /* Dynamic reset ULI526X : system error or transmit time-out */
1021 tmp_cr8 = inl(db->ioaddr + DCR8);
1022 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1023 db->reset_cr8++;
1024 db->wait_reset = 1;
1025 }
1026 db->interval_rx_cnt = 0;
1027
1028 /* TX polling kick monitor */
1029 if ( db->tx_packet_cnt &&
1030 time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_KICK) ) {
1031 outl(0x1, dev->base_addr + DCR1); // Tx polling again
1032
1033 // TX Timeout
1034 if ( time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_TIMEOUT) ) {
1035 db->reset_TXtimeout++;
1036 db->wait_reset = 1;
1037 netdev_err(dev, " Tx timeout - resetting\n");
1038 }
1039 }
1040
1041 if (db->wait_reset) {
1042 ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1043 db->reset_count++;
1044 uli526x_dynamic_reset(dev);
1045 db->timer.expires = ULI526X_TIMER_WUT;
1046 add_timer(&db->timer);
1047 spin_unlock_irqrestore(&db->lock, flags);
1048 return;
1049 }
1050
1051 /* Link status check, Dynamic media type change */
1052 if((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)!=0)
1053 tmp_cr12 = 3;
1054
1055 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1056 /* Link Failed */
1057 ULI526X_DBUG(0, "Link Failed", tmp_cr12);
1058 netif_carrier_off(dev);
1059 netdev_info(dev, "NIC Link is Down\n");
1060 db->link_failed = 1;
1061
1062 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1063 /* AUTO don't need */
1064 if ( !(db->media_mode & 0x8) )
1065 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1066
1067 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1068 if (db->media_mode & ULI526X_AUTO) {
1069 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1070 update_cr6(db->cr6_data, db->ioaddr);
1071 }
1072 } else
1073 if ((tmp_cr12 & 0x3) && db->link_failed) {
1074 ULI526X_DBUG(0, "Link link OK", tmp_cr12);
1075 db->link_failed = 0;
1076
1077 /* Auto Sense Speed */
1078 if ( (db->media_mode & ULI526X_AUTO) &&
1079 uli526x_sense_speed(db) )
1080 db->link_failed = 1;
1081 uli526x_process_mode(db);
1082
1083 if(db->link_failed==0)
1084 {
1085 netdev_info(dev, "NIC Link is Up %d Mbps %s duplex\n",
1086 (db->op_mode == ULI526X_100MHF ||
1087 db->op_mode == ULI526X_100MFD)
1088 ? 100 : 10,
1089 (db->op_mode == ULI526X_10MFD ||
1090 db->op_mode == ULI526X_100MFD)
1091 ? "Full" : "Half");
1092 netif_carrier_on(dev);
1093 }
1094 /* SHOW_MEDIA_TYPE(db->op_mode); */
1095 }
1096 else if(!(tmp_cr12 & 0x3) && db->link_failed)
1097 {
1098 if(db->init==1)
1099 {
1100 netdev_info(dev, "NIC Link is Down\n");
1101 netif_carrier_off(dev);
1102 }
1103 }
1104 db->init=0;
1105
1106 /* Timer active again */
1107 db->timer.expires = ULI526X_TIMER_WUT;
1108 add_timer(&db->timer);
1109 spin_unlock_irqrestore(&db->lock, flags);
1110 }
1111
1112
1113 /*
1114 * Stop ULI526X board
1115 * Free Tx/Rx allocated memory
1116 * Init system variable
1117 */
1118
1119 static void uli526x_reset_prepare(struct net_device *dev)
1120 {
1121 struct uli526x_board_info *db = netdev_priv(dev);
1122
1123 /* Sopt MAC controller */
1124 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1125 update_cr6(db->cr6_data, dev->base_addr);
1126 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1127 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1128
1129 /* Disable upper layer interface */
1130 netif_stop_queue(dev);
1131
1132 /* Free Rx Allocate buffer */
1133 uli526x_free_rxbuffer(db);
1134
1135 /* system variable init */
1136 db->tx_packet_cnt = 0;
1137 db->rx_avail_cnt = 0;
1138 db->link_failed = 1;
1139 db->init=1;
1140 db->wait_reset = 0;
1141 }
1142
1143
1144 /*
1145 * Dynamic reset the ULI526X board
1146 * Stop ULI526X board
1147 * Free Tx/Rx allocated memory
1148 * Reset ULI526X board
1149 * Re-initialize ULI526X board
1150 */
1151
1152 static void uli526x_dynamic_reset(struct net_device *dev)
1153 {
1154 ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
1155
1156 uli526x_reset_prepare(dev);
1157
1158 /* Re-initialize ULI526X board */
1159 uli526x_init(dev);
1160
1161 /* Restart upper layer interface */
1162 netif_wake_queue(dev);
1163 }
1164
1165
1166 #ifdef CONFIG_PM
1167
1168 /*
1169 * Suspend the interface.
1170 */
1171
1172 static int uli526x_suspend(struct pci_dev *pdev, pm_message_t state)
1173 {
1174 struct net_device *dev = pci_get_drvdata(pdev);
1175 pci_power_t power_state;
1176 int err;
1177
1178 ULI526X_DBUG(0, "uli526x_suspend", 0);
1179
1180 if (!netdev_priv(dev))
1181 return 0;
1182
1183 pci_save_state(pdev);
1184
1185 if (!netif_running(dev))
1186 return 0;
1187
1188 netif_device_detach(dev);
1189 uli526x_reset_prepare(dev);
1190
1191 power_state = pci_choose_state(pdev, state);
1192 pci_enable_wake(pdev, power_state, 0);
1193 err = pci_set_power_state(pdev, power_state);
1194 if (err) {
1195 netif_device_attach(dev);
1196 /* Re-initialize ULI526X board */
1197 uli526x_init(dev);
1198 /* Restart upper layer interface */
1199 netif_wake_queue(dev);
1200 }
1201
1202 return err;
1203 }
1204
1205 /*
1206 * Resume the interface.
1207 */
1208
1209 static int uli526x_resume(struct pci_dev *pdev)
1210 {
1211 struct net_device *dev = pci_get_drvdata(pdev);
1212 int err;
1213
1214 ULI526X_DBUG(0, "uli526x_resume", 0);
1215
1216 if (!netdev_priv(dev))
1217 return 0;
1218
1219 pci_restore_state(pdev);
1220
1221 if (!netif_running(dev))
1222 return 0;
1223
1224 err = pci_set_power_state(pdev, PCI_D0);
1225 if (err) {
1226 netdev_warn(dev, "Could not put device into D0\n");
1227 return err;
1228 }
1229
1230 netif_device_attach(dev);
1231 /* Re-initialize ULI526X board */
1232 uli526x_init(dev);
1233 /* Restart upper layer interface */
1234 netif_wake_queue(dev);
1235
1236 return 0;
1237 }
1238
1239 #else /* !CONFIG_PM */
1240
1241 #define uli526x_suspend NULL
1242 #define uli526x_resume NULL
1243
1244 #endif /* !CONFIG_PM */
1245
1246
1247 /*
1248 * free all allocated rx buffer
1249 */
1250
1251 static void uli526x_free_rxbuffer(struct uli526x_board_info * db)
1252 {
1253 ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
1254
1255 /* free allocated rx buffer */
1256 while (db->rx_avail_cnt) {
1257 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1258 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1259 db->rx_avail_cnt--;
1260 }
1261 }
1262
1263
1264 /*
1265 * Reuse the SK buffer
1266 */
1267
1268 static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb)
1269 {
1270 struct rx_desc *rxptr = db->rx_insert_ptr;
1271
1272 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1273 rxptr->rx_skb_ptr = skb;
1274 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1275 skb_tail_pointer(skb),
1276 RX_ALLOC_SIZE,
1277 PCI_DMA_FROMDEVICE));
1278 wmb();
1279 rxptr->rdes0 = cpu_to_le32(0x80000000);
1280 db->rx_avail_cnt++;
1281 db->rx_insert_ptr = rxptr->next_rx_desc;
1282 } else
1283 ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1284 }
1285
1286
1287 /*
1288 * Initialize transmit/Receive descriptor
1289 * Using Chain structure, and allocate Tx/Rx buffer
1290 */
1291
1292 static void uli526x_descriptor_init(struct uli526x_board_info *db, unsigned long ioaddr)
1293 {
1294 struct tx_desc *tmp_tx;
1295 struct rx_desc *tmp_rx;
1296 unsigned char *tmp_buf;
1297 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1298 dma_addr_t tmp_buf_dma;
1299 int i;
1300
1301 ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
1302
1303 /* tx descriptor start pointer */
1304 db->tx_insert_ptr = db->first_tx_desc;
1305 db->tx_remove_ptr = db->first_tx_desc;
1306 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1307
1308 /* rx descriptor start pointer */
1309 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1310 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1311 db->rx_insert_ptr = db->first_rx_desc;
1312 db->rx_ready_ptr = db->first_rx_desc;
1313 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1314
1315 /* Init Transmit chain */
1316 tmp_buf = db->buf_pool_start;
1317 tmp_buf_dma = db->buf_pool_dma_start;
1318 tmp_tx_dma = db->first_tx_desc_dma;
1319 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1320 tmp_tx->tx_buf_ptr = tmp_buf;
1321 tmp_tx->tdes0 = cpu_to_le32(0);
1322 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1323 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1324 tmp_tx_dma += sizeof(struct tx_desc);
1325 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1326 tmp_tx->next_tx_desc = tmp_tx + 1;
1327 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1328 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1329 }
1330 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1331 tmp_tx->next_tx_desc = db->first_tx_desc;
1332
1333 /* Init Receive descriptor chain */
1334 tmp_rx_dma=db->first_rx_desc_dma;
1335 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1336 tmp_rx->rdes0 = cpu_to_le32(0);
1337 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1338 tmp_rx_dma += sizeof(struct rx_desc);
1339 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1340 tmp_rx->next_rx_desc = tmp_rx + 1;
1341 }
1342 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1343 tmp_rx->next_rx_desc = db->first_rx_desc;
1344
1345 /* pre-allocate Rx buffer */
1346 allocate_rx_buffer(db);
1347 }
1348
1349
1350 /*
1351 * Update CR6 value
1352 * Firstly stop ULI526X, then written value and start
1353 */
1354
1355 static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1356 {
1357
1358 outl(cr6_data, ioaddr + DCR6);
1359 udelay(5);
1360 }
1361
1362
1363 /*
1364 * Send a setup frame for M5261/M5263
1365 * This setup frame initialize ULI526X address filter mode
1366 */
1367
1368 #ifdef __BIG_ENDIAN
1369 #define FLT_SHIFT 16
1370 #else
1371 #define FLT_SHIFT 0
1372 #endif
1373
1374 static void send_filter_frame(struct net_device *dev, int mc_cnt)
1375 {
1376 struct uli526x_board_info *db = netdev_priv(dev);
1377 struct netdev_hw_addr *ha;
1378 struct tx_desc *txptr;
1379 u16 * addrptr;
1380 u32 * suptr;
1381 int i;
1382
1383 ULI526X_DBUG(0, "send_filter_frame()", 0);
1384
1385 txptr = db->tx_insert_ptr;
1386 suptr = (u32 *) txptr->tx_buf_ptr;
1387
1388 /* Node address */
1389 addrptr = (u16 *) dev->dev_addr;
1390 *suptr++ = addrptr[0] << FLT_SHIFT;
1391 *suptr++ = addrptr[1] << FLT_SHIFT;
1392 *suptr++ = addrptr[2] << FLT_SHIFT;
1393
1394 /* broadcast address */
1395 *suptr++ = 0xffff << FLT_SHIFT;
1396 *suptr++ = 0xffff << FLT_SHIFT;
1397 *suptr++ = 0xffff << FLT_SHIFT;
1398
1399 /* fit the multicast address */
1400 netdev_for_each_mc_addr(ha, dev) {
1401 addrptr = (u16 *) ha->addr;
1402 *suptr++ = addrptr[0] << FLT_SHIFT;
1403 *suptr++ = addrptr[1] << FLT_SHIFT;
1404 *suptr++ = addrptr[2] << FLT_SHIFT;
1405 }
1406
1407 for (i = netdev_mc_count(dev); i < 14; i++) {
1408 *suptr++ = 0xffff << FLT_SHIFT;
1409 *suptr++ = 0xffff << FLT_SHIFT;
1410 *suptr++ = 0xffff << FLT_SHIFT;
1411 }
1412
1413 /* prepare the setup frame */
1414 db->tx_insert_ptr = txptr->next_tx_desc;
1415 txptr->tdes1 = cpu_to_le32(0x890000c0);
1416
1417 /* Resource Check and Send the setup packet */
1418 if (db->tx_packet_cnt < TX_DESC_CNT) {
1419 /* Resource Empty */
1420 db->tx_packet_cnt++;
1421 txptr->tdes0 = cpu_to_le32(0x80000000);
1422 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1423 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1424 update_cr6(db->cr6_data, dev->base_addr);
1425 dev->trans_start = jiffies;
1426 } else
1427 netdev_err(dev, "No Tx resource - Send_filter_frame!\n");
1428 }
1429
1430
1431 /*
1432 * Allocate rx buffer,
1433 * As possible as allocate maxiumn Rx buffer
1434 */
1435
1436 static void allocate_rx_buffer(struct uli526x_board_info *db)
1437 {
1438 struct rx_desc *rxptr;
1439 struct sk_buff *skb;
1440
1441 rxptr = db->rx_insert_ptr;
1442
1443 while(db->rx_avail_cnt < RX_DESC_CNT) {
1444 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1445 break;
1446 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1447 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1448 skb_tail_pointer(skb),
1449 RX_ALLOC_SIZE,
1450 PCI_DMA_FROMDEVICE));
1451 wmb();
1452 rxptr->rdes0 = cpu_to_le32(0x80000000);
1453 rxptr = rxptr->next_rx_desc;
1454 db->rx_avail_cnt++;
1455 }
1456
1457 db->rx_insert_ptr = rxptr;
1458 }
1459
1460
1461 /*
1462 * Read one word data from the serial ROM
1463 */
1464
1465 static u16 read_srom_word(long ioaddr, int offset)
1466 {
1467 int i;
1468 u16 srom_data = 0;
1469 long cr9_ioaddr = ioaddr + DCR9;
1470
1471 outl(CR9_SROM_READ, cr9_ioaddr);
1472 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1473
1474 /* Send the Read Command 110b */
1475 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1476 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1477 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1478
1479 /* Send the offset */
1480 for (i = 5; i >= 0; i--) {
1481 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1482 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1483 }
1484
1485 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1486
1487 for (i = 16; i > 0; i--) {
1488 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1489 udelay(5);
1490 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1491 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1492 udelay(5);
1493 }
1494
1495 outl(CR9_SROM_READ, cr9_ioaddr);
1496 return srom_data;
1497 }
1498
1499
1500 /*
1501 * Auto sense the media mode
1502 */
1503
1504 static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1505 {
1506 u8 ErrFlag = 0;
1507 u16 phy_mode;
1508
1509 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1510 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1511
1512 if ( (phy_mode & 0x24) == 0x24 ) {
1513
1514 phy_mode = ((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)<<7);
1515 if(phy_mode&0x8000)
1516 phy_mode = 0x8000;
1517 else if(phy_mode&0x4000)
1518 phy_mode = 0x4000;
1519 else if(phy_mode&0x2000)
1520 phy_mode = 0x2000;
1521 else
1522 phy_mode = 0x1000;
1523
1524 switch (phy_mode) {
1525 case 0x1000: db->op_mode = ULI526X_10MHF; break;
1526 case 0x2000: db->op_mode = ULI526X_10MFD; break;
1527 case 0x4000: db->op_mode = ULI526X_100MHF; break;
1528 case 0x8000: db->op_mode = ULI526X_100MFD; break;
1529 default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break;
1530 }
1531 } else {
1532 db->op_mode = ULI526X_10MHF;
1533 ULI526X_DBUG(0, "Link Failed :", phy_mode);
1534 ErrFlag = 1;
1535 }
1536
1537 return ErrFlag;
1538 }
1539
1540
1541 /*
1542 * Set 10/100 phyxcer capability
1543 * AUTO mode : phyxcer register4 is NIC capability
1544 * Force mode: phyxcer register4 is the force media
1545 */
1546
1547 static void uli526x_set_phyxcer(struct uli526x_board_info *db)
1548 {
1549 u16 phy_reg;
1550
1551 /* Phyxcer capability setting */
1552 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1553
1554 if (db->media_mode & ULI526X_AUTO) {
1555 /* AUTO Mode */
1556 phy_reg |= db->PHY_reg4;
1557 } else {
1558 /* Force Mode */
1559 switch(db->media_mode) {
1560 case ULI526X_10MHF: phy_reg |= 0x20; break;
1561 case ULI526X_10MFD: phy_reg |= 0x40; break;
1562 case ULI526X_100MHF: phy_reg |= 0x80; break;
1563 case ULI526X_100MFD: phy_reg |= 0x100; break;
1564 }
1565
1566 }
1567
1568 /* Write new capability to Phyxcer Reg4 */
1569 if ( !(phy_reg & 0x01e0)) {
1570 phy_reg|=db->PHY_reg4;
1571 db->media_mode|=ULI526X_AUTO;
1572 }
1573 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1574
1575 /* Restart Auto-Negotiation */
1576 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1577 udelay(50);
1578 }
1579
1580
1581 /*
1582 * Process op-mode
1583 AUTO mode : PHY controller in Auto-negotiation Mode
1584 * Force mode: PHY controller in force mode with HUB
1585 * N-way force capability with SWITCH
1586 */
1587
1588 static void uli526x_process_mode(struct uli526x_board_info *db)
1589 {
1590 u16 phy_reg;
1591
1592 /* Full Duplex Mode Check */
1593 if (db->op_mode & 0x4)
1594 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1595 else
1596 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1597
1598 update_cr6(db->cr6_data, db->ioaddr);
1599
1600 /* 10/100M phyxcer force mode need */
1601 if ( !(db->media_mode & 0x8)) {
1602 /* Forece Mode */
1603 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1604 if ( !(phy_reg & 0x1) ) {
1605 /* parter without N-Way capability */
1606 phy_reg = 0x0;
1607 switch(db->op_mode) {
1608 case ULI526X_10MHF: phy_reg = 0x0; break;
1609 case ULI526X_10MFD: phy_reg = 0x100; break;
1610 case ULI526X_100MHF: phy_reg = 0x2000; break;
1611 case ULI526X_100MFD: phy_reg = 0x2100; break;
1612 }
1613 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
1614 }
1615 }
1616 }
1617
1618
1619 /*
1620 * Write a word to Phy register
1621 */
1622
1623 static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id)
1624 {
1625 u16 i;
1626 unsigned long ioaddr;
1627
1628 if(chip_id == PCI_ULI5263_ID)
1629 {
1630 phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
1631 return;
1632 }
1633 /* M5261/M5263 Chip */
1634 ioaddr = iobase + DCR9;
1635
1636 /* Send 33 synchronization clock to Phy controller */
1637 for (i = 0; i < 35; i++)
1638 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1639
1640 /* Send start command(01) to Phy */
1641 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1642 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1643
1644 /* Send write command(01) to Phy */
1645 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1646 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1647
1648 /* Send Phy address */
1649 for (i = 0x10; i > 0; i = i >> 1)
1650 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1651
1652 /* Send register address */
1653 for (i = 0x10; i > 0; i = i >> 1)
1654 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1655
1656 /* written trasnition */
1657 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1658 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1659
1660 /* Write a word data to PHY controller */
1661 for ( i = 0x8000; i > 0; i >>= 1)
1662 phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1663
1664 }
1665
1666
1667 /*
1668 * Read a word data from phy register
1669 */
1670
1671 static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1672 {
1673 int i;
1674 u16 phy_data;
1675 unsigned long ioaddr;
1676
1677 if(chip_id == PCI_ULI5263_ID)
1678 return phy_readby_cr10(iobase, phy_addr, offset);
1679 /* M5261/M5263 Chip */
1680 ioaddr = iobase + DCR9;
1681
1682 /* Send 33 synchronization clock to Phy controller */
1683 for (i = 0; i < 35; i++)
1684 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1685
1686 /* Send start command(01) to Phy */
1687 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1688 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1689
1690 /* Send read command(10) to Phy */
1691 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1692 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1693
1694 /* Send Phy address */
1695 for (i = 0x10; i > 0; i = i >> 1)
1696 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1697
1698 /* Send register address */
1699 for (i = 0x10; i > 0; i = i >> 1)
1700 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1701
1702 /* Skip transition state */
1703 phy_read_1bit(ioaddr, chip_id);
1704
1705 /* read 16bit data */
1706 for (phy_data = 0, i = 0; i < 16; i++) {
1707 phy_data <<= 1;
1708 phy_data |= phy_read_1bit(ioaddr, chip_id);
1709 }
1710
1711 return phy_data;
1712 }
1713
1714 static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
1715 {
1716 unsigned long ioaddr,cr10_value;
1717
1718 ioaddr = iobase + DCR10;
1719 cr10_value = phy_addr;
1720 cr10_value = (cr10_value<<5) + offset;
1721 cr10_value = (cr10_value<<16) + 0x08000000;
1722 outl(cr10_value,ioaddr);
1723 udelay(1);
1724 while(1)
1725 {
1726 cr10_value = inl(ioaddr);
1727 if(cr10_value&0x10000000)
1728 break;
1729 }
1730 return cr10_value & 0x0ffff;
1731 }
1732
1733 static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data)
1734 {
1735 unsigned long ioaddr,cr10_value;
1736
1737 ioaddr = iobase + DCR10;
1738 cr10_value = phy_addr;
1739 cr10_value = (cr10_value<<5) + offset;
1740 cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
1741 outl(cr10_value,ioaddr);
1742 udelay(1);
1743 }
1744 /*
1745 * Write one bit data to Phy Controller
1746 */
1747
1748 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
1749 {
1750 outl(phy_data , ioaddr); /* MII Clock Low */
1751 udelay(1);
1752 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1753 udelay(1);
1754 outl(phy_data , ioaddr); /* MII Clock Low */
1755 udelay(1);
1756 }
1757
1758
1759 /*
1760 * Read one bit phy data from PHY controller
1761 */
1762
1763 static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
1764 {
1765 u16 phy_data;
1766
1767 outl(0x50000 , ioaddr);
1768 udelay(1);
1769 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1770 outl(0x40000 , ioaddr);
1771 udelay(1);
1772
1773 return phy_data;
1774 }
1775
1776
1777 static DEFINE_PCI_DEVICE_TABLE(uli526x_pci_tbl) = {
1778 { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID },
1779 { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID },
1780 { 0, }
1781 };
1782 MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl);
1783
1784
1785 static struct pci_driver uli526x_driver = {
1786 .name = "uli526x",
1787 .id_table = uli526x_pci_tbl,
1788 .probe = uli526x_init_one,
1789 .remove = __devexit_p(uli526x_remove_one),
1790 .suspend = uli526x_suspend,
1791 .resume = uli526x_resume,
1792 };
1793
1794 MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
1795 MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
1796 MODULE_LICENSE("GPL");
1797
1798 module_param(debug, int, 0644);
1799 module_param(mode, int, 0);
1800 module_param(cr6set, int, 0);
1801 MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)");
1802 MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1803
1804 /* Description:
1805 * when user used insmod to add module, system invoked init_module()
1806 * to register the services.
1807 */
1808
1809 static int __init uli526x_init_module(void)
1810 {
1811
1812 pr_info("%s\n", version);
1813 printed_version = 1;
1814
1815 ULI526X_DBUG(0, "init_module() ", debug);
1816
1817 if (debug)
1818 uli526x_debug = debug; /* set debug flag */
1819 if (cr6set)
1820 uli526x_cr6_user_set = cr6set;
1821
1822 switch (mode) {
1823 case ULI526X_10MHF:
1824 case ULI526X_100MHF:
1825 case ULI526X_10MFD:
1826 case ULI526X_100MFD:
1827 uli526x_media_mode = mode;
1828 break;
1829 default:
1830 uli526x_media_mode = ULI526X_AUTO;
1831 break;
1832 }
1833
1834 return pci_register_driver(&uli526x_driver);
1835 }
1836
1837
1838 /*
1839 * Description:
1840 * when user used rmmod to delete module, system invoked clean_module()
1841 * to un-register all registered services.
1842 */
1843
1844 static void __exit uli526x_cleanup_module(void)
1845 {
1846 ULI526X_DBUG(0, "uli526x_clean_module() ", debug);
1847 pci_unregister_driver(&uli526x_driver);
1848 }
1849
1850 module_init(uli526x_init_module);
1851 module_exit(uli526x_cleanup_module);