drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c

   1 /*******************************************************************************
   2   This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   3   DWC Ether MAC 10/100/1000 Universal version 3.41a  has been used for
   4   developing this code.
   5
   6   This only implements the mac core functions for this chip.
   7
   8   Copyright (C) 2007-2009  STMicroelectronics Ltd
   9
  10   This program is free software; you can redistribute it and/or modify it
  11   under the terms and conditions of the GNU General Public License,
  12   version 2, as published by the Free Software Foundation.
  13
  14   This program is distributed in the hope it will be useful, but WITHOUT
  15   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17   more details.
  18
  19   You should have received a copy of the GNU General Public License along with
  20   this program; if not, write to the Free Software Foundation, Inc.,
  21   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  22
  23   The full GNU General Public License is included in this distribution in
  24   the file called "COPYING".
  25
  26   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  27 *******************************************************************************/
  28
  29 #include <linux/crc32.h>
  30 #include <linux/slab.h>
  31 #include <asm/io.h>
  32 #include "dwmac1000.h"
  33
  34 static void dwmac1000_core_init(void __iomem *ioaddr)
  35 {
  36         u32 value = readl(ioaddr + GMAC_CONTROL);
  37         value |= GMAC_CORE_INIT;
  38         writel(value, ioaddr + GMAC_CONTROL);
  39
  40         /* Mask GMAC interrupts */
  41         writel(0x207, ioaddr + GMAC_INT_MASK);
  42
  43 #ifdef STMMAC_VLAN_TAG_USED
  44         /* Tag detection without filtering */
  45         writel(0x0, ioaddr + GMAC_VLAN_TAG);
  46 #endif
  47 }
  48
  49 static int dwmac1000_rx_coe_supported(void __iomem *ioaddr)
  50 {
  51         u32 value = readl(ioaddr + GMAC_CONTROL);
  52
  53         value |= GMAC_CONTROL_IPC;
  54         writel(value, ioaddr + GMAC_CONTROL);
  55
  56         value = readl(ioaddr + GMAC_CONTROL);
  57
  58         return !!(value & GMAC_CONTROL_IPC);
  59 }
  60
  61 static void dwmac1000_dump_regs(void __iomem *ioaddr)
  62 {
  63         int i;
  64         pr_info("\tDWMAC1000 regs (base addr = 0x%p)\n", ioaddr);
  65
  66         for (i = 0; i < 55; i++) {
  67                 int offset = i * 4;
  68                 pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
  69                         offset, readl(ioaddr + offset));
  70         }
  71 }
  72
  73 static void dwmac1000_set_umac_addr(void __iomem *ioaddr, unsigned char *addr,
  74                                 unsigned int reg_n)
  75 {
  76         stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
  77                                 GMAC_ADDR_LOW(reg_n));
  78 }
  79
  80 static void dwmac1000_get_umac_addr(void __iomem *ioaddr, unsigned char *addr,
  81                                 unsigned int reg_n)
  82 {
  83         stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
  84                                 GMAC_ADDR_LOW(reg_n));
  85 }
  86
  87 static void dwmac1000_set_filter(struct net_device *dev)
  88 {
  89         void __iomem *ioaddr = (void __iomem *) dev->base_addr;
  90         unsigned int value = 0;
  91
  92         CHIP_DBG(KERN_INFO "%s: # mcasts %d, # unicast %d\n",
  93                  __func__, netdev_mc_count(dev), netdev_uc_count(dev));
  94
  95         if (dev->flags & IFF_PROMISC)
  96                 value = GMAC_FRAME_FILTER_PR;
  97         else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
  98                    || (dev->flags & IFF_ALLMULTI)) {
  99                 value = GMAC_FRAME_FILTER_PM;   /* pass all multi */
 100                 writel(0xffffffff, ioaddr + GMAC_HASH_HIGH);
 101                 writel(0xffffffff, ioaddr + GMAC_HASH_LOW);
 102         } else if (!netdev_mc_empty(dev)) {
 103                 u32 mc_filter[2];
 104                 struct netdev_hw_addr *ha;
 105
 106                 /* Hash filter for multicast */
 107                 value = GMAC_FRAME_FILTER_HMC;
 108
 109                 memset(mc_filter, 0, sizeof(mc_filter));
 110                 netdev_for_each_mc_addr(ha, dev) {
 111                         /* The upper 6 bits of the calculated CRC are used to
 112                            index the contens of the hash table */
 113                         int bit_nr =
 114                             bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26;
 115                         /* The most significant bit determines the register to
 116                          * use (H/L) while the other 5 bits determine the bit
 117                          * within the register. */
 118                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
 119                 }
 120                 writel(mc_filter[0], ioaddr + GMAC_HASH_LOW);
 121                 writel(mc_filter[1], ioaddr + GMAC_HASH_HIGH);
 122         }
 123
 124         /* Handle multiple unicast addresses (perfect filtering)*/
 125         if (netdev_uc_count(dev) > GMAC_MAX_UNICAST_ADDRESSES)
 126                 /* Switch to promiscuous mode is more than 16 addrs
 127                    are required */
 128                 value |= GMAC_FRAME_FILTER_PR;
 129         else {
 130                 int reg = 1;
 131                 struct netdev_hw_addr *ha;
 132
 133                 netdev_for_each_uc_addr(ha, dev) {
 134                         dwmac1000_set_umac_addr(ioaddr, ha->addr, reg);
 135                         reg++;
 136                 }
 137         }
 138
 139 #ifdef FRAME_FILTER_DEBUG
 140         /* Enable Receive all mode (to debug filtering_fail errors) */
 141         value |= GMAC_FRAME_FILTER_RA;
 142 #endif
 143         writel(value, ioaddr + GMAC_FRAME_FILTER);
 144
 145         CHIP_DBG(KERN_INFO "\tFrame Filter reg: 0x%08x\n\tHash regs: "
 146             "HI 0x%08x, LO 0x%08x\n", readl(ioaddr + GMAC_FRAME_FILTER),
 147             readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW));
 148 }
 149
 150 static void dwmac1000_flow_ctrl(void __iomem *ioaddr, unsigned int duplex,
 151                            unsigned int fc, unsigned int pause_time)
 152 {
 153         unsigned int flow = 0;
 154
 155         CHIP_DBG(KERN_DEBUG "GMAC Flow-Control:\n");
 156         if (fc & FLOW_RX) {
 157                 CHIP_DBG(KERN_DEBUG "\tReceive Flow-Control ON\n");
 158                 flow |= GMAC_FLOW_CTRL_RFE;
 159         }
 160         if (fc & FLOW_TX) {
 161                 CHIP_DBG(KERN_DEBUG "\tTransmit Flow-Control ON\n");
 162                 flow |= GMAC_FLOW_CTRL_TFE;
 163         }
 164
 165         if (duplex) {
 166                 CHIP_DBG(KERN_DEBUG "\tduplex mode: PAUSE %d\n", pause_time);
 167                 flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
 168         }
 169
 170         writel(flow, ioaddr + GMAC_FLOW_CTRL);
 171 }
 172
 173 static void dwmac1000_pmt(void __iomem *ioaddr, unsigned long mode)
 174 {
 175         unsigned int pmt = 0;
 176
 177         if (mode & WAKE_MAGIC) {
 178                 CHIP_DBG(KERN_DEBUG "GMAC: WOL Magic frame\n");
 179                 pmt |= power_down | magic_pkt_en;
 180         }
 181         if (mode & WAKE_UCAST) {
 182                 CHIP_DBG(KERN_DEBUG "GMAC: WOL on global unicast\n");
 183                 pmt |= global_unicast;
 184         }
 185
 186         writel(pmt, ioaddr + GMAC_PMT);
 187 }
 188
 189
 190 static void dwmac1000_irq_status(void __iomem *ioaddr)
 191 {
 192         u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
 193
 194         /* Not used events (e.g. MMC interrupts) are not handled. */
 195         if ((intr_status & mmc_tx_irq))
 196                 CHIP_DBG(KERN_DEBUG "GMAC: MMC tx interrupt: 0x%08x\n",
 197                     readl(ioaddr + GMAC_MMC_TX_INTR));
 198         if (unlikely(intr_status & mmc_rx_irq))
 199                 CHIP_DBG(KERN_DEBUG "GMAC: MMC rx interrupt: 0x%08x\n",
 200                     readl(ioaddr + GMAC_MMC_RX_INTR));
 201         if (unlikely(intr_status & mmc_rx_csum_offload_irq))
 202                 CHIP_DBG(KERN_DEBUG "GMAC: MMC rx csum offload: 0x%08x\n",
 203                     readl(ioaddr + GMAC_MMC_RX_CSUM_OFFLOAD));
 204         if (unlikely(intr_status & pmt_irq)) {
 205                 CHIP_DBG(KERN_DEBUG "GMAC: received Magic frame\n");
 206                 /* clear the PMT bits 5 and 6 by reading the PMT
 207                  * status register. */
 208                 readl(ioaddr + GMAC_PMT);
 209         }
 210 }
 211
 212 static const struct stmmac_ops dwmac1000_ops = {
 213         .core_init = dwmac1000_core_init,
 214         .rx_coe = dwmac1000_rx_coe_supported,
 215         .dump_regs = dwmac1000_dump_regs,
 216         .host_irq_status = dwmac1000_irq_status,
 217         .set_filter = dwmac1000_set_filter,
 218         .flow_ctrl = dwmac1000_flow_ctrl,
 219         .pmt = dwmac1000_pmt,
 220         .set_umac_addr = dwmac1000_set_umac_addr,
 221         .get_umac_addr = dwmac1000_get_umac_addr,
 222 };
 223
 224 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr)
 225 {
 226         struct mac_device_info *mac;
 227         u32 hwid = readl(ioaddr + GMAC_VERSION);
 228
 229         mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
 230         if (!mac)
 231                 return NULL;
 232
 233         mac->mac = &dwmac1000_ops;
 234         mac->dma = &dwmac1000_dma_ops;
 235
 236         mac->link.port = GMAC_CONTROL_PS;
 237         mac->link.duplex = GMAC_CONTROL_DM;
 238         mac->link.speed = GMAC_CONTROL_FES;
 239         mac->mii.addr = GMAC_MII_ADDR;
 240         mac->mii.data = GMAC_MII_DATA;
 241         mac->synopsys_uid = hwid;
 242
 243         return mac;
 244 }