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OMAPDSS: VENC: fix NULL pointer dereference in DSS2 VENC sysfs debug attr on OMAP4
[zen-stable.git] / drivers / net / wireless / iwlegacy / 3945.c
blobc80eb9b315517621f41aa90b58ba8c4c6b8a896c
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/delay.h>
34 #include <linux/sched.h>
35 #include <linux/skbuff.h>
36 #include <linux/netdevice.h>
37 #include <linux/firmware.h>
38 #include <linux/etherdevice.h>
39 #include <asm/unaligned.h>
40 #include <net/mac80211.h>
41
42 #include "common.h"
43 #include "3945.h"
44
45 /* Send led command */
46 static int
47 il3945_send_led_cmd(struct il_priv *il, struct il_led_cmd *led_cmd)
48 {
49 struct il_host_cmd cmd = {
50 .id = C_LEDS,
51 .len = sizeof(struct il_led_cmd),
52 .data = led_cmd,
53 .flags = CMD_ASYNC,
54 .callback = NULL,
55 };
56
57 return il_send_cmd(il, &cmd);
58 }
59
60 const struct il_led_ops il3945_led_ops = {
61 .cmd = il3945_send_led_cmd,
62 };
63
64 #define IL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
65 [RATE_##r##M_IDX] = { RATE_##r##M_PLCP, \
66 RATE_##r##M_IEEE, \
67 RATE_##ip##M_IDX, \
68 RATE_##in##M_IDX, \
69 RATE_##rp##M_IDX, \
70 RATE_##rn##M_IDX, \
71 RATE_##pp##M_IDX, \
72 RATE_##np##M_IDX, \
73 RATE_##r##M_IDX_TBL, \
74 RATE_##ip##M_IDX_TBL }
75
76 /*
77 * Parameter order:
78 * rate, prev rate, next rate, prev tgg rate, next tgg rate
79 *
80 * If there isn't a valid next or previous rate then INV is used which
81 * maps to RATE_INVALID
82 *
83 */
84 const struct il3945_rate_info il3945_rates[RATE_COUNT_3945] = {
85 IL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
86 IL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
87 IL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
88 IL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
89 IL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
90 IL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
91 IL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
92 IL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
93 IL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
94 IL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
95 IL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
96 IL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV), /* 54mbps */
97 };
98
99 static inline u8
100 il3945_get_prev_ieee_rate(u8 rate_idx)
101 {
102 u8 rate = il3945_rates[rate_idx].prev_ieee;
103
104 if (rate == RATE_INVALID)
105 rate = rate_idx;
106 return rate;
107 }
108
109 /* 1 = enable the il3945_disable_events() function */
110 #define IL_EVT_DISABLE (0)
111 #define IL_EVT_DISABLE_SIZE (1532/32)
112
113 /**
114 * il3945_disable_events - Disable selected events in uCode event log
115 *
116 * Disable an event by writing "1"s into "disable"
117 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
118 * Default values of 0 enable uCode events to be logged.
119 * Use for only special debugging. This function is just a placeholder as-is,
120 * you'll need to provide the special bits! ...
121 * ... and set IL_EVT_DISABLE to 1. */
122 void
123 il3945_disable_events(struct il_priv *il)
124 {
125 int i;
126 u32 base; /* SRAM address of event log header */
127 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
128 u32 array_size; /* # of u32 entries in array */
129 static const u32 evt_disable[IL_EVT_DISABLE_SIZE] = {
130 0x00000000, /* 31 - 0 Event id numbers */
131 0x00000000, /* 63 - 32 */
132 0x00000000, /* 95 - 64 */
133 0x00000000, /* 127 - 96 */
134 0x00000000, /* 159 - 128 */
135 0x00000000, /* 191 - 160 */
136 0x00000000, /* 223 - 192 */
137 0x00000000, /* 255 - 224 */
138 0x00000000, /* 287 - 256 */
139 0x00000000, /* 319 - 288 */
140 0x00000000, /* 351 - 320 */
141 0x00000000, /* 383 - 352 */
142 0x00000000, /* 415 - 384 */
143 0x00000000, /* 447 - 416 */
144 0x00000000, /* 479 - 448 */
145 0x00000000, /* 511 - 480 */
146 0x00000000, /* 543 - 512 */
147 0x00000000, /* 575 - 544 */
148 0x00000000, /* 607 - 576 */
149 0x00000000, /* 639 - 608 */
150 0x00000000, /* 671 - 640 */
151 0x00000000, /* 703 - 672 */
152 0x00000000, /* 735 - 704 */
153 0x00000000, /* 767 - 736 */
154 0x00000000, /* 799 - 768 */
155 0x00000000, /* 831 - 800 */
156 0x00000000, /* 863 - 832 */
157 0x00000000, /* 895 - 864 */
158 0x00000000, /* 927 - 896 */
159 0x00000000, /* 959 - 928 */
160 0x00000000, /* 991 - 960 */
161 0x00000000, /* 1023 - 992 */
162 0x00000000, /* 1055 - 1024 */
163 0x00000000, /* 1087 - 1056 */
164 0x00000000, /* 1119 - 1088 */
165 0x00000000, /* 1151 - 1120 */
166 0x00000000, /* 1183 - 1152 */
167 0x00000000, /* 1215 - 1184 */
168 0x00000000, /* 1247 - 1216 */
169 0x00000000, /* 1279 - 1248 */
170 0x00000000, /* 1311 - 1280 */
171 0x00000000, /* 1343 - 1312 */
172 0x00000000, /* 1375 - 1344 */
173 0x00000000, /* 1407 - 1376 */
174 0x00000000, /* 1439 - 1408 */
175 0x00000000, /* 1471 - 1440 */
176 0x00000000, /* 1503 - 1472 */
177 };
178
179 base = le32_to_cpu(il->card_alive.log_event_table_ptr);
180 if (!il3945_hw_valid_rtc_data_addr(base)) {
181 IL_ERR("Invalid event log pointer 0x%08X\n", base);
182 return;
183 }
184
185 disable_ptr = il_read_targ_mem(il, base + (4 * sizeof(u32)));
186 array_size = il_read_targ_mem(il, base + (5 * sizeof(u32)));
187
188 if (IL_EVT_DISABLE && array_size == IL_EVT_DISABLE_SIZE) {
189 D_INFO("Disabling selected uCode log events at 0x%x\n",
190 disable_ptr);
191 for (i = 0; i < IL_EVT_DISABLE_SIZE; i++)
192 il_write_targ_mem(il, disable_ptr + (i * sizeof(u32)),
193 evt_disable[i]);
194
195 } else {
196 D_INFO("Selected uCode log events may be disabled\n");
197 D_INFO(" by writing \"1\"s into disable bitmap\n");
198 D_INFO(" in SRAM at 0x%x, size %d u32s\n", disable_ptr,
199 array_size);
200 }
201
202 }
203
204 static int
205 il3945_hwrate_to_plcp_idx(u8 plcp)
206 {
207 int idx;
208
209 for (idx = 0; idx < RATE_COUNT_3945; idx++)
210 if (il3945_rates[idx].plcp == plcp)
211 return idx;
212 return -1;
213 }
214
215 #ifdef CONFIG_IWLEGACY_DEBUG
216 #define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
217
218 static const char *
219 il3945_get_tx_fail_reason(u32 status)
220 {
221 switch (status & TX_STATUS_MSK) {
222 case TX_3945_STATUS_SUCCESS:
223 return "SUCCESS";
224 TX_STATUS_ENTRY(SHORT_LIMIT);
225 TX_STATUS_ENTRY(LONG_LIMIT);
226 TX_STATUS_ENTRY(FIFO_UNDERRUN);
227 TX_STATUS_ENTRY(MGMNT_ABORT);
228 TX_STATUS_ENTRY(NEXT_FRAG);
229 TX_STATUS_ENTRY(LIFE_EXPIRE);
230 TX_STATUS_ENTRY(DEST_PS);
231 TX_STATUS_ENTRY(ABORTED);
232 TX_STATUS_ENTRY(BT_RETRY);
233 TX_STATUS_ENTRY(STA_INVALID);
234 TX_STATUS_ENTRY(FRAG_DROPPED);
235 TX_STATUS_ENTRY(TID_DISABLE);
236 TX_STATUS_ENTRY(FRAME_FLUSHED);
237 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
238 TX_STATUS_ENTRY(TX_LOCKED);
239 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
240 }
241
242 return "UNKNOWN";
243 }
244 #else
245 static inline const char *
246 il3945_get_tx_fail_reason(u32 status)
247 {
248 return "";
249 }
250 #endif
251
252 /*
253 * get ieee prev rate from rate scale table.
254 * for A and B mode we need to overright prev
255 * value
256 */
257 int
258 il3945_rs_next_rate(struct il_priv *il, int rate)
259 {
260 int next_rate = il3945_get_prev_ieee_rate(rate);
261
262 switch (il->band) {
263 case IEEE80211_BAND_5GHZ:
264 if (rate == RATE_12M_IDX)
265 next_rate = RATE_9M_IDX;
266 else if (rate == RATE_6M_IDX)
267 next_rate = RATE_6M_IDX;
268 break;
269 case IEEE80211_BAND_2GHZ:
270 if (!(il->_3945.sta_supp_rates & IL_OFDM_RATES_MASK) &&
271 il_is_associated(il)) {
272 if (rate == RATE_11M_IDX)
273 next_rate = RATE_5M_IDX;
274 }
275 break;
276
277 default:
278 break;
279 }
280
281 return next_rate;
282 }
283
284 /**
285 * il3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
286 *
287 * When FW advances 'R' idx, all entries between old and new 'R' idx
288 * need to be reclaimed. As result, some free space forms. If there is
289 * enough free space (> low mark), wake the stack that feeds us.
290 */
291 static void
292 il3945_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx)
293 {
294 struct il_tx_queue *txq = &il->txq[txq_id];
295 struct il_queue *q = &txq->q;
296 struct il_tx_info *tx_info;
297
298 BUG_ON(txq_id == IL39_CMD_QUEUE_NUM);
299
300 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
301 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
302
303 tx_info = &txq->txb[txq->q.read_ptr];
304 ieee80211_tx_status_irqsafe(il->hw, tx_info->skb);
305 tx_info->skb = NULL;
306 il->cfg->ops->lib->txq_free_tfd(il, txq);
307 }
308
309 if (il_queue_space(q) > q->low_mark && txq_id >= 0 &&
310 txq_id != IL39_CMD_QUEUE_NUM && il->mac80211_registered)
311 il_wake_queue(il, txq);
312 }
313
314 /**
315 * il3945_hdl_tx - Handle Tx response
316 */
317 static void
318 il3945_hdl_tx(struct il_priv *il, struct il_rx_buf *rxb)
319 {
320 struct il_rx_pkt *pkt = rxb_addr(rxb);
321 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
322 int txq_id = SEQ_TO_QUEUE(sequence);
323 int idx = SEQ_TO_IDX(sequence);
324 struct il_tx_queue *txq = &il->txq[txq_id];
325 struct ieee80211_tx_info *info;
326 struct il3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
327 u32 status = le32_to_cpu(tx_resp->status);
328 int rate_idx;
329 int fail;
330
331 if (idx >= txq->q.n_bd || il_queue_used(&txq->q, idx) == 0) {
332 IL_ERR("Read idx for DMA queue txq_id (%d) idx %d "
333 "is out of range [0-%d] %d %d\n", txq_id, idx,
334 txq->q.n_bd, txq->q.write_ptr, txq->q.read_ptr);
335 return;
336 }
337
338 txq->time_stamp = jiffies;
339 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
340 ieee80211_tx_info_clear_status(info);
341
342 /* Fill the MRR chain with some info about on-chip retransmissions */
343 rate_idx = il3945_hwrate_to_plcp_idx(tx_resp->rate);
344 if (info->band == IEEE80211_BAND_5GHZ)
345 rate_idx -= IL_FIRST_OFDM_RATE;
346
347 fail = tx_resp->failure_frame;
348
349 info->status.rates[0].idx = rate_idx;
350 info->status.rates[0].count = fail + 1; /* add final attempt */
351
352 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
353 info->flags |=
354 ((status & TX_STATUS_MSK) ==
355 TX_STATUS_SUCCESS) ? IEEE80211_TX_STAT_ACK : 0;
356
357 D_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n", txq_id,
358 il3945_get_tx_fail_reason(status), status, tx_resp->rate,
359 tx_resp->failure_frame);
360
361 D_TX_REPLY("Tx queue reclaim %d\n", idx);
362 il3945_tx_queue_reclaim(il, txq_id, idx);
363
364 if (status & TX_ABORT_REQUIRED_MSK)
365 IL_ERR("TODO: Implement Tx ABORT REQUIRED!!!\n");
366 }
367
368 /*****************************************************************************
369 *
370 * Intel PRO/Wireless 3945ABG/BG Network Connection
371 *
372 * RX handler implementations
373 *
374 *****************************************************************************/
375 #ifdef CONFIG_IWLEGACY_DEBUGFS
376 static void
377 il3945_accumulative_stats(struct il_priv *il, __le32 * stats)
378 {
379 int i;
380 __le32 *prev_stats;
381 u32 *accum_stats;
382 u32 *delta, *max_delta;
383
384 prev_stats = (__le32 *) &il->_3945.stats;
385 accum_stats = (u32 *) &il->_3945.accum_stats;
386 delta = (u32 *) &il->_3945.delta_stats;
387 max_delta = (u32 *) &il->_3945.max_delta;
388
389 for (i = sizeof(__le32); i < sizeof(struct il3945_notif_stats);
390 i +=
391 sizeof(__le32), stats++, prev_stats++, delta++, max_delta++,
392 accum_stats++) {
393 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
394 *delta =
395 (le32_to_cpu(*stats) - le32_to_cpu(*prev_stats));
396 *accum_stats += *delta;
397 if (*delta > *max_delta)
398 *max_delta = *delta;
399 }
400 }
401
402 /* reset accumulative stats for "no-counter" type stats */
403 il->_3945.accum_stats.general.temperature =
404 il->_3945.stats.general.temperature;
405 il->_3945.accum_stats.general.ttl_timestamp =
406 il->_3945.stats.general.ttl_timestamp;
407 }
408 #endif
409
410 void
411 il3945_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb)
412 {
413 struct il_rx_pkt *pkt = rxb_addr(rxb);
414
415 D_RX("Statistics notification received (%d vs %d).\n",
416 (int)sizeof(struct il3945_notif_stats),
417 le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK);
418 #ifdef CONFIG_IWLEGACY_DEBUGFS
419 il3945_accumulative_stats(il, (__le32 *) &pkt->u.raw);
420 #endif
421
422 memcpy(&il->_3945.stats, pkt->u.raw, sizeof(il->_3945.stats));
423 }
424
425 void
426 il3945_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb)
427 {
428 struct il_rx_pkt *pkt = rxb_addr(rxb);
429 __le32 *flag = (__le32 *) &pkt->u.raw;
430
431 if (le32_to_cpu(*flag) & UCODE_STATS_CLEAR_MSK) {
432 #ifdef CONFIG_IWLEGACY_DEBUGFS
433 memset(&il->_3945.accum_stats, 0,
434 sizeof(struct il3945_notif_stats));
435 memset(&il->_3945.delta_stats, 0,
436 sizeof(struct il3945_notif_stats));
437 memset(&il->_3945.max_delta, 0,
438 sizeof(struct il3945_notif_stats));
439 #endif
440 D_RX("Statistics have been cleared\n");
441 }
442 il3945_hdl_stats(il, rxb);
443 }
444
445 /******************************************************************************
446 *
447 * Misc. internal state and helper functions
448 *
449 ******************************************************************************/
450
451 /* This is necessary only for a number of stats, see the caller. */
452 static int
453 il3945_is_network_packet(struct il_priv *il, struct ieee80211_hdr *header)
454 {
455 /* Filter incoming packets to determine if they are targeted toward
456 * this network, discarding packets coming from ourselves */
457 switch (il->iw_mode) {
458 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
459 /* packets to our IBSS update information */
460 return !compare_ether_addr(header->addr3, il->bssid);
461 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
462 /* packets to our IBSS update information */
463 return !compare_ether_addr(header->addr2, il->bssid);
464 default:
465 return 1;
466 }
467 }
468
469 static void
470 il3945_pass_packet_to_mac80211(struct il_priv *il, struct il_rx_buf *rxb,
471 struct ieee80211_rx_status *stats)
472 {
473 struct il_rx_pkt *pkt = rxb_addr(rxb);
474 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IL_RX_DATA(pkt);
475 struct il3945_rx_frame_hdr *rx_hdr = IL_RX_HDR(pkt);
476 struct il3945_rx_frame_end *rx_end = IL_RX_END(pkt);
477 u16 len = le16_to_cpu(rx_hdr->len);
478 struct sk_buff *skb;
479 __le16 fc = hdr->frame_control;
480
481 /* We received data from the HW, so stop the watchdog */
482 if (unlikely
483 (len + IL39_RX_FRAME_SIZE >
484 PAGE_SIZE << il->hw_params.rx_page_order)) {
485 D_DROP("Corruption detected!\n");
486 return;
487 }
488
489 /* We only process data packets if the interface is open */
490 if (unlikely(!il->is_open)) {
491 D_DROP("Dropping packet while interface is not open.\n");
492 return;
493 }
494
495 skb = dev_alloc_skb(128);
496 if (!skb) {
497 IL_ERR("dev_alloc_skb failed\n");
498 return;
499 }
500
501 if (!il3945_mod_params.sw_crypto)
502 il_set_decrypted_flag(il, (struct ieee80211_hdr *)rxb_addr(rxb),
503 le32_to_cpu(rx_end->status), stats);
504
505 skb_add_rx_frag(skb, 0, rxb->page,
506 (void *)rx_hdr->payload - (void *)pkt, len);
507
508 il_update_stats(il, false, fc, len);
509 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
510
511 ieee80211_rx(il->hw, skb);
512 il->alloc_rxb_page--;
513 rxb->page = NULL;
514 }
515
516 #define IL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
517
518 static void
519 il3945_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb)
520 {
521 struct ieee80211_hdr *header;
522 struct ieee80211_rx_status rx_status;
523 struct il_rx_pkt *pkt = rxb_addr(rxb);
524 struct il3945_rx_frame_stats *rx_stats = IL_RX_STATS(pkt);
525 struct il3945_rx_frame_hdr *rx_hdr = IL_RX_HDR(pkt);
526 struct il3945_rx_frame_end *rx_end = IL_RX_END(pkt);
527 u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg);
528 u16 rx_stats_noise_diff __maybe_unused =
529 le16_to_cpu(rx_stats->noise_diff);
530 u8 network_packet;
531
532 rx_status.flag = 0;
533 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
534 rx_status.band =
535 (rx_hdr->
536 phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? IEEE80211_BAND_2GHZ :
537 IEEE80211_BAND_5GHZ;
538 rx_status.freq =
539 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel),
540 rx_status.band);
541
542 rx_status.rate_idx = il3945_hwrate_to_plcp_idx(rx_hdr->rate);
543 if (rx_status.band == IEEE80211_BAND_5GHZ)
544 rx_status.rate_idx -= IL_FIRST_OFDM_RATE;
545
546 rx_status.antenna =
547 (le16_to_cpu(rx_hdr->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) >>
548 4;
549
550 /* set the preamble flag if appropriate */
551 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
552 rx_status.flag |= RX_FLAG_SHORTPRE;
553
554 if ((unlikely(rx_stats->phy_count > 20))) {
555 D_DROP("dsp size out of range [0,20]: %d/n",
556 rx_stats->phy_count);
557 return;
558 }
559
560 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR) ||
561 !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
562 D_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
563 return;
564 }
565
566 /* Convert 3945's rssi indicator to dBm */
567 rx_status.signal = rx_stats->rssi - IL39_RSSI_OFFSET;
568
569 D_STATS("Rssi %d sig_avg %d noise_diff %d\n", rx_status.signal,
570 rx_stats_sig_avg, rx_stats_noise_diff);
571
572 header = (struct ieee80211_hdr *)IL_RX_DATA(pkt);
573
574 network_packet = il3945_is_network_packet(il, header);
575
576 D_STATS("[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
577 network_packet ? '*' : ' ', le16_to_cpu(rx_hdr->channel),
578 rx_status.signal, rx_status.signal, rx_status.rate_idx);
579
580 il_dbg_log_rx_data_frame(il, le16_to_cpu(rx_hdr->len), header);
581
582 if (network_packet) {
583 il->_3945.last_beacon_time =
584 le32_to_cpu(rx_end->beacon_timestamp);
585 il->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
586 il->_3945.last_rx_rssi = rx_status.signal;
587 }
588
589 il3945_pass_packet_to_mac80211(il, rxb, &rx_status);
590 }
591
592 int
593 il3945_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
594 dma_addr_t addr, u16 len, u8 reset, u8 pad)
595 {
596 int count;
597 struct il_queue *q;
598 struct il3945_tfd *tfd, *tfd_tmp;
599
600 q = &txq->q;
601 tfd_tmp = (struct il3945_tfd *)txq->tfds;
602 tfd = &tfd_tmp[q->write_ptr];
603
604 if (reset)
605 memset(tfd, 0, sizeof(*tfd));
606
607 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
608
609 if (count >= NUM_TFD_CHUNKS || count < 0) {
610 IL_ERR("Error can not send more than %d chunks\n",
611 NUM_TFD_CHUNKS);
612 return -EINVAL;
613 }
614
615 tfd->tbs[count].addr = cpu_to_le32(addr);
616 tfd->tbs[count].len = cpu_to_le32(len);
617
618 count++;
619
620 tfd->control_flags =
621 cpu_to_le32(TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad));
622
623 return 0;
624 }
625
626 /**
627 * il3945_hw_txq_free_tfd - Free one TFD, those at idx [txq->q.read_ptr]
628 *
629 * Does NOT advance any idxes
630 */
631 void
632 il3945_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq)
633 {
634 struct il3945_tfd *tfd_tmp = (struct il3945_tfd *)txq->tfds;
635 int idx = txq->q.read_ptr;
636 struct il3945_tfd *tfd = &tfd_tmp[idx];
637 struct pci_dev *dev = il->pci_dev;
638 int i;
639 int counter;
640
641 /* sanity check */
642 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
643 if (counter > NUM_TFD_CHUNKS) {
644 IL_ERR("Too many chunks: %i\n", counter);
645 /* @todo issue fatal error, it is quite serious situation */
646 return;
647 }
648
649 /* Unmap tx_cmd */
650 if (counter)
651 pci_unmap_single(dev, dma_unmap_addr(&txq->meta[idx], mapping),
652 dma_unmap_len(&txq->meta[idx], len),
653 PCI_DMA_TODEVICE);
654
655 /* unmap chunks if any */
656
657 for (i = 1; i < counter; i++)
658 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
659 le32_to_cpu(tfd->tbs[i].len),
660 PCI_DMA_TODEVICE);
661
662 /* free SKB */
663 if (txq->txb) {
664 struct sk_buff *skb;
665
666 skb = txq->txb[txq->q.read_ptr].skb;
667
668 /* can be called from irqs-disabled context */
669 if (skb) {
670 dev_kfree_skb_any(skb);
671 txq->txb[txq->q.read_ptr].skb = NULL;
672 }
673 }
674 }
675
676 /**
677 * il3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
678 *
679 */
680 void
681 il3945_hw_build_tx_cmd_rate(struct il_priv *il, struct il_device_cmd *cmd,
682 struct ieee80211_tx_info *info,
683 struct ieee80211_hdr *hdr, int sta_id)
684 {
685 u16 hw_value = ieee80211_get_tx_rate(il->hw, info)->hw_value;
686 u16 rate_idx = min(hw_value & 0xffff, RATE_COUNT_3945 - 1);
687 u16 rate_mask;
688 int rate;
689 const u8 rts_retry_limit = 7;
690 u8 data_retry_limit;
691 __le32 tx_flags;
692 __le16 fc = hdr->frame_control;
693 struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
694
695 rate = il3945_rates[rate_idx].plcp;
696 tx_flags = tx_cmd->tx_flags;
697
698 /* We need to figure out how to get the sta->supp_rates while
699 * in this running context */
700 rate_mask = RATES_MASK_3945;
701
702 /* Set retry limit on DATA packets and Probe Responses */
703 if (ieee80211_is_probe_resp(fc))
704 data_retry_limit = 3;
705 else
706 data_retry_limit = IL_DEFAULT_TX_RETRY;
707 tx_cmd->data_retry_limit = data_retry_limit;
708 /* Set retry limit on RTS packets */
709 tx_cmd->rts_retry_limit = min(data_retry_limit, rts_retry_limit);
710
711 tx_cmd->rate = rate;
712 tx_cmd->tx_flags = tx_flags;
713
714 /* OFDM */
715 tx_cmd->supp_rates[0] =
716 ((rate_mask & IL_OFDM_RATES_MASK) >> IL_FIRST_OFDM_RATE) & 0xFF;
717
718 /* CCK */
719 tx_cmd->supp_rates[1] = (rate_mask & 0xF);
720
721 D_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
722 "cck/ofdm mask: 0x%x/0x%x\n", sta_id, tx_cmd->rate,
723 le32_to_cpu(tx_cmd->tx_flags), tx_cmd->supp_rates[1],
724 tx_cmd->supp_rates[0]);
725 }
726
727 static u8
728 il3945_sync_sta(struct il_priv *il, int sta_id, u16 tx_rate)
729 {
730 unsigned long flags_spin;
731 struct il_station_entry *station;
732
733 if (sta_id == IL_INVALID_STATION)
734 return IL_INVALID_STATION;
735
736 spin_lock_irqsave(&il->sta_lock, flags_spin);
737 station = &il->stations[sta_id];
738
739 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
740 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
741 station->sta.mode = STA_CONTROL_MODIFY_MSK;
742 il_send_add_sta(il, &station->sta, CMD_ASYNC);
743 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
744
745 D_RATE("SCALE sync station %d to rate %d\n", sta_id, tx_rate);
746 return sta_id;
747 }
748
749 static void
750 il3945_set_pwr_vmain(struct il_priv *il)
751 {
752 /*
753 * (for documentation purposes)
754 * to set power to V_AUX, do
755
756 if (pci_pme_capable(il->pci_dev, PCI_D3cold)) {
757 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
758 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
759 ~APMG_PS_CTRL_MSK_PWR_SRC);
760
761 _il_poll_bit(il, CSR_GPIO_IN,
762 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
763 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
764 }
765 */
766
767 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
768 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
769 ~APMG_PS_CTRL_MSK_PWR_SRC);
770
771 _il_poll_bit(il, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
772 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
773 }
774
775 static int
776 il3945_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
777 {
778 il_wr(il, FH39_RCSR_RBD_BASE(0), rxq->bd_dma);
779 il_wr(il, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
780 il_wr(il, FH39_RCSR_WPTR(0), 0);
781 il_wr(il, FH39_RCSR_CONFIG(0),
782 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
783 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
784 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
785 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 | (RX_QUEUE_SIZE_LOG
786 <<
787 FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE)
788 | FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST | (1 <<
789 FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH)
790 | FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
791
792 /* fake read to flush all prev I/O */
793 il_rd(il, FH39_RSSR_CTRL);
794
795 return 0;
796 }
797
798 static int
799 il3945_tx_reset(struct il_priv *il)
800 {
801
802 /* bypass mode */
803 il_wr_prph(il, ALM_SCD_MODE_REG, 0x2);
804
805 /* RA 0 is active */
806 il_wr_prph(il, ALM_SCD_ARASTAT_REG, 0x01);
807
808 /* all 6 fifo are active */
809 il_wr_prph(il, ALM_SCD_TXFACT_REG, 0x3f);
810
811 il_wr_prph(il, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
812 il_wr_prph(il, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
813 il_wr_prph(il, ALM_SCD_TXF4MF_REG, 0x000004);
814 il_wr_prph(il, ALM_SCD_TXF5MF_REG, 0x000005);
815
816 il_wr(il, FH39_TSSR_CBB_BASE, il->_3945.shared_phys);
817
818 il_wr(il, FH39_TSSR_MSG_CONFIG,
819 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
820 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
821 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
822 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
823 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
824 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
825 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
826
827 return 0;
828 }
829
830 /**
831 * il3945_txq_ctx_reset - Reset TX queue context
832 *
833 * Destroys all DMA structures and initialize them again
834 */
835 static int
836 il3945_txq_ctx_reset(struct il_priv *il)
837 {
838 int rc;
839 int txq_id, slots_num;
840
841 il3945_hw_txq_ctx_free(il);
842
843 /* allocate tx queue structure */
844 rc = il_alloc_txq_mem(il);
845 if (rc)
846 return rc;
847
848 /* Tx CMD queue */
849 rc = il3945_tx_reset(il);
850 if (rc)
851 goto error;
852
853 /* Tx queue(s) */
854 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
855 slots_num =
856 (txq_id ==
857 IL39_CMD_QUEUE_NUM) ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
858 rc = il_tx_queue_init(il, &il->txq[txq_id], slots_num, txq_id);
859 if (rc) {
860 IL_ERR("Tx %d queue init failed\n", txq_id);
861 goto error;
862 }
863 }
864
865 return rc;
866
867 error:
868 il3945_hw_txq_ctx_free(il);
869 return rc;
870 }
871
872 /*
873 * Start up 3945's basic functionality after it has been reset
874 * (e.g. after platform boot, or shutdown via il_apm_stop())
875 * NOTE: This does not load uCode nor start the embedded processor
876 */
877 static int
878 il3945_apm_init(struct il_priv *il)
879 {
880 int ret = il_apm_init(il);
881
882 /* Clear APMG (NIC's internal power management) interrupts */
883 il_wr_prph(il, APMG_RTC_INT_MSK_REG, 0x0);
884 il_wr_prph(il, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
885
886 /* Reset radio chip */
887 il_set_bits_prph(il, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
888 udelay(5);
889 il_clear_bits_prph(il, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
890
891 return ret;
892 }
893
894 static void
895 il3945_nic_config(struct il_priv *il)
896 {
897 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
898 unsigned long flags;
899 u8 rev_id = il->pci_dev->revision;
900
901 spin_lock_irqsave(&il->lock, flags);
902
903 /* Determine HW type */
904 D_INFO("HW Revision ID = 0x%X\n", rev_id);
905
906 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
907 D_INFO("RTP type\n");
908 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
909 D_INFO("3945 RADIO-MB type\n");
910 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
911 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
912 } else {
913 D_INFO("3945 RADIO-MM type\n");
914 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
915 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
916 }
917
918 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
919 D_INFO("SKU OP mode is mrc\n");
920 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
921 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
922 } else
923 D_INFO("SKU OP mode is basic\n");
924
925 if ((eeprom->board_revision & 0xF0) == 0xD0) {
926 D_INFO("3945ABG revision is 0x%X\n", eeprom->board_revision);
927 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
928 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
929 } else {
930 D_INFO("3945ABG revision is 0x%X\n", eeprom->board_revision);
931 il_clear_bit(il, CSR_HW_IF_CONFIG_REG,
932 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
933 }
934
935 if (eeprom->almgor_m_version <= 1) {
936 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
937 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
938 D_INFO("Card M type A version is 0x%X\n",
939 eeprom->almgor_m_version);
940 } else {
941 D_INFO("Card M type B version is 0x%X\n",
942 eeprom->almgor_m_version);
943 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
944 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
945 }
946 spin_unlock_irqrestore(&il->lock, flags);
947
948 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
949 D_RF_KILL("SW RF KILL supported in EEPROM.\n");
950
951 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
952 D_RF_KILL("HW RF KILL supported in EEPROM.\n");
953 }
954
955 int
956 il3945_hw_nic_init(struct il_priv *il)
957 {
958 int rc;
959 unsigned long flags;
960 struct il_rx_queue *rxq = &il->rxq;
961
962 spin_lock_irqsave(&il->lock, flags);
963 il->cfg->ops->lib->apm_ops.init(il);
964 spin_unlock_irqrestore(&il->lock, flags);
965
966 il3945_set_pwr_vmain(il);
967
968 il->cfg->ops->lib->apm_ops.config(il);
969
970 /* Allocate the RX queue, or reset if it is already allocated */
971 if (!rxq->bd) {
972 rc = il_rx_queue_alloc(il);
973 if (rc) {
974 IL_ERR("Unable to initialize Rx queue\n");
975 return -ENOMEM;
976 }
977 } else
978 il3945_rx_queue_reset(il, rxq);
979
980 il3945_rx_replenish(il);
981
982 il3945_rx_init(il, rxq);
983
984 /* Look at using this instead:
985 rxq->need_update = 1;
986 il_rx_queue_update_write_ptr(il, rxq);
987 */
988
989 il_wr(il, FH39_RCSR_WPTR(0), rxq->write & ~7);
990
991 rc = il3945_txq_ctx_reset(il);
992 if (rc)
993 return rc;
994
995 set_bit(S_INIT, &il->status);
996
997 return 0;
998 }
999
1000 /**
1001 * il3945_hw_txq_ctx_free - Free TXQ Context
1002 *
1003 * Destroy all TX DMA queues and structures
1004 */
1005 void
1006 il3945_hw_txq_ctx_free(struct il_priv *il)
1007 {
1008 int txq_id;
1009
1010 /* Tx queues */
1011 if (il->txq)
1012 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
1013 if (txq_id == IL39_CMD_QUEUE_NUM)
1014 il_cmd_queue_free(il);
1015 else
1016 il_tx_queue_free(il, txq_id);
1017
1018 /* free tx queue structure */
1019 il_txq_mem(il);
1020 }
1021
1022 void
1023 il3945_hw_txq_ctx_stop(struct il_priv *il)
1024 {
1025 int txq_id;
1026
1027 /* stop SCD */
1028 il_wr_prph(il, ALM_SCD_MODE_REG, 0);
1029 il_wr_prph(il, ALM_SCD_TXFACT_REG, 0);
1030
1031 /* reset TFD queues */
1032 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
1033 il_wr(il, FH39_TCSR_CONFIG(txq_id), 0x0);
1034 il_poll_bit(il, FH39_TSSR_TX_STATUS,
1035 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1036 1000);
1037 }
1038
1039 il3945_hw_txq_ctx_free(il);
1040 }
1041
1042 /**
1043 * il3945_hw_reg_adjust_power_by_temp
1044 * return idx delta into power gain settings table
1045 */
1046 static int
1047 il3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1048 {
1049 return (new_reading - old_reading) * (-11) / 100;
1050 }
1051
1052 /**
1053 * il3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1054 */
1055 static inline int
1056 il3945_hw_reg_temp_out_of_range(int temperature)
1057 {
1058 return (temperature < -260 || temperature > 25) ? 1 : 0;
1059 }
1060
1061 int
1062 il3945_hw_get_temperature(struct il_priv *il)
1063 {
1064 return _il_rd(il, CSR_UCODE_DRV_GP2);
1065 }
1066
1067 /**
1068 * il3945_hw_reg_txpower_get_temperature
1069 * get the current temperature by reading from NIC
1070 */
1071 static int
1072 il3945_hw_reg_txpower_get_temperature(struct il_priv *il)
1073 {
1074 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1075 int temperature;
1076
1077 temperature = il3945_hw_get_temperature(il);
1078
1079 /* driver's okay range is -260 to +25.
1080 * human readable okay range is 0 to +285 */
1081 D_INFO("Temperature: %d\n", temperature + IL_TEMP_CONVERT);
1082
1083 /* handle insane temp reading */
1084 if (il3945_hw_reg_temp_out_of_range(temperature)) {
1085 IL_ERR("Error bad temperature value %d\n", temperature);
1086
1087 /* if really really hot(?),
1088 * substitute the 3rd band/group's temp measured at factory */
1089 if (il->last_temperature > 100)
1090 temperature = eeprom->groups[2].temperature;
1091 else /* else use most recent "sane" value from driver */
1092 temperature = il->last_temperature;
1093 }
1094
1095 return temperature; /* raw, not "human readable" */
1096 }
1097
1098 /* Adjust Txpower only if temperature variance is greater than threshold.
1099 *
1100 * Both are lower than older versions' 9 degrees */
1101 #define IL_TEMPERATURE_LIMIT_TIMER 6
1102
1103 /**
1104 * il3945_is_temp_calib_needed - determines if new calibration is needed
1105 *
1106 * records new temperature in tx_mgr->temperature.
1107 * replaces tx_mgr->last_temperature *only* if calib needed
1108 * (assumes caller will actually do the calibration!). */
1109 static int
1110 il3945_is_temp_calib_needed(struct il_priv *il)
1111 {
1112 int temp_diff;
1113
1114 il->temperature = il3945_hw_reg_txpower_get_temperature(il);
1115 temp_diff = il->temperature - il->last_temperature;
1116
1117 /* get absolute value */
1118 if (temp_diff < 0) {
1119 D_POWER("Getting cooler, delta %d,\n", temp_diff);
1120 temp_diff = -temp_diff;
1121 } else if (temp_diff == 0)
1122 D_POWER("Same temp,\n");
1123 else
1124 D_POWER("Getting warmer, delta %d,\n", temp_diff);
1125
1126 /* if we don't need calibration, *don't* update last_temperature */
1127 if (temp_diff < IL_TEMPERATURE_LIMIT_TIMER) {
1128 D_POWER("Timed thermal calib not needed\n");
1129 return 0;
1130 }
1131
1132 D_POWER("Timed thermal calib needed\n");
1133
1134 /* assume that caller will actually do calib ...
1135 * update the "last temperature" value */
1136 il->last_temperature = il->temperature;
1137 return 1;
1138 }
1139
1140 #define IL_MAX_GAIN_ENTRIES 78
1141 #define IL_CCK_FROM_OFDM_POWER_DIFF -5
1142 #define IL_CCK_FROM_OFDM_IDX_DIFF (10)
1143
1144 /* radio and DSP power table, each step is 1/2 dB.
1145 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1146 static struct il3945_tx_power power_gain_table[2][IL_MAX_GAIN_ENTRIES] = {
1147 {
1148 {251, 127}, /* 2.4 GHz, highest power */
1149 {251, 127},
1150 {251, 127},
1151 {251, 127},
1152 {251, 125},
1153 {251, 110},
1154 {251, 105},
1155 {251, 98},
1156 {187, 125},
1157 {187, 115},
1158 {187, 108},
1159 {187, 99},
1160 {243, 119},
1161 {243, 111},
1162 {243, 105},
1163 {243, 97},
1164 {243, 92},
1165 {211, 106},
1166 {211, 100},
1167 {179, 120},
1168 {179, 113},
1169 {179, 107},
1170 {147, 125},
1171 {147, 119},
1172 {147, 112},
1173 {147, 106},
1174 {147, 101},
1175 {147, 97},
1176 {147, 91},
1177 {115, 107},
1178 {235, 121},
1179 {235, 115},
1180 {235, 109},
1181 {203, 127},
1182 {203, 121},
1183 {203, 115},
1184 {203, 108},
1185 {203, 102},
1186 {203, 96},
1187 {203, 92},
1188 {171, 110},
1189 {171, 104},
1190 {171, 98},
1191 {139, 116},
1192 {227, 125},
1193 {227, 119},
1194 {227, 113},
1195 {227, 107},
1196 {227, 101},
1197 {227, 96},
1198 {195, 113},
1199 {195, 106},
1200 {195, 102},
1201 {195, 95},
1202 {163, 113},
1203 {163, 106},
1204 {163, 102},
1205 {163, 95},
1206 {131, 113},
1207 {131, 106},
1208 {131, 102},
1209 {131, 95},
1210 {99, 113},
1211 {99, 106},
1212 {99, 102},
1213 {99, 95},
1214 {67, 113},
1215 {67, 106},
1216 {67, 102},
1217 {67, 95},
1218 {35, 113},
1219 {35, 106},
1220 {35, 102},
1221 {35, 95},
1222 {3, 113},
1223 {3, 106},
1224 {3, 102},
1225 {3, 95} /* 2.4 GHz, lowest power */
1226 },
1227 {
1228 {251, 127}, /* 5.x GHz, highest power */
1229 {251, 120},
1230 {251, 114},
1231 {219, 119},
1232 {219, 101},
1233 {187, 113},
1234 {187, 102},
1235 {155, 114},
1236 {155, 103},
1237 {123, 117},
1238 {123, 107},
1239 {123, 99},
1240 {123, 92},
1241 {91, 108},
1242 {59, 125},
1243 {59, 118},
1244 {59, 109},
1245 {59, 102},
1246 {59, 96},
1247 {59, 90},
1248 {27, 104},
1249 {27, 98},
1250 {27, 92},
1251 {115, 118},
1252 {115, 111},
1253 {115, 104},
1254 {83, 126},
1255 {83, 121},
1256 {83, 113},
1257 {83, 105},
1258 {83, 99},
1259 {51, 118},
1260 {51, 111},
1261 {51, 104},
1262 {51, 98},
1263 {19, 116},
1264 {19, 109},
1265 {19, 102},
1266 {19, 98},
1267 {19, 93},
1268 {171, 113},
1269 {171, 107},
1270 {171, 99},
1271 {139, 120},
1272 {139, 113},
1273 {139, 107},
1274 {139, 99},
1275 {107, 120},
1276 {107, 113},
1277 {107, 107},
1278 {107, 99},
1279 {75, 120},
1280 {75, 113},
1281 {75, 107},
1282 {75, 99},
1283 {43, 120},
1284 {43, 113},
1285 {43, 107},
1286 {43, 99},
1287 {11, 120},
1288 {11, 113},
1289 {11, 107},
1290 {11, 99},
1291 {131, 107},
1292 {131, 99},
1293 {99, 120},
1294 {99, 113},
1295 {99, 107},
1296 {99, 99},
1297 {67, 120},
1298 {67, 113},
1299 {67, 107},
1300 {67, 99},
1301 {35, 120},
1302 {35, 113},
1303 {35, 107},
1304 {35, 99},
1305 {3, 120} /* 5.x GHz, lowest power */
1306 }
1307 };
1308
1309 static inline u8
1310 il3945_hw_reg_fix_power_idx(int idx)
1311 {
1312 if (idx < 0)
1313 return 0;
1314 if (idx >= IL_MAX_GAIN_ENTRIES)
1315 return IL_MAX_GAIN_ENTRIES - 1;
1316 return (u8) idx;
1317 }
1318
1319 /* Kick off thermal recalibration check every 60 seconds */
1320 #define REG_RECALIB_PERIOD (60)
1321
1322 /**
1323 * il3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1324 *
1325 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1326 * or 6 Mbit (OFDM) rates.
1327 */
1328 static void
1329 il3945_hw_reg_set_scan_power(struct il_priv *il, u32 scan_tbl_idx, s32 rate_idx,
1330 const s8 *clip_pwrs,
1331 struct il_channel_info *ch_info, int band_idx)
1332 {
1333 struct il3945_scan_power_info *scan_power_info;
1334 s8 power;
1335 u8 power_idx;
1336
1337 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_idx];
1338
1339 /* use this channel group's 6Mbit clipping/saturation pwr,
1340 * but cap at regulatory scan power restriction (set during init
1341 * based on eeprom channel data) for this channel. */
1342 power = min(ch_info->scan_power, clip_pwrs[RATE_6M_IDX_TBL]);
1343
1344 power = min(power, il->tx_power_user_lmt);
1345 scan_power_info->requested_power = power;
1346
1347 /* find difference between new scan *power* and current "normal"
1348 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1349 * current "normal" temperature-compensated Tx power *idx* for
1350 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1351 * *idx*. */
1352 power_idx =
1353 ch_info->power_info[rate_idx].power_table_idx - (power -
1354 ch_info->
1355 power_info
1356 [RATE_6M_IDX_TBL].
1357 requested_power) *
1358 2;
1359
1360 /* store reference idx that we use when adjusting *all* scan
1361 * powers. So we can accommodate user (all channel) or spectrum
1362 * management (single channel) power changes "between" temperature
1363 * feedback compensation procedures.
1364 * don't force fit this reference idx into gain table; it may be a
1365 * negative number. This will help avoid errors when we're at
1366 * the lower bounds (highest gains, for warmest temperatures)
1367 * of the table. */
1368
1369 /* don't exceed table bounds for "real" setting */
1370 power_idx = il3945_hw_reg_fix_power_idx(power_idx);
1371
1372 scan_power_info->power_table_idx = power_idx;
1373 scan_power_info->tpc.tx_gain =
1374 power_gain_table[band_idx][power_idx].tx_gain;
1375 scan_power_info->tpc.dsp_atten =
1376 power_gain_table[band_idx][power_idx].dsp_atten;
1377 }
1378
1379 /**
1380 * il3945_send_tx_power - fill in Tx Power command with gain settings
1381 *
1382 * Configures power settings for all rates for the current channel,
1383 * using values from channel info struct, and send to NIC
1384 */
1385 static int
1386 il3945_send_tx_power(struct il_priv *il)
1387 {
1388 int rate_idx, i;
1389 const struct il_channel_info *ch_info = NULL;
1390 struct il3945_txpowertable_cmd txpower = {
1391 .channel = il->ctx.active.channel,
1392 };
1393 u16 chan;
1394
1395 if (WARN_ONCE
1396 (test_bit(S_SCAN_HW, &il->status),
1397 "TX Power requested while scanning!\n"))
1398 return -EAGAIN;
1399
1400 chan = le16_to_cpu(il->ctx.active.channel);
1401
1402 txpower.band = (il->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1403 ch_info = il_get_channel_info(il, il->band, chan);
1404 if (!ch_info) {
1405 IL_ERR("Failed to get channel info for channel %d [%d]\n", chan,
1406 il->band);
1407 return -EINVAL;
1408 }
1409
1410 if (!il_is_channel_valid(ch_info)) {
1411 D_POWER("Not calling TX_PWR_TBL_CMD on " "non-Tx channel.\n");
1412 return 0;
1413 }
1414
1415 /* fill cmd with power settings for all rates for current channel */
1416 /* Fill OFDM rate */
1417 for (rate_idx = IL_FIRST_OFDM_RATE, i = 0;
1418 rate_idx <= IL39_LAST_OFDM_RATE; rate_idx++, i++) {
1419
1420 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1421 txpower.power[i].rate = il3945_rates[rate_idx].plcp;
1422
1423 D_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1424 le16_to_cpu(txpower.channel), txpower.band,
1425 txpower.power[i].tpc.tx_gain,
1426 txpower.power[i].tpc.dsp_atten, txpower.power[i].rate);
1427 }
1428 /* Fill CCK rates */
1429 for (rate_idx = IL_FIRST_CCK_RATE; rate_idx <= IL_LAST_CCK_RATE;
1430 rate_idx++, i++) {
1431 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1432 txpower.power[i].rate = il3945_rates[rate_idx].plcp;
1433
1434 D_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1435 le16_to_cpu(txpower.channel), txpower.band,
1436 txpower.power[i].tpc.tx_gain,
1437 txpower.power[i].tpc.dsp_atten, txpower.power[i].rate);
1438 }
1439
1440 return il_send_cmd_pdu(il, C_TX_PWR_TBL,
1441 sizeof(struct il3945_txpowertable_cmd),
1442 &txpower);
1443
1444 }
1445
1446 /**
1447 * il3945_hw_reg_set_new_power - Configures power tables at new levels
1448 * @ch_info: Channel to update. Uses power_info.requested_power.
1449 *
1450 * Replace requested_power and base_power_idx ch_info fields for
1451 * one channel.
1452 *
1453 * Called if user or spectrum management changes power preferences.
1454 * Takes into account h/w and modulation limitations (clip power).
1455 *
1456 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1457 *
1458 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1459 * properly fill out the scan powers, and actual h/w gain settings,
1460 * and send changes to NIC
1461 */
1462 static int
1463 il3945_hw_reg_set_new_power(struct il_priv *il, struct il_channel_info *ch_info)
1464 {
1465 struct il3945_channel_power_info *power_info;
1466 int power_changed = 0;
1467 int i;
1468 const s8 *clip_pwrs;
1469 int power;
1470
1471 /* Get this chnlgrp's rate-to-max/clip-powers table */
1472 clip_pwrs = il->_3945.clip_groups[ch_info->group_idx].clip_powers;
1473
1474 /* Get this channel's rate-to-current-power settings table */
1475 power_info = ch_info->power_info;
1476
1477 /* update OFDM Txpower settings */
1478 for (i = RATE_6M_IDX_TBL; i <= RATE_54M_IDX_TBL; i++, ++power_info) {
1479 int delta_idx;
1480
1481 /* limit new power to be no more than h/w capability */
1482 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1483 if (power == power_info->requested_power)
1484 continue;
1485
1486 /* find difference between old and new requested powers,
1487 * update base (non-temp-compensated) power idx */
1488 delta_idx = (power - power_info->requested_power) * 2;
1489 power_info->base_power_idx -= delta_idx;
1490
1491 /* save new requested power value */
1492 power_info->requested_power = power;
1493
1494 power_changed = 1;
1495 }
1496
1497 /* update CCK Txpower settings, based on OFDM 12M setting ...
1498 * ... all CCK power settings for a given channel are the *same*. */
1499 if (power_changed) {
1500 power =
1501 ch_info->power_info[RATE_12M_IDX_TBL].requested_power +
1502 IL_CCK_FROM_OFDM_POWER_DIFF;
1503
1504 /* do all CCK rates' il3945_channel_power_info structures */
1505 for (i = RATE_1M_IDX_TBL; i <= RATE_11M_IDX_TBL; i++) {
1506 power_info->requested_power = power;
1507 power_info->base_power_idx =
1508 ch_info->power_info[RATE_12M_IDX_TBL].
1509 base_power_idx + IL_CCK_FROM_OFDM_IDX_DIFF;
1510 ++power_info;
1511 }
1512 }
1513
1514 return 0;
1515 }
1516
1517 /**
1518 * il3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1519 *
1520 * NOTE: Returned power limit may be less (but not more) than requested,
1521 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1522 * (no consideration for h/w clipping limitations).
1523 */
1524 static int
1525 il3945_hw_reg_get_ch_txpower_limit(struct il_channel_info *ch_info)
1526 {
1527 s8 max_power;
1528
1529 #if 0
1530 /* if we're using TGd limits, use lower of TGd or EEPROM */
1531 if (ch_info->tgd_data.max_power != 0)
1532 max_power =
1533 min(ch_info->tgd_data.max_power,
1534 ch_info->eeprom.max_power_avg);
1535
1536 /* else just use EEPROM limits */
1537 else
1538 #endif
1539 max_power = ch_info->eeprom.max_power_avg;
1540
1541 return min(max_power, ch_info->max_power_avg);
1542 }
1543
1544 /**
1545 * il3945_hw_reg_comp_txpower_temp - Compensate for temperature
1546 *
1547 * Compensate txpower settings of *all* channels for temperature.
1548 * This only accounts for the difference between current temperature
1549 * and the factory calibration temperatures, and bases the new settings
1550 * on the channel's base_power_idx.
1551 *
1552 * If RxOn is "associated", this sends the new Txpower to NIC!
1553 */
1554 static int
1555 il3945_hw_reg_comp_txpower_temp(struct il_priv *il)
1556 {
1557 struct il_channel_info *ch_info = NULL;
1558 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1559 int delta_idx;
1560 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1561 u8 a_band;
1562 u8 rate_idx;
1563 u8 scan_tbl_idx;
1564 u8 i;
1565 int ref_temp;
1566 int temperature = il->temperature;
1567
1568 if (il->disable_tx_power_cal || test_bit(S_SCANNING, &il->status)) {
1569 /* do not perform tx power calibration */
1570 return 0;
1571 }
1572 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1573 for (i = 0; i < il->channel_count; i++) {
1574 ch_info = &il->channel_info[i];
1575 a_band = il_is_channel_a_band(ch_info);
1576
1577 /* Get this chnlgrp's factory calibration temperature */
1578 ref_temp = (s16) eeprom->groups[ch_info->group_idx].temperature;
1579
1580 /* get power idx adjustment based on current and factory
1581 * temps */
1582 delta_idx =
1583 il3945_hw_reg_adjust_power_by_temp(temperature, ref_temp);
1584
1585 /* set tx power value for all rates, OFDM and CCK */
1586 for (rate_idx = 0; rate_idx < RATE_COUNT_3945; rate_idx++) {
1587 int power_idx =
1588 ch_info->power_info[rate_idx].base_power_idx;
1589
1590 /* temperature compensate */
1591 power_idx += delta_idx;
1592
1593 /* stay within table range */
1594 power_idx = il3945_hw_reg_fix_power_idx(power_idx);
1595 ch_info->power_info[rate_idx].power_table_idx =
1596 (u8) power_idx;
1597 ch_info->power_info[rate_idx].tpc =
1598 power_gain_table[a_band][power_idx];
1599 }
1600
1601 /* Get this chnlgrp's rate-to-max/clip-powers table */
1602 clip_pwrs =
1603 il->_3945.clip_groups[ch_info->group_idx].clip_powers;
1604
1605 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1606 for (scan_tbl_idx = 0; scan_tbl_idx < IL_NUM_SCAN_RATES;
1607 scan_tbl_idx++) {
1608 s32 actual_idx =
1609 (scan_tbl_idx ==
1610 0) ? RATE_1M_IDX_TBL : RATE_6M_IDX_TBL;
1611 il3945_hw_reg_set_scan_power(il, scan_tbl_idx,
1612 actual_idx, clip_pwrs,
1613 ch_info, a_band);
1614 }
1615 }
1616
1617 /* send Txpower command for current channel to ucode */
1618 return il->cfg->ops->lib->send_tx_power(il);
1619 }
1620
1621 int
1622 il3945_hw_reg_set_txpower(struct il_priv *il, s8 power)
1623 {
1624 struct il_channel_info *ch_info;
1625 s8 max_power;
1626 u8 a_band;
1627 u8 i;
1628
1629 if (il->tx_power_user_lmt == power) {
1630 D_POWER("Requested Tx power same as current " "limit: %ddBm.\n",
1631 power);
1632 return 0;
1633 }
1634
1635 D_POWER("Setting upper limit clamp to %ddBm.\n", power);
1636 il->tx_power_user_lmt = power;
1637
1638 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1639
1640 for (i = 0; i < il->channel_count; i++) {
1641 ch_info = &il->channel_info[i];
1642 a_band = il_is_channel_a_band(ch_info);
1643
1644 /* find minimum power of all user and regulatory constraints
1645 * (does not consider h/w clipping limitations) */
1646 max_power = il3945_hw_reg_get_ch_txpower_limit(ch_info);
1647 max_power = min(power, max_power);
1648 if (max_power != ch_info->curr_txpow) {
1649 ch_info->curr_txpow = max_power;
1650
1651 /* this considers the h/w clipping limitations */
1652 il3945_hw_reg_set_new_power(il, ch_info);
1653 }
1654 }
1655
1656 /* update txpower settings for all channels,
1657 * send to NIC if associated. */
1658 il3945_is_temp_calib_needed(il);
1659 il3945_hw_reg_comp_txpower_temp(il);
1660
1661 return 0;
1662 }
1663
1664 static int
1665 il3945_send_rxon_assoc(struct il_priv *il, struct il_rxon_context *ctx)
1666 {
1667 int rc = 0;
1668 struct il_rx_pkt *pkt;
1669 struct il3945_rxon_assoc_cmd rxon_assoc;
1670 struct il_host_cmd cmd = {
1671 .id = C_RXON_ASSOC,
1672 .len = sizeof(rxon_assoc),
1673 .flags = CMD_WANT_SKB,
1674 .data = &rxon_assoc,
1675 };
1676 const struct il_rxon_cmd *rxon1 = &ctx->staging;
1677 const struct il_rxon_cmd *rxon2 = &ctx->active;
1678
1679 if (rxon1->flags == rxon2->flags &&
1680 rxon1->filter_flags == rxon2->filter_flags &&
1681 rxon1->cck_basic_rates == rxon2->cck_basic_rates &&
1682 rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates) {
1683 D_INFO("Using current RXON_ASSOC. Not resending.\n");
1684 return 0;
1685 }
1686
1687 rxon_assoc.flags = ctx->staging.flags;
1688 rxon_assoc.filter_flags = ctx->staging.filter_flags;
1689 rxon_assoc.ofdm_basic_rates = ctx->staging.ofdm_basic_rates;
1690 rxon_assoc.cck_basic_rates = ctx->staging.cck_basic_rates;
1691 rxon_assoc.reserved = 0;
1692
1693 rc = il_send_cmd_sync(il, &cmd);
1694 if (rc)
1695 return rc;
1696
1697 pkt = (struct il_rx_pkt *)cmd.reply_page;
1698 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
1699 IL_ERR("Bad return from C_RXON_ASSOC command\n");
1700 rc = -EIO;
1701 }
1702
1703 il_free_pages(il, cmd.reply_page);
1704
1705 return rc;
1706 }
1707
1708 /**
1709 * il3945_commit_rxon - commit staging_rxon to hardware
1710 *
1711 * The RXON command in staging_rxon is committed to the hardware and
1712 * the active_rxon structure is updated with the new data. This
1713 * function correctly transitions out of the RXON_ASSOC_MSK state if
1714 * a HW tune is required based on the RXON structure changes.
1715 */
1716 int
1717 il3945_commit_rxon(struct il_priv *il, struct il_rxon_context *ctx)
1718 {
1719 /* cast away the const for active_rxon in this function */
1720 struct il3945_rxon_cmd *active_rxon = (void *)&ctx->active;
1721 struct il3945_rxon_cmd *staging_rxon = (void *)&ctx->staging;
1722 int rc = 0;
1723 bool new_assoc = !!(staging_rxon->filter_flags & RXON_FILTER_ASSOC_MSK);
1724
1725 if (test_bit(S_EXIT_PENDING, &il->status))
1726 return -EINVAL;
1727
1728 if (!il_is_alive(il))
1729 return -1;
1730
1731 /* always get timestamp with Rx frame */
1732 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1733
1734 /* select antenna */
1735 staging_rxon->flags &= ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1736 staging_rxon->flags |= il3945_get_antenna_flags(il);
1737
1738 rc = il_check_rxon_cmd(il, ctx);
1739 if (rc) {
1740 IL_ERR("Invalid RXON configuration. Not committing.\n");
1741 return -EINVAL;
1742 }
1743
1744 /* If we don't need to send a full RXON, we can use
1745 * il3945_rxon_assoc_cmd which is used to reconfigure filter
1746 * and other flags for the current radio configuration. */
1747 if (!il_full_rxon_required(il, &il->ctx)) {
1748 rc = il_send_rxon_assoc(il, &il->ctx);
1749 if (rc) {
1750 IL_ERR("Error setting RXON_ASSOC "
1751 "configuration (%d).\n", rc);
1752 return rc;
1753 }
1754
1755 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1756 /*
1757 * We do not commit tx power settings while channel changing,
1758 * do it now if tx power changed.
1759 */
1760 il_set_tx_power(il, il->tx_power_next, false);
1761 return 0;
1762 }
1763
1764 /* If we are currently associated and the new config requires
1765 * an RXON_ASSOC and the new config wants the associated mask enabled,
1766 * we must clear the associated from the active configuration
1767 * before we apply the new config */
1768 if (il_is_associated(il) && new_assoc) {
1769 D_INFO("Toggling associated bit on current RXON\n");
1770 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1771
1772 /*
1773 * reserved4 and 5 could have been filled by the iwlcore code.
1774 * Let's clear them before pushing to the 3945.
1775 */
1776 active_rxon->reserved4 = 0;
1777 active_rxon->reserved5 = 0;
1778 rc = il_send_cmd_pdu(il, C_RXON, sizeof(struct il3945_rxon_cmd),
1779 &il->ctx.active);
1780
1781 /* If the mask clearing failed then we set
1782 * active_rxon back to what it was previously */
1783 if (rc) {
1784 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1785 IL_ERR("Error clearing ASSOC_MSK on current "
1786 "configuration (%d).\n", rc);
1787 return rc;
1788 }
1789 il_clear_ucode_stations(il, &il->ctx);
1790 il_restore_stations(il, &il->ctx);
1791 }
1792
1793 D_INFO("Sending RXON\n" "* with%s RXON_FILTER_ASSOC_MSK\n"
1794 "* channel = %d\n" "* bssid = %pM\n", (new_assoc ? "" : "out"),
1795 le16_to_cpu(staging_rxon->channel), staging_rxon->bssid_addr);
1796
1797 /*
1798 * reserved4 and 5 could have been filled by the iwlcore code.
1799 * Let's clear them before pushing to the 3945.
1800 */
1801 staging_rxon->reserved4 = 0;
1802 staging_rxon->reserved5 = 0;
1803
1804 il_set_rxon_hwcrypto(il, ctx, !il3945_mod_params.sw_crypto);
1805
1806 /* Apply the new configuration */
1807 rc = il_send_cmd_pdu(il, C_RXON, sizeof(struct il3945_rxon_cmd),
1808 staging_rxon);
1809 if (rc) {
1810 IL_ERR("Error setting new configuration (%d).\n", rc);
1811 return rc;
1812 }
1813
1814 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1815
1816 if (!new_assoc) {
1817 il_clear_ucode_stations(il, &il->ctx);
1818 il_restore_stations(il, &il->ctx);
1819 }
1820
1821 /* If we issue a new RXON command which required a tune then we must
1822 * send a new TXPOWER command or we won't be able to Tx any frames */
1823 rc = il_set_tx_power(il, il->tx_power_next, true);
1824 if (rc) {
1825 IL_ERR("Error setting Tx power (%d).\n", rc);
1826 return rc;
1827 }
1828
1829 /* Init the hardware's rate fallback order based on the band */
1830 rc = il3945_init_hw_rate_table(il);
1831 if (rc) {
1832 IL_ERR("Error setting HW rate table: %02X\n", rc);
1833 return -EIO;
1834 }
1835
1836 return 0;
1837 }
1838
1839 /**
1840 * il3945_reg_txpower_periodic - called when time to check our temperature.
1841 *
1842 * -- reset periodic timer
1843 * -- see if temp has changed enough to warrant re-calibration ... if so:
1844 * -- correct coeffs for temp (can reset temp timer)
1845 * -- save this temp as "last",
1846 * -- send new set of gain settings to NIC
1847 * NOTE: This should continue working, even when we're not associated,
1848 * so we can keep our internal table of scan powers current. */
1849 void
1850 il3945_reg_txpower_periodic(struct il_priv *il)
1851 {
1852 /* This will kick in the "brute force"
1853 * il3945_hw_reg_comp_txpower_temp() below */
1854 if (!il3945_is_temp_calib_needed(il))
1855 goto reschedule;
1856
1857 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1858 * This is based *only* on current temperature,
1859 * ignoring any previous power measurements */
1860 il3945_hw_reg_comp_txpower_temp(il);
1861
1862 reschedule:
1863 queue_delayed_work(il->workqueue, &il->_3945.thermal_periodic,
1864 REG_RECALIB_PERIOD * HZ);
1865 }
1866
1867 static void
1868 il3945_bg_reg_txpower_periodic(struct work_struct *work)
1869 {
1870 struct il_priv *il = container_of(work, struct il_priv,
1871 _3945.thermal_periodic.work);
1872
1873 mutex_lock(&il->mutex);
1874 if (test_bit(S_EXIT_PENDING, &il->status) || il->txq == NULL)
1875 goto out;
1876
1877 il3945_reg_txpower_periodic(il);
1878 out:
1879 mutex_unlock(&il->mutex);
1880 }
1881
1882 /**
1883 * il3945_hw_reg_get_ch_grp_idx - find the channel-group idx (0-4) for channel.
1884 *
1885 * This function is used when initializing channel-info structs.
1886 *
1887 * NOTE: These channel groups do *NOT* match the bands above!
1888 * These channel groups are based on factory-tested channels;
1889 * on A-band, EEPROM's "group frequency" entries represent the top
1890 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
1891 */
1892 static u16
1893 il3945_hw_reg_get_ch_grp_idx(struct il_priv *il,
1894 const struct il_channel_info *ch_info)
1895 {
1896 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1897 struct il3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
1898 u8 group;
1899 u16 group_idx = 0; /* based on factory calib frequencies */
1900 u8 grp_channel;
1901
1902 /* Find the group idx for the channel ... don't use idx 1(?) */
1903 if (il_is_channel_a_band(ch_info)) {
1904 for (group = 1; group < 5; group++) {
1905 grp_channel = ch_grp[group].group_channel;
1906 if (ch_info->channel <= grp_channel) {
1907 group_idx = group;
1908 break;
1909 }
1910 }
1911 /* group 4 has a few channels *above* its factory cal freq */
1912 if (group == 5)
1913 group_idx = 4;
1914 } else
1915 group_idx = 0; /* 2.4 GHz, group 0 */
1916
1917 D_POWER("Chnl %d mapped to grp %d\n", ch_info->channel, group_idx);
1918 return group_idx;
1919 }
1920
1921 /**
1922 * il3945_hw_reg_get_matched_power_idx - Interpolate to get nominal idx
1923 *
1924 * Interpolate to get nominal (i.e. at factory calibration temperature) idx
1925 * into radio/DSP gain settings table for requested power.
1926 */
1927 static int
1928 il3945_hw_reg_get_matched_power_idx(struct il_priv *il, s8 requested_power,
1929 s32 setting_idx, s32 *new_idx)
1930 {
1931 const struct il3945_eeprom_txpower_group *chnl_grp = NULL;
1932 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1933 s32 idx0, idx1;
1934 s32 power = 2 * requested_power;
1935 s32 i;
1936 const struct il3945_eeprom_txpower_sample *samples;
1937 s32 gains0, gains1;
1938 s32 res;
1939 s32 denominator;
1940
1941 chnl_grp = &eeprom->groups[setting_idx];
1942 samples = chnl_grp->samples;
1943 for (i = 0; i < 5; i++) {
1944 if (power == samples[i].power) {
1945 *new_idx = samples[i].gain_idx;
1946 return 0;
1947 }
1948 }
1949
1950 if (power > samples[1].power) {
1951 idx0 = 0;
1952 idx1 = 1;
1953 } else if (power > samples[2].power) {
1954 idx0 = 1;
1955 idx1 = 2;
1956 } else if (power > samples[3].power) {
1957 idx0 = 2;
1958 idx1 = 3;
1959 } else {
1960 idx0 = 3;
1961 idx1 = 4;
1962 }
1963
1964 denominator = (s32) samples[idx1].power - (s32) samples[idx0].power;
1965 if (denominator == 0)
1966 return -EINVAL;
1967 gains0 = (s32) samples[idx0].gain_idx * (1 << 19);
1968 gains1 = (s32) samples[idx1].gain_idx * (1 << 19);
1969 res =
1970 gains0 + (gains1 - gains0) * ((s32) power -
1971 (s32) samples[idx0].power) /
1972 denominator + (1 << 18);
1973 *new_idx = res >> 19;
1974 return 0;
1975 }
1976
1977 static void
1978 il3945_hw_reg_init_channel_groups(struct il_priv *il)
1979 {
1980 u32 i;
1981 s32 rate_idx;
1982 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1983 const struct il3945_eeprom_txpower_group *group;
1984
1985 D_POWER("Initializing factory calib info from EEPROM\n");
1986
1987 for (i = 0; i < IL_NUM_TX_CALIB_GROUPS; i++) {
1988 s8 *clip_pwrs; /* table of power levels for each rate */
1989 s8 satur_pwr; /* saturation power for each chnl group */
1990 group = &eeprom->groups[i];
1991
1992 /* sanity check on factory saturation power value */
1993 if (group->saturation_power < 40) {
1994 IL_WARN("Error: saturation power is %d, "
1995 "less than minimum expected 40\n",
1996 group->saturation_power);
1997 return;
1998 }
1999
2000 /*
2001 * Derive requested power levels for each rate, based on
2002 * hardware capabilities (saturation power for band).
2003 * Basic value is 3dB down from saturation, with further
2004 * power reductions for highest 3 data rates. These
2005 * backoffs provide headroom for high rate modulation
2006 * power peaks, without too much distortion (clipping).
2007 */
2008 /* we'll fill in this array with h/w max power levels */
2009 clip_pwrs = (s8 *) il->_3945.clip_groups[i].clip_powers;
2010
2011 /* divide factory saturation power by 2 to find -3dB level */
2012 satur_pwr = (s8) (group->saturation_power >> 1);
2013
2014 /* fill in channel group's nominal powers for each rate */
2015 for (rate_idx = 0; rate_idx < RATE_COUNT_3945;
2016 rate_idx++, clip_pwrs++) {
2017 switch (rate_idx) {
2018 case RATE_36M_IDX_TBL:
2019 if (i == 0) /* B/G */
2020 *clip_pwrs = satur_pwr;
2021 else /* A */
2022 *clip_pwrs = satur_pwr - 5;
2023 break;
2024 case RATE_48M_IDX_TBL:
2025 if (i == 0)
2026 *clip_pwrs = satur_pwr - 7;
2027 else
2028 *clip_pwrs = satur_pwr - 10;
2029 break;
2030 case RATE_54M_IDX_TBL:
2031 if (i == 0)
2032 *clip_pwrs = satur_pwr - 9;
2033 else
2034 *clip_pwrs = satur_pwr - 12;
2035 break;
2036 default:
2037 *clip_pwrs = satur_pwr;
2038 break;
2039 }
2040 }
2041 }
2042 }
2043
2044 /**
2045 * il3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2046 *
2047 * Second pass (during init) to set up il->channel_info
2048 *
2049 * Set up Tx-power settings in our channel info database for each VALID
2050 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2051 * and current temperature.
2052 *
2053 * Since this is based on current temperature (at init time), these values may
2054 * not be valid for very long, but it gives us a starting/default point,
2055 * and allows us to active (i.e. using Tx) scan.
2056 *
2057 * This does *not* write values to NIC, just sets up our internal table.
2058 */
2059 int
2060 il3945_txpower_set_from_eeprom(struct il_priv *il)
2061 {
2062 struct il_channel_info *ch_info = NULL;
2063 struct il3945_channel_power_info *pwr_info;
2064 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
2065 int delta_idx;
2066 u8 rate_idx;
2067 u8 scan_tbl_idx;
2068 const s8 *clip_pwrs; /* array of power levels for each rate */
2069 u8 gain, dsp_atten;
2070 s8 power;
2071 u8 pwr_idx, base_pwr_idx, a_band;
2072 u8 i;
2073 int temperature;
2074
2075 /* save temperature reference,
2076 * so we can determine next time to calibrate */
2077 temperature = il3945_hw_reg_txpower_get_temperature(il);
2078 il->last_temperature = temperature;
2079
2080 il3945_hw_reg_init_channel_groups(il);
2081
2082 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2083 for (i = 0, ch_info = il->channel_info; i < il->channel_count;
2084 i++, ch_info++) {
2085 a_band = il_is_channel_a_band(ch_info);
2086 if (!il_is_channel_valid(ch_info))
2087 continue;
2088
2089 /* find this channel's channel group (*not* "band") idx */
2090 ch_info->group_idx = il3945_hw_reg_get_ch_grp_idx(il, ch_info);
2091
2092 /* Get this chnlgrp's rate->max/clip-powers table */
2093 clip_pwrs =
2094 il->_3945.clip_groups[ch_info->group_idx].clip_powers;
2095
2096 /* calculate power idx *adjustment* value according to
2097 * diff between current temperature and factory temperature */
2098 delta_idx =
2099 il3945_hw_reg_adjust_power_by_temp(temperature,
2100 eeprom->groups[ch_info->
2101 group_idx].
2102 temperature);
2103
2104 D_POWER("Delta idx for channel %d: %d [%d]\n", ch_info->channel,
2105 delta_idx, temperature + IL_TEMP_CONVERT);
2106
2107 /* set tx power value for all OFDM rates */
2108 for (rate_idx = 0; rate_idx < IL_OFDM_RATES; rate_idx++) {
2109 s32 uninitialized_var(power_idx);
2110 int rc;
2111
2112 /* use channel group's clip-power table,
2113 * but don't exceed channel's max power */
2114 s8 pwr = min(ch_info->max_power_avg,
2115 clip_pwrs[rate_idx]);
2116
2117 pwr_info = &ch_info->power_info[rate_idx];
2118
2119 /* get base (i.e. at factory-measured temperature)
2120 * power table idx for this rate's power */
2121 rc = il3945_hw_reg_get_matched_power_idx(il, pwr,
2122 ch_info->
2123 group_idx,
2124 &power_idx);
2125 if (rc) {
2126 IL_ERR("Invalid power idx\n");
2127 return rc;
2128 }
2129 pwr_info->base_power_idx = (u8) power_idx;
2130
2131 /* temperature compensate */
2132 power_idx += delta_idx;
2133
2134 /* stay within range of gain table */
2135 power_idx = il3945_hw_reg_fix_power_idx(power_idx);
2136
2137 /* fill 1 OFDM rate's il3945_channel_power_info struct */
2138 pwr_info->requested_power = pwr;
2139 pwr_info->power_table_idx = (u8) power_idx;
2140 pwr_info->tpc.tx_gain =
2141 power_gain_table[a_band][power_idx].tx_gain;
2142 pwr_info->tpc.dsp_atten =
2143 power_gain_table[a_band][power_idx].dsp_atten;
2144 }
2145
2146 /* set tx power for CCK rates, based on OFDM 12 Mbit settings */
2147 pwr_info = &ch_info->power_info[RATE_12M_IDX_TBL];
2148 power = pwr_info->requested_power + IL_CCK_FROM_OFDM_POWER_DIFF;
2149 pwr_idx = pwr_info->power_table_idx + IL_CCK_FROM_OFDM_IDX_DIFF;
2150 base_pwr_idx =
2151 pwr_info->base_power_idx + IL_CCK_FROM_OFDM_IDX_DIFF;
2152
2153 /* stay within table range */
2154 pwr_idx = il3945_hw_reg_fix_power_idx(pwr_idx);
2155 gain = power_gain_table[a_band][pwr_idx].tx_gain;
2156 dsp_atten = power_gain_table[a_band][pwr_idx].dsp_atten;
2157
2158 /* fill each CCK rate's il3945_channel_power_info structure
2159 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2160 * NOTE: CCK rates start at end of OFDM rates! */
2161 for (rate_idx = 0; rate_idx < IL_CCK_RATES; rate_idx++) {
2162 pwr_info =
2163 &ch_info->power_info[rate_idx + IL_OFDM_RATES];
2164 pwr_info->requested_power = power;
2165 pwr_info->power_table_idx = pwr_idx;
2166 pwr_info->base_power_idx = base_pwr_idx;
2167 pwr_info->tpc.tx_gain = gain;
2168 pwr_info->tpc.dsp_atten = dsp_atten;
2169 }
2170
2171 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2172 for (scan_tbl_idx = 0; scan_tbl_idx < IL_NUM_SCAN_RATES;
2173 scan_tbl_idx++) {
2174 s32 actual_idx =
2175 (scan_tbl_idx ==
2176 0) ? RATE_1M_IDX_TBL : RATE_6M_IDX_TBL;
2177 il3945_hw_reg_set_scan_power(il, scan_tbl_idx,
2178 actual_idx, clip_pwrs,
2179 ch_info, a_band);
2180 }
2181 }
2182
2183 return 0;
2184 }
2185
2186 int
2187 il3945_hw_rxq_stop(struct il_priv *il)
2188 {
2189 int rc;
2190
2191 il_wr(il, FH39_RCSR_CONFIG(0), 0);
2192 rc = il_poll_bit(il, FH39_RSSR_STATUS,
2193 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2194 if (rc < 0)
2195 IL_ERR("Can't stop Rx DMA.\n");
2196
2197 return 0;
2198 }
2199
2200 int
2201 il3945_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq)
2202 {
2203 int txq_id = txq->q.id;
2204
2205 struct il3945_shared *shared_data = il->_3945.shared_virt;
2206
2207 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32) txq->q.dma_addr);
2208
2209 il_wr(il, FH39_CBCC_CTRL(txq_id), 0);
2210 il_wr(il, FH39_CBCC_BASE(txq_id), 0);
2211
2212 il_wr(il, FH39_TCSR_CONFIG(txq_id),
2213 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2214 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2215 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2216 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2217 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2218
2219 /* fake read to flush all prev. writes */
2220 _il_rd(il, FH39_TSSR_CBB_BASE);
2221
2222 return 0;
2223 }
2224
2225 /*
2226 * HCMD utils
2227 */
2228 static u16
2229 il3945_get_hcmd_size(u8 cmd_id, u16 len)
2230 {
2231 switch (cmd_id) {
2232 case C_RXON:
2233 return sizeof(struct il3945_rxon_cmd);
2234 case C_POWER_TBL:
2235 return sizeof(struct il3945_powertable_cmd);
2236 default:
2237 return len;
2238 }
2239 }
2240
2241 static u16
2242 il3945_build_addsta_hcmd(const struct il_addsta_cmd *cmd, u8 * data)
2243 {
2244 struct il3945_addsta_cmd *addsta = (struct il3945_addsta_cmd *)data;
2245 addsta->mode = cmd->mode;
2246 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2247 memcpy(&addsta->key, &cmd->key, sizeof(struct il4965_keyinfo));
2248 addsta->station_flags = cmd->station_flags;
2249 addsta->station_flags_msk = cmd->station_flags_msk;
2250 addsta->tid_disable_tx = cpu_to_le16(0);
2251 addsta->rate_n_flags = cmd->rate_n_flags;
2252 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2253 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2254 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2255
2256 return (u16) sizeof(struct il3945_addsta_cmd);
2257 }
2258
2259 static int
2260 il3945_add_bssid_station(struct il_priv *il, const u8 * addr, u8 * sta_id_r)
2261 {
2262 struct il_rxon_context *ctx = &il->ctx;
2263 int ret;
2264 u8 sta_id;
2265 unsigned long flags;
2266
2267 if (sta_id_r)
2268 *sta_id_r = IL_INVALID_STATION;
2269
2270 ret = il_add_station_common(il, ctx, addr, 0, NULL, &sta_id);
2271 if (ret) {
2272 IL_ERR("Unable to add station %pM\n", addr);
2273 return ret;
2274 }
2275
2276 if (sta_id_r)
2277 *sta_id_r = sta_id;
2278
2279 spin_lock_irqsave(&il->sta_lock, flags);
2280 il->stations[sta_id].used |= IL_STA_LOCAL;
2281 spin_unlock_irqrestore(&il->sta_lock, flags);
2282
2283 return 0;
2284 }
2285
2286 static int
2287 il3945_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif,
2288 bool add)
2289 {
2290 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
2291 int ret;
2292
2293 if (add) {
2294 ret =
2295 il3945_add_bssid_station(il, vif->bss_conf.bssid,
2296 &vif_priv->ibss_bssid_sta_id);
2297 if (ret)
2298 return ret;
2299
2300 il3945_sync_sta(il, vif_priv->ibss_bssid_sta_id,
2301 (il->band ==
2302 IEEE80211_BAND_5GHZ) ? RATE_6M_PLCP :
2303 RATE_1M_PLCP);
2304 il3945_rate_scale_init(il->hw, vif_priv->ibss_bssid_sta_id);
2305
2306 return 0;
2307 }
2308
2309 return il_remove_station(il, vif_priv->ibss_bssid_sta_id,
2310 vif->bss_conf.bssid);
2311 }
2312
2313 /**
2314 * il3945_init_hw_rate_table - Initialize the hardware rate fallback table
2315 */
2316 int
2317 il3945_init_hw_rate_table(struct il_priv *il)
2318 {
2319 int rc, i, idx, prev_idx;
2320 struct il3945_rate_scaling_cmd rate_cmd = {
2321 .reserved = {0, 0, 0},
2322 };
2323 struct il3945_rate_scaling_info *table = rate_cmd.table;
2324
2325 for (i = 0; i < ARRAY_SIZE(il3945_rates); i++) {
2326 idx = il3945_rates[i].table_rs_idx;
2327
2328 table[idx].rate_n_flags = cpu_to_le16(il3945_rates[i].plcp);
2329 table[idx].try_cnt = il->retry_rate;
2330 prev_idx = il3945_get_prev_ieee_rate(i);
2331 table[idx].next_rate_idx = il3945_rates[prev_idx].table_rs_idx;
2332 }
2333
2334 switch (il->band) {
2335 case IEEE80211_BAND_5GHZ:
2336 D_RATE("Select A mode rate scale\n");
2337 /* If one of the following CCK rates is used,
2338 * have it fall back to the 6M OFDM rate */
2339 for (i = RATE_1M_IDX_TBL; i <= RATE_11M_IDX_TBL; i++)
2340 table[i].next_rate_idx =
2341 il3945_rates[IL_FIRST_OFDM_RATE].table_rs_idx;
2342
2343 /* Don't fall back to CCK rates */
2344 table[RATE_12M_IDX_TBL].next_rate_idx = RATE_9M_IDX_TBL;
2345
2346 /* Don't drop out of OFDM rates */
2347 table[RATE_6M_IDX_TBL].next_rate_idx =
2348 il3945_rates[IL_FIRST_OFDM_RATE].table_rs_idx;
2349 break;
2350
2351 case IEEE80211_BAND_2GHZ:
2352 D_RATE("Select B/G mode rate scale\n");
2353 /* If an OFDM rate is used, have it fall back to the
2354 * 1M CCK rates */
2355
2356 if (!(il->_3945.sta_supp_rates & IL_OFDM_RATES_MASK) &&
2357 il_is_associated(il)) {
2358
2359 idx = IL_FIRST_CCK_RATE;
2360 for (i = RATE_6M_IDX_TBL; i <= RATE_54M_IDX_TBL; i++)
2361 table[i].next_rate_idx =
2362 il3945_rates[idx].table_rs_idx;
2363
2364 idx = RATE_11M_IDX_TBL;
2365 /* CCK shouldn't fall back to OFDM... */
2366 table[idx].next_rate_idx = RATE_5M_IDX_TBL;
2367 }
2368 break;
2369
2370 default:
2371 WARN_ON(1);
2372 break;
2373 }
2374
2375 /* Update the rate scaling for control frame Tx */
2376 rate_cmd.table_id = 0;
2377 rc = il_send_cmd_pdu(il, C_RATE_SCALE, sizeof(rate_cmd), &rate_cmd);
2378 if (rc)
2379 return rc;
2380
2381 /* Update the rate scaling for data frame Tx */
2382 rate_cmd.table_id = 1;
2383 return il_send_cmd_pdu(il, C_RATE_SCALE, sizeof(rate_cmd), &rate_cmd);
2384 }
2385
2386 /* Called when initializing driver */
2387 int
2388 il3945_hw_set_hw_params(struct il_priv *il)
2389 {
2390 memset((void *)&il->hw_params, 0, sizeof(struct il_hw_params));
2391
2392 il->_3945.shared_virt =
2393 dma_alloc_coherent(&il->pci_dev->dev, sizeof(struct il3945_shared),
2394 &il->_3945.shared_phys, GFP_KERNEL);
2395 if (!il->_3945.shared_virt) {
2396 IL_ERR("failed to allocate pci memory\n");
2397 return -ENOMEM;
2398 }
2399
2400 /* Assign number of Usable TX queues */
2401 il->hw_params.max_txq_num = il->cfg->base_params->num_of_queues;
2402
2403 il->hw_params.tfd_size = sizeof(struct il3945_tfd);
2404 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_3K);
2405 il->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2406 il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2407 il->hw_params.max_stations = IL3945_STATION_COUNT;
2408 il->ctx.bcast_sta_id = IL3945_BROADCAST_ID;
2409
2410 il->sta_key_max_num = STA_KEY_MAX_NUM;
2411
2412 il->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2413 il->hw_params.max_beacon_itrvl = IL39_MAX_UCODE_BEACON_INTERVAL;
2414 il->hw_params.beacon_time_tsf_bits = IL3945_EXT_BEACON_TIME_POS;
2415
2416 return 0;
2417 }
2418
2419 unsigned int
2420 il3945_hw_get_beacon_cmd(struct il_priv *il, struct il3945_frame *frame,
2421 u8 rate)
2422 {
2423 struct il3945_tx_beacon_cmd *tx_beacon_cmd;
2424 unsigned int frame_size;
2425
2426 tx_beacon_cmd = (struct il3945_tx_beacon_cmd *)&frame->u;
2427 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2428
2429 tx_beacon_cmd->tx.sta_id = il->ctx.bcast_sta_id;
2430 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2431
2432 frame_size =
2433 il3945_fill_beacon_frame(il, tx_beacon_cmd->frame,
2434 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2435
2436 BUG_ON(frame_size > MAX_MPDU_SIZE);
2437 tx_beacon_cmd->tx.len = cpu_to_le16((u16) frame_size);
2438
2439 tx_beacon_cmd->tx.rate = rate;
2440 tx_beacon_cmd->tx.tx_flags =
2441 (TX_CMD_FLG_SEQ_CTL_MSK | TX_CMD_FLG_TSF_MSK);
2442
2443 /* supp_rates[0] == OFDM start at IL_FIRST_OFDM_RATE */
2444 tx_beacon_cmd->tx.supp_rates[0] =
2445 (IL_OFDM_BASIC_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
2446
2447 tx_beacon_cmd->tx.supp_rates[1] = (IL_CCK_BASIC_RATES_MASK & 0xF);
2448
2449 return sizeof(struct il3945_tx_beacon_cmd) + frame_size;
2450 }
2451
2452 void
2453 il3945_hw_handler_setup(struct il_priv *il)
2454 {
2455 il->handlers[C_TX] = il3945_hdl_tx;
2456 il->handlers[N_3945_RX] = il3945_hdl_rx;
2457 }
2458
2459 void
2460 il3945_hw_setup_deferred_work(struct il_priv *il)
2461 {
2462 INIT_DELAYED_WORK(&il->_3945.thermal_periodic,
2463 il3945_bg_reg_txpower_periodic);
2464 }
2465
2466 void
2467 il3945_hw_cancel_deferred_work(struct il_priv *il)
2468 {
2469 cancel_delayed_work(&il->_3945.thermal_periodic);
2470 }
2471
2472 /* check contents of special bootstrap uCode SRAM */
2473 static int
2474 il3945_verify_bsm(struct il_priv *il)
2475 {
2476 __le32 *image = il->ucode_boot.v_addr;
2477 u32 len = il->ucode_boot.len;
2478 u32 reg;
2479 u32 val;
2480
2481 D_INFO("Begin verify bsm\n");
2482
2483 /* verify BSM SRAM contents */
2484 val = il_rd_prph(il, BSM_WR_DWCOUNT_REG);
2485 for (reg = BSM_SRAM_LOWER_BOUND; reg < BSM_SRAM_LOWER_BOUND + len;
2486 reg += sizeof(u32), image++) {
2487 val = il_rd_prph(il, reg);
2488 if (val != le32_to_cpu(*image)) {
2489 IL_ERR("BSM uCode verification failed at "
2490 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2491 BSM_SRAM_LOWER_BOUND, reg - BSM_SRAM_LOWER_BOUND,
2492 len, val, le32_to_cpu(*image));
2493 return -EIO;
2494 }
2495 }
2496
2497 D_INFO("BSM bootstrap uCode image OK\n");
2498
2499 return 0;
2500 }
2501
2502 /******************************************************************************
2503 *
2504 * EEPROM related functions
2505 *
2506 ******************************************************************************/
2507
2508 /*
2509 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2510 * embedded controller) as EEPROM reader; each read is a series of pulses
2511 * to/from the EEPROM chip, not a single event, so even reads could conflict
2512 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2513 * simply claims ownership, which should be safe when this function is called
2514 * (i.e. before loading uCode!).
2515 */
2516 static int
2517 il3945_eeprom_acquire_semaphore(struct il_priv *il)
2518 {
2519 _il_clear_bit(il, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2520 return 0;
2521 }
2522
2523 static void
2524 il3945_eeprom_release_semaphore(struct il_priv *il)
2525 {
2526 return;
2527 }
2528
2529 /**
2530 * il3945_load_bsm - Load bootstrap instructions
2531 *
2532 * BSM operation:
2533 *
2534 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2535 * in special SRAM that does not power down during RFKILL. When powering back
2536 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2537 * the bootstrap program into the on-board processor, and starts it.
2538 *
2539 * The bootstrap program loads (via DMA) instructions and data for a new
2540 * program from host DRAM locations indicated by the host driver in the
2541 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2542 * automatically.
2543 *
2544 * When initializing the NIC, the host driver points the BSM to the
2545 * "initialize" uCode image. This uCode sets up some internal data, then
2546 * notifies host via "initialize alive" that it is complete.
2547 *
2548 * The host then replaces the BSM_DRAM_* pointer values to point to the
2549 * normal runtime uCode instructions and a backup uCode data cache buffer
2550 * (filled initially with starting data values for the on-board processor),
2551 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2552 * which begins normal operation.
2553 *
2554 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2555 * the backup data cache in DRAM before SRAM is powered down.
2556 *
2557 * When powering back up, the BSM loads the bootstrap program. This reloads
2558 * the runtime uCode instructions and the backup data cache into SRAM,
2559 * and re-launches the runtime uCode from where it left off.
2560 */
2561 static int
2562 il3945_load_bsm(struct il_priv *il)
2563 {
2564 __le32 *image = il->ucode_boot.v_addr;
2565 u32 len = il->ucode_boot.len;
2566 dma_addr_t pinst;
2567 dma_addr_t pdata;
2568 u32 inst_len;
2569 u32 data_len;
2570 int rc;
2571 int i;
2572 u32 done;
2573 u32 reg_offset;
2574
2575 D_INFO("Begin load bsm\n");
2576
2577 /* make sure bootstrap program is no larger than BSM's SRAM size */
2578 if (len > IL39_MAX_BSM_SIZE)
2579 return -EINVAL;
2580
2581 /* Tell bootstrap uCode where to find the "Initialize" uCode
2582 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2583 * NOTE: il3945_initialize_alive_start() will replace these values,
2584 * after the "initialize" uCode has run, to point to
2585 * runtime/protocol instructions and backup data cache. */
2586 pinst = il->ucode_init.p_addr;
2587 pdata = il->ucode_init_data.p_addr;
2588 inst_len = il->ucode_init.len;
2589 data_len = il->ucode_init_data.len;
2590
2591 il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
2592 il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
2593 il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2594 il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2595
2596 /* Fill BSM memory with bootstrap instructions */
2597 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2598 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2599 reg_offset += sizeof(u32), image++)
2600 _il_wr_prph(il, reg_offset, le32_to_cpu(*image));
2601
2602 rc = il3945_verify_bsm(il);
2603 if (rc)
2604 return rc;
2605
2606 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2607 il_wr_prph(il, BSM_WR_MEM_SRC_REG, 0x0);
2608 il_wr_prph(il, BSM_WR_MEM_DST_REG, IL39_RTC_INST_LOWER_BOUND);
2609 il_wr_prph(il, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2610
2611 /* Load bootstrap code into instruction SRAM now,
2612 * to prepare to load "initialize" uCode */
2613 il_wr_prph(il, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
2614
2615 /* Wait for load of bootstrap uCode to finish */
2616 for (i = 0; i < 100; i++) {
2617 done = il_rd_prph(il, BSM_WR_CTRL_REG);
2618 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2619 break;
2620 udelay(10);
2621 }
2622 if (i < 100)
2623 D_INFO("BSM write complete, poll %d iterations\n", i);
2624 else {
2625 IL_ERR("BSM write did not complete!\n");
2626 return -EIO;
2627 }
2628
2629 /* Enable future boot loads whenever power management unit triggers it
2630 * (e.g. when powering back up after power-save shutdown) */
2631 il_wr_prph(il, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
2632
2633 return 0;
2634 }
2635
2636 static struct il_hcmd_ops il3945_hcmd = {
2637 .rxon_assoc = il3945_send_rxon_assoc,
2638 .commit_rxon = il3945_commit_rxon,
2639 };
2640
2641 static struct il_lib_ops il3945_lib = {
2642 .txq_attach_buf_to_tfd = il3945_hw_txq_attach_buf_to_tfd,
2643 .txq_free_tfd = il3945_hw_txq_free_tfd,
2644 .txq_init = il3945_hw_tx_queue_init,
2645 .load_ucode = il3945_load_bsm,
2646 .dump_nic_error_log = il3945_dump_nic_error_log,
2647 .apm_ops = {
2648 .init = il3945_apm_init,
2649 .config = il3945_nic_config,
2650 },
2651 .eeprom_ops = {
2652 .regulatory_bands = {
2653 EEPROM_REGULATORY_BAND_1_CHANNELS,
2654 EEPROM_REGULATORY_BAND_2_CHANNELS,
2655 EEPROM_REGULATORY_BAND_3_CHANNELS,
2656 EEPROM_REGULATORY_BAND_4_CHANNELS,
2657 EEPROM_REGULATORY_BAND_5_CHANNELS,
2658 EEPROM_REGULATORY_BAND_NO_HT40,
2659 EEPROM_REGULATORY_BAND_NO_HT40,
2660 },
2661 .acquire_semaphore = il3945_eeprom_acquire_semaphore,
2662 .release_semaphore = il3945_eeprom_release_semaphore,
2663 },
2664 .send_tx_power = il3945_send_tx_power,
2665 .is_valid_rtc_data_addr = il3945_hw_valid_rtc_data_addr,
2666
2667 #ifdef CONFIG_IWLEGACY_DEBUGFS
2668 .debugfs_ops = {
2669 .rx_stats_read = il3945_ucode_rx_stats_read,
2670 .tx_stats_read = il3945_ucode_tx_stats_read,
2671 .general_stats_read = il3945_ucode_general_stats_read,
2672 },
2673 #endif
2674 };
2675
2676 static const struct il_legacy_ops il3945_legacy_ops = {
2677 .post_associate = il3945_post_associate,
2678 .config_ap = il3945_config_ap,
2679 .manage_ibss_station = il3945_manage_ibss_station,
2680 };
2681
2682 static struct il_hcmd_utils_ops il3945_hcmd_utils = {
2683 .get_hcmd_size = il3945_get_hcmd_size,
2684 .build_addsta_hcmd = il3945_build_addsta_hcmd,
2685 .request_scan = il3945_request_scan,
2686 .post_scan = il3945_post_scan,
2687 };
2688
2689 static const struct il_ops il3945_ops = {
2690 .lib = &il3945_lib,
2691 .hcmd = &il3945_hcmd,
2692 .utils = &il3945_hcmd_utils,
2693 .led = &il3945_led_ops,
2694 .legacy = &il3945_legacy_ops,
2695 .ieee80211_ops = &il3945_hw_ops,
2696 };
2697
2698 static struct il_base_params il3945_base_params = {
2699 .eeprom_size = IL3945_EEPROM_IMG_SIZE,
2700 .num_of_queues = IL39_NUM_QUEUES,
2701 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2702 .set_l0s = false,
2703 .use_bsm = true,
2704 .led_compensation = 64,
2705 .wd_timeout = IL_DEF_WD_TIMEOUT,
2706 };
2707
2708 static struct il_cfg il3945_bg_cfg = {
2709 .name = "3945BG",
2710 .fw_name_pre = IL3945_FW_PRE,
2711 .ucode_api_max = IL3945_UCODE_API_MAX,
2712 .ucode_api_min = IL3945_UCODE_API_MIN,
2713 .sku = IL_SKU_G,
2714 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2715 .ops = &il3945_ops,
2716 .mod_params = &il3945_mod_params,
2717 .base_params = &il3945_base_params,
2718 .led_mode = IL_LED_BLINK,
2719 };
2720
2721 static struct il_cfg il3945_abg_cfg = {
2722 .name = "3945ABG",
2723 .fw_name_pre = IL3945_FW_PRE,
2724 .ucode_api_max = IL3945_UCODE_API_MAX,
2725 .ucode_api_min = IL3945_UCODE_API_MIN,
2726 .sku = IL_SKU_A | IL_SKU_G,
2727 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2728 .ops = &il3945_ops,
2729 .mod_params = &il3945_mod_params,
2730 .base_params = &il3945_base_params,
2731 .led_mode = IL_LED_BLINK,
2732 };
2733
2734 DEFINE_PCI_DEVICE_TABLE(il3945_hw_card_ids) = {
2735 {IL_PCI_DEVICE(0x4222, 0x1005, il3945_bg_cfg)},
2736 {IL_PCI_DEVICE(0x4222, 0x1034, il3945_bg_cfg)},
2737 {IL_PCI_DEVICE(0x4222, 0x1044, il3945_bg_cfg)},
2738 {IL_PCI_DEVICE(0x4227, 0x1014, il3945_bg_cfg)},
2739 {IL_PCI_DEVICE(0x4222, PCI_ANY_ID, il3945_abg_cfg)},
2740 {IL_PCI_DEVICE(0x4227, PCI_ANY_ID, il3945_abg_cfg)},
2741 {0}
2742 };
2743
2744 MODULE_DEVICE_TABLE(pci, il3945_hw_card_ids);