OMAPDSS: VENC: fix NULL pointer dereference in DSS2 VENC sysfs debug attr on OMAP4
[zen-stable.git] / drivers / net / wireless / iwlwifi / iwl-eeprom.h
blob9fa937ec35e38ca314284453ebad05de058c505e
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63 #ifndef __iwl_eeprom_h__
64 #define __iwl_eeprom_h__
66 #include <net/mac80211.h>
68 struct iwl_priv;
69 struct iwl_shared;
72 * EEPROM access time values:
74 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
75 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
76 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
77 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
79 #define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
81 #define IWL_EEPROM_SEM_TIMEOUT 10 /* microseconds */
82 #define IWL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
86 * Regulatory channel usage flags in EEPROM struct iwl4965_eeprom_channel.flags.
88 * IBSS and/or AP operation is allowed *only* on those channels with
89 * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because
90 * RADAR detection is not supported by the 4965 driver, but is a
91 * requirement for establishing a new network for legal operation on channels
92 * requiring RADAR detection or restricting ACTIVE scanning.
94 * NOTE: "WIDE" flag does not indicate anything about "HT40" 40 MHz channels.
95 * It only indicates that 20 MHz channel use is supported; HT40 channel
96 * usage is indicated by a separate set of regulatory flags for each
97 * HT40 channel pair.
99 * NOTE: Using a channel inappropriately will result in a uCode error!
101 #define IWL_NUM_TX_CALIB_GROUPS 5
102 enum {
103 EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */
104 EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */
105 /* Bit 2 Reserved */
106 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */
107 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */
108 EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */
109 /* Bit 6 Reserved (was Narrow Channel) */
110 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */
113 /* SKU Capabilities */
114 #define EEPROM_SKU_CAP_BAND_24GHZ (1 << 4)
115 #define EEPROM_SKU_CAP_BAND_52GHZ (1 << 5)
116 #define EEPROM_SKU_CAP_11N_ENABLE (1 << 6)
117 #define EEPROM_SKU_CAP_AMT_ENABLE (1 << 7)
118 #define EEPROM_SKU_CAP_IPAN_ENABLE (1 << 8)
120 /* *regulatory* channel data format in eeprom, one for each channel.
121 * There are separate entries for HT40 (40 MHz) vs. normal (20 MHz) channels. */
122 struct iwl_eeprom_channel {
123 u8 flags; /* EEPROM_CHANNEL_* flags copied from EEPROM */
124 s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */
125 } __packed;
127 enum iwl_eeprom_enhanced_txpwr_flags {
128 IWL_EEPROM_ENH_TXP_FL_VALID = BIT(0),
129 IWL_EEPROM_ENH_TXP_FL_BAND_52G = BIT(1),
130 IWL_EEPROM_ENH_TXP_FL_OFDM = BIT(2),
131 IWL_EEPROM_ENH_TXP_FL_40MHZ = BIT(3),
132 IWL_EEPROM_ENH_TXP_FL_HT_AP = BIT(4),
133 IWL_EEPROM_ENH_TXP_FL_RES1 = BIT(5),
134 IWL_EEPROM_ENH_TXP_FL_RES2 = BIT(6),
135 IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE = BIT(7),
139 * iwl_eeprom_enhanced_txpwr structure
140 * This structure presents the enhanced regulatory tx power limit layout
141 * in eeprom image
142 * Enhanced regulatory tx power portion of eeprom image can be broken down
143 * into individual structures; each one is 8 bytes in size and contain the
144 * following information
145 * @flags: entry flags
146 * @channel: channel number
147 * @chain_a_max_pwr: chain a max power in 1/2 dBm
148 * @chain_b_max_pwr: chain b max power in 1/2 dBm
149 * @chain_c_max_pwr: chain c max power in 1/2 dBm
150 * @delta_20_in_40: 20-in-40 deltas (hi/lo)
151 * @mimo2_max_pwr: mimo2 max power in 1/2 dBm
152 * @mimo3_max_pwr: mimo3 max power in 1/2 dBm
155 struct iwl_eeprom_enhanced_txpwr {
156 u8 flags;
157 u8 channel;
158 s8 chain_a_max;
159 s8 chain_b_max;
160 s8 chain_c_max;
161 u8 delta_20_in_40;
162 s8 mimo2_max;
163 s8 mimo3_max;
164 } __packed;
166 /* calibration */
167 struct iwl_eeprom_calib_hdr {
168 u8 version;
169 u8 pa_type;
170 __le16 voltage;
171 } __packed;
173 #define EEPROM_CALIB_ALL (INDIRECT_ADDRESS | INDIRECT_CALIBRATION)
174 #define EEPROM_XTAL ((2*0x128) | EEPROM_CALIB_ALL)
176 /* temperature */
177 #define EEPROM_KELVIN_TEMPERATURE ((2*0x12A) | EEPROM_CALIB_ALL)
178 #define EEPROM_RAW_TEMPERATURE ((2*0x12B) | EEPROM_CALIB_ALL)
181 /* agn links */
182 #define EEPROM_LINK_HOST (2*0x64)
183 #define EEPROM_LINK_GENERAL (2*0x65)
184 #define EEPROM_LINK_REGULATORY (2*0x66)
185 #define EEPROM_LINK_CALIBRATION (2*0x67)
186 #define EEPROM_LINK_PROCESS_ADJST (2*0x68)
187 #define EEPROM_LINK_OTHERS (2*0x69)
188 #define EEPROM_LINK_TXP_LIMIT (2*0x6a)
189 #define EEPROM_LINK_TXP_LIMIT_SIZE (2*0x6b)
191 /* agn regulatory - indirect access */
192 #define EEPROM_REG_BAND_1_CHANNELS ((0x08)\
193 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 28 bytes */
194 #define EEPROM_REG_BAND_2_CHANNELS ((0x26)\
195 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 26 bytes */
196 #define EEPROM_REG_BAND_3_CHANNELS ((0x42)\
197 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 24 bytes */
198 #define EEPROM_REG_BAND_4_CHANNELS ((0x5C)\
199 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 22 bytes */
200 #define EEPROM_REG_BAND_5_CHANNELS ((0x74)\
201 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 12 bytes */
202 #define EEPROM_REG_BAND_24_HT40_CHANNELS ((0x82)\
203 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 14 bytes */
204 #define EEPROM_REG_BAND_52_HT40_CHANNELS ((0x92)\
205 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 22 bytes */
207 /* 6000 regulatory - indirect access */
208 #define EEPROM_6000_REG_BAND_24_HT40_CHANNELS ((0x80)\
209 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 14 bytes */
211 /* 5000 Specific */
212 #define EEPROM_5000_TX_POWER_VERSION (4)
213 #define EEPROM_5000_EEPROM_VERSION (0x11A)
215 /* 5050 Specific */
216 #define EEPROM_5050_TX_POWER_VERSION (4)
217 #define EEPROM_5050_EEPROM_VERSION (0x21E)
219 /* 1000 Specific */
220 #define EEPROM_1000_TX_POWER_VERSION (4)
221 #define EEPROM_1000_EEPROM_VERSION (0x15C)
223 /* 6x00 Specific */
224 #define EEPROM_6000_TX_POWER_VERSION (4)
225 #define EEPROM_6000_EEPROM_VERSION (0x423)
227 /* 6x50 Specific */
228 #define EEPROM_6050_TX_POWER_VERSION (4)
229 #define EEPROM_6050_EEPROM_VERSION (0x532)
231 /* 6150 Specific */
232 #define EEPROM_6150_TX_POWER_VERSION (6)
233 #define EEPROM_6150_EEPROM_VERSION (0x553)
235 /* 6x05 Specific */
236 #define EEPROM_6005_TX_POWER_VERSION (6)
237 #define EEPROM_6005_EEPROM_VERSION (0x709)
239 /* 6x30 Specific */
240 #define EEPROM_6030_TX_POWER_VERSION (6)
241 #define EEPROM_6030_EEPROM_VERSION (0x709)
243 /* 2x00 Specific */
244 #define EEPROM_2000_TX_POWER_VERSION (6)
245 #define EEPROM_2000_EEPROM_VERSION (0x805)
247 /* 6x35 Specific */
248 #define EEPROM_6035_TX_POWER_VERSION (6)
249 #define EEPROM_6035_EEPROM_VERSION (0x753)
252 /* OTP */
253 /* lower blocks contain EEPROM image and calibration data */
254 #define OTP_LOW_IMAGE_SIZE (2 * 512 * sizeof(u16)) /* 2 KB */
255 /* high blocks contain PAPD data */
256 #define OTP_HIGH_IMAGE_SIZE_6x00 (6 * 512 * sizeof(u16)) /* 6 KB */
257 #define OTP_HIGH_IMAGE_SIZE_1000 (0x200 * sizeof(u16)) /* 1024 bytes */
258 #define OTP_MAX_LL_ITEMS_1000 (3) /* OTP blocks for 1000 */
259 #define OTP_MAX_LL_ITEMS_6x00 (4) /* OTP blocks for 6x00 */
260 #define OTP_MAX_LL_ITEMS_6x50 (7) /* OTP blocks for 6x50 */
261 #define OTP_MAX_LL_ITEMS_2x00 (4) /* OTP blocks for 2x00 */
263 /* 2.4 GHz */
264 extern const u8 iwl_eeprom_band_1[14];
266 #define ADDRESS_MSK 0x0000FFFF
267 #define INDIRECT_TYPE_MSK 0x000F0000
268 #define INDIRECT_HOST 0x00010000
269 #define INDIRECT_GENERAL 0x00020000
270 #define INDIRECT_REGULATORY 0x00030000
271 #define INDIRECT_CALIBRATION 0x00040000
272 #define INDIRECT_PROCESS_ADJST 0x00050000
273 #define INDIRECT_OTHERS 0x00060000
274 #define INDIRECT_TXP_LIMIT 0x00070000
275 #define INDIRECT_TXP_LIMIT_SIZE 0x00080000
276 #define INDIRECT_ADDRESS 0x00100000
278 /* General */
279 #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
280 #define EEPROM_SUBSYSTEM_ID (2*0x0A) /* 2 bytes */
281 #define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
282 #define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
283 #define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
284 #define EEPROM_VERSION (2*0x44) /* 2 bytes */
285 #define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */
286 #define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
287 #define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */
288 #define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */
290 /* The following masks are to be applied on EEPROM_RADIO_CONFIG */
291 #define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */
292 #define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */
293 #define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */
294 #define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */
295 #define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */
296 #define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */
298 #define EEPROM_RF_CONFIG_TYPE_MAX 0x3
300 #define EEPROM_REGULATORY_BAND_NO_HT40 (0)
302 struct iwl_eeprom_ops {
303 const u32 regulatory_bands[7];
304 void (*update_enhanced_txpower) (struct iwl_priv *priv);
308 int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev);
309 void iwl_eeprom_free(struct iwl_shared *shrd);
310 int iwl_eeprom_check_version(struct iwl_priv *priv);
311 int iwl_eeprom_check_sku(struct iwl_priv *priv);
312 const u8 *iwl_eeprom_query_addr(const struct iwl_shared *shrd, size_t offset);
313 u16 iwl_eeprom_query16(const struct iwl_shared *shrd, size_t offset);
314 int iwl_init_channel_map(struct iwl_priv *priv);
315 void iwl_free_channel_map(struct iwl_priv *priv);
316 const struct iwl_channel_info *iwl_get_channel_info(
317 const struct iwl_priv *priv,
318 enum ieee80211_band band, u16 channel);
319 void iwl_rf_config(struct iwl_priv *priv);
321 #endif /* __iwl_eeprom_h__ */