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OMAPDSS: VENC: fix NULL pointer dereference in DSS2 VENC sysfs debug attr on OMAP4
[zen-stable.git] / drivers / net / wireless / rtlwifi / rtl8192cu / hw.c
blobd3a93410bdca747d563cb456350f2c7aeffb8149
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32 #include "../wifi.h"
33 #include "../efuse.h"
34 #include "../base.h"
35 #include "../cam.h"
36 #include "../ps.h"
37 #include "../usb.h"
38 #include "reg.h"
39 #include "def.h"
40 #include "phy.h"
41 #include "mac.h"
42 #include "dm.h"
43 #include "hw.h"
44 #include "../rtl8192ce/hw.h"
45 #include "trx.h"
46 #include "led.h"
47 #include "table.h"
48
49 static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw)
50 {
51 struct rtl_priv *rtlpriv = rtl_priv(hw);
52 struct rtl_phy *rtlphy = &(rtlpriv->phy);
53 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
54
55 rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH;
56 rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY;
57 if (IS_HIGHT_PA(rtlefuse->board_type)) {
58 rtlphy->hwparam_tables[PHY_REG_PG].length =
59 RTL8192CUPHY_REG_Array_PG_HPLength;
60 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
61 RTL8192CUPHY_REG_Array_PG_HP;
62 } else {
63 rtlphy->hwparam_tables[PHY_REG_PG].length =
64 RTL8192CUPHY_REG_ARRAY_PGLENGTH;
65 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
66 RTL8192CUPHY_REG_ARRAY_PG;
67 }
68 /* 2T */
69 rtlphy->hwparam_tables[PHY_REG_2T].length =
70 RTL8192CUPHY_REG_2TARRAY_LENGTH;
71 rtlphy->hwparam_tables[PHY_REG_2T].pdata =
72 RTL8192CUPHY_REG_2TARRAY;
73 rtlphy->hwparam_tables[RADIOA_2T].length =
74 RTL8192CURADIOA_2TARRAYLENGTH;
75 rtlphy->hwparam_tables[RADIOA_2T].pdata =
76 RTL8192CURADIOA_2TARRAY;
77 rtlphy->hwparam_tables[RADIOB_2T].length =
78 RTL8192CURADIOB_2TARRAYLENGTH;
79 rtlphy->hwparam_tables[RADIOB_2T].pdata =
80 RTL8192CU_RADIOB_2TARRAY;
81 rtlphy->hwparam_tables[AGCTAB_2T].length =
82 RTL8192CUAGCTAB_2TARRAYLENGTH;
83 rtlphy->hwparam_tables[AGCTAB_2T].pdata =
84 RTL8192CUAGCTAB_2TARRAY;
85 /* 1T */
86 if (IS_HIGHT_PA(rtlefuse->board_type)) {
87 rtlphy->hwparam_tables[PHY_REG_1T].length =
88 RTL8192CUPHY_REG_1T_HPArrayLength;
89 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
90 RTL8192CUPHY_REG_1T_HPArray;
91 rtlphy->hwparam_tables[RADIOA_1T].length =
92 RTL8192CURadioA_1T_HPArrayLength;
93 rtlphy->hwparam_tables[RADIOA_1T].pdata =
94 RTL8192CURadioA_1T_HPArray;
95 rtlphy->hwparam_tables[RADIOB_1T].length =
96 RTL8192CURADIOB_1TARRAYLENGTH;
97 rtlphy->hwparam_tables[RADIOB_1T].pdata =
98 RTL8192CU_RADIOB_1TARRAY;
99 rtlphy->hwparam_tables[AGCTAB_1T].length =
100 RTL8192CUAGCTAB_1T_HPArrayLength;
101 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
102 Rtl8192CUAGCTAB_1T_HPArray;
103 } else {
104 rtlphy->hwparam_tables[PHY_REG_1T].length =
105 RTL8192CUPHY_REG_1TARRAY_LENGTH;
106 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
107 RTL8192CUPHY_REG_1TARRAY;
108 rtlphy->hwparam_tables[RADIOA_1T].length =
109 RTL8192CURADIOA_1TARRAYLENGTH;
110 rtlphy->hwparam_tables[RADIOA_1T].pdata =
111 RTL8192CU_RADIOA_1TARRAY;
112 rtlphy->hwparam_tables[RADIOB_1T].length =
113 RTL8192CURADIOB_1TARRAYLENGTH;
114 rtlphy->hwparam_tables[RADIOB_1T].pdata =
115 RTL8192CU_RADIOB_1TARRAY;
116 rtlphy->hwparam_tables[AGCTAB_1T].length =
117 RTL8192CUAGCTAB_1TARRAYLENGTH;
118 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
119 RTL8192CUAGCTAB_1TARRAY;
120 }
121 }
122
123 static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
124 bool autoload_fail,
125 u8 *hwinfo)
126 {
127 struct rtl_priv *rtlpriv = rtl_priv(hw);
128 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
129 u8 rf_path, index, tempval;
130 u16 i;
131
132 for (rf_path = 0; rf_path < 2; rf_path++) {
133 for (i = 0; i < 3; i++) {
134 if (!autoload_fail) {
135 rtlefuse->
136 eeprom_chnlarea_txpwr_cck[rf_path][i] =
137 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
138 rtlefuse->
139 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
140 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
141 i];
142 } else {
143 rtlefuse->
144 eeprom_chnlarea_txpwr_cck[rf_path][i] =
145 EEPROM_DEFAULT_TXPOWERLEVEL;
146 rtlefuse->
147 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
148 EEPROM_DEFAULT_TXPOWERLEVEL;
149 }
150 }
151 }
152 for (i = 0; i < 3; i++) {
153 if (!autoload_fail)
154 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
155 else
156 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
157 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_A][i] =
158 (tempval & 0xf);
159 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_B][i] =
160 ((tempval & 0xf0) >> 4);
161 }
162 for (rf_path = 0; rf_path < 2; rf_path++)
163 for (i = 0; i < 3; i++)
164 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
165 ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
166 i, rtlefuse->
167 eeprom_chnlarea_txpwr_cck[rf_path][i]));
168 for (rf_path = 0; rf_path < 2; rf_path++)
169 for (i = 0; i < 3; i++)
170 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
171 ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
172 rf_path, i,
173 rtlefuse->
174 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]));
175 for (rf_path = 0; rf_path < 2; rf_path++)
176 for (i = 0; i < 3; i++)
177 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
178 ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
179 rf_path, i,
180 rtlefuse->
181 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
182 [i]));
183 for (rf_path = 0; rf_path < 2; rf_path++) {
184 for (i = 0; i < 14; i++) {
185 index = _rtl92c_get_chnl_group((u8) i);
186 rtlefuse->txpwrlevel_cck[rf_path][i] =
187 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
188 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
189 rtlefuse->
190 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
191 if ((rtlefuse->
192 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
193 rtlefuse->
194 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][index])
195 > 0) {
196 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
197 rtlefuse->
198 eeprom_chnlarea_txpwr_ht40_1s[rf_path]
199 [index] - rtlefuse->
200 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
201 [index];
202 } else {
203 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
204 }
205 }
206 for (i = 0; i < 14; i++) {
207 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
208 ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
209 "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
210 rtlefuse->txpwrlevel_cck[rf_path][i],
211 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
212 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]));
213 }
214 }
215 for (i = 0; i < 3; i++) {
216 if (!autoload_fail) {
217 rtlefuse->eeprom_pwrlimit_ht40[i] =
218 hwinfo[EEPROM_TXPWR_GROUP + i];
219 rtlefuse->eeprom_pwrlimit_ht20[i] =
220 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
221 } else {
222 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
223 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
224 }
225 }
226 for (rf_path = 0; rf_path < 2; rf_path++) {
227 for (i = 0; i < 14; i++) {
228 index = _rtl92c_get_chnl_group((u8) i);
229 if (rf_path == RF90_PATH_A) {
230 rtlefuse->pwrgroup_ht20[rf_path][i] =
231 (rtlefuse->eeprom_pwrlimit_ht20[index]
232 & 0xf);
233 rtlefuse->pwrgroup_ht40[rf_path][i] =
234 (rtlefuse->eeprom_pwrlimit_ht40[index]
235 & 0xf);
236 } else if (rf_path == RF90_PATH_B) {
237 rtlefuse->pwrgroup_ht20[rf_path][i] =
238 ((rtlefuse->eeprom_pwrlimit_ht20[index]
239 & 0xf0) >> 4);
240 rtlefuse->pwrgroup_ht40[rf_path][i] =
241 ((rtlefuse->eeprom_pwrlimit_ht40[index]
242 & 0xf0) >> 4);
243 }
244 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
245 ("RF-%d pwrgroup_ht20[%d] = 0x%x\n",
246 rf_path, i,
247 rtlefuse->pwrgroup_ht20[rf_path][i]));
248 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
249 ("RF-%d pwrgroup_ht40[%d] = 0x%x\n",
250 rf_path, i,
251 rtlefuse->pwrgroup_ht40[rf_path][i]));
252 }
253 }
254 for (i = 0; i < 14; i++) {
255 index = _rtl92c_get_chnl_group((u8) i);
256 if (!autoload_fail)
257 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
258 else
259 tempval = EEPROM_DEFAULT_HT20_DIFF;
260 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
261 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
262 ((tempval >> 4) & 0xF);
263 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
264 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
265 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
266 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
267 index = _rtl92c_get_chnl_group((u8) i);
268 if (!autoload_fail)
269 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
270 else
271 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
272 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
273 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
274 ((tempval >> 4) & 0xF);
275 }
276 rtlefuse->legacy_ht_txpowerdiff =
277 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
278 for (i = 0; i < 14; i++)
279 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
280 ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
281 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]));
282 for (i = 0; i < 14; i++)
283 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
284 ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
285 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]));
286 for (i = 0; i < 14; i++)
287 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
288 ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
289 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]));
290 for (i = 0; i < 14; i++)
291 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
292 ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
293 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]));
294 if (!autoload_fail)
295 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
296 else
297 rtlefuse->eeprom_regulatory = 0;
298 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
299 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory));
300 if (!autoload_fail) {
301 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
302 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
303 } else {
304 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
305 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
306 }
307 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
308 ("TSSI_A = 0x%x, TSSI_B = 0x%x\n",
309 rtlefuse->eeprom_tssi[RF90_PATH_A],
310 rtlefuse->eeprom_tssi[RF90_PATH_B]));
311 if (!autoload_fail)
312 tempval = hwinfo[EEPROM_THERMAL_METER];
313 else
314 tempval = EEPROM_DEFAULT_THERMALMETER;
315 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
316 if (rtlefuse->eeprom_thermalmeter < 0x06 ||
317 rtlefuse->eeprom_thermalmeter > 0x1c)
318 rtlefuse->eeprom_thermalmeter = 0x12;
319 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
320 rtlefuse->apk_thermalmeterignore = true;
321 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
322 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
323 ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
324 }
325
326 static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents)
327 {
328 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
329 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
330 u8 boardType;
331
332 if (IS_NORMAL_CHIP(rtlhal->version)) {
333 boardType = ((contents[EEPROM_RF_OPT1]) &
334 BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/
335 } else {
336 boardType = contents[EEPROM_RF_OPT4];
337 boardType &= BOARD_TYPE_TEST_MASK;
338 }
339 rtlefuse->board_type = boardType;
340 if (IS_HIGHT_PA(rtlefuse->board_type))
341 rtlefuse->external_pa = 1;
342 pr_info("Board Type %x\n", rtlefuse->board_type);
343
344 #ifdef CONFIG_ANTENNA_DIVERSITY
345 /* Antenna Diversity setting. */
346 if (registry_par->antdiv_cfg == 2) /* 2: From Efuse */
347 rtl_efuse->antenna_cfg = (contents[EEPROM_RF_OPT1]&0x18)>>3;
348 else
349 rtl_efuse->antenna_cfg = registry_par->antdiv_cfg; /* 0:OFF, */
350
351 pr_info("Antenna Config %x\n", rtl_efuse->antenna_cfg);
352 #endif
353 }
354
355 #ifdef CONFIG_BT_COEXIST
356 static void _update_bt_param(_adapter *padapter)
357 {
358 struct btcoexist_priv *pbtpriv = &(padapter->halpriv.bt_coexist);
359 struct registry_priv *registry_par = &padapter->registrypriv;
360 if (2 != registry_par->bt_iso) {
361 /* 0:Low, 1:High, 2:From Efuse */
362 pbtpriv->BT_Ant_isolation = registry_par->bt_iso;
363 }
364 if (registry_par->bt_sco == 1) {
365 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter, 4.Busy,
366 * 5.OtherBusy */
367 pbtpriv->BT_Service = BT_OtherAction;
368 } else if (registry_par->bt_sco == 2) {
369 pbtpriv->BT_Service = BT_SCO;
370 } else if (registry_par->bt_sco == 4) {
371 pbtpriv->BT_Service = BT_Busy;
372 } else if (registry_par->bt_sco == 5) {
373 pbtpriv->BT_Service = BT_OtherBusy;
374 } else {
375 pbtpriv->BT_Service = BT_Idle;
376 }
377 pbtpriv->BT_Ampdu = registry_par->bt_ampdu;
378 pbtpriv->bCOBT = _TRUE;
379 pbtpriv->BtEdcaUL = 0;
380 pbtpriv->BtEdcaDL = 0;
381 pbtpriv->BtRssiState = 0xff;
382 pbtpriv->bInitSet = _FALSE;
383 pbtpriv->bBTBusyTraffic = _FALSE;
384 pbtpriv->bBTTrafficModeSet = _FALSE;
385 pbtpriv->bBTNonTrafficModeSet = _FALSE;
386 pbtpriv->CurrentState = 0;
387 pbtpriv->PreviousState = 0;
388 pr_info("BT Coexistance = %s\n",
389 (pbtpriv->BT_Coexist == _TRUE) ? "enable" : "disable");
390 if (pbtpriv->BT_Coexist) {
391 if (pbtpriv->BT_Ant_Num == Ant_x2)
392 pr_info("BlueTooth BT_Ant_Num = Antx2\n");
393 else if (pbtpriv->BT_Ant_Num == Ant_x1)
394 pr_info("BlueTooth BT_Ant_Num = Antx1\n");
395 switch (pbtpriv->BT_CoexistType) {
396 case BT_2Wire:
397 pr_info("BlueTooth BT_CoexistType = BT_2Wire\n");
398 break;
399 case BT_ISSC_3Wire:
400 pr_info("BlueTooth BT_CoexistType = BT_ISSC_3Wire\n");
401 break;
402 case BT_Accel:
403 pr_info("BlueTooth BT_CoexistType = BT_Accel\n");
404 break;
405 case BT_CSR_BC4:
406 pr_info("BlueTooth BT_CoexistType = BT_CSR_BC4\n");
407 break;
408 case BT_CSR_BC8:
409 pr_info("BlueTooth BT_CoexistType = BT_CSR_BC8\n");
410 break;
411 case BT_RTL8756:
412 pr_info("BlueTooth BT_CoexistType = BT_RTL8756\n");
413 break;
414 default:
415 pr_info("BlueTooth BT_CoexistType = Unknown\n");
416 break;
417 }
418 pr_info("BlueTooth BT_Ant_isolation = %d\n",
419 pbtpriv->BT_Ant_isolation);
420 switch (pbtpriv->BT_Service) {
421 case BT_OtherAction:
422 pr_info("BlueTooth BT_Service = BT_OtherAction\n");
423 break;
424 case BT_SCO:
425 pr_info("BlueTooth BT_Service = BT_SCO\n");
426 break;
427 case BT_Busy:
428 pr_info("BlueTooth BT_Service = BT_Busy\n");
429 break;
430 case BT_OtherBusy:
431 pr_info("BlueTooth BT_Service = BT_OtherBusy\n");
432 break;
433 default:
434 pr_info("BlueTooth BT_Service = BT_Idle\n");
435 break;
436 }
437 pr_info("BT_RadioSharedType = 0x%x\n",
438 pbtpriv->BT_RadioSharedType);
439 }
440 }
441
442 #define GET_BT_COEXIST(priv) (&priv->bt_coexist)
443
444 static void _rtl92cu_read_bluetooth_coexistInfo(struct ieee80211_hw *hw,
445 u8 *contents,
446 bool bautoloadfailed);
447 {
448 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
449 bool isNormal = IS_NORMAL_CHIP(pHalData->VersionID);
450 struct btcoexist_priv *pbtpriv = &pHalData->bt_coexist;
451 u8 rf_opt4;
452
453 _rtw_memset(pbtpriv, 0, sizeof(struct btcoexist_priv));
454 if (AutoloadFail) {
455 pbtpriv->BT_Coexist = _FALSE;
456 pbtpriv->BT_CoexistType = BT_2Wire;
457 pbtpriv->BT_Ant_Num = Ant_x2;
458 pbtpriv->BT_Ant_isolation = 0;
459 pbtpriv->BT_RadioSharedType = BT_Radio_Shared;
460 return;
461 }
462 if (isNormal) {
463 if (pHalData->BoardType == BOARD_USB_COMBO)
464 pbtpriv->BT_Coexist = _TRUE;
465 else
466 pbtpriv->BT_Coexist = ((PROMContent[EEPROM_RF_OPT3] &
467 0x20) >> 5); /* bit[5] */
468 rf_opt4 = PROMContent[EEPROM_RF_OPT4];
469 pbtpriv->BT_CoexistType = ((rf_opt4&0xe)>>1); /* bit [3:1] */
470 pbtpriv->BT_Ant_Num = (rf_opt4&0x1); /* bit [0] */
471 pbtpriv->BT_Ant_isolation = ((rf_opt4&0x10)>>4); /* bit [4] */
472 pbtpriv->BT_RadioSharedType = ((rf_opt4&0x20)>>5); /* bit [5] */
473 } else {
474 pbtpriv->BT_Coexist = (PROMContent[EEPROM_RF_OPT4] >> 4) ?
475 _TRUE : _FALSE;
476 }
477 _update_bt_param(Adapter);
478 }
479 #endif
480
481 static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw)
482 {
483 struct rtl_priv *rtlpriv = rtl_priv(hw);
484 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
485 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
486 u16 i, usvalue;
487 u8 hwinfo[HWSET_MAX_SIZE] = {0};
488 u16 eeprom_id;
489
490 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
491 rtl_efuse_shadow_map_update(hw);
492 memcpy((void *)hwinfo,
493 (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
494 HWSET_MAX_SIZE);
495 } else if (rtlefuse->epromtype == EEPROM_93C46) {
496 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
497 ("RTL819X Not boot from eeprom, check it !!"));
498 }
499 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_LOUD, ("MAP\n"),
500 hwinfo, HWSET_MAX_SIZE);
501 eeprom_id = le16_to_cpu(*((__le16 *)&hwinfo[0]));
502 if (eeprom_id != RTL8190_EEPROM_ID) {
503 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
504 ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
505 rtlefuse->autoload_failflag = true;
506 } else {
507 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
508 rtlefuse->autoload_failflag = false;
509 }
510 if (rtlefuse->autoload_failflag)
511 return;
512 for (i = 0; i < 6; i += 2) {
513 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
514 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
515 }
516 pr_info("MAC address: %pM\n", rtlefuse->dev_addr);
517 _rtl92cu_read_txpower_info_from_hwpg(hw,
518 rtlefuse->autoload_failflag, hwinfo);
519 rtlefuse->eeprom_vid = le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_VID]);
520 rtlefuse->eeprom_did = le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_DID]);
521 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
522 (" VID = 0x%02x PID = 0x%02x\n",
523 rtlefuse->eeprom_vid, rtlefuse->eeprom_did));
524 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
525 rtlefuse->eeprom_version =
526 le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_VERSION]);
527 rtlefuse->txpwr_fromeprom = true;
528 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
529 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
530 ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid));
531 if (rtlhal->oem_id == RT_CID_DEFAULT) {
532 switch (rtlefuse->eeprom_oemid) {
533 case EEPROM_CID_DEFAULT:
534 if (rtlefuse->eeprom_did == 0x8176) {
535 if ((rtlefuse->eeprom_svid == 0x103C &&
536 rtlefuse->eeprom_smid == 0x1629))
537 rtlhal->oem_id = RT_CID_819x_HP;
538 else
539 rtlhal->oem_id = RT_CID_DEFAULT;
540 } else {
541 rtlhal->oem_id = RT_CID_DEFAULT;
542 }
543 break;
544 case EEPROM_CID_TOSHIBA:
545 rtlhal->oem_id = RT_CID_TOSHIBA;
546 break;
547 case EEPROM_CID_QMI:
548 rtlhal->oem_id = RT_CID_819x_QMI;
549 break;
550 case EEPROM_CID_WHQL:
551 default:
552 rtlhal->oem_id = RT_CID_DEFAULT;
553 break;
554 }
555 }
556 _rtl92cu_read_board_type(hw, hwinfo);
557 #ifdef CONFIG_BT_COEXIST
558 _rtl92cu_read_bluetooth_coexistInfo(hw, hwinfo,
559 rtlefuse->autoload_failflag);
560 #endif
561 }
562
563 static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw)
564 {
565 struct rtl_priv *rtlpriv = rtl_priv(hw);
566 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
567 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
568
569 switch (rtlhal->oem_id) {
570 case RT_CID_819x_HP:
571 usb_priv->ledctl.led_opendrain = true;
572 break;
573 case RT_CID_819x_Lenovo:
574 case RT_CID_DEFAULT:
575 case RT_CID_TOSHIBA:
576 case RT_CID_CCX:
577 case RT_CID_819x_Acer:
578 case RT_CID_WHQL:
579 default:
580 break;
581 }
582 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
583 ("RT Customized ID: 0x%02X\n", rtlhal->oem_id));
584 }
585
586 void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw)
587 {
588
589 struct rtl_priv *rtlpriv = rtl_priv(hw);
590 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
591 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
592 u8 tmp_u1b;
593
594 if (!IS_NORMAL_CHIP(rtlhal->version))
595 return;
596 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
597 rtlefuse->epromtype = (tmp_u1b & BOOT_FROM_EEPROM) ?
598 EEPROM_93C46 : EEPROM_BOOT_EFUSE;
599 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from %s\n",
600 (tmp_u1b & BOOT_FROM_EEPROM) ? "EERROM" : "EFUSE"));
601 rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true;
602 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload %s\n",
603 (tmp_u1b & EEPROM_EN) ? "OK!!" : "ERR!!"));
604 _rtl92cu_read_adapter_info(hw);
605 _rtl92cu_hal_customized_behavior(hw);
606 return;
607 }
608
609 static int _rtl92cu_init_power_on(struct ieee80211_hw *hw)
610 {
611 struct rtl_priv *rtlpriv = rtl_priv(hw);
612 int status = 0;
613 u16 value16;
614 u8 value8;
615 /* polling autoload done. */
616 u32 pollingCount = 0;
617
618 do {
619 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) {
620 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
621 ("Autoload Done!\n"));
622 break;
623 }
624 if (pollingCount++ > 100) {
625 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
626 ("Failed to polling REG_APS_FSMCO[PFM_ALDN]"
627 " done!\n"));
628 return -ENODEV;
629 }
630 } while (true);
631 /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */
632 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
633 /* Power on when re-enter from IPS/Radio off/card disable */
634 /* enable SPS into PWM mode */
635 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
636 udelay(100);
637 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
638 if (0 == (value8 & LDV12_EN)) {
639 value8 |= LDV12_EN;
640 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
641 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
642 (" power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x.\n",
643 value8));
644 udelay(100);
645 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
646 value8 &= ~ISO_MD2PP;
647 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8);
648 }
649 /* auto enable WLAN */
650 pollingCount = 0;
651 value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO);
652 value16 |= APFM_ONMAC;
653 rtl_write_word(rtlpriv, REG_APS_FSMCO, value16);
654 do {
655 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) {
656 pr_info("MAC auto ON okay!\n");
657 break;
658 }
659 if (pollingCount++ > 100) {
660 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
661 ("Failed to polling REG_APS_FSMCO[APFM_ONMAC]"
662 " done!\n"));
663 return -ENODEV;
664 }
665 } while (true);
666 /* Enable Radio ,GPIO ,and LED function */
667 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812);
668 /* release RF digital isolation */
669 value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
670 value16 &= ~ISO_DIOR;
671 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16);
672 /* Reconsider when to do this operation after asking HWSD. */
673 pollingCount = 0;
674 rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv,
675 REG_APSD_CTRL) & ~BIT(6)));
676 do {
677 pollingCount++;
678 } while ((pollingCount < 200) &&
679 (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7)));
680 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
681 value16 = rtl_read_word(rtlpriv, REG_CR);
682 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |
683 PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC);
684 rtl_write_word(rtlpriv, REG_CR, value16);
685 return status;
686 }
687
688 static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw,
689 bool wmm_enable,
690 u8 out_ep_num,
691 u8 queue_sel)
692 {
693 struct rtl_priv *rtlpriv = rtl_priv(hw);
694 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
695 bool isChipN = IS_NORMAL_CHIP(rtlhal->version);
696 u32 outEPNum = (u32)out_ep_num;
697 u32 numHQ = 0;
698 u32 numLQ = 0;
699 u32 numNQ = 0;
700 u32 numPubQ;
701 u32 value32;
702 u8 value8;
703 u32 txQPageNum, txQPageUnit, txQRemainPage;
704
705 if (!wmm_enable) {
706 numPubQ = (isChipN) ? CHIP_B_PAGE_NUM_PUBQ :
707 CHIP_A_PAGE_NUM_PUBQ;
708 txQPageNum = TX_TOTAL_PAGE_NUMBER - numPubQ;
709
710 txQPageUnit = txQPageNum/outEPNum;
711 txQRemainPage = txQPageNum % outEPNum;
712 if (queue_sel & TX_SELE_HQ)
713 numHQ = txQPageUnit;
714 if (queue_sel & TX_SELE_LQ)
715 numLQ = txQPageUnit;
716 /* HIGH priority queue always present in the configuration of
717 * 2 out-ep. Remainder pages have assigned to High queue */
718 if ((outEPNum > 1) && (txQRemainPage))
719 numHQ += txQRemainPage;
720 /* NOTE: This step done before writting REG_RQPN. */
721 if (isChipN) {
722 if (queue_sel & TX_SELE_NQ)
723 numNQ = txQPageUnit;
724 value8 = (u8)_NPQ(numNQ);
725 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
726 }
727 } else {
728 /* for WMM ,number of out-ep must more than or equal to 2! */
729 numPubQ = isChipN ? WMM_CHIP_B_PAGE_NUM_PUBQ :
730 WMM_CHIP_A_PAGE_NUM_PUBQ;
731 if (queue_sel & TX_SELE_HQ) {
732 numHQ = isChipN ? WMM_CHIP_B_PAGE_NUM_HPQ :
733 WMM_CHIP_A_PAGE_NUM_HPQ;
734 }
735 if (queue_sel & TX_SELE_LQ) {
736 numLQ = isChipN ? WMM_CHIP_B_PAGE_NUM_LPQ :
737 WMM_CHIP_A_PAGE_NUM_LPQ;
738 }
739 /* NOTE: This step done before writting REG_RQPN. */
740 if (isChipN) {
741 if (queue_sel & TX_SELE_NQ)
742 numNQ = WMM_CHIP_B_PAGE_NUM_NPQ;
743 value8 = (u8)_NPQ(numNQ);
744 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
745 }
746 }
747 /* TX DMA */
748 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
749 rtl_write_dword(rtlpriv, REG_RQPN, value32);
750 }
751
752 static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable)
753 {
754 struct rtl_priv *rtlpriv = rtl_priv(hw);
755 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
756 u8 txpktbuf_bndy;
757 u8 value8;
758
759 if (!wmm_enable)
760 txpktbuf_bndy = TX_PAGE_BOUNDARY;
761 else /* for WMM */
762 txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version))
763 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
764 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
765 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
766 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
767 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
768 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
769 rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy);
770 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
771 value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128);
772 rtl_write_byte(rtlpriv, REG_PBP, value8);
773 }
774
775 static void _rtl92c_init_chipN_reg_priority(struct ieee80211_hw *hw, u16 beQ,
776 u16 bkQ, u16 viQ, u16 voQ,
777 u16 mgtQ, u16 hiQ)
778 {
779 struct rtl_priv *rtlpriv = rtl_priv(hw);
780 u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7);
781
782 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
783 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
784 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
785 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, value16);
786 }
787
788 static void _rtl92cu_init_chipN_one_out_ep_priority(struct ieee80211_hw *hw,
789 bool wmm_enable,
790 u8 queue_sel)
791 {
792 u16 uninitialized_var(value);
793
794 switch (queue_sel) {
795 case TX_SELE_HQ:
796 value = QUEUE_HIGH;
797 break;
798 case TX_SELE_LQ:
799 value = QUEUE_LOW;
800 break;
801 case TX_SELE_NQ:
802 value = QUEUE_NORMAL;
803 break;
804 default:
805 WARN_ON(1); /* Shall not reach here! */
806 break;
807 }
808 _rtl92c_init_chipN_reg_priority(hw, value, value, value, value,
809 value, value);
810 pr_info("Tx queue select: 0x%02x\n", queue_sel);
811 }
812
813 static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw,
814 bool wmm_enable,
815 u8 queue_sel)
816 {
817 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
818 u16 uninitialized_var(valueHi);
819 u16 uninitialized_var(valueLow);
820
821 switch (queue_sel) {
822 case (TX_SELE_HQ | TX_SELE_LQ):
823 valueHi = QUEUE_HIGH;
824 valueLow = QUEUE_LOW;
825 break;
826 case (TX_SELE_NQ | TX_SELE_LQ):
827 valueHi = QUEUE_NORMAL;
828 valueLow = QUEUE_LOW;
829 break;
830 case (TX_SELE_HQ | TX_SELE_NQ):
831 valueHi = QUEUE_HIGH;
832 valueLow = QUEUE_NORMAL;
833 break;
834 default:
835 WARN_ON(1);
836 break;
837 }
838 if (!wmm_enable) {
839 beQ = valueLow;
840 bkQ = valueLow;
841 viQ = valueHi;
842 voQ = valueHi;
843 mgtQ = valueHi;
844 hiQ = valueHi;
845 } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
846 beQ = valueHi;
847 bkQ = valueLow;
848 viQ = valueLow;
849 voQ = valueHi;
850 mgtQ = valueHi;
851 hiQ = valueHi;
852 }
853 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
854 pr_info("Tx queue select: 0x%02x\n", queue_sel);
855 }
856
857 static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw,
858 bool wmm_enable,
859 u8 queue_sel)
860 {
861 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
862 struct rtl_priv *rtlpriv = rtl_priv(hw);
863
864 if (!wmm_enable) { /* typical setting */
865 beQ = QUEUE_LOW;
866 bkQ = QUEUE_LOW;
867 viQ = QUEUE_NORMAL;
868 voQ = QUEUE_HIGH;
869 mgtQ = QUEUE_HIGH;
870 hiQ = QUEUE_HIGH;
871 } else { /* for WMM */
872 beQ = QUEUE_LOW;
873 bkQ = QUEUE_NORMAL;
874 viQ = QUEUE_NORMAL;
875 voQ = QUEUE_HIGH;
876 mgtQ = QUEUE_HIGH;
877 hiQ = QUEUE_HIGH;
878 }
879 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
880 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
881 ("Tx queue select :0x%02x..\n", queue_sel));
882 }
883
884 static void _rtl92cu_init_chipN_queue_priority(struct ieee80211_hw *hw,
885 bool wmm_enable,
886 u8 out_ep_num,
887 u8 queue_sel)
888 {
889 switch (out_ep_num) {
890 case 1:
891 _rtl92cu_init_chipN_one_out_ep_priority(hw, wmm_enable,
892 queue_sel);
893 break;
894 case 2:
895 _rtl92cu_init_chipN_two_out_ep_priority(hw, wmm_enable,
896 queue_sel);
897 break;
898 case 3:
899 _rtl92cu_init_chipN_three_out_ep_priority(hw, wmm_enable,
900 queue_sel);
901 break;
902 default:
903 WARN_ON(1); /* Shall not reach here! */
904 break;
905 }
906 }
907
908 static void _rtl92cu_init_chipT_queue_priority(struct ieee80211_hw *hw,
909 bool wmm_enable,
910 u8 out_ep_num,
911 u8 queue_sel)
912 {
913 u8 hq_sele = 0;
914 struct rtl_priv *rtlpriv = rtl_priv(hw);
915
916 switch (out_ep_num) {
917 case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */
918 if (!wmm_enable) /* typical setting */
919 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ |
920 HQSEL_HIQ;
921 else /* for WMM */
922 hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ |
923 HQSEL_HIQ;
924 break;
925 case 1:
926 if (TX_SELE_LQ == queue_sel) {
927 /* map all endpoint to Low queue */
928 hq_sele = 0;
929 } else if (TX_SELE_HQ == queue_sel) {
930 /* map all endpoint to High queue */
931 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ |
932 HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ;
933 }
934 break;
935 default:
936 WARN_ON(1); /* Shall not reach here! */
937 break;
938 }
939 rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele);
940 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
941 ("Tx queue select :0x%02x..\n", hq_sele));
942 }
943
944 static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw,
945 bool wmm_enable,
946 u8 out_ep_num,
947 u8 queue_sel)
948 {
949 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
950 if (IS_NORMAL_CHIP(rtlhal->version))
951 _rtl92cu_init_chipN_queue_priority(hw, wmm_enable, out_ep_num,
952 queue_sel);
953 else
954 _rtl92cu_init_chipT_queue_priority(hw, wmm_enable, out_ep_num,
955 queue_sel);
956 }
957
958 static void _rtl92cu_init_usb_aggregation(struct ieee80211_hw *hw)
959 {
960 }
961
962 static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw)
963 {
964 u16 value16;
965
966 struct rtl_priv *rtlpriv = rtl_priv(hw);
967 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
968
969 mac->rx_conf = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APPFCS |
970 RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
971 RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32);
972 rtl_write_dword(rtlpriv, REG_RCR, mac->rx_conf);
973 /* Accept all multicast address */
974 rtl_write_dword(rtlpriv, REG_MAR, 0xFFFFFFFF);
975 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xFFFFFFFF);
976 /* Accept all management frames */
977 value16 = 0xFFFF;
978 rtl92c_set_mgt_filter(hw, value16);
979 /* Reject all control frame - default value is 0 */
980 rtl92c_set_ctrl_filter(hw, 0x0);
981 /* Accept all data frames */
982 value16 = 0xFFFF;
983 rtl92c_set_data_filter(hw, value16);
984 }
985
986 static int _rtl92cu_init_mac(struct ieee80211_hw *hw)
987 {
988 struct rtl_priv *rtlpriv = rtl_priv(hw);
989 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
990 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
991 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
992 int err = 0;
993 u32 boundary = 0;
994 u8 wmm_enable = false; /* TODO */
995 u8 out_ep_nums = rtlusb->out_ep_nums;
996 u8 queue_sel = rtlusb->out_queue_sel;
997 err = _rtl92cu_init_power_on(hw);
998
999 if (err) {
1000 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1001 ("Failed to init power on!\n"));
1002 return err;
1003 }
1004 if (!wmm_enable) {
1005 boundary = TX_PAGE_BOUNDARY;
1006 } else { /* for WMM */
1007 boundary = (IS_NORMAL_CHIP(rtlhal->version))
1008 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
1009 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
1010 }
1011 if (false == rtl92c_init_llt_table(hw, boundary)) {
1012 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1013 ("Failed to init LLT Table!\n"));
1014 return -EINVAL;
1015 }
1016 _rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums,
1017 queue_sel);
1018 _rtl92c_init_trx_buffer(hw, wmm_enable);
1019 _rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums,
1020 queue_sel);
1021 /* Get Rx PHY status in order to report RSSI and others. */
1022 rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE);
1023 rtl92c_init_interrupt(hw);
1024 rtl92c_init_network_type(hw);
1025 _rtl92cu_init_wmac_setting(hw);
1026 rtl92c_init_adaptive_ctrl(hw);
1027 rtl92c_init_edca(hw);
1028 rtl92c_init_rate_fallback(hw);
1029 rtl92c_init_retry_function(hw);
1030 _rtl92cu_init_usb_aggregation(hw);
1031 rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20);
1032 rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version));
1033 rtl92c_init_beacon_parameters(hw, rtlhal->version);
1034 rtl92c_init_ampdu_aggregation(hw);
1035 rtl92c_init_beacon_max_error(hw, true);
1036 return err;
1037 }
1038
1039 void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw)
1040 {
1041 struct rtl_priv *rtlpriv = rtl_priv(hw);
1042 u8 sec_reg_value = 0x0;
1043 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1044
1045 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1046 ("PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1047 rtlpriv->sec.pairwise_enc_algorithm,
1048 rtlpriv->sec.group_enc_algorithm));
1049 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1050 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1051 ("not open sw encryption\n"));
1052 return;
1053 }
1054 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
1055 if (rtlpriv->sec.use_defaultkey) {
1056 sec_reg_value |= SCR_TxUseDK;
1057 sec_reg_value |= SCR_RxUseDK;
1058 }
1059 if (IS_NORMAL_CHIP(rtlhal->version))
1060 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1061 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1062 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
1063 ("The SECR-value %x\n", sec_reg_value));
1064 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1065 }
1066
1067 static void _rtl92cu_hw_configure(struct ieee80211_hw *hw)
1068 {
1069 struct rtl_priv *rtlpriv = rtl_priv(hw);
1070 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1071
1072 /* To Fix MAC loopback mode fail. */
1073 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
1074 rtl_write_byte(rtlpriv, 0x15, 0xe9);
1075 /* HW SEQ CTRL */
1076 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
1077 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
1078 /* fixed USB interface interference issue */
1079 rtl_write_byte(rtlpriv, 0xfe40, 0xe0);
1080 rtl_write_byte(rtlpriv, 0xfe41, 0x8d);
1081 rtl_write_byte(rtlpriv, 0xfe42, 0x80);
1082 rtlusb->reg_bcn_ctrl_val = 0x18;
1083 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
1084 }
1085
1086 static void _InitPABias(struct ieee80211_hw *hw)
1087 {
1088 struct rtl_priv *rtlpriv = rtl_priv(hw);
1089 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1090 u8 pa_setting;
1091
1092 /* FIXED PA current issue */
1093 pa_setting = efuse_read_1byte(hw, 0x1FA);
1094 if (!(pa_setting & BIT(0))) {
1095 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
1096 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
1097 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
1098 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
1099 }
1100 if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) &&
1101 IS_92C_SERIAL(rtlhal->version)) {
1102 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
1103 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
1104 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
1105 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
1106 }
1107 if (!(pa_setting & BIT(4))) {
1108 pa_setting = rtl_read_byte(rtlpriv, 0x16);
1109 pa_setting &= 0x0F;
1110 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90);
1111 }
1112 }
1113
1114 static void _InitAntenna_Selection(struct ieee80211_hw *hw)
1115 {
1116 #ifdef CONFIG_ANTENNA_DIVERSITY
1117 struct rtl_priv *rtlpriv = rtl_priv(hw);
1118 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1119 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1120
1121 if (pHalData->AntDivCfg == 0)
1122 return;
1123
1124 if (rtlphy->rf_type == RF_1T1R) {
1125 rtl_write_dword(rtlpriv, REG_LEDCFG0,
1126 rtl_read_dword(rtlpriv,
1127 REG_LEDCFG0)|BIT(23));
1128 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1129 if (rtl_get_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300) ==
1130 Antenna_A)
1131 pHalData->CurAntenna = Antenna_A;
1132 else
1133 pHalData->CurAntenna = Antenna_B;
1134 }
1135 #endif
1136 }
1137
1138 static void _dump_registers(struct ieee80211_hw *hw)
1139 {
1140 }
1141
1142 static void _update_mac_setting(struct ieee80211_hw *hw)
1143 {
1144 struct rtl_priv *rtlpriv = rtl_priv(hw);
1145 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1146
1147 mac->rx_conf = rtl_read_dword(rtlpriv, REG_RCR);
1148 mac->rx_mgt_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1149 mac->rx_ctrl_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1150 mac->rx_data_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1151 }
1152
1153 int rtl92cu_hw_init(struct ieee80211_hw *hw)
1154 {
1155 struct rtl_priv *rtlpriv = rtl_priv(hw);
1156 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1157 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1158 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1159 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1160 int err = 0;
1161 static bool iqk_initialized;
1162
1163 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU;
1164 err = _rtl92cu_init_mac(hw);
1165 if (err) {
1166 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("init mac failed!\n"));
1167 return err;
1168 }
1169 err = rtl92c_download_fw(hw);
1170 if (err) {
1171 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1172 ("Failed to download FW. Init HW without FW now..\n"));
1173 err = 1;
1174 return err;
1175 }
1176 rtlhal->last_hmeboxnum = 0; /* h2c */
1177 _rtl92cu_phy_param_tab_init(hw);
1178 rtl92cu_phy_mac_config(hw);
1179 rtl92cu_phy_bb_config(hw);
1180 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1181 rtl92c_phy_rf_config(hw);
1182 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
1183 !IS_92C_SERIAL(rtlhal->version)) {
1184 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
1185 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
1186 }
1187 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1188 RF_CHNLBW, RFREG_OFFSET_MASK);
1189 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1190 RF_CHNLBW, RFREG_OFFSET_MASK);
1191 rtl92cu_bb_block_on(hw);
1192 rtl_cam_reset_all_entry(hw);
1193 rtl92cu_enable_hw_security_config(hw);
1194 ppsc->rfpwr_state = ERFON;
1195 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1196 if (ppsc->rfpwr_state == ERFON) {
1197 rtl92c_phy_set_rfpath_switch(hw, 1);
1198 if (iqk_initialized) {
1199 rtl92c_phy_iq_calibrate(hw, false);
1200 } else {
1201 rtl92c_phy_iq_calibrate(hw, false);
1202 iqk_initialized = true;
1203 }
1204 rtl92c_dm_check_txpower_tracking(hw);
1205 rtl92c_phy_lc_calibrate(hw);
1206 }
1207 _rtl92cu_hw_configure(hw);
1208 _InitPABias(hw);
1209 _InitAntenna_Selection(hw);
1210 _update_mac_setting(hw);
1211 rtl92c_dm_init(hw);
1212 _dump_registers(hw);
1213 return err;
1214 }
1215
1216 static void _DisableRFAFEAndResetBB(struct ieee80211_hw *hw)
1217 {
1218 struct rtl_priv *rtlpriv = rtl_priv(hw);
1219 /**************************************
1220 a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue
1221 b. RF path 0 offset 0x00 = 0x00 disable RF
1222 c. APSD_CTRL 0x600[7:0] = 0x40
1223 d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine
1224 e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine
1225 ***************************************/
1226 u8 eRFPath = 0, value8 = 0;
1227 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1228 rtl_set_rfreg(hw, (enum radio_path)eRFPath, 0x0, MASKBYTE0, 0x0);
1229
1230 value8 |= APSDOFF;
1231 rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/
1232 value8 = 0;
1233 value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
1234 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/
1235 value8 &= (~FEN_BB_GLB_RSTn);
1236 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/
1237 }
1238
1239 static void _ResetDigitalProcedure1(struct ieee80211_hw *hw, bool bWithoutHWSM)
1240 {
1241 struct rtl_priv *rtlpriv = rtl_priv(hw);
1242 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1243
1244 if (rtlhal->fw_version <= 0x20) {
1245 /*****************************
1246 f. MCUFWDL 0x80[7:0]=0 reset MCU ready status
1247 g. SYS_FUNC_EN 0x02[10]= 0 reset MCU reg, (8051 reset)
1248 h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC reg, DCORE
1249 i. SYS_FUNC_EN 0x02[10]= 1 enable MCU reg, (8051 enable)
1250 ******************************/
1251 u16 valu16 = 0;
1252
1253 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1254 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1255 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 &
1256 (~FEN_CPUEN))); /* reset MCU ,8051 */
1257 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF;
1258 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1259 (FEN_HWPDN|FEN_ELDR))); /* reset MAC */
1260 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1261 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1262 FEN_CPUEN)); /* enable MCU ,8051 */
1263 } else {
1264 u8 retry_cnts = 0;
1265
1266 /* IF fw in RAM code, do reset */
1267 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) {
1268 /* reset MCU ready status */
1269 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1270 /* 8051 reset by self */
1271 rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20);
1272 while ((retry_cnts++ < 100) &&
1273 (FEN_CPUEN & rtl_read_word(rtlpriv,
1274 REG_SYS_FUNC_EN))) {
1275 udelay(50);
1276 }
1277 if (retry_cnts >= 100) {
1278 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1279 ("#####=> 8051 reset failed!.."
1280 ".......................\n"););
1281 /* if 8051 reset fail, reset MAC. */
1282 rtl_write_byte(rtlpriv,
1283 REG_SYS_FUNC_EN + 1,
1284 0x50);
1285 udelay(100);
1286 }
1287 }
1288 /* Reset MAC and Enable 8051 */
1289 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54);
1290 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1291 }
1292 if (bWithoutHWSM) {
1293 /*****************************
1294 Without HW auto state machine
1295 g.SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock
1296 h.AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL
1297 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK
1298 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9 isolated digital to PON
1299 ******************************/
1300 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1301 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1302 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F);
1303 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9);
1304 }
1305 }
1306
1307 static void _ResetDigitalProcedure2(struct ieee80211_hw *hw)
1308 {
1309 struct rtl_priv *rtlpriv = rtl_priv(hw);
1310 /*****************************
1311 k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction
1312 l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock
1313 m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON
1314 ******************************/
1315 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1316 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82);
1317 }
1318
1319 static void _DisableGPIO(struct ieee80211_hw *hw)
1320 {
1321 struct rtl_priv *rtlpriv = rtl_priv(hw);
1322 /***************************************
1323 j. GPIO_PIN_CTRL 0x44[31:0]=0x000
1324 k. Value = GPIO_PIN_CTRL[7:0]
1325 l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level
1326 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1327 n. LEDCFG 0x4C[15:0] = 0x8080
1328 ***************************************/
1329 u8 value8;
1330 u16 value16;
1331 u32 value32;
1332
1333 /* 1. Disable GPIO[7:0] */
1334 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000);
1335 value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1336 value8 = (u8) (value32&0x000000FF);
1337 value32 |= ((value8<<8) | 0x00FF0000);
1338 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32);
1339 /* 2. Disable GPIO[10:8] */
1340 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00);
1341 value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F;
1342 value8 = (u8) (value16&0x000F);
1343 value16 |= ((value8<<4) | 0x0780);
1344 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16);
1345 /* 3. Disable LED0 & 1 */
1346 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1347 }
1348
1349 static void _DisableAnalog(struct ieee80211_hw *hw, bool bWithoutHWSM)
1350 {
1351 struct rtl_priv *rtlpriv = rtl_priv(hw);
1352 u16 value16 = 0;
1353 u8 value8 = 0;
1354
1355 if (bWithoutHWSM) {
1356 /*****************************
1357 n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power
1358 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power
1359 r. When driver call disable, the ASIC will turn off remaining
1360 clock automatically
1361 ******************************/
1362 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1363 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
1364 value8 &= (~LDV12_EN);
1365 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
1366 }
1367
1368 /*****************************
1369 h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode
1370 i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend
1371 ******************************/
1372 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1373 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
1374 rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16);
1375 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1376 }
1377
1378 static void _CardDisableHWSM(struct ieee80211_hw *hw)
1379 {
1380 /* ==== RF Off Sequence ==== */
1381 _DisableRFAFEAndResetBB(hw);
1382 /* ==== Reset digital sequence ====== */
1383 _ResetDigitalProcedure1(hw, false);
1384 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1385 _DisableGPIO(hw);
1386 /* ==== Disable analog sequence === */
1387 _DisableAnalog(hw, false);
1388 }
1389
1390 static void _CardDisableWithoutHWSM(struct ieee80211_hw *hw)
1391 {
1392 /*==== RF Off Sequence ==== */
1393 _DisableRFAFEAndResetBB(hw);
1394 /* ==== Reset digital sequence ====== */
1395 _ResetDigitalProcedure1(hw, true);
1396 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1397 _DisableGPIO(hw);
1398 /* ==== Reset digital sequence ====== */
1399 _ResetDigitalProcedure2(hw);
1400 /* ==== Disable analog sequence === */
1401 _DisableAnalog(hw, true);
1402 }
1403
1404 static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
1405 u8 set_bits, u8 clear_bits)
1406 {
1407 struct rtl_priv *rtlpriv = rtl_priv(hw);
1408 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1409
1410 rtlusb->reg_bcn_ctrl_val |= set_bits;
1411 rtlusb->reg_bcn_ctrl_val &= ~clear_bits;
1412 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlusb->reg_bcn_ctrl_val);
1413 }
1414
1415 static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw)
1416 {
1417 struct rtl_priv *rtlpriv = rtl_priv(hw);
1418 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1419 u8 tmp1byte = 0;
1420 if (IS_NORMAL_CHIP(rtlhal->version)) {
1421 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1422 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1423 tmp1byte & (~BIT(6)));
1424 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
1425 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1426 tmp1byte &= ~(BIT(0));
1427 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1428 } else {
1429 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1430 rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6));
1431 }
1432 }
1433
1434 static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw)
1435 {
1436 struct rtl_priv *rtlpriv = rtl_priv(hw);
1437 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1438 u8 tmp1byte = 0;
1439
1440 if (IS_NORMAL_CHIP(rtlhal->version)) {
1441 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1442 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1443 tmp1byte | BIT(6));
1444 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1445 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1446 tmp1byte |= BIT(0);
1447 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1448 } else {
1449 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1450 rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6)));
1451 }
1452 }
1453
1454 static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw)
1455 {
1456 struct rtl_priv *rtlpriv = rtl_priv(hw);
1457 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1458
1459 if (IS_NORMAL_CHIP(rtlhal->version))
1460 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1));
1461 else
1462 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1463 }
1464
1465 static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw)
1466 {
1467 struct rtl_priv *rtlpriv = rtl_priv(hw);
1468 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1469
1470 if (IS_NORMAL_CHIP(rtlhal->version))
1471 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0);
1472 else
1473 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1474 }
1475
1476 static int _rtl92cu_set_media_status(struct ieee80211_hw *hw,
1477 enum nl80211_iftype type)
1478 {
1479 struct rtl_priv *rtlpriv = rtl_priv(hw);
1480 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1481 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1482
1483 bt_msr &= 0xfc;
1484 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF);
1485 if (type == NL80211_IFTYPE_UNSPECIFIED || type ==
1486 NL80211_IFTYPE_STATION) {
1487 _rtl92cu_stop_tx_beacon(hw);
1488 _rtl92cu_enable_bcn_sub_func(hw);
1489 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1490 _rtl92cu_resume_tx_beacon(hw);
1491 _rtl92cu_disable_bcn_sub_func(hw);
1492 } else {
1493 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("Set HW_VAR_MEDIA_"
1494 "STATUS:No such media status(%x).\n", type));
1495 }
1496 switch (type) {
1497 case NL80211_IFTYPE_UNSPECIFIED:
1498 bt_msr |= MSR_NOLINK;
1499 ledaction = LED_CTL_LINK;
1500 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1501 ("Set Network type to NO LINK!\n"));
1502 break;
1503 case NL80211_IFTYPE_ADHOC:
1504 bt_msr |= MSR_ADHOC;
1505 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1506 ("Set Network type to Ad Hoc!\n"));
1507 break;
1508 case NL80211_IFTYPE_STATION:
1509 bt_msr |= MSR_INFRA;
1510 ledaction = LED_CTL_LINK;
1511 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1512 ("Set Network type to STA!\n"));
1513 break;
1514 case NL80211_IFTYPE_AP:
1515 bt_msr |= MSR_AP;
1516 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1517 ("Set Network type to AP!\n"));
1518 break;
1519 default:
1520 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1521 ("Network type %d not support!\n", type));
1522 goto error_out;
1523 }
1524 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1525 rtlpriv->cfg->ops->led_control(hw, ledaction);
1526 if ((bt_msr & 0xfc) == MSR_AP)
1527 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1528 else
1529 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1530 return 0;
1531 error_out:
1532 return 1;
1533 }
1534
1535 void rtl92cu_card_disable(struct ieee80211_hw *hw)
1536 {
1537 struct rtl_priv *rtlpriv = rtl_priv(hw);
1538 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1539 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1540 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1541 enum nl80211_iftype opmode;
1542
1543 mac->link_state = MAC80211_NOLINK;
1544 opmode = NL80211_IFTYPE_UNSPECIFIED;
1545 _rtl92cu_set_media_status(hw, opmode);
1546 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1547 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1548 if (rtlusb->disableHWSM)
1549 _CardDisableHWSM(hw);
1550 else
1551 _CardDisableWithoutHWSM(hw);
1552 }
1553
1554 void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1555 {
1556 /* dummy routine needed for callback from rtl_op_configure_filter() */
1557 }
1558
1559 /*========================================================================== */
1560
1561 static void _rtl92cu_set_check_bssid(struct ieee80211_hw *hw,
1562 enum nl80211_iftype type)
1563 {
1564 struct rtl_priv *rtlpriv = rtl_priv(hw);
1565 u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1566 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1567 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1568 u8 filterout_non_associated_bssid = false;
1569
1570 switch (type) {
1571 case NL80211_IFTYPE_ADHOC:
1572 case NL80211_IFTYPE_STATION:
1573 filterout_non_associated_bssid = true;
1574 break;
1575 case NL80211_IFTYPE_UNSPECIFIED:
1576 case NL80211_IFTYPE_AP:
1577 default:
1578 break;
1579 }
1580 if (filterout_non_associated_bssid) {
1581 if (IS_NORMAL_CHIP(rtlhal->version)) {
1582 switch (rtlphy->current_io_type) {
1583 case IO_CMD_RESUME_DM_BY_SCAN:
1584 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1585 rtlpriv->cfg->ops->set_hw_reg(hw,
1586 HW_VAR_RCR, (u8 *)(&reg_rcr));
1587 /* enable update TSF */
1588 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1589 break;
1590 case IO_CMD_PAUSE_DM_BY_SCAN:
1591 reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1592 rtlpriv->cfg->ops->set_hw_reg(hw,
1593 HW_VAR_RCR, (u8 *)(&reg_rcr));
1594 /* disable update TSF */
1595 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1596 break;
1597 }
1598 } else {
1599 reg_rcr |= (RCR_CBSSID);
1600 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1601 (u8 *)(&reg_rcr));
1602 _rtl92cu_set_bcn_ctrl_reg(hw, 0, (BIT(4)|BIT(5)));
1603 }
1604 } else if (filterout_non_associated_bssid == false) {
1605 if (IS_NORMAL_CHIP(rtlhal->version)) {
1606 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1607 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1608 (u8 *)(&reg_rcr));
1609 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1610 } else {
1611 reg_rcr &= (~RCR_CBSSID);
1612 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1613 (u8 *)(&reg_rcr));
1614 _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4)|BIT(5)), 0);
1615 }
1616 }
1617 }
1618
1619 int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1620 {
1621 if (_rtl92cu_set_media_status(hw, type))
1622 return -EOPNOTSUPP;
1623 _rtl92cu_set_check_bssid(hw, type);
1624 return 0;
1625 }
1626
1627 static void _InitBeaconParameters(struct ieee80211_hw *hw)
1628 {
1629 struct rtl_priv *rtlpriv = rtl_priv(hw);
1630 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1631
1632 rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010);
1633
1634 /* TODO: Remove these magic number */
1635 rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404);
1636 rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);
1637 rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
1638 /* Change beacon AIFS to the largest number
1639 * beacause test chip does not contension before sending beacon. */
1640 if (IS_NORMAL_CHIP(rtlhal->version))
1641 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F);
1642 else
1643 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF);
1644 }
1645
1646 static void _beacon_function_enable(struct ieee80211_hw *hw, bool Enable,
1647 bool Linked)
1648 {
1649 struct rtl_priv *rtlpriv = rtl_priv(hw);
1650
1651 _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00);
1652 rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F);
1653 }
1654
1655 void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw)
1656 {
1657
1658 struct rtl_priv *rtlpriv = rtl_priv(hw);
1659 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1660 u16 bcn_interval, atim_window;
1661 u32 value32;
1662
1663 bcn_interval = mac->beacon_interval;
1664 atim_window = 2; /*FIX MERGE */
1665 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1666 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1667 _InitBeaconParameters(hw);
1668 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
1669 /*
1670 * Force beacon frame transmission even after receiving beacon frame
1671 * from other ad hoc STA
1672 *
1673 *
1674 * Reset TSF Timer to zero, added by Roger. 2008.06.24
1675 */
1676 value32 = rtl_read_dword(rtlpriv, REG_TCR);
1677 value32 &= ~TSFRST;
1678 rtl_write_dword(rtlpriv, REG_TCR, value32);
1679 value32 |= TSFRST;
1680 rtl_write_dword(rtlpriv, REG_TCR, value32);
1681 RT_TRACE(rtlpriv, COMP_INIT|COMP_BEACON, DBG_LOUD,
1682 ("SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n",
1683 value32));
1684 /* TODO: Modify later (Find the right parameters)
1685 * NOTE: Fix test chip's bug (about contention windows's randomness) */
1686 if ((mac->opmode == NL80211_IFTYPE_ADHOC) ||
1687 (mac->opmode == NL80211_IFTYPE_AP)) {
1688 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50);
1689 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50);
1690 }
1691 _beacon_function_enable(hw, true, true);
1692 }
1693
1694 void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw)
1695 {
1696 struct rtl_priv *rtlpriv = rtl_priv(hw);
1697 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1698 u16 bcn_interval = mac->beacon_interval;
1699
1700 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1701 ("beacon_interval:%d\n", bcn_interval));
1702 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1703 }
1704
1705 void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
1706 u32 add_msr, u32 rm_msr)
1707 {
1708 }
1709
1710 void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1711 {
1712 struct rtl_priv *rtlpriv = rtl_priv(hw);
1713 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1714 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1715
1716 switch (variable) {
1717 case HW_VAR_RCR:
1718 *((u32 *)(val)) = mac->rx_conf;
1719 break;
1720 case HW_VAR_RF_STATE:
1721 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
1722 break;
1723 case HW_VAR_FWLPS_RF_ON:{
1724 enum rf_pwrstate rfState;
1725 u32 val_rcr;
1726
1727 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
1728 (u8 *)(&rfState));
1729 if (rfState == ERFOFF) {
1730 *((bool *) (val)) = true;
1731 } else {
1732 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1733 val_rcr &= 0x00070000;
1734 if (val_rcr)
1735 *((bool *) (val)) = false;
1736 else
1737 *((bool *) (val)) = true;
1738 }
1739 break;
1740 }
1741 case HW_VAR_FW_PSMODE_STATUS:
1742 *((bool *) (val)) = ppsc->fw_current_inpsmode;
1743 break;
1744 case HW_VAR_CORRECT_TSF:{
1745 u64 tsf;
1746 u32 *ptsf_low = (u32 *)&tsf;
1747 u32 *ptsf_high = ((u32 *)&tsf) + 1;
1748
1749 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
1750 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
1751 *((u64 *)(val)) = tsf;
1752 break;
1753 }
1754 case HW_VAR_MGT_FILTER:
1755 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1756 break;
1757 case HW_VAR_CTRL_FILTER:
1758 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1759 break;
1760 case HW_VAR_DATA_FILTER:
1761 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1762 break;
1763 default:
1764 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1765 ("switch case not process\n"));
1766 break;
1767 }
1768 }
1769
1770 void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1771 {
1772 struct rtl_priv *rtlpriv = rtl_priv(hw);
1773 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1774 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1775 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1776 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1777 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1778 enum wireless_mode wirelessmode = mac->mode;
1779 u8 idx = 0;
1780
1781 switch (variable) {
1782 case HW_VAR_ETHER_ADDR:{
1783 for (idx = 0; idx < ETH_ALEN; idx++) {
1784 rtl_write_byte(rtlpriv, (REG_MACID + idx),
1785 val[idx]);
1786 }
1787 break;
1788 }
1789 case HW_VAR_BASIC_RATE:{
1790 u16 rate_cfg = ((u16 *) val)[0];
1791 u8 rate_index = 0;
1792
1793 rate_cfg &= 0x15f;
1794 /* TODO */
1795 /* if (mac->current_network.vender == HT_IOT_PEER_CISCO
1796 * && ((rate_cfg & 0x150) == 0)) {
1797 * rate_cfg |= 0x010;
1798 * } */
1799 rate_cfg |= 0x01;
1800 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
1801 rtl_write_byte(rtlpriv, REG_RRSR + 1,
1802 (rate_cfg >> 8) & 0xff);
1803 while (rate_cfg > 0x1) {
1804 rate_cfg >>= 1;
1805 rate_index++;
1806 }
1807 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
1808 rate_index);
1809 break;
1810 }
1811 case HW_VAR_BSSID:{
1812 for (idx = 0; idx < ETH_ALEN; idx++) {
1813 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
1814 val[idx]);
1815 }
1816 break;
1817 }
1818 case HW_VAR_SIFS:{
1819 rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]);
1820 rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]);
1821 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
1822 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
1823 rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]);
1824 rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]);
1825 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1826 ("HW_VAR_SIFS\n"));
1827 break;
1828 }
1829 case HW_VAR_SLOT_TIME:{
1830 u8 e_aci;
1831 u8 QOS_MODE = 1;
1832
1833 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
1834 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1835 ("HW_VAR_SLOT_TIME %x\n", val[0]));
1836 if (QOS_MODE) {
1837 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
1838 rtlpriv->cfg->ops->set_hw_reg(hw,
1839 HW_VAR_AC_PARAM,
1840 (u8 *)(&e_aci));
1841 } else {
1842 u8 sifstime = 0;
1843 u8 u1bAIFS;
1844
1845 if (IS_WIRELESS_MODE_A(wirelessmode) ||
1846 IS_WIRELESS_MODE_N_24G(wirelessmode) ||
1847 IS_WIRELESS_MODE_N_5G(wirelessmode))
1848 sifstime = 16;
1849 else
1850 sifstime = 10;
1851 u1bAIFS = sifstime + (2 * val[0]);
1852 rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM,
1853 u1bAIFS);
1854 rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM,
1855 u1bAIFS);
1856 rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM,
1857 u1bAIFS);
1858 rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM,
1859 u1bAIFS);
1860 }
1861 break;
1862 }
1863 case HW_VAR_ACK_PREAMBLE:{
1864 u8 reg_tmp;
1865 u8 short_preamble = (bool) (*(u8 *) val);
1866 reg_tmp = 0;
1867 if (short_preamble)
1868 reg_tmp |= 0x80;
1869 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
1870 break;
1871 }
1872 case HW_VAR_AMPDU_MIN_SPACE:{
1873 u8 min_spacing_to_set;
1874 u8 sec_min_space;
1875
1876 min_spacing_to_set = *((u8 *) val);
1877 if (min_spacing_to_set <= 7) {
1878 switch (rtlpriv->sec.pairwise_enc_algorithm) {
1879 case NO_ENCRYPTION:
1880 case AESCCMP_ENCRYPTION:
1881 sec_min_space = 0;
1882 break;
1883 case WEP40_ENCRYPTION:
1884 case WEP104_ENCRYPTION:
1885 case TKIP_ENCRYPTION:
1886 sec_min_space = 6;
1887 break;
1888 default:
1889 sec_min_space = 7;
1890 break;
1891 }
1892 if (min_spacing_to_set < sec_min_space)
1893 min_spacing_to_set = sec_min_space;
1894 mac->min_space_cfg = ((mac->min_space_cfg &
1895 0xf8) |
1896 min_spacing_to_set);
1897 *val = min_spacing_to_set;
1898 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1899 ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
1900 mac->min_space_cfg));
1901 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1902 mac->min_space_cfg);
1903 }
1904 break;
1905 }
1906 case HW_VAR_SHORTGI_DENSITY:{
1907 u8 density_to_set;
1908
1909 density_to_set = *((u8 *) val);
1910 density_to_set &= 0x1f;
1911 mac->min_space_cfg &= 0x07;
1912 mac->min_space_cfg |= (density_to_set << 3);
1913 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1914 ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
1915 mac->min_space_cfg));
1916 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1917 mac->min_space_cfg);
1918 break;
1919 }
1920 case HW_VAR_AMPDU_FACTOR:{
1921 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1922 u8 factor_toset;
1923 u8 *p_regtoset = NULL;
1924 u8 index = 0;
1925
1926 p_regtoset = regtoset_normal;
1927 factor_toset = *((u8 *) val);
1928 if (factor_toset <= 3) {
1929 factor_toset = (1 << (factor_toset + 2));
1930 if (factor_toset > 0xf)
1931 factor_toset = 0xf;
1932 for (index = 0; index < 4; index++) {
1933 if ((p_regtoset[index] & 0xf0) >
1934 (factor_toset << 4))
1935 p_regtoset[index] =
1936 (p_regtoset[index] & 0x0f)
1937 | (factor_toset << 4);
1938 if ((p_regtoset[index] & 0x0f) >
1939 factor_toset)
1940 p_regtoset[index] =
1941 (p_regtoset[index] & 0xf0)
1942 | (factor_toset);
1943 rtl_write_byte(rtlpriv,
1944 (REG_AGGLEN_LMT + index),
1945 p_regtoset[index]);
1946 }
1947 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1948 ("Set HW_VAR_AMPDU_FACTOR: %#x\n",
1949 factor_toset));
1950 }
1951 break;
1952 }
1953 case HW_VAR_AC_PARAM:{
1954 u8 e_aci = *((u8 *) val);
1955 u32 u4b_ac_param;
1956 u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min);
1957 u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max);
1958 u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op);
1959
1960 u4b_ac_param = (u32) mac->ac[e_aci].aifs;
1961 u4b_ac_param |= (u32) ((cw_min & 0xF) <<
1962 AC_PARAM_ECW_MIN_OFFSET);
1963 u4b_ac_param |= (u32) ((cw_max & 0xF) <<
1964 AC_PARAM_ECW_MAX_OFFSET);
1965 u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET;
1966 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1967 ("queue:%x, ac_param:%x\n", e_aci,
1968 u4b_ac_param));
1969 switch (e_aci) {
1970 case AC1_BK:
1971 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM,
1972 u4b_ac_param);
1973 break;
1974 case AC0_BE:
1975 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
1976 u4b_ac_param);
1977 break;
1978 case AC2_VI:
1979 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM,
1980 u4b_ac_param);
1981 break;
1982 case AC3_VO:
1983 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM,
1984 u4b_ac_param);
1985 break;
1986 default:
1987 RT_ASSERT(false, ("SetHwReg8185(): invalid"
1988 " aci: %d !\n", e_aci));
1989 break;
1990 }
1991 if (rtlusb->acm_method != eAcmWay2_SW)
1992 rtlpriv->cfg->ops->set_hw_reg(hw,
1993 HW_VAR_ACM_CTRL, (u8 *)(&e_aci));
1994 break;
1995 }
1996 case HW_VAR_ACM_CTRL:{
1997 u8 e_aci = *((u8 *) val);
1998 union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)
1999 (&(mac->ac[0].aifs));
2000 u8 acm = p_aci_aifsn->f.acm;
2001 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
2002
2003 acm_ctrl =
2004 acm_ctrl | ((rtlusb->acm_method == 2) ? 0x0 : 0x1);
2005 if (acm) {
2006 switch (e_aci) {
2007 case AC0_BE:
2008 acm_ctrl |= AcmHw_BeqEn;
2009 break;
2010 case AC2_VI:
2011 acm_ctrl |= AcmHw_ViqEn;
2012 break;
2013 case AC3_VO:
2014 acm_ctrl |= AcmHw_VoqEn;
2015 break;
2016 default:
2017 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2018 ("HW_VAR_ACM_CTRL acm set "
2019 "failed: eACI is %d\n", acm));
2020 break;
2021 }
2022 } else {
2023 switch (e_aci) {
2024 case AC0_BE:
2025 acm_ctrl &= (~AcmHw_BeqEn);
2026 break;
2027 case AC2_VI:
2028 acm_ctrl &= (~AcmHw_ViqEn);
2029 break;
2030 case AC3_VO:
2031 acm_ctrl &= (~AcmHw_BeqEn);
2032 break;
2033 default:
2034 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2035 ("switch case not process\n"));
2036 break;
2037 }
2038 }
2039 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
2040 ("SetHwReg8190pci(): [HW_VAR_ACM_CTRL] "
2041 "Write 0x%X\n", acm_ctrl));
2042 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
2043 break;
2044 }
2045 case HW_VAR_RCR:{
2046 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
2047 mac->rx_conf = ((u32 *) (val))[0];
2048 RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG,
2049 ("### Set RCR(0x%08x) ###\n", mac->rx_conf));
2050 break;
2051 }
2052 case HW_VAR_RETRY_LIMIT:{
2053 u8 retry_limit = ((u8 *) (val))[0];
2054
2055 rtl_write_word(rtlpriv, REG_RL,
2056 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
2057 retry_limit << RETRY_LIMIT_LONG_SHIFT);
2058 RT_TRACE(rtlpriv, COMP_MLME, DBG_DMESG, ("Set HW_VAR_R"
2059 "ETRY_LIMIT(0x%08x)\n", retry_limit));
2060 break;
2061 }
2062 case HW_VAR_DUAL_TSF_RST:
2063 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
2064 break;
2065 case HW_VAR_EFUSE_BYTES:
2066 rtlefuse->efuse_usedbytes = *((u16 *) val);
2067 break;
2068 case HW_VAR_EFUSE_USAGE:
2069 rtlefuse->efuse_usedpercentage = *((u8 *) val);
2070 break;
2071 case HW_VAR_IO_CMD:
2072 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
2073 break;
2074 case HW_VAR_WPA_CONFIG:
2075 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
2076 break;
2077 case HW_VAR_SET_RPWM:{
2078 u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM);
2079
2080 if (rpwm_val & BIT(7))
2081 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
2082 (*(u8 *)val));
2083 else
2084 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
2085 ((*(u8 *)val) | BIT(7)));
2086 break;
2087 }
2088 case HW_VAR_H2C_FW_PWRMODE:{
2089 u8 psmode = (*(u8 *) val);
2090
2091 if ((psmode != FW_PS_ACTIVE_MODE) &&
2092 (!IS_92C_SERIAL(rtlhal->version)))
2093 rtl92c_dm_rf_saving(hw, true);
2094 rtl92c_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
2095 break;
2096 }
2097 case HW_VAR_FW_PSMODE_STATUS:
2098 ppsc->fw_current_inpsmode = *((bool *) val);
2099 break;
2100 case HW_VAR_H2C_FW_JOINBSSRPT:{
2101 u8 mstatus = (*(u8 *) val);
2102 u8 tmp_reg422;
2103 bool recover = false;
2104
2105 if (mstatus == RT_MEDIA_CONNECT) {
2106 rtlpriv->cfg->ops->set_hw_reg(hw,
2107 HW_VAR_AID, NULL);
2108 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03);
2109 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
2110 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
2111 tmp_reg422 = rtl_read_byte(rtlpriv,
2112 REG_FWHW_TXQ_CTRL + 2);
2113 if (tmp_reg422 & BIT(6))
2114 recover = true;
2115 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
2116 tmp_reg422 & (~BIT(6)));
2117 rtl92c_set_fw_rsvdpagepkt(hw, 0);
2118 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
2119 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
2120 if (recover)
2121 rtl_write_byte(rtlpriv,
2122 REG_FWHW_TXQ_CTRL + 2,
2123 tmp_reg422 | BIT(6));
2124 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
2125 }
2126 rtl92c_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
2127 break;
2128 }
2129 case HW_VAR_AID:{
2130 u16 u2btmp;
2131
2132 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
2133 u2btmp &= 0xC000;
2134 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
2135 (u2btmp | mac->assoc_id));
2136 break;
2137 }
2138 case HW_VAR_CORRECT_TSF:{
2139 u8 btype_ibss = ((u8 *) (val))[0];
2140
2141 if (btype_ibss)
2142 _rtl92cu_stop_tx_beacon(hw);
2143 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
2144 rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf &
2145 0xffffffff));
2146 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
2147 (u32)((mac->tsf >> 32) & 0xffffffff));
2148 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
2149 if (btype_ibss)
2150 _rtl92cu_resume_tx_beacon(hw);
2151 break;
2152 }
2153 case HW_VAR_MGT_FILTER:
2154 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val);
2155 break;
2156 case HW_VAR_CTRL_FILTER:
2157 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val);
2158 break;
2159 case HW_VAR_DATA_FILTER:
2160 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val);
2161 break;
2162 default:
2163 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
2164 "not process\n"));
2165 break;
2166 }
2167 }
2168
2169 void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
2170 struct ieee80211_sta *sta,
2171 u8 rssi_level)
2172 {
2173 struct rtl_priv *rtlpriv = rtl_priv(hw);
2174 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2175 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2176 u32 ratr_value = (u32) mac->basic_rates;
2177 u8 *mcsrate = mac->mcs;
2178 u8 ratr_index = 0;
2179 u8 nmode = mac->ht_enable;
2180 u8 mimo_ps = 1;
2181 u16 shortgi_rate = 0;
2182 u32 tmp_ratr_value = 0;
2183 u8 curtxbw_40mhz = mac->bw_40;
2184 u8 curshortgi_40mhz = mac->sgi_40;
2185 u8 curshortgi_20mhz = mac->sgi_20;
2186 enum wireless_mode wirelessmode = mac->mode;
2187
2188 ratr_value |= ((*(u16 *) (mcsrate))) << 12;
2189 switch (wirelessmode) {
2190 case WIRELESS_MODE_B:
2191 if (ratr_value & 0x0000000c)
2192 ratr_value &= 0x0000000d;
2193 else
2194 ratr_value &= 0x0000000f;
2195 break;
2196 case WIRELESS_MODE_G:
2197 ratr_value &= 0x00000FF5;
2198 break;
2199 case WIRELESS_MODE_N_24G:
2200 case WIRELESS_MODE_N_5G:
2201 nmode = 1;
2202 if (mimo_ps == 0) {
2203 ratr_value &= 0x0007F005;
2204 } else {
2205 u32 ratr_mask;
2206
2207 if (get_rf_type(rtlphy) == RF_1T2R ||
2208 get_rf_type(rtlphy) == RF_1T1R)
2209 ratr_mask = 0x000ff005;
2210 else
2211 ratr_mask = 0x0f0ff005;
2212 if (curtxbw_40mhz)
2213 ratr_mask |= 0x00000010;
2214 ratr_value &= ratr_mask;
2215 }
2216 break;
2217 default:
2218 if (rtlphy->rf_type == RF_1T2R)
2219 ratr_value &= 0x000ff0ff;
2220 else
2221 ratr_value &= 0x0f0ff0ff;
2222 break;
2223 }
2224 ratr_value &= 0x0FFFFFFF;
2225 if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
2226 (!curtxbw_40mhz && curshortgi_20mhz))) {
2227 ratr_value |= 0x10000000;
2228 tmp_ratr_value = (ratr_value >> 12);
2229 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2230 if ((1 << shortgi_rate) & tmp_ratr_value)
2231 break;
2232 }
2233 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2234 (shortgi_rate << 4) | (shortgi_rate);
2235 }
2236 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2237 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("%x\n", rtl_read_dword(rtlpriv,
2238 REG_ARFR0)));
2239 }
2240
2241 void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
2242 {
2243 struct rtl_priv *rtlpriv = rtl_priv(hw);
2244 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2245 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2246 u32 ratr_bitmap = (u32) mac->basic_rates;
2247 u8 *p_mcsrate = mac->mcs;
2248 u8 ratr_index = 0;
2249 u8 curtxbw_40mhz = mac->bw_40;
2250 u8 curshortgi_40mhz = mac->sgi_40;
2251 u8 curshortgi_20mhz = mac->sgi_20;
2252 enum wireless_mode wirelessmode = mac->mode;
2253 bool shortgi = false;
2254 u8 rate_mask[5];
2255 u8 macid = 0;
2256 u8 mimops = 1;
2257
2258 ratr_bitmap |= (p_mcsrate[1] << 20) | (p_mcsrate[0] << 12);
2259 switch (wirelessmode) {
2260 case WIRELESS_MODE_B:
2261 ratr_index = RATR_INX_WIRELESS_B;
2262 if (ratr_bitmap & 0x0000000c)
2263 ratr_bitmap &= 0x0000000d;
2264 else
2265 ratr_bitmap &= 0x0000000f;
2266 break;
2267 case WIRELESS_MODE_G:
2268 ratr_index = RATR_INX_WIRELESS_GB;
2269 if (rssi_level == 1)
2270 ratr_bitmap &= 0x00000f00;
2271 else if (rssi_level == 2)
2272 ratr_bitmap &= 0x00000ff0;
2273 else
2274 ratr_bitmap &= 0x00000ff5;
2275 break;
2276 case WIRELESS_MODE_A:
2277 ratr_index = RATR_INX_WIRELESS_A;
2278 ratr_bitmap &= 0x00000ff0;
2279 break;
2280 case WIRELESS_MODE_N_24G:
2281 case WIRELESS_MODE_N_5G:
2282 ratr_index = RATR_INX_WIRELESS_NGB;
2283 if (mimops == 0) {
2284 if (rssi_level == 1)
2285 ratr_bitmap &= 0x00070000;
2286 else if (rssi_level == 2)
2287 ratr_bitmap &= 0x0007f000;
2288 else
2289 ratr_bitmap &= 0x0007f005;
2290 } else {
2291 if (rtlphy->rf_type == RF_1T2R ||
2292 rtlphy->rf_type == RF_1T1R) {
2293 if (curtxbw_40mhz) {
2294 if (rssi_level == 1)
2295 ratr_bitmap &= 0x000f0000;
2296 else if (rssi_level == 2)
2297 ratr_bitmap &= 0x000ff000;
2298 else
2299 ratr_bitmap &= 0x000ff015;
2300 } else {
2301 if (rssi_level == 1)
2302 ratr_bitmap &= 0x000f0000;
2303 else if (rssi_level == 2)
2304 ratr_bitmap &= 0x000ff000;
2305 else
2306 ratr_bitmap &= 0x000ff005;
2307 }
2308 } else {
2309 if (curtxbw_40mhz) {
2310 if (rssi_level == 1)
2311 ratr_bitmap &= 0x0f0f0000;
2312 else if (rssi_level == 2)
2313 ratr_bitmap &= 0x0f0ff000;
2314 else
2315 ratr_bitmap &= 0x0f0ff015;
2316 } else {
2317 if (rssi_level == 1)
2318 ratr_bitmap &= 0x0f0f0000;
2319 else if (rssi_level == 2)
2320 ratr_bitmap &= 0x0f0ff000;
2321 else
2322 ratr_bitmap &= 0x0f0ff005;
2323 }
2324 }
2325 }
2326 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2327 (!curtxbw_40mhz && curshortgi_20mhz)) {
2328 if (macid == 0)
2329 shortgi = true;
2330 else if (macid == 1)
2331 shortgi = false;
2332 }
2333 break;
2334 default:
2335 ratr_index = RATR_INX_WIRELESS_NGB;
2336 if (rtlphy->rf_type == RF_1T2R)
2337 ratr_bitmap &= 0x000ff0ff;
2338 else
2339 ratr_bitmap &= 0x0f0ff0ff;
2340 break;
2341 }
2342 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("ratr_bitmap :%x\n",
2343 ratr_bitmap));
2344 *(u32 *)&rate_mask = ((ratr_bitmap & 0x0fffffff) |
2345 ratr_index << 28);
2346 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2347 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("Rate_index:%x, "
2348 "ratr_val:%x, %x:%x:%x:%x:%x\n",
2349 ratr_index, ratr_bitmap,
2350 rate_mask[0], rate_mask[1],
2351 rate_mask[2], rate_mask[3],
2352 rate_mask[4]));
2353 rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
2354 }
2355
2356 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw)
2357 {
2358 struct rtl_priv *rtlpriv = rtl_priv(hw);
2359 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2360 u16 sifs_timer;
2361
2362 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2363 (u8 *)&mac->slot_time);
2364 if (!mac->ht_enable)
2365 sifs_timer = 0x0a0a;
2366 else
2367 sifs_timer = 0x0e0e;
2368 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2369 }
2370
2371 bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
2372 {
2373 struct rtl_priv *rtlpriv = rtl_priv(hw);
2374 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2375 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2376 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2377 u8 u1tmp = 0;
2378 bool actuallyset = false;
2379 unsigned long flag = 0;
2380 /* to do - usb autosuspend */
2381 u8 usb_autosuspend = 0;
2382
2383 if (ppsc->swrf_processing)
2384 return false;
2385 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2386 if (ppsc->rfchange_inprogress) {
2387 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2388 return false;
2389 } else {
2390 ppsc->rfchange_inprogress = true;
2391 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2392 }
2393 cur_rfstate = ppsc->rfpwr_state;
2394 if (usb_autosuspend) {
2395 /* to do................... */
2396 } else {
2397 if (ppsc->pwrdown_mode) {
2398 u1tmp = rtl_read_byte(rtlpriv, REG_HSISR);
2399 e_rfpowerstate_toset = (u1tmp & BIT(7)) ?
2400 ERFOFF : ERFON;
2401 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2402 ("pwrdown, 0x5c(BIT7)=%02x\n", u1tmp));
2403 } else {
2404 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG,
2405 rtl_read_byte(rtlpriv,
2406 REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2407 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2408 e_rfpowerstate_toset = (u1tmp & BIT(3)) ?
2409 ERFON : ERFOFF;
2410 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2411 ("GPIO_IN=%02x\n", u1tmp));
2412 }
2413 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("N-SS RF =%x\n",
2414 e_rfpowerstate_toset));
2415 }
2416 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2417 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("GPIOChangeRF - HW "
2418 "Radio ON, RF ON\n"));
2419 ppsc->hwradiooff = false;
2420 actuallyset = true;
2421 } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset ==
2422 ERFOFF)) {
2423 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("GPIOChangeRF - HW"
2424 " Radio OFF\n"));
2425 ppsc->hwradiooff = true;
2426 actuallyset = true;
2427 } else {
2428 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD ,
2429 ("pHalData->bHwRadioOff and eRfPowerStateToSet do not"
2430 " match: pHalData->bHwRadioOff %x, eRfPowerStateToSet "
2431 "%x\n", ppsc->hwradiooff, e_rfpowerstate_toset));
2432 }
2433 if (actuallyset) {
2434 ppsc->hwradiooff = true;
2435 if (e_rfpowerstate_toset == ERFON) {
2436 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
2437 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM))
2438 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2439 else if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2440 && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3))
2441 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2442 }
2443 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2444 ppsc->rfchange_inprogress = false;
2445 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2446 /* For power down module, we need to enable register block
2447 * contrl reg at 0x1c. Then enable power down control bit
2448 * of register 0x04 BIT4 and BIT15 as 1.
2449 */
2450 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) {
2451 /* Enable register area 0x0-0xc. */
2452 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
2453 if (IS_HARDWARE_TYPE_8723U(rtlhal)) {
2454 /*
2455 * We should configure HW PDn source for WiFi
2456 * ONLY, and then our HW will be set in
2457 * power-down mode if PDn source from all
2458 * functions are configured.
2459 */
2460 u1tmp = rtl_read_byte(rtlpriv,
2461 REG_MULTI_FUNC_CTRL);
2462 rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL,
2463 (u1tmp|WL_HWPDN_EN));
2464 } else {
2465 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812);
2466 }
2467 }
2468 if (e_rfpowerstate_toset == ERFOFF) {
2469 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)
2470 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2471 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2472 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2473 }
2474 } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) {
2475 /* Enter D3 or ASPM after GPIO had been done. */
2476 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)
2477 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2478 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2479 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2480 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2481 ppsc->rfchange_inprogress = false;
2482 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2483 } else {
2484 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2485 ppsc->rfchange_inprogress = false;
2486 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2487 }
2488 *valid = 1;
2489 return !ppsc->hwradiooff;
2490 }