drivers/net/wireless/rtlwifi/rtl8192de/dm.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #ifndef __RTL92C_DM_H__
  31 #define __RTL92C_DM_H__
  32
  33 #define HAL_DM_DIG_DISABLE                      BIT(0)
  34 #define HAL_DM_HIPWR_DISABLE                    BIT(1)
  35
  36 #define OFDM_TABLE_LENGTH                       37
  37 #define OFDM_TABLE_SIZE_92D                     43
  38 #define CCK_TABLE_LENGTH                        33
  39
  40 #define CCK_TABLE_SIZE                          33
  41
  42 #define BW_AUTO_SWITCH_HIGH_LOW                 25
  43 #define BW_AUTO_SWITCH_LOW_HIGH                 30
  44
  45 #define DM_DIG_THRESH_HIGH                      40
  46 #define DM_DIG_THRESH_LOW                       35
  47
  48 #define DM_FALSEALARM_THRESH_LOW                400
  49 #define DM_FALSEALARM_THRESH_HIGH               1000
  50
  51 #define DM_DIG_MAX                              0x3e
  52 #define DM_DIG_MIN                              0x1c
  53
  54 #define DM_DIG_FA_UPPER                         0x32
  55 #define DM_DIG_FA_LOWER                         0x20
  56 #define DM_DIG_FA_TH0                           0x100
  57 #define DM_DIG_FA_TH1                           0x400
  58 #define DM_DIG_FA_TH2                           0x600
  59
  60 #define DM_DIG_BACKOFF_MAX                      12
  61 #define DM_DIG_BACKOFF_MIN                      -4
  62 #define DM_DIG_BACKOFF_DEFAULT                  10
  63
  64 #define RXPATHSELECTION_SS_TH_lOW               30
  65 #define RXPATHSELECTION_DIFF_TH                 18
  66
  67 #define DM_RATR_STA_INIT                        0
  68 #define DM_RATR_STA_HIGH                        1
  69 #define DM_RATR_STA_MIDDLE                      2
  70 #define DM_RATR_STA_LOW                         3
  71
  72 #define CTS2SELF_THVAL                          30
  73 #define REGC38_TH                               20
  74
  75 #define WAIOTTHVAL                              25
  76
  77 #define TXHIGHPWRLEVEL_NORMAL                   0
  78 #define TXHIGHPWRLEVEL_LEVEL1                   1
  79 #define TXHIGHPWRLEVEL_LEVEL2                   2
  80 #define TXHIGHPWRLEVEL_BT1                      3
  81 #define TXHIGHPWRLEVEL_BT2                      4
  82
  83 #define DM_TYPE_BYFW                            0
  84 #define DM_TYPE_BYDRIVER                        1
  85
  86 #define TX_POWER_NEAR_FIELD_THRESH_LVL2         74
  87 #define TX_POWER_NEAR_FIELD_THRESH_LVL1         67
  88 #define INDEX_MAPPING_NUM                       13
  89
  90 struct ps_t {
  91         u8 pre_ccastate;
  92         u8 cur_ccasate;
  93
  94         u8 pre_rfstate;
  95         u8 cur_rfstate;
  96
  97         long rssi_val_min;
  98 };
  99
 100 struct dig_t {
 101         u8 dig_enable_flag;
 102         u8 dig_ext_port_stage;
 103
 104         u32 rssi_lowthresh;
 105         u32 rssi_highthresh;
 106
 107         u32 fa_lowthresh;
 108         u32 fa_highthresh;
 109
 110         u8 cursta_connectctate;
 111         u8 presta_connectstate;
 112         u8 curmultista_connectstate;
 113
 114         u8 pre_igvalue;
 115         u8 cur_igvalue;
 116
 117         char backoff_val;
 118         char backoff_val_range_max;
 119         char backoff_val_range_min;
 120         u8 rx_gain_range_max;
 121         u8 rx_gain_range_min;
 122         u8 min_undecorated_pwdb_for_dm;
 123         long last_min_undecorated_pwdb_for_dm;
 124
 125         u8 pre_cck_pd_state;
 126         u8 cur_cck_pd_state;
 127
 128         u8 pre_cck_fa_state;
 129         u8 cur_cck_fa_state;
 130
 131         u8 pre_ccastate;
 132         u8 cur_ccasate;
 133
 134         u8 large_fa_hit;
 135         u8 forbidden_igi;
 136         u32 recover_cnt;
 137 };
 138
 139 struct swat {
 140         u8 failure_cnt;
 141         u8 try_flag;
 142         u8 stop_trying;
 143         long pre_rssi;
 144         long trying_threshold;
 145         u8 cur_antenna;
 146         u8 pre_antenna;
 147 };
 148
 149 enum tag_dynamic_init_gain_operation_type_definition {
 150         DIG_TYPE_THRESH_HIGH = 0,
 151         DIG_TYPE_THRESH_LOW = 1,
 152         DIG_TYPE_BACKOFF = 2,
 153         DIG_TYPE_RX_GAIN_MIN = 3,
 154         DIG_TYPE_RX_GAIN_MAX = 4,
 155         DIG_TYPE_ENABLE = 5,
 156         DIG_TYPE_DISABLE = 6,
 157         DIG_OP_TYPE_MAX
 158 };
 159
 160 enum tag_cck_packet_detection_threshold_type_definition {
 161         CCK_PD_STAGE_LOWRSSI = 0,
 162         CCK_PD_STAGE_HIGHRSSI = 1,
 163         CCK_FA_STAGE_LOW = 2,
 164         CCK_FA_STAGE_HIGH = 3,
 165         CCK_PD_STAGE_MAX = 4,
 166 };
 167
 168 enum dm_1r_cca {
 169         CCA_1R = 0,
 170         CCA_2R = 1,
 171         CCA_MAX = 2,
 172 };
 173
 174 enum dm_rf {
 175         RF_SAVE = 0,
 176         RF_NORMAL = 1,
 177         RF_MAX = 2,
 178 };
 179
 180 enum dm_sw_ant_switch {
 181         ANS_ANTENNA_B = 1,
 182         ANS_ANTENNA_A = 2,
 183         ANS_ANTENNA_MAX = 3,
 184 };
 185
 186 enum dm_dig_ext_port_alg {
 187         DIG_EXT_PORT_STAGE_0 = 0,
 188         DIG_EXT_PORT_STAGE_1 = 1,
 189         DIG_EXT_PORT_STAGE_2 = 2,
 190         DIG_EXT_PORT_STAGE_3 = 3,
 191         DIG_EXT_PORT_STAGE_MAX = 4,
 192 };
 193
 194 enum dm_dig_connect {
 195         DIG_STA_DISCONNECT = 0,
 196         DIG_STA_CONNECT = 1,
 197         DIG_STA_BEFORE_CONNECT = 2,
 198         DIG_MULTISTA_DISCONNECT = 3,
 199         DIG_MULTISTA_CONNECT = 4,
 200         DIG_CONNECT_MAX
 201 };
 202
 203 extern struct dig_t de_digtable;
 204
 205 void rtl92d_dm_init(struct ieee80211_hw *hw);
 206 void rtl92d_dm_watchdog(struct ieee80211_hw *hw);
 207 void rtl92d_dm_init_edca_turbo(struct ieee80211_hw *hw);
 208 void rtl92d_dm_write_dig(struct ieee80211_hw *hw);
 209 void rtl92d_dm_check_txpower_tracking_thermal_meter(struct ieee80211_hw *hw);
 210 void rtl92d_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
 211
 212 #endif