drivers/net/wireless/rtlwifi/rtl8192de/sw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32 #include <linux/vmalloc.h>
  33 #include <linux/module.h>
  34
  35 #include "../wifi.h"
  36 #include "../core.h"
  37 #include "../pci.h"
  38 #include "reg.h"
  39 #include "def.h"
  40 #include "phy.h"
  41 #include "dm.h"
  42 #include "hw.h"
  43 #include "sw.h"
  44 #include "trx.h"
  45 #include "led.h"
  46
  47 static void rtl92d_init_aspm_vars(struct ieee80211_hw *hw)
  48 {
  49         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  50
  51         /*close ASPM for AMD defaultly */
  52         rtlpci->const_amdpci_aspm = 0;
  53
  54         /*
  55          * ASPM PS mode.
  56          * 0 - Disable ASPM,
  57          * 1 - Enable ASPM without Clock Req,
  58          * 2 - Enable ASPM with Clock Req,
  59          * 3 - Alwyas Enable ASPM with Clock Req,
  60          * 4 - Always Enable ASPM without Clock Req.
  61          * set defult to RTL8192CE:3 RTL8192E:2
  62          * */
  63         rtlpci->const_pci_aspm = 3;
  64
  65         /*Setting for PCI-E device */
  66         rtlpci->const_devicepci_aspm_setting = 0x03;
  67
  68         /*Setting for PCI-E bridge */
  69         rtlpci->const_hostpci_aspm_setting = 0x02;
  70
  71         /*
  72          * In Hw/Sw Radio Off situation.
  73          * 0 - Default,
  74          * 1 - From ASPM setting without low Mac Pwr,
  75          * 2 - From ASPM setting with low Mac Pwr,
  76          * 3 - Bus D3
  77          * set default to RTL8192CE:0 RTL8192SE:2
  78          */
  79         rtlpci->const_hwsw_rfoff_d3 = 0;
  80
  81         /*
  82          * This setting works for those device with
  83          * backdoor ASPM setting such as EPHY setting.
  84          * 0 - Not support ASPM,
  85          * 1 - Support ASPM,
  86          * 2 - According to chipset.
  87          */
  88         rtlpci->const_support_pciaspm = 1;
  89 }
  90
  91 static int rtl92d_init_sw_vars(struct ieee80211_hw *hw)
  92 {
  93         int err;
  94         u8 tid;
  95         struct rtl_priv *rtlpriv = rtl_priv(hw);
  96         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  97         static int header_print;
  98
  99         rtlpriv->dm.dm_initialgain_enable = true;
 100         rtlpriv->dm.dm_flag = 0;
 101         rtlpriv->dm.disable_framebursting = false;
 102         rtlpriv->dm.thermalvalue = 0;
 103         rtlpriv->dm.useramask = true;
 104
 105         /* dual mac */
 106         if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G)
 107                 rtlpriv->phy.current_channel = 36;
 108         else
 109                 rtlpriv->phy.current_channel = 1;
 110
 111         if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {
 112                 rtlpriv->rtlhal.disable_amsdu_8k = true;
 113                 /* No long RX - reduce fragmentation */
 114                 rtlpci->rxbuffersize = 4096;
 115         }
 116
 117         rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
 118
 119         rtlpci->receive_config = (
 120                         RCR_APPFCS
 121                         | RCR_AMF
 122                         | RCR_ADF
 123                         | RCR_APP_MIC
 124                         | RCR_APP_ICV
 125                         | RCR_AICV
 126                         | RCR_ACRC32
 127                         | RCR_AB
 128                         | RCR_AM
 129                         | RCR_APM
 130                         | RCR_APP_PHYST_RXFF
 131                         | RCR_HTC_LOC_CTRL
 132         );
 133
 134         rtlpci->irq_mask[0] = (u32) (
 135                         IMR_ROK
 136                         | IMR_VODOK
 137                         | IMR_VIDOK
 138                         | IMR_BEDOK
 139                         | IMR_BKDOK
 140                         | IMR_MGNTDOK
 141                         | IMR_HIGHDOK
 142                         | IMR_BDOK
 143                         | IMR_RDU
 144                         | IMR_RXFOVW
 145         );
 146
 147         rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD);
 148
 149         /* for debug level */
 150         rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
 151         /* for LPS & IPS */
 152         rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
 153         rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
 154         rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
 155         if (!rtlpriv->psc.inactiveps)
 156                 pr_info("rtl8192ce: Power Save off (module option)\n");
 157         if (!rtlpriv->psc.fwctrl_lps)
 158                 pr_info("rtl8192ce: FW Power Save off (module option)\n");
 159         rtlpriv->psc.reg_fwctrl_lps = 3;
 160         rtlpriv->psc.reg_max_lps_awakeintvl = 5;
 161         /* for ASPM, you can close aspm through
 162          * set const_support_pciaspm = 0 */
 163         rtl92d_init_aspm_vars(hw);
 164
 165         if (rtlpriv->psc.reg_fwctrl_lps == 1)
 166                 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
 167         else if (rtlpriv->psc.reg_fwctrl_lps == 2)
 168                 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
 169         else if (rtlpriv->psc.reg_fwctrl_lps == 3)
 170                 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
 171
 172         /* for early mode */
 173         rtlpriv->rtlhal.earlymode_enable = true;
 174         for (tid = 0; tid < 8; tid++)
 175                 skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]);
 176
 177         /* Only load firmware for first MAC */
 178         if (header_print)
 179                 return 0;
 180
 181         /* for firmware buf */
 182         rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
 183         if (!rtlpriv->rtlhal.pfirmware) {
 184                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 185                          ("Can't alloc buffer for fw.\n"));
 186                 return 1;
 187         }
 188
 189         rtlpriv->max_fw_size = 0x8000;
 190         pr_info("Driver for Realtek RTL8192DE WLAN interface\n");
 191         pr_info("Loading firmware file %s\n", rtlpriv->cfg->fw_name);
 192         header_print++;
 193
 194         /* request fw */
 195         err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
 196                                       rtlpriv->io.dev, GFP_KERNEL, hw,
 197                                       rtl_fw_cb);
 198         if (err) {
 199                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 200                          ("Failed to request firmware!\n"));
 201                 return 1;
 202         }
 203
 204         return 0;
 205 }
 206
 207 static void rtl92d_deinit_sw_vars(struct ieee80211_hw *hw)
 208 {
 209         struct rtl_priv *rtlpriv = rtl_priv(hw);
 210         u8 tid;
 211
 212         if (rtlpriv->rtlhal.pfirmware) {
 213                 vfree(rtlpriv->rtlhal.pfirmware);
 214                 rtlpriv->rtlhal.pfirmware = NULL;
 215         }
 216         for (tid = 0; tid < 8; tid++)
 217                 skb_queue_purge(&rtlpriv->mac80211.skb_waitq[tid]);
 218 }
 219
 220 static struct rtl_hal_ops rtl8192de_hal_ops = {
 221         .init_sw_vars = rtl92d_init_sw_vars,
 222         .deinit_sw_vars = rtl92d_deinit_sw_vars,
 223         .read_eeprom_info = rtl92de_read_eeprom_info,
 224         .interrupt_recognized = rtl92de_interrupt_recognized,
 225         .hw_init = rtl92de_hw_init,
 226         .hw_disable = rtl92de_card_disable,
 227         .hw_suspend = rtl92de_suspend,
 228         .hw_resume = rtl92de_resume,
 229         .enable_interrupt = rtl92de_enable_interrupt,
 230         .disable_interrupt = rtl92de_disable_interrupt,
 231         .set_network_type = rtl92de_set_network_type,
 232         .set_chk_bssid = rtl92de_set_check_bssid,
 233         .set_qos = rtl92de_set_qos,
 234         .set_bcn_reg = rtl92de_set_beacon_related_registers,
 235         .set_bcn_intv = rtl92de_set_beacon_interval,
 236         .update_interrupt_mask = rtl92de_update_interrupt_mask,
 237         .get_hw_reg = rtl92de_get_hw_reg,
 238         .set_hw_reg = rtl92de_set_hw_reg,
 239         .update_rate_tbl = rtl92de_update_hal_rate_tbl,
 240         .fill_tx_desc = rtl92de_tx_fill_desc,
 241         .fill_tx_cmddesc = rtl92de_tx_fill_cmddesc,
 242         .query_rx_desc = rtl92de_rx_query_desc,
 243         .set_channel_access = rtl92de_update_channel_access_setting,
 244         .radio_onoff_checking = rtl92de_gpio_radio_on_off_checking,
 245         .set_bw_mode = rtl92d_phy_set_bw_mode,
 246         .switch_channel = rtl92d_phy_sw_chnl,
 247         .dm_watchdog = rtl92d_dm_watchdog,
 248         .scan_operation_backup = rtl92d_phy_scan_operation_backup,
 249         .set_rf_power_state = rtl92d_phy_set_rf_power_state,
 250         .led_control = rtl92de_led_control,
 251         .set_desc = rtl92de_set_desc,
 252         .get_desc = rtl92de_get_desc,
 253         .tx_polling = rtl92de_tx_polling,
 254         .enable_hw_sec = rtl92de_enable_hw_security_config,
 255         .set_key = rtl92de_set_key,
 256         .init_sw_leds = rtl92de_init_sw_leds,
 257         .get_bbreg = rtl92d_phy_query_bb_reg,
 258         .set_bbreg = rtl92d_phy_set_bb_reg,
 259         .get_rfreg = rtl92d_phy_query_rf_reg,
 260         .set_rfreg = rtl92d_phy_set_rf_reg,
 261         .linked_set_reg = rtl92d_linked_set_reg,
 262 };
 263
 264 static struct rtl_mod_params rtl92de_mod_params = {
 265         .sw_crypto = false,
 266         .inactiveps = true,
 267         .swctrl_lps = true,
 268         .fwctrl_lps = false,
 269         .debug = DBG_EMERG,
 270 };
 271
 272 static struct rtl_hal_cfg rtl92de_hal_cfg = {
 273         .bar_id = 2,
 274         .write_readback = true,
 275         .name = "rtl8192de",
 276         .fw_name = "rtlwifi/rtl8192defw.bin",
 277         .ops = &rtl8192de_hal_ops,
 278         .mod_params = &rtl92de_mod_params,
 279
 280         .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
 281         .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
 282         .maps[SYS_CLK] = REG_SYS_CLKR,
 283         .maps[MAC_RCR_AM] = RCR_AM,
 284         .maps[MAC_RCR_AB] = RCR_AB,
 285         .maps[MAC_RCR_ACRC32] = RCR_ACRC32,
 286         .maps[MAC_RCR_ACF] = RCR_ACF,
 287         .maps[MAC_RCR_AAP] = RCR_AAP,
 288
 289         .maps[EFUSE_TEST] = REG_EFUSE_TEST,
 290         .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
 291         .maps[EFUSE_CLK] = 0,   /* just for 92se */
 292         .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
 293         .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
 294         .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
 295         .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
 296         .maps[EFUSE_ANA8M] = 0, /* just for 92se */
 297         .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
 298         .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
 299         .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
 300
 301         .maps[RWCAM] = REG_CAMCMD,
 302         .maps[WCAMI] = REG_CAMWRITE,
 303         .maps[RCAMO] = REG_CAMREAD,
 304         .maps[CAMDBG] = REG_CAMDBG,
 305         .maps[SECR] = REG_SECCFG,
 306         .maps[SEC_CAM_NONE] = CAM_NONE,
 307         .maps[SEC_CAM_WEP40] = CAM_WEP40,
 308         .maps[SEC_CAM_TKIP] = CAM_TKIP,
 309         .maps[SEC_CAM_AES] = CAM_AES,
 310         .maps[SEC_CAM_WEP104] = CAM_WEP104,
 311
 312         .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
 313         .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
 314         .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
 315         .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
 316         .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
 317         .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
 318         .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
 319         .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
 320         .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
 321         .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
 322         .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
 323         .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
 324         .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
 325         .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
 326         .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
 327         .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
 328
 329         .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
 330         .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
 331         .maps[RTL_IMR_BcnInt] = IMR_BcnInt,
 332         .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
 333         .maps[RTL_IMR_RDU] = IMR_RDU,
 334         .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
 335         .maps[RTL_IMR_BDOK] = IMR_BDOK,
 336         .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
 337         .maps[RTL_IMR_TBDER] = IMR_TBDER,
 338         .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
 339         .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
 340         .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
 341         .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
 342         .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
 343         .maps[RTL_IMR_VODOK] = IMR_VODOK,
 344         .maps[RTL_IMR_ROK] = IMR_ROK,
 345         .maps[RTL_IBSS_INT_MASKS] = (IMR_BcnInt | IMR_TBDOK | IMR_TBDER),
 346
 347         .maps[RTL_RC_CCK_RATE1M] = DESC92_RATE1M,
 348         .maps[RTL_RC_CCK_RATE2M] = DESC92_RATE2M,
 349         .maps[RTL_RC_CCK_RATE5_5M] = DESC92_RATE5_5M,
 350         .maps[RTL_RC_CCK_RATE11M] = DESC92_RATE11M,
 351         .maps[RTL_RC_OFDM_RATE6M] = DESC92_RATE6M,
 352         .maps[RTL_RC_OFDM_RATE9M] = DESC92_RATE9M,
 353         .maps[RTL_RC_OFDM_RATE12M] = DESC92_RATE12M,
 354         .maps[RTL_RC_OFDM_RATE18M] = DESC92_RATE18M,
 355         .maps[RTL_RC_OFDM_RATE24M] = DESC92_RATE24M,
 356         .maps[RTL_RC_OFDM_RATE36M] = DESC92_RATE36M,
 357         .maps[RTL_RC_OFDM_RATE48M] = DESC92_RATE48M,
 358         .maps[RTL_RC_OFDM_RATE54M] = DESC92_RATE54M,
 359
 360         .maps[RTL_RC_HT_RATEMCS7] = DESC92_RATEMCS7,
 361         .maps[RTL_RC_HT_RATEMCS15] = DESC92_RATEMCS15,
 362 };
 363
 364 static struct pci_device_id rtl92de_pci_ids[] __devinitdata = {
 365         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8193, rtl92de_hal_cfg)},
 366         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x002B, rtl92de_hal_cfg)},
 367         {},
 368 };
 369
 370 MODULE_DEVICE_TABLE(pci, rtl92de_pci_ids);
 371
 372 MODULE_AUTHOR("lizhaoming       <chaoming_li@realsil.com.cn>");
 373 MODULE_AUTHOR("Realtek WlanFAE  <wlanfae@realtek.com>");
 374 MODULE_AUTHOR("Larry Finger     <Larry.Finger@lwfinger.net>");
 375 MODULE_LICENSE("GPL");
 376 MODULE_DESCRIPTION("Realtek 8192DE 802.11n Dual Mac PCI wireless");
 377 MODULE_FIRMWARE("rtlwifi/rtl8192defw.bin");
 378
 379 module_param_named(swenc, rtl92de_mod_params.sw_crypto, bool, 0444);
 380 module_param_named(debug, rtl92de_mod_params.debug, int, 0444);
 381 module_param_named(ips, rtl92de_mod_params.inactiveps, bool, 0444);
 382 module_param_named(swlps, rtl92de_mod_params.swctrl_lps, bool, 0444);
 383 module_param_named(fwlps, rtl92de_mod_params.fwctrl_lps, bool, 0444);
 384 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
 385 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
 386 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
 387 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
 388 MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
 389
 390 static const struct dev_pm_ops rtlwifi_pm_ops = {
 391         .suspend = rtl_pci_suspend,
 392         .resume = rtl_pci_resume,
 393         .freeze = rtl_pci_suspend,
 394         .thaw = rtl_pci_resume,
 395         .poweroff = rtl_pci_suspend,
 396         .restore = rtl_pci_resume,
 397 };
 398
 399 static struct pci_driver rtl92de_driver = {
 400         .name = KBUILD_MODNAME,
 401         .id_table = rtl92de_pci_ids,
 402         .probe = rtl_pci_probe,
 403         .remove = rtl_pci_disconnect,
 404         .driver.pm = &rtlwifi_pm_ops,
 405 };
 406
 407 /* add global spin lock to solve the problem that
 408  * Dul mac register operation on the same time */
 409 spinlock_t globalmutex_power;
 410 spinlock_t globalmutex_for_fwdownload;
 411 spinlock_t globalmutex_for_power_and_efuse;
 412
 413 static int __init rtl92de_module_init(void)
 414 {
 415         int ret = 0;
 416
 417         spin_lock_init(&globalmutex_power);
 418         spin_lock_init(&globalmutex_for_fwdownload);
 419         spin_lock_init(&globalmutex_for_power_and_efuse);
 420
 421         ret = pci_register_driver(&rtl92de_driver);
 422         if (ret)
 423                 RT_ASSERT(false, (": No device found\n"));
 424         return ret;
 425 }
 426
 427 static void __exit rtl92de_module_exit(void)
 428 {
 429         pci_unregister_driver(&rtl92de_driver);
 430 }
 431
 432 module_init(rtl92de_module_init);
 433 module_exit(rtl92de_module_exit);