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OMAPDSS: VENC: fix NULL pointer dereference in DSS2 VENC sysfs debug attr on OMAP4
[zen-stable.git] / drivers / net / wireless / rtlwifi / rtl8192se / hw.c
blob58b1a6a864f93783f7994f51b96af2cfe77f3ffb
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32 #include "../wifi.h"
33 #include "../efuse.h"
34 #include "../base.h"
35 #include "../regd.h"
36 #include "../cam.h"
37 #include "../ps.h"
38 #include "../pci.h"
39 #include "reg.h"
40 #include "def.h"
41 #include "phy.h"
42 #include "dm.h"
43 #include "fw.h"
44 #include "led.h"
45 #include "hw.h"
46
47 void rtl92se_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
48 {
49 struct rtl_priv *rtlpriv = rtl_priv(hw);
50 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
51 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
52
53 switch (variable) {
54 case HW_VAR_RCR: {
55 *((u32 *) (val)) = rtlpci->receive_config;
56 break;
57 }
58 case HW_VAR_RF_STATE: {
59 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
60 break;
61 }
62 case HW_VAR_FW_PSMODE_STATUS: {
63 *((bool *) (val)) = ppsc->fw_current_inpsmode;
64 break;
65 }
66 case HW_VAR_CORRECT_TSF: {
67 u64 tsf;
68 u32 *ptsf_low = (u32 *)&tsf;
69 u32 *ptsf_high = ((u32 *)&tsf) + 1;
70
71 *ptsf_high = rtl_read_dword(rtlpriv, (TSFR + 4));
72 *ptsf_low = rtl_read_dword(rtlpriv, TSFR);
73
74 *((u64 *) (val)) = tsf;
75
76 break;
77 }
78 case HW_VAR_MRC: {
79 *((bool *)(val)) = rtlpriv->dm.current_mrc_switch;
80 break;
81 }
82 default: {
83 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
84 ("switch case not process\n"));
85 break;
86 }
87 }
88 }
89
90 void rtl92se_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
91 {
92 struct rtl_priv *rtlpriv = rtl_priv(hw);
93 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
94 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
95 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
96 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
97 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
98
99 switch (variable) {
100 case HW_VAR_ETHER_ADDR:{
101 rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]);
102 rtl_write_word(rtlpriv, IDR4, ((u16 *)(val + 4))[0]);
103 break;
104 }
105 case HW_VAR_BASIC_RATE:{
106 u16 rate_cfg = ((u16 *) val)[0];
107 u8 rate_index = 0;
108
109 if (rtlhal->version == VERSION_8192S_ACUT)
110 rate_cfg = rate_cfg & 0x150;
111 else
112 rate_cfg = rate_cfg & 0x15f;
113
114 rate_cfg |= 0x01;
115
116 rtl_write_byte(rtlpriv, RRSR, rate_cfg & 0xff);
117 rtl_write_byte(rtlpriv, RRSR + 1,
118 (rate_cfg >> 8) & 0xff);
119
120 while (rate_cfg > 0x1) {
121 rate_cfg = (rate_cfg >> 1);
122 rate_index++;
123 }
124 rtl_write_byte(rtlpriv, INIRTSMCS_SEL, rate_index);
125
126 break;
127 }
128 case HW_VAR_BSSID:{
129 rtl_write_dword(rtlpriv, BSSIDR, ((u32 *)(val))[0]);
130 rtl_write_word(rtlpriv, BSSIDR + 4,
131 ((u16 *)(val + 4))[0]);
132 break;
133 }
134 case HW_VAR_SIFS:{
135 rtl_write_byte(rtlpriv, SIFS_OFDM, val[0]);
136 rtl_write_byte(rtlpriv, SIFS_OFDM + 1, val[1]);
137 break;
138 }
139 case HW_VAR_SLOT_TIME:{
140 u8 e_aci;
141
142 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
143 ("HW_VAR_SLOT_TIME %x\n", val[0]));
144
145 rtl_write_byte(rtlpriv, SLOT_TIME, val[0]);
146
147 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
148 rtlpriv->cfg->ops->set_hw_reg(hw,
149 HW_VAR_AC_PARAM,
150 (u8 *)(&e_aci));
151 }
152 break;
153 }
154 case HW_VAR_ACK_PREAMBLE:{
155 u8 reg_tmp;
156 u8 short_preamble = (bool) (*(u8 *) val);
157 reg_tmp = (mac->cur_40_prime_sc) << 5;
158 if (short_preamble)
159 reg_tmp |= 0x80;
160
161 rtl_write_byte(rtlpriv, RRSR + 2, reg_tmp);
162 break;
163 }
164 case HW_VAR_AMPDU_MIN_SPACE:{
165 u8 min_spacing_to_set;
166 u8 sec_min_space;
167
168 min_spacing_to_set = *((u8 *)val);
169 if (min_spacing_to_set <= 7) {
170 if (rtlpriv->sec.pairwise_enc_algorithm ==
171 NO_ENCRYPTION)
172 sec_min_space = 0;
173 else
174 sec_min_space = 1;
175
176 if (min_spacing_to_set < sec_min_space)
177 min_spacing_to_set = sec_min_space;
178 if (min_spacing_to_set > 5)
179 min_spacing_to_set = 5;
180
181 mac->min_space_cfg =
182 ((mac->min_space_cfg & 0xf8) |
183 min_spacing_to_set);
184
185 *val = min_spacing_to_set;
186
187 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
188 ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
189 mac->min_space_cfg));
190
191 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
192 mac->min_space_cfg);
193 }
194 break;
195 }
196 case HW_VAR_SHORTGI_DENSITY:{
197 u8 density_to_set;
198
199 density_to_set = *((u8 *) val);
200 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
201 mac->min_space_cfg |= (density_to_set << 3);
202
203 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
204 ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
205 mac->min_space_cfg));
206
207 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
208 mac->min_space_cfg);
209
210 break;
211 }
212 case HW_VAR_AMPDU_FACTOR:{
213 u8 factor_toset;
214 u8 regtoset;
215 u8 factorlevel[18] = {
216 2, 4, 4, 7, 7, 13, 13,
217 13, 2, 7, 7, 13, 13,
218 15, 15, 15, 15, 0};
219 u8 index = 0;
220
221 factor_toset = *((u8 *) val);
222 if (factor_toset <= 3) {
223 factor_toset = (1 << (factor_toset + 2));
224 if (factor_toset > 0xf)
225 factor_toset = 0xf;
226
227 for (index = 0; index < 17; index++) {
228 if (factorlevel[index] > factor_toset)
229 factorlevel[index] =
230 factor_toset;
231 }
232
233 for (index = 0; index < 8; index++) {
234 regtoset = ((factorlevel[index * 2]) |
235 (factorlevel[index *
236 2 + 1] << 4));
237 rtl_write_byte(rtlpriv,
238 AGGLEN_LMT_L + index,
239 regtoset);
240 }
241
242 regtoset = ((factorlevel[16]) |
243 (factorlevel[17] << 4));
244 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, regtoset);
245
246 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
247 ("Set HW_VAR_AMPDU_FACTOR: %#x\n",
248 factor_toset));
249 }
250 break;
251 }
252 case HW_VAR_AC_PARAM:{
253 u8 e_aci = *((u8 *) val);
254 rtl92s_dm_init_edca_turbo(hw);
255
256 if (rtlpci->acm_method != eAcmWay2_SW)
257 rtlpriv->cfg->ops->set_hw_reg(hw,
258 HW_VAR_ACM_CTRL,
259 (u8 *)(&e_aci));
260 break;
261 }
262 case HW_VAR_ACM_CTRL:{
263 u8 e_aci = *((u8 *) val);
264 union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)(&(
265 mac->ac[0].aifs));
266 u8 acm = p_aci_aifsn->f.acm;
267 u8 acm_ctrl = rtl_read_byte(rtlpriv, AcmHwCtrl);
268
269 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ?
270 0x0 : 0x1);
271
272 if (acm) {
273 switch (e_aci) {
274 case AC0_BE:
275 acm_ctrl |= AcmHw_BeqEn;
276 break;
277 case AC2_VI:
278 acm_ctrl |= AcmHw_ViqEn;
279 break;
280 case AC3_VO:
281 acm_ctrl |= AcmHw_VoqEn;
282 break;
283 default:
284 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
285 ("HW_VAR_ACM_CTRL acm set "
286 "failed: eACI is %d\n", acm));
287 break;
288 }
289 } else {
290 switch (e_aci) {
291 case AC0_BE:
292 acm_ctrl &= (~AcmHw_BeqEn);
293 break;
294 case AC2_VI:
295 acm_ctrl &= (~AcmHw_ViqEn);
296 break;
297 case AC3_VO:
298 acm_ctrl &= (~AcmHw_BeqEn);
299 break;
300 default:
301 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
302 ("switch case not process\n"));
303 break;
304 }
305 }
306
307 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
308 ("HW_VAR_ACM_CTRL Write 0x%X\n", acm_ctrl));
309 rtl_write_byte(rtlpriv, AcmHwCtrl, acm_ctrl);
310 break;
311 }
312 case HW_VAR_RCR:{
313 rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]);
314 rtlpci->receive_config = ((u32 *) (val))[0];
315 break;
316 }
317 case HW_VAR_RETRY_LIMIT:{
318 u8 retry_limit = ((u8 *) (val))[0];
319
320 rtl_write_word(rtlpriv, RETRY_LIMIT,
321 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
322 retry_limit << RETRY_LIMIT_LONG_SHIFT);
323 break;
324 }
325 case HW_VAR_DUAL_TSF_RST: {
326 break;
327 }
328 case HW_VAR_EFUSE_BYTES: {
329 rtlefuse->efuse_usedbytes = *((u16 *) val);
330 break;
331 }
332 case HW_VAR_EFUSE_USAGE: {
333 rtlefuse->efuse_usedpercentage = *((u8 *) val);
334 break;
335 }
336 case HW_VAR_IO_CMD: {
337 break;
338 }
339 case HW_VAR_WPA_CONFIG: {
340 rtl_write_byte(rtlpriv, REG_SECR, *((u8 *) val));
341 break;
342 }
343 case HW_VAR_SET_RPWM:{
344 break;
345 }
346 case HW_VAR_H2C_FW_PWRMODE:{
347 break;
348 }
349 case HW_VAR_FW_PSMODE_STATUS: {
350 ppsc->fw_current_inpsmode = *((bool *) val);
351 break;
352 }
353 case HW_VAR_H2C_FW_JOINBSSRPT:{
354 break;
355 }
356 case HW_VAR_AID:{
357 break;
358 }
359 case HW_VAR_CORRECT_TSF:{
360 break;
361 }
362 case HW_VAR_MRC: {
363 bool bmrc_toset = *((bool *)val);
364 u8 u1bdata = 0;
365
366 if (bmrc_toset) {
367 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
368 MASKBYTE0, 0x33);
369 u1bdata = (u8)rtl_get_bbreg(hw,
370 ROFDM1_TRXPATHENABLE,
371 MASKBYTE0);
372 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
373 MASKBYTE0,
374 ((u1bdata & 0xf0) | 0x03));
375 u1bdata = (u8)rtl_get_bbreg(hw,
376 ROFDM0_TRXPATHENABLE,
377 MASKBYTE1);
378 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
379 MASKBYTE1,
380 (u1bdata | 0x04));
381
382 /* Update current settings. */
383 rtlpriv->dm.current_mrc_switch = bmrc_toset;
384 } else {
385 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
386 MASKBYTE0, 0x13);
387 u1bdata = (u8)rtl_get_bbreg(hw,
388 ROFDM1_TRXPATHENABLE,
389 MASKBYTE0);
390 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
391 MASKBYTE0,
392 ((u1bdata & 0xf0) | 0x01));
393 u1bdata = (u8)rtl_get_bbreg(hw,
394 ROFDM0_TRXPATHENABLE,
395 MASKBYTE1);
396 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
397 MASKBYTE1, (u1bdata & 0xfb));
398
399 /* Update current settings. */
400 rtlpriv->dm.current_mrc_switch = bmrc_toset;
401 }
402
403 break;
404 }
405 default:
406 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
407 ("switch case not process\n"));
408 break;
409 }
410
411 }
412
413 void rtl92se_enable_hw_security_config(struct ieee80211_hw *hw)
414 {
415 struct rtl_priv *rtlpriv = rtl_priv(hw);
416 u8 sec_reg_value = 0x0;
417
418 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("PairwiseEncAlgorithm = %d "
419 "GroupEncAlgorithm = %d\n",
420 rtlpriv->sec.pairwise_enc_algorithm,
421 rtlpriv->sec.group_enc_algorithm));
422
423 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
424 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
425 ("not open hw encryption\n"));
426 return;
427 }
428
429 sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
430
431 if (rtlpriv->sec.use_defaultkey) {
432 sec_reg_value |= SCR_TXUSEDK;
433 sec_reg_value |= SCR_RXUSEDK;
434 }
435
436 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, ("The SECR-value %x\n",
437 sec_reg_value));
438
439 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
440
441 }
442
443 static u8 _rtl92ce_halset_sysclk(struct ieee80211_hw *hw, u8 data)
444 {
445 struct rtl_priv *rtlpriv = rtl_priv(hw);
446 u8 waitcount = 100;
447 bool bresult = false;
448 u8 tmpvalue;
449
450 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
451
452 /* Wait the MAC synchronized. */
453 udelay(400);
454
455 /* Check if it is set ready. */
456 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
457 bresult = ((tmpvalue & BIT(7)) == (data & BIT(7)));
458
459 if ((data & (BIT(6) | BIT(7))) == false) {
460 waitcount = 100;
461 tmpvalue = 0;
462
463 while (1) {
464 waitcount--;
465
466 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
467 if ((tmpvalue & BIT(6)))
468 break;
469
470 pr_err("wait for BIT(6) return value %x\n", tmpvalue);
471 if (waitcount == 0)
472 break;
473
474 udelay(10);
475 }
476
477 if (waitcount == 0)
478 bresult = false;
479 else
480 bresult = true;
481 }
482
483 return bresult;
484 }
485
486 void rtl8192se_gpiobit3_cfg_inputmode(struct ieee80211_hw *hw)
487 {
488 struct rtl_priv *rtlpriv = rtl_priv(hw);
489 u8 u1tmp;
490
491 /* The following config GPIO function */
492 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
493 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
494
495 /* config GPIO3 to input */
496 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
497 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
498
499 }
500
501 static u8 _rtl92se_rf_onoff_detect(struct ieee80211_hw *hw)
502 {
503 struct rtl_priv *rtlpriv = rtl_priv(hw);
504 u8 u1tmp;
505 u8 retval = ERFON;
506
507 /* The following config GPIO function */
508 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
509 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
510
511 /* config GPIO3 to input */
512 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
513 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
514
515 /* On some of the platform, driver cannot read correct
516 * value without delay between Write_GPIO_SEL and Read_GPIO_IN */
517 mdelay(10);
518
519 /* check GPIO3 */
520 u1tmp = rtl_read_byte(rtlpriv, GPIO_IN_SE);
521 retval = (u1tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? ERFON : ERFOFF;
522
523 return retval;
524 }
525
526 static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw *hw)
527 {
528 struct rtl_priv *rtlpriv = rtl_priv(hw);
529 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
530 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
531
532 u8 i;
533 u8 tmpu1b;
534 u16 tmpu2b;
535 u8 pollingcnt = 20;
536
537 if (rtlpci->first_init) {
538 /* Reset PCIE Digital */
539 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
540 tmpu1b &= 0xFE;
541 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
542 udelay(1);
543 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b | BIT(0));
544 }
545
546 /* Switch to SW IO control */
547 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
548 if (tmpu1b & BIT(7)) {
549 tmpu1b &= ~(BIT(6) | BIT(7));
550
551 /* Set failed, return to prevent hang. */
552 if (!_rtl92ce_halset_sysclk(hw, tmpu1b))
553 return;
554 }
555
556 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
557 udelay(50);
558 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
559 udelay(50);
560
561 /* Clear FW RPWM for FW control LPS.*/
562 rtl_write_byte(rtlpriv, RPWM, 0x0);
563
564 /* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */
565 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
566 tmpu1b &= 0x73;
567 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
568 /* wait for BIT 10/11/15 to pull high automatically!! */
569 mdelay(1);
570
571 rtl_write_byte(rtlpriv, CMDR, 0);
572 rtl_write_byte(rtlpriv, TCR, 0);
573
574 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
575 tmpu1b = rtl_read_byte(rtlpriv, 0x562);
576 tmpu1b |= 0x08;
577 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
578 tmpu1b &= ~(BIT(3));
579 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
580
581 /* Enable AFE clock source */
582 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
583 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
584 /* Delay 1.5ms */
585 mdelay(2);
586 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
587 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
588
589 /* Enable AFE Macro Block's Bandgap */
590 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
591 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
592 mdelay(1);
593
594 /* Enable AFE Mbias */
595 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
596 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
597 mdelay(1);
598
599 /* Enable LDOA15 block */
600 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
601 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
602
603 /* Set Digital Vdd to Retention isolation Path. */
604 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
605 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
606
607 /* For warm reboot NIC disappera bug. */
608 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
609 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
610
611 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
612
613 /* Enable AFE PLL Macro Block */
614 /* We need to delay 100u before enabling PLL. */
615 udelay(200);
616 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
617 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
618
619 /* for divider reset */
620 udelay(100);
621 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) |
622 BIT(4) | BIT(6)));
623 udelay(10);
624 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
625 udelay(10);
626
627 /* Enable MAC 80MHZ clock */
628 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
629 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
630 mdelay(1);
631
632 /* Release isolation AFE PLL & MD */
633 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
634
635 /* Enable MAC clock */
636 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
637 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
638
639 /* Enable Core digital and enable IOREG R/W */
640 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
641 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
642
643 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
644 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b & ~(BIT(7)));
645
646 /* enable REG_EN */
647 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
648
649 /* Switch the control path. */
650 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
651 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
652
653 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
654 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
655 if (!_rtl92ce_halset_sysclk(hw, tmpu1b))
656 return; /* Set failed, return to prevent hang. */
657
658 rtl_write_word(rtlpriv, CMDR, 0x07FC);
659
660 /* MH We must enable the section of code to prevent load IMEM fail. */
661 /* Load MAC register from WMAc temporarily We simulate macreg. */
662 /* txt HW will provide MAC txt later */
663 rtl_write_byte(rtlpriv, 0x6, 0x30);
664 rtl_write_byte(rtlpriv, 0x49, 0xf0);
665
666 rtl_write_byte(rtlpriv, 0x4b, 0x81);
667
668 rtl_write_byte(rtlpriv, 0xb5, 0x21);
669
670 rtl_write_byte(rtlpriv, 0xdc, 0xff);
671 rtl_write_byte(rtlpriv, 0xdd, 0xff);
672 rtl_write_byte(rtlpriv, 0xde, 0xff);
673 rtl_write_byte(rtlpriv, 0xdf, 0xff);
674
675 rtl_write_byte(rtlpriv, 0x11a, 0x00);
676 rtl_write_byte(rtlpriv, 0x11b, 0x00);
677
678 for (i = 0; i < 32; i++)
679 rtl_write_byte(rtlpriv, INIMCS_SEL + i, 0x1b);
680
681 rtl_write_byte(rtlpriv, 0x236, 0xff);
682
683 rtl_write_byte(rtlpriv, 0x503, 0x22);
684
685 if (ppsc->support_aspm && !ppsc->support_backdoor)
686 rtl_write_byte(rtlpriv, 0x560, 0x40);
687 else
688 rtl_write_byte(rtlpriv, 0x560, 0x00);
689
690 rtl_write_byte(rtlpriv, DBG_PORT, 0x91);
691
692 /* Set RX Desc Address */
693 rtl_write_dword(rtlpriv, RDQDA, rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
694 rtl_write_dword(rtlpriv, RCDA, rtlpci->rx_ring[RX_CMD_QUEUE].dma);
695
696 /* Set TX Desc Address */
697 rtl_write_dword(rtlpriv, TBKDA, rtlpci->tx_ring[BK_QUEUE].dma);
698 rtl_write_dword(rtlpriv, TBEDA, rtlpci->tx_ring[BE_QUEUE].dma);
699 rtl_write_dword(rtlpriv, TVIDA, rtlpci->tx_ring[VI_QUEUE].dma);
700 rtl_write_dword(rtlpriv, TVODA, rtlpci->tx_ring[VO_QUEUE].dma);
701 rtl_write_dword(rtlpriv, TBDA, rtlpci->tx_ring[BEACON_QUEUE].dma);
702 rtl_write_dword(rtlpriv, TCDA, rtlpci->tx_ring[TXCMD_QUEUE].dma);
703 rtl_write_dword(rtlpriv, TMDA, rtlpci->tx_ring[MGNT_QUEUE].dma);
704 rtl_write_dword(rtlpriv, THPDA, rtlpci->tx_ring[HIGH_QUEUE].dma);
705 rtl_write_dword(rtlpriv, HDA, rtlpci->tx_ring[HCCA_QUEUE].dma);
706
707 rtl_write_word(rtlpriv, CMDR, 0x37FC);
708
709 /* To make sure that TxDMA can ready to download FW. */
710 /* We should reset TxDMA if IMEM RPT was not ready. */
711 do {
712 tmpu1b = rtl_read_byte(rtlpriv, TCR);
713 if ((tmpu1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE)
714 break;
715
716 udelay(5);
717 } while (pollingcnt--);
718
719 if (pollingcnt <= 0) {
720 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
721 ("Polling TXDMA_INIT_VALUE "
722 "timeout!! Current TCR(%#x)\n", tmpu1b));
723 tmpu1b = rtl_read_byte(rtlpriv, CMDR);
724 rtl_write_byte(rtlpriv, CMDR, tmpu1b & (~TXDMA_EN));
725 udelay(2);
726 /* Reset TxDMA */
727 rtl_write_byte(rtlpriv, CMDR, tmpu1b | TXDMA_EN);
728 }
729
730 /* After MACIO reset,we must refresh LED state. */
731 if ((ppsc->rfoff_reason == RF_CHANGE_BY_IPS) ||
732 (ppsc->rfoff_reason == 0)) {
733 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
734 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
735 enum rf_pwrstate rfpwr_state_toset;
736 rfpwr_state_toset = _rtl92se_rf_onoff_detect(hw);
737
738 if (rfpwr_state_toset == ERFON)
739 rtl92se_sw_led_on(hw, pLed0);
740 }
741 }
742
743 static void _rtl92se_macconfig_after_fwdownload(struct ieee80211_hw *hw)
744 {
745 struct rtl_priv *rtlpriv = rtl_priv(hw);
746 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
747 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
748 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
749 u8 i;
750 u16 tmpu2b;
751
752 /* 1. System Configure Register (Offset: 0x0000 - 0x003F) */
753
754 /* 2. Command Control Register (Offset: 0x0040 - 0x004F) */
755 /* Turn on 0x40 Command register */
756 rtl_write_word(rtlpriv, CMDR, (BBRSTN | BB_GLB_RSTN |
757 SCHEDULE_EN | MACRXEN | MACTXEN | DDMA_EN | FW2HW_EN |
758 RXDMA_EN | TXDMA_EN | HCI_RXDMA_EN | HCI_TXDMA_EN));
759
760 /* Set TCR TX DMA pre 2 FULL enable bit */
761 rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) |
762 TXDMAPRE2FULL);
763
764 /* Set RCR */
765 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
766
767 /* 3. MACID Setting Register (Offset: 0x0050 - 0x007F) */
768
769 /* 4. Timing Control Register (Offset: 0x0080 - 0x009F) */
770 /* Set CCK/OFDM SIFS */
771 /* CCK SIFS shall always be 10us. */
772 rtl_write_word(rtlpriv, SIFS_CCK, 0x0a0a);
773 rtl_write_word(rtlpriv, SIFS_OFDM, 0x1010);
774
775 /* Set AckTimeout */
776 rtl_write_byte(rtlpriv, ACK_TIMEOUT, 0x40);
777
778 /* Beacon related */
779 rtl_write_word(rtlpriv, BCN_INTERVAL, 100);
780 rtl_write_word(rtlpriv, ATIMWND, 2);
781
782 /* 5. FIFO Control Register (Offset: 0x00A0 - 0x015F) */
783 /* 5.1 Initialize Number of Reserved Pages in Firmware Queue */
784 /* Firmware allocate now, associate with FW internal setting.!!! */
785
786 /* 5.2 Setting TX/RX page size 0/1/2/3/4=64/128/256/512/1024 */
787 /* 5.3 Set driver info, we only accept PHY status now. */
788 /* 5.4 Set RXDMA arbitration to control RXDMA/MAC/FW R/W for RXFIFO */
789 rtl_write_byte(rtlpriv, RXDMA, rtl_read_byte(rtlpriv, RXDMA) | BIT(6));
790
791 /* 6. Adaptive Control Register (Offset: 0x0160 - 0x01CF) */
792 /* Set RRSR to all legacy rate and HT rate
793 * CCK rate is supported by default.
794 * CCK rate will be filtered out only when associated
795 * AP does not support it.
796 * Only enable ACK rate to OFDM 24M
797 * Disable RRSR for CCK rate in A-Cut */
798
799 if (rtlhal->version == VERSION_8192S_ACUT)
800 rtl_write_byte(rtlpriv, RRSR, 0xf0);
801 else if (rtlhal->version == VERSION_8192S_BCUT)
802 rtl_write_byte(rtlpriv, RRSR, 0xff);
803 rtl_write_byte(rtlpriv, RRSR + 1, 0x01);
804 rtl_write_byte(rtlpriv, RRSR + 2, 0x00);
805
806 /* A-Cut IC do not support CCK rate. We forbid ARFR to */
807 /* fallback to CCK rate */
808 for (i = 0; i < 8; i++) {
809 /*Disable RRSR for CCK rate in A-Cut */
810 if (rtlhal->version == VERSION_8192S_ACUT)
811 rtl_write_dword(rtlpriv, ARFR0 + i * 4, 0x1f0ff0f0);
812 }
813
814 /* Different rate use different AMPDU size */
815 /* MCS32/ MCS15_SG use max AMPDU size 15*2=30K */
816 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, 0x0f);
817 /* MCS0/1/2/3 use max AMPDU size 4*2=8K */
818 rtl_write_word(rtlpriv, AGGLEN_LMT_L, 0x7442);
819 /* MCS4/5 use max AMPDU size 8*2=16K 6/7 use 10*2=20K */
820 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 2, 0xddd7);
821 /* MCS8/9 use max AMPDU size 8*2=16K 10/11 use 10*2=20K */
822 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 4, 0xd772);
823 /* MCS12/13/14/15 use max AMPDU size 15*2=30K */
824 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 6, 0xfffd);
825
826 /* Set Data / Response auto rate fallack retry count */
827 rtl_write_dword(rtlpriv, DARFRC, 0x04010000);
828 rtl_write_dword(rtlpriv, DARFRC + 4, 0x09070605);
829 rtl_write_dword(rtlpriv, RARFRC, 0x04010000);
830 rtl_write_dword(rtlpriv, RARFRC + 4, 0x09070605);
831
832 /* 7. EDCA Setting Register (Offset: 0x01D0 - 0x01FF) */
833 /* Set all rate to support SG */
834 rtl_write_word(rtlpriv, SG_RATE, 0xFFFF);
835
836 /* 8. WMAC, BA, and CCX related Register (Offset: 0x0200 - 0x023F) */
837 /* Set NAV protection length */
838 rtl_write_word(rtlpriv, NAV_PROT_LEN, 0x0080);
839 /* CF-END Threshold */
840 rtl_write_byte(rtlpriv, CFEND_TH, 0xFF);
841 /* Set AMPDU minimum space */
842 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 0x07);
843 /* Set TXOP stall control for several queue/HI/BCN/MGT/ */
844 rtl_write_byte(rtlpriv, TXOP_STALL_CTRL, 0x00);
845
846 /* 9. Security Control Register (Offset: 0x0240 - 0x025F) */
847 /* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */
848 /* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */
849 /* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */
850 /* 13. Test Mode and Debug Control Register (Offset: 0x0310 - 0x034F) */
851
852 /* 14. Set driver info, we only accept PHY status now. */
853 rtl_write_byte(rtlpriv, RXDRVINFO_SZ, 4);
854
855 /* 15. For EEPROM R/W Workaround */
856 /* 16. For EFUSE to share REG_SYS_FUNC_EN with EEPROM!!! */
857 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
858 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmpu2b | BIT(13));
859 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
860 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, tmpu2b & (~BIT(8)));
861
862 /* 17. For EFUSE */
863 /* We may R/W EFUSE in EEPROM mode */
864 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
865 u8 tempval;
866
867 tempval = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL + 1);
868 tempval &= 0xFE;
869 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, tempval);
870
871 /* Change Program timing */
872 rtl_write_byte(rtlpriv, REG_EFUSE_CTRL + 3, 0x72);
873 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("EFUSE CONFIG OK\n"));
874 }
875
876 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("OK\n"));
877
878 }
879
880 static void _rtl92se_hw_configure(struct ieee80211_hw *hw)
881 {
882 struct rtl_priv *rtlpriv = rtl_priv(hw);
883 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
884 struct rtl_phy *rtlphy = &(rtlpriv->phy);
885 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
886
887 u8 reg_bw_opmode = 0;
888 u32 reg_rrsr = 0;
889 u8 regtmp = 0;
890
891 reg_bw_opmode = BW_OPMODE_20MHZ;
892 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
893
894 regtmp = rtl_read_byte(rtlpriv, INIRTSMCS_SEL);
895 reg_rrsr = ((reg_rrsr & 0x000fffff) << 8) | regtmp;
896 rtl_write_dword(rtlpriv, INIRTSMCS_SEL, reg_rrsr);
897 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
898
899 /* Set Retry Limit here */
900 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
901 (u8 *)(&rtlpci->shortretry_limit));
902
903 rtl_write_byte(rtlpriv, MLT, 0x8f);
904
905 /* For Min Spacing configuration. */
906 switch (rtlphy->rf_type) {
907 case RF_1T2R:
908 case RF_1T1R:
909 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
910 break;
911 case RF_2T2R:
912 case RF_2T2R_GREEN:
913 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
914 break;
915 }
916 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, rtlhal->minspace_cfg);
917 }
918
919 int rtl92se_hw_init(struct ieee80211_hw *hw)
920 {
921 struct rtl_priv *rtlpriv = rtl_priv(hw);
922 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
923 struct rtl_phy *rtlphy = &(rtlpriv->phy);
924 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
925 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
926 u8 tmp_byte = 0;
927
928 bool rtstatus = true;
929 u8 tmp_u1b;
930 int err = false;
931 u8 i;
932 int wdcapra_add[] = {
933 EDCAPARA_BE, EDCAPARA_BK,
934 EDCAPARA_VI, EDCAPARA_VO};
935 u8 secr_value = 0x0;
936
937 rtlpci->being_init_adapter = true;
938
939 rtlpriv->intf_ops->disable_aspm(hw);
940
941 /* 1. MAC Initialize */
942 /* Before FW download, we have to set some MAC register */
943 _rtl92se_macconfig_before_fwdownload(hw);
944
945 rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv,
946 PMC_FSM) >> 16) & 0xF);
947
948 rtl8192se_gpiobit3_cfg_inputmode(hw);
949
950 /* 2. download firmware */
951 rtstatus = rtl92s_download_fw(hw);
952 if (!rtstatus) {
953 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
954 ("Failed to download FW. "
955 "Init HW without FW now.., "
956 "Please copy FW into"
957 "/lib/firmware/rtlwifi\n"));
958 return 1;
959 }
960
961 /* After FW download, we have to reset MAC register */
962 _rtl92se_macconfig_after_fwdownload(hw);
963
964 /*Retrieve default FW Cmd IO map. */
965 rtlhal->fwcmd_iomap = rtl_read_word(rtlpriv, LBUS_MON_ADDR);
966 rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, LBUS_ADDR_MASK);
967
968 /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */
969 if (rtl92s_phy_mac_config(hw) != true) {
970 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("MAC Config failed\n"));
971 return rtstatus;
972 }
973
974 /* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */
975 /* We must set flag avoid BB/RF config period later!! */
976 rtl_write_dword(rtlpriv, CMDR, 0x37FC);
977
978 /* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */
979 if (rtl92s_phy_bb_config(hw) != true) {
980 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, ("BB Config failed\n"));
981 return rtstatus;
982 }
983
984 /* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */
985 /* Before initalizing RF. We can not use FW to do RF-R/W. */
986
987 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
988
989 /* RF Power Save */
990 #if 0
991 /* H/W or S/W RF OFF before sleep. */
992 if (rtlpriv->psc.rfoff_reason > RF_CHANGE_BY_PS) {
993 u32 rfoffreason = rtlpriv->psc.rfoff_reason;
994
995 rtlpriv->psc.rfoff_reason = RF_CHANGE_BY_INIT;
996 rtlpriv->psc.rfpwr_state = ERFON;
997 /* FIXME: check spinlocks if this block is uncommented */
998 rtl_ps_set_rf_state(hw, ERFOFF, rfoffreason);
999 } else {
1000 /* gpio radio on/off is out of adapter start */
1001 if (rtlpriv->psc.hwradiooff == false) {
1002 rtlpriv->psc.rfpwr_state = ERFON;
1003 rtlpriv->psc.rfoff_reason = 0;
1004 }
1005 }
1006 #endif
1007
1008 /* Before RF-R/W we must execute the IO from Scott's suggestion. */
1009 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, 0xDB);
1010 if (rtlhal->version == VERSION_8192S_ACUT)
1011 rtl_write_byte(rtlpriv, SPS1_CTRL + 3, 0x07);
1012 else
1013 rtl_write_byte(rtlpriv, RF_CTRL, 0x07);
1014
1015 if (rtl92s_phy_rf_config(hw) != true) {
1016 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("RF Config failed\n"));
1017 return rtstatus;
1018 }
1019
1020 /* After read predefined TXT, we must set BB/MAC/RF
1021 * register as our requirement */
1022
1023 rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw,
1024 (enum radio_path)0,
1025 RF_CHNLBW,
1026 RFREG_OFFSET_MASK);
1027 rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw,
1028 (enum radio_path)1,
1029 RF_CHNLBW,
1030 RFREG_OFFSET_MASK);
1031
1032 /*---- Set CCK and OFDM Block "ON"----*/
1033 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1034 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1035
1036 /*3 Set Hardware(Do nothing now) */
1037 _rtl92se_hw_configure(hw);
1038
1039 /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1040 /* TX power index for different rate set. */
1041 /* Get original hw reg values */
1042 rtl92s_phy_get_hw_reg_originalvalue(hw);
1043 /* Write correct tx power index */
1044 rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1045
1046 /* We must set MAC address after firmware download. */
1047 for (i = 0; i < 6; i++)
1048 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1049
1050 /* EEPROM R/W workaround */
1051 tmp_u1b = rtl_read_byte(rtlpriv, MAC_PINMUX_CFG);
1052 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, tmp_u1b & (~BIT(3)));
1053
1054 rtl_write_byte(rtlpriv, 0x4d, 0x0);
1055
1056 if (hal_get_firmwareversion(rtlpriv) >= 0x49) {
1057 tmp_byte = rtl_read_byte(rtlpriv, FW_RSVD_PG_CRTL) & (~BIT(4));
1058 tmp_byte = tmp_byte | BIT(5);
1059 rtl_write_byte(rtlpriv, FW_RSVD_PG_CRTL, tmp_byte);
1060 rtl_write_dword(rtlpriv, TXDESC_MSK, 0xFFFFCFFF);
1061 }
1062
1063 /* We enable high power and RA related mechanism after NIC
1064 * initialized. */
1065 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT);
1066
1067 /* Add to prevent ASPM bug. */
1068 /* Always enable hst and NIC clock request. */
1069 rtl92s_phy_switch_ephy_parameter(hw);
1070
1071 /* Security related
1072 * 1. Clear all H/W keys.
1073 * 2. Enable H/W encryption/decryption. */
1074 rtl_cam_reset_all_entry(hw);
1075 secr_value |= SCR_TXENCENABLE;
1076 secr_value |= SCR_RXENCENABLE;
1077 secr_value |= SCR_NOSKMC;
1078 rtl_write_byte(rtlpriv, REG_SECR, secr_value);
1079
1080 for (i = 0; i < 4; i++)
1081 rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322);
1082
1083 if (rtlphy->rf_type == RF_1T2R) {
1084 bool mrc2set = true;
1085 /* Turn on B-Path */
1086 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set);
1087 }
1088
1089 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON);
1090 rtl92s_dm_init(hw);
1091 rtlpci->being_init_adapter = false;
1092
1093 return err;
1094 }
1095
1096 void rtl92se_set_mac_addr(struct rtl_io *io, const u8 * addr)
1097 {
1098 }
1099
1100 void rtl92se_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1101 {
1102 struct rtl_priv *rtlpriv = rtl_priv(hw);
1103 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1104 u32 reg_rcr = rtlpci->receive_config;
1105
1106 if (rtlpriv->psc.rfpwr_state != ERFON)
1107 return;
1108
1109 if (check_bssid) {
1110 reg_rcr |= (RCR_CBSSID);
1111 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1112 } else if (check_bssid == false) {
1113 reg_rcr &= (~RCR_CBSSID);
1114 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1115 }
1116
1117 }
1118
1119 static int _rtl92se_set_media_status(struct ieee80211_hw *hw,
1120 enum nl80211_iftype type)
1121 {
1122 struct rtl_priv *rtlpriv = rtl_priv(hw);
1123 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1124 u32 temp;
1125 bt_msr &= ~MSR_LINK_MASK;
1126
1127 switch (type) {
1128 case NL80211_IFTYPE_UNSPECIFIED:
1129 bt_msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
1130 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1131 ("Set Network type to NO LINK!\n"));
1132 break;
1133 case NL80211_IFTYPE_ADHOC:
1134 bt_msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
1135 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1136 ("Set Network type to Ad Hoc!\n"));
1137 break;
1138 case NL80211_IFTYPE_STATION:
1139 bt_msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
1140 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1141 ("Set Network type to STA!\n"));
1142 break;
1143 case NL80211_IFTYPE_AP:
1144 bt_msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
1145 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1146 ("Set Network type to AP!\n"));
1147 break;
1148 default:
1149 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1150 ("Network type %d not support!\n", type));
1151 return 1;
1152 break;
1153
1154 }
1155
1156 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1157
1158 temp = rtl_read_dword(rtlpriv, TCR);
1159 rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8)));
1160 rtl_write_dword(rtlpriv, TCR, temp | BIT(8));
1161
1162
1163 return 0;
1164 }
1165
1166 /* HW_VAR_MEDIA_STATUS & HW_VAR_CECHK_BSSID */
1167 int rtl92se_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1168 {
1169 struct rtl_priv *rtlpriv = rtl_priv(hw);
1170
1171 if (_rtl92se_set_media_status(hw, type))
1172 return -EOPNOTSUPP;
1173
1174 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1175 if (type != NL80211_IFTYPE_AP)
1176 rtl92se_set_check_bssid(hw, true);
1177 } else {
1178 rtl92se_set_check_bssid(hw, false);
1179 }
1180
1181 return 0;
1182 }
1183
1184 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1185 void rtl92se_set_qos(struct ieee80211_hw *hw, int aci)
1186 {
1187 struct rtl_priv *rtlpriv = rtl_priv(hw);
1188 rtl92s_dm_init_edca_turbo(hw);
1189
1190 switch (aci) {
1191 case AC1_BK:
1192 rtl_write_dword(rtlpriv, EDCAPARA_BK, 0xa44f);
1193 break;
1194 case AC0_BE:
1195 /* rtl_write_dword(rtlpriv, EDCAPARA_BE, u4b_ac_param); */
1196 break;
1197 case AC2_VI:
1198 rtl_write_dword(rtlpriv, EDCAPARA_VI, 0x5e4322);
1199 break;
1200 case AC3_VO:
1201 rtl_write_dword(rtlpriv, EDCAPARA_VO, 0x2f3222);
1202 break;
1203 default:
1204 RT_ASSERT(false, ("invalid aci: %d !\n", aci));
1205 break;
1206 }
1207 }
1208
1209 void rtl92se_enable_interrupt(struct ieee80211_hw *hw)
1210 {
1211 struct rtl_priv *rtlpriv = rtl_priv(hw);
1212 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1213
1214 rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]);
1215 /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */
1216 rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F);
1217 }
1218
1219 void rtl92se_disable_interrupt(struct ieee80211_hw *hw)
1220 {
1221 struct rtl_priv *rtlpriv;
1222 struct rtl_pci *rtlpci;
1223
1224 rtlpriv = rtl_priv(hw);
1225 /* if firmware not available, no interrupts */
1226 if (!rtlpriv || !rtlpriv->max_fw_size)
1227 return;
1228 rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1229 rtl_write_dword(rtlpriv, INTA_MASK, 0);
1230 rtl_write_dword(rtlpriv, INTA_MASK + 4, 0);
1231
1232 synchronize_irq(rtlpci->pdev->irq);
1233 }
1234
1235
1236 static u8 _rtl92s_set_sysclk(struct ieee80211_hw *hw, u8 data)
1237 {
1238 struct rtl_priv *rtlpriv = rtl_priv(hw);
1239 u8 waitcnt = 100;
1240 bool result = false;
1241 u8 tmp;
1242
1243 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
1244
1245 /* Wait the MAC synchronized. */
1246 udelay(400);
1247
1248 /* Check if it is set ready. */
1249 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1250 result = ((tmp & BIT(7)) == (data & BIT(7)));
1251
1252 if ((data & (BIT(6) | BIT(7))) == false) {
1253 waitcnt = 100;
1254 tmp = 0;
1255
1256 while (1) {
1257 waitcnt--;
1258 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1259
1260 if ((tmp & BIT(6)))
1261 break;
1262
1263 pr_err("wait for BIT(6) return value %x\n", tmp);
1264
1265 if (waitcnt == 0)
1266 break;
1267 udelay(10);
1268 }
1269
1270 if (waitcnt == 0)
1271 result = false;
1272 else
1273 result = true;
1274 }
1275
1276 return result;
1277 }
1278
1279 static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw)
1280 {
1281 struct rtl_priv *rtlpriv = rtl_priv(hw);
1282 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1283 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1284 u8 u1btmp;
1285
1286 if (rtlhal->driver_going2unload)
1287 rtl_write_byte(rtlpriv, 0x560, 0x0);
1288
1289 /* Power save for BB/RF */
1290 u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
1291 u1btmp |= BIT(0);
1292 rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
1293 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
1294 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
1295 rtl_write_word(rtlpriv, CMDR, 0x57FC);
1296 udelay(100);
1297 rtl_write_word(rtlpriv, CMDR, 0x77FC);
1298 rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
1299 udelay(10);
1300 rtl_write_word(rtlpriv, CMDR, 0x37FC);
1301 udelay(10);
1302 rtl_write_word(rtlpriv, CMDR, 0x77FC);
1303 udelay(10);
1304 rtl_write_word(rtlpriv, CMDR, 0x57FC);
1305 rtl_write_word(rtlpriv, CMDR, 0x0000);
1306
1307 if (rtlhal->driver_going2unload) {
1308 u1btmp = rtl_read_byte(rtlpriv, (REG_SYS_FUNC_EN + 1));
1309 u1btmp &= ~(BIT(0));
1310 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1btmp);
1311 }
1312
1313 u1btmp = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1314
1315 /* Add description. After switch control path. register
1316 * after page1 will be invisible. We can not do any IO
1317 * for register>0x40. After resume&MACIO reset, we need
1318 * to remember previous reg content. */
1319 if (u1btmp & BIT(7)) {
1320 u1btmp &= ~(BIT(6) | BIT(7));
1321 if (!_rtl92s_set_sysclk(hw, u1btmp)) {
1322 pr_err("Switch ctrl path fail\n");
1323 return;
1324 }
1325 }
1326
1327 /* Power save for MAC */
1328 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS &&
1329 !rtlhal->driver_going2unload) {
1330 /* enable LED function */
1331 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1332 /* SW/HW radio off or halt adapter!! For example S3/S4 */
1333 } else {
1334 /* LED function disable. Power range is about 8mA now. */
1335 /* if write 0xF1 disconnet_pci power
1336 * ifconfig wlan0 down power are both high 35:70 */
1337 /* if write oxF9 disconnet_pci power
1338 * ifconfig wlan0 down power are both low 12:45*/
1339 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1340 }
1341
1342 rtl_write_byte(rtlpriv, SYS_CLKR + 1, 0x70);
1343 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, 0x68);
1344 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x00);
1345 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1346 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, 0x0E);
1347 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1348
1349 }
1350
1351 static void _rtl92se_gen_refreshledstate(struct ieee80211_hw *hw)
1352 {
1353 struct rtl_priv *rtlpriv = rtl_priv(hw);
1354 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1355 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1356 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
1357
1358 if (rtlpci->up_first_time == 1)
1359 return;
1360
1361 if (rtlpriv->psc.rfoff_reason == RF_CHANGE_BY_IPS)
1362 rtl92se_sw_led_on(hw, pLed0);
1363 else
1364 rtl92se_sw_led_off(hw, pLed0);
1365 }
1366
1367
1368 static void _rtl92se_power_domain_init(struct ieee80211_hw *hw)
1369 {
1370 struct rtl_priv *rtlpriv = rtl_priv(hw);
1371 u16 tmpu2b;
1372 u8 tmpu1b;
1373
1374 rtlpriv->psc.pwrdomain_protect = true;
1375
1376 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1377 if (tmpu1b & BIT(7)) {
1378 tmpu1b &= ~(BIT(6) | BIT(7));
1379 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1380 rtlpriv->psc.pwrdomain_protect = false;
1381 return;
1382 }
1383 }
1384
1385 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
1386 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1387
1388 /* Reset MAC-IO and CPU and Core Digital BIT10/11/15 */
1389 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1390
1391 /* If IPS we need to turn LED on. So we not
1392 * not disable BIT 3/7 of reg3. */
1393 if (rtlpriv->psc.rfoff_reason & (RF_CHANGE_BY_IPS | RF_CHANGE_BY_HW))
1394 tmpu1b &= 0xFB;
1395 else
1396 tmpu1b &= 0x73;
1397
1398 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
1399 /* wait for BIT 10/11/15 to pull high automatically!! */
1400 mdelay(1);
1401
1402 rtl_write_byte(rtlpriv, CMDR, 0);
1403 rtl_write_byte(rtlpriv, TCR, 0);
1404
1405 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
1406 tmpu1b = rtl_read_byte(rtlpriv, 0x562);
1407 tmpu1b |= 0x08;
1408 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1409 tmpu1b &= ~(BIT(3));
1410 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1411
1412 /* Enable AFE clock source */
1413 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
1414 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
1415 /* Delay 1.5ms */
1416 udelay(1500);
1417 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
1418 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
1419
1420 /* Enable AFE Macro Block's Bandgap */
1421 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1422 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
1423 mdelay(1);
1424
1425 /* Enable AFE Mbias */
1426 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1427 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
1428 mdelay(1);
1429
1430 /* Enable LDOA15 block */
1431 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
1432 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
1433
1434 /* Set Digital Vdd to Retention isolation Path. */
1435 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
1436 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
1437
1438
1439 /* For warm reboot NIC disappera bug. */
1440 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1441 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
1442
1443 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
1444
1445 /* Enable AFE PLL Macro Block */
1446 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
1447 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
1448 /* Enable MAC 80MHZ clock */
1449 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
1450 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
1451 mdelay(1);
1452
1453 /* Release isolation AFE PLL & MD */
1454 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
1455
1456 /* Enable MAC clock */
1457 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1458 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
1459
1460 /* Enable Core digital and enable IOREG R/W */
1461 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1462 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
1463 /* enable REG_EN */
1464 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
1465
1466 /* Switch the control path. */
1467 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1468 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
1469
1470 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1471 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
1472 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1473 rtlpriv->psc.pwrdomain_protect = false;
1474 return;
1475 }
1476
1477 rtl_write_word(rtlpriv, CMDR, 0x37FC);
1478
1479 /* After MACIO reset,we must refresh LED state. */
1480 _rtl92se_gen_refreshledstate(hw);
1481
1482 rtlpriv->psc.pwrdomain_protect = false;
1483 }
1484
1485 void rtl92se_card_disable(struct ieee80211_hw *hw)
1486 {
1487 struct rtl_priv *rtlpriv = rtl_priv(hw);
1488 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1489 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1490 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1491 enum nl80211_iftype opmode;
1492 u8 wait = 30;
1493
1494 rtlpriv->intf_ops->enable_aspm(hw);
1495
1496 if (rtlpci->driver_is_goingto_unload ||
1497 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1498 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1499
1500 /* we should chnge GPIO to input mode
1501 * this will drop away current about 25mA*/
1502 rtl8192se_gpiobit3_cfg_inputmode(hw);
1503
1504 /* this is very important for ips power save */
1505 while (wait-- >= 10 && rtlpriv->psc.pwrdomain_protect) {
1506 if (rtlpriv->psc.pwrdomain_protect)
1507 mdelay(20);
1508 else
1509 break;
1510 }
1511
1512 mac->link_state = MAC80211_NOLINK;
1513 opmode = NL80211_IFTYPE_UNSPECIFIED;
1514 _rtl92se_set_media_status(hw, opmode);
1515
1516 _rtl92s_phy_set_rfhalt(hw);
1517 udelay(100);
1518 }
1519
1520 void rtl92se_interrupt_recognized(struct ieee80211_hw *hw, u32 *p_inta,
1521 u32 *p_intb)
1522 {
1523 struct rtl_priv *rtlpriv = rtl_priv(hw);
1524 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1525
1526 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1527 rtl_write_dword(rtlpriv, ISR, *p_inta);
1528
1529 *p_intb = rtl_read_dword(rtlpriv, ISR + 4) & rtlpci->irq_mask[1];
1530 rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1531 }
1532
1533 void rtl92se_set_beacon_related_registers(struct ieee80211_hw *hw)
1534 {
1535 struct rtl_priv *rtlpriv = rtl_priv(hw);
1536 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1537 u16 bcntime_cfg = 0;
1538 u16 bcn_cw = 6, bcn_ifs = 0xf;
1539 u16 atim_window = 2;
1540
1541 /* ATIM Window (in unit of TU). */
1542 rtl_write_word(rtlpriv, ATIMWND, atim_window);
1543
1544 /* Beacon interval (in unit of TU). */
1545 rtl_write_word(rtlpriv, BCN_INTERVAL, mac->beacon_interval);
1546
1547 /* DrvErlyInt (in unit of TU). (Time to send
1548 * interrupt to notify driver to change
1549 * beacon content) */
1550 rtl_write_word(rtlpriv, BCN_DRV_EARLY_INT, 10 << 4);
1551
1552 /* BcnDMATIM(in unit of us). Indicates the
1553 * time before TBTT to perform beacon queue DMA */
1554 rtl_write_word(rtlpriv, BCN_DMATIME, 256);
1555
1556 /* Force beacon frame transmission even
1557 * after receiving beacon frame from
1558 * other ad hoc STA */
1559 rtl_write_byte(rtlpriv, BCN_ERR_THRESH, 100);
1560
1561 /* Beacon Time Configuration */
1562 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1563 bcntime_cfg |= (bcn_cw << BCN_TCFG_CW_SHIFT);
1564
1565 /* TODO: bcn_ifs may required to be changed on ASIC */
1566 bcntime_cfg |= bcn_ifs << BCN_TCFG_IFS;
1567
1568 /*for beacon changed */
1569 rtl92s_phy_set_beacon_hwreg(hw, mac->beacon_interval);
1570 }
1571
1572 void rtl92se_set_beacon_interval(struct ieee80211_hw *hw)
1573 {
1574 struct rtl_priv *rtlpriv = rtl_priv(hw);
1575 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1576 u16 bcn_interval = mac->beacon_interval;
1577
1578 /* Beacon interval (in unit of TU). */
1579 rtl_write_word(rtlpriv, BCN_INTERVAL, bcn_interval);
1580 /* 2008.10.24 added by tynli for beacon changed. */
1581 rtl92s_phy_set_beacon_hwreg(hw, bcn_interval);
1582 }
1583
1584 void rtl92se_update_interrupt_mask(struct ieee80211_hw *hw,
1585 u32 add_msr, u32 rm_msr)
1586 {
1587 struct rtl_priv *rtlpriv = rtl_priv(hw);
1588 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1589
1590 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1591 ("add_msr:%x, rm_msr:%x\n", add_msr, rm_msr));
1592
1593 if (add_msr)
1594 rtlpci->irq_mask[0] |= add_msr;
1595
1596 if (rm_msr)
1597 rtlpci->irq_mask[0] &= (~rm_msr);
1598
1599 rtl92se_disable_interrupt(hw);
1600 rtl92se_enable_interrupt(hw);
1601 }
1602
1603 static void _rtl8192se_get_IC_Inferiority(struct ieee80211_hw *hw)
1604 {
1605 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1606 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1607 u8 efuse_id;
1608
1609 rtlhal->ic_class = IC_INFERIORITY_A;
1610
1611 /* Only retrieving while using EFUSE. */
1612 if ((rtlefuse->epromtype == EEPROM_BOOT_EFUSE) &&
1613 !rtlefuse->autoload_failflag) {
1614 efuse_id = efuse_read_1byte(hw, EFUSE_IC_ID_OFFSET);
1615
1616 if (efuse_id == 0xfe)
1617 rtlhal->ic_class = IC_INFERIORITY_B;
1618 }
1619 }
1620
1621 static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1622 {
1623 struct rtl_priv *rtlpriv = rtl_priv(hw);
1624 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1625 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1626 u16 i, usvalue;
1627 u16 eeprom_id;
1628 u8 tempval;
1629 u8 hwinfo[HWSET_MAX_SIZE_92S];
1630 u8 rf_path, index;
1631
1632 if (rtlefuse->epromtype == EEPROM_93C46) {
1633 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1634 ("RTL819X Not boot from eeprom, check it !!"));
1635 } else if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1636 rtl_efuse_shadow_map_update(hw);
1637
1638 memcpy((void *)hwinfo, (void *)
1639 &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1640 HWSET_MAX_SIZE_92S);
1641 }
1642
1643 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP\n"),
1644 hwinfo, HWSET_MAX_SIZE_92S);
1645
1646 eeprom_id = *((u16 *)&hwinfo[0]);
1647 if (eeprom_id != RTL8190_EEPROM_ID) {
1648 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1649 ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
1650 rtlefuse->autoload_failflag = true;
1651 } else {
1652 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1653 rtlefuse->autoload_failflag = false;
1654 }
1655
1656 if (rtlefuse->autoload_failflag)
1657 return;
1658
1659 _rtl8192se_get_IC_Inferiority(hw);
1660
1661 /* Read IC Version && Channel Plan */
1662 /* VID, DID SE 0xA-D */
1663 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1664 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1665 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1666 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1667 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1668
1669 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1670 ("EEPROMId = 0x%4x\n", eeprom_id));
1671 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1672 ("EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid));
1673 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1674 ("EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did));
1675 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1676 ("EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid));
1677 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1678 ("EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid));
1679
1680 for (i = 0; i < 6; i += 2) {
1681 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1682 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1683 }
1684
1685 for (i = 0; i < 6; i++)
1686 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1687
1688 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1689 ("%pM\n", rtlefuse->dev_addr));
1690
1691 /* Get Tx Power Level by Channel */
1692 /* Read Tx power of Channel 1 ~ 14 from EEPROM. */
1693 /* 92S suupport RF A & B */
1694 for (rf_path = 0; rf_path < 2; rf_path++) {
1695 for (i = 0; i < 3; i++) {
1696 /* Read CCK RF A & B Tx power */
1697 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1698 hwinfo[EEPROM_TXPOWERBASE + rf_path * 3 + i];
1699
1700 /* Read OFDM RF A & B Tx power for 1T */
1701 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1702 hwinfo[EEPROM_TXPOWERBASE + 6 + rf_path * 3 + i];
1703
1704 /* Read OFDM RF A & B Tx power for 2T */
1705 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][i]
1706 = hwinfo[EEPROM_TXPOWERBASE + 12 +
1707 rf_path * 3 + i];
1708 }
1709 }
1710
1711 for (rf_path = 0; rf_path < 2; rf_path++)
1712 for (i = 0; i < 3; i++)
1713 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1714 ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
1715 i, rtlefuse->eeprom_chnlarea_txpwr_cck
1716 [rf_path][i]));
1717 for (rf_path = 0; rf_path < 2; rf_path++)
1718 for (i = 0; i < 3; i++)
1719 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1720 ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1721 rf_path, i,
1722 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1723 [rf_path][i]));
1724 for (rf_path = 0; rf_path < 2; rf_path++)
1725 for (i = 0; i < 3; i++)
1726 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1727 ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1728 rf_path, i,
1729 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif
1730 [rf_path][i]));
1731
1732 for (rf_path = 0; rf_path < 2; rf_path++) {
1733
1734 /* Assign dedicated channel tx power */
1735 for (i = 0; i < 14; i++) {
1736 /* channel 1~3 use the same Tx Power Level. */
1737 if (i < 3)
1738 index = 0;
1739 /* Channel 4-8 */
1740 else if (i < 8)
1741 index = 1;
1742 /* Channel 9-14 */
1743 else
1744 index = 2;
1745
1746 /* Record A & B CCK /OFDM - 1T/2T Channel area
1747 * tx power */
1748 rtlefuse->txpwrlevel_cck[rf_path][i] =
1749 rtlefuse->eeprom_chnlarea_txpwr_cck
1750 [rf_path][index];
1751 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1752 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1753 [rf_path][index];
1754 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1755 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif
1756 [rf_path][index];
1757 }
1758
1759 for (i = 0; i < 14; i++) {
1760 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1761 ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
1762 "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
1763 rtlefuse->txpwrlevel_cck[rf_path][i],
1764 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1765 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]));
1766 }
1767 }
1768
1769 for (rf_path = 0; rf_path < 2; rf_path++) {
1770 for (i = 0; i < 3; i++) {
1771 /* Read Power diff limit. */
1772 rtlefuse->eeprom_pwrgroup[rf_path][i] =
1773 hwinfo[EEPROM_TXPWRGROUP + rf_path * 3 + i];
1774 }
1775 }
1776
1777 for (rf_path = 0; rf_path < 2; rf_path++) {
1778 /* Fill Pwr group */
1779 for (i = 0; i < 14; i++) {
1780 /* Chanel 1-3 */
1781 if (i < 3)
1782 index = 0;
1783 /* Channel 4-8 */
1784 else if (i < 8)
1785 index = 1;
1786 /* Channel 9-13 */
1787 else
1788 index = 2;
1789
1790 rtlefuse->pwrgroup_ht20[rf_path][i] =
1791 (rtlefuse->eeprom_pwrgroup[rf_path][index] &
1792 0xf);
1793 rtlefuse->pwrgroup_ht40[rf_path][i] =
1794 ((rtlefuse->eeprom_pwrgroup[rf_path][index] &
1795 0xf0) >> 4);
1796
1797 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1798 ("RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1799 rf_path, i,
1800 rtlefuse->pwrgroup_ht20[rf_path][i]));
1801 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1802 ("RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1803 rf_path, i,
1804 rtlefuse->pwrgroup_ht40[rf_path][i]));
1805 }
1806 }
1807
1808 for (i = 0; i < 14; i++) {
1809 /* Read tx power difference between HT OFDM 20/40 MHZ */
1810 /* channel 1-3 */
1811 if (i < 3)
1812 index = 0;
1813 /* Channel 4-8 */
1814 else if (i < 8)
1815 index = 1;
1816 /* Channel 9-14 */
1817 else
1818 index = 2;
1819
1820 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_HT20_DIFF +
1821 index]) & 0xff;
1822 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1823 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1824 ((tempval >> 4) & 0xF);
1825
1826 /* Read OFDM<->HT tx power diff */
1827 /* Channel 1-3 */
1828 if (i < 3)
1829 index = 0;
1830 /* Channel 4-8 */
1831 else if (i < 8)
1832 index = 0x11;
1833 /* Channel 9-14 */
1834 else
1835 index = 1;
1836
1837 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_OFDM_DIFF + index])
1838 & 0xff;
1839 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] =
1840 (tempval & 0xF);
1841 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1842 ((tempval >> 4) & 0xF);
1843
1844 tempval = (*(u8 *)&hwinfo[TX_PWR_SAFETY_CHK]);
1845 rtlefuse->txpwr_safetyflag = (tempval & 0x01);
1846 }
1847
1848 rtlefuse->eeprom_regulatory = 0;
1849 if (rtlefuse->eeprom_version >= 2) {
1850 /* BIT(0)~2 */
1851 if (rtlefuse->eeprom_version >= 4)
1852 rtlefuse->eeprom_regulatory =
1853 (hwinfo[EEPROM_REGULATORY] & 0x7);
1854 else /* BIT(0) */
1855 rtlefuse->eeprom_regulatory =
1856 (hwinfo[EEPROM_REGULATORY] & 0x1);
1857 }
1858 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1859 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory));
1860
1861 for (i = 0; i < 14; i++)
1862 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1863 ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1864 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]));
1865 for (i = 0; i < 14; i++)
1866 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1867 ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
1868 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]));
1869 for (i = 0; i < 14; i++)
1870 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1871 ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1872 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]));
1873 for (i = 0; i < 14; i++)
1874 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1875 ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
1876 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]));
1877
1878 RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("TxPwrSafetyFlag = %d\n",
1879 rtlefuse->txpwr_safetyflag));
1880
1881 /* Read RF-indication and Tx Power gain
1882 * index diff of legacy to HT OFDM rate. */
1883 tempval = (*(u8 *)&hwinfo[EEPROM_RFIND_POWERDIFF]) & 0xff;
1884 rtlefuse->eeprom_txpowerdiff = tempval;
1885 rtlefuse->legacy_httxpowerdiff =
1886 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0];
1887
1888 RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("TxPowerDiff = %#x\n",
1889 rtlefuse->eeprom_txpowerdiff));
1890
1891 /* Get TSSI value for each path. */
1892 usvalue = *(u16 *)&hwinfo[EEPROM_TSSI_A];
1893 rtlefuse->eeprom_tssi[RF90_PATH_A] = (u8)((usvalue & 0xff00) >> 8);
1894 usvalue = *(u8 *)&hwinfo[EEPROM_TSSI_B];
1895 rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff);
1896
1897 RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1898 rtlefuse->eeprom_tssi[RF90_PATH_A],
1899 rtlefuse->eeprom_tssi[RF90_PATH_B]));
1900
1901 /* Read antenna tx power offset of B/C/D to A from EEPROM */
1902 /* and read ThermalMeter from EEPROM */
1903 tempval = *(u8 *)&hwinfo[EEPROM_THERMALMETER];
1904 rtlefuse->eeprom_thermalmeter = tempval;
1905 RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("thermalmeter = 0x%x\n",
1906 rtlefuse->eeprom_thermalmeter));
1907
1908 /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */
1909 rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f);
1910 rtlefuse->tssi_13dbm = rtlefuse->eeprom_thermalmeter * 100;
1911
1912 /* Read CrystalCap from EEPROM */
1913 tempval = (*(u8 *)&hwinfo[EEPROM_CRYSTALCAP]) >> 4;
1914 rtlefuse->eeprom_crystalcap = tempval;
1915 /* CrystalCap, BIT(12)~15 */
1916 rtlefuse->crystalcap = rtlefuse->eeprom_crystalcap;
1917
1918 /* Read IC Version && Channel Plan */
1919 /* Version ID, Channel plan */
1920 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1921 rtlefuse->txpwr_fromeprom = true;
1922 RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("EEPROM ChannelPlan = 0x%4x\n",
1923 rtlefuse->eeprom_channelplan));
1924
1925 /* Read Customer ID or Board Type!!! */
1926 tempval = *(u8 *)&hwinfo[EEPROM_BOARDTYPE];
1927 /* Change RF type definition */
1928 if (tempval == 0)
1929 rtlphy->rf_type = RF_2T2R;
1930 else if (tempval == 1)
1931 rtlphy->rf_type = RF_1T2R;
1932 else if (tempval == 2)
1933 rtlphy->rf_type = RF_1T2R;
1934 else if (tempval == 3)
1935 rtlphy->rf_type = RF_1T1R;
1936
1937 /* 1T2R but 1SS (1x1 receive combining) */
1938 rtlefuse->b1x1_recvcombine = false;
1939 if (rtlphy->rf_type == RF_1T2R) {
1940 tempval = rtl_read_byte(rtlpriv, 0x07);
1941 if (!(tempval & BIT(0))) {
1942 rtlefuse->b1x1_recvcombine = true;
1943 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1944 ("RF_TYPE=1T2R but only 1SS\n"));
1945 }
1946 }
1947 rtlefuse->b1ss_support = rtlefuse->b1x1_recvcombine;
1948 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMID];
1949
1950 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("EEPROM Customer ID: 0x%2x",
1951 rtlefuse->eeprom_oemid));
1952
1953 /* set channel paln to world wide 13 */
1954 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1955 }
1956
1957 void rtl92se_read_eeprom_info(struct ieee80211_hw *hw)
1958 {
1959 struct rtl_priv *rtlpriv = rtl_priv(hw);
1960 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1961 u8 tmp_u1b = 0;
1962
1963 tmp_u1b = rtl_read_byte(rtlpriv, EPROM_CMD);
1964
1965 if (tmp_u1b & BIT(4)) {
1966 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EEPROM\n"));
1967 rtlefuse->epromtype = EEPROM_93C46;
1968 } else {
1969 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EFUSE\n"));
1970 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1971 }
1972
1973 if (tmp_u1b & BIT(5)) {
1974 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1975 rtlefuse->autoload_failflag = false;
1976 _rtl92se_read_adapter_info(hw);
1977 } else {
1978 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Autoload ERR!!\n"));
1979 rtlefuse->autoload_failflag = true;
1980 }
1981 }
1982
1983 static void rtl92se_update_hal_rate_table(struct ieee80211_hw *hw,
1984 struct ieee80211_sta *sta)
1985 {
1986 struct rtl_priv *rtlpriv = rtl_priv(hw);
1987 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1988 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1989 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1990 u32 ratr_value;
1991 u8 ratr_index = 0;
1992 u8 nmode = mac->ht_enable;
1993 u8 mimo_ps = IEEE80211_SMPS_OFF;
1994 u16 shortgi_rate = 0;
1995 u32 tmp_ratr_value = 0;
1996 u8 curtxbw_40mhz = mac->bw_40;
1997 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1998 1 : 0;
1999 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2000 1 : 0;
2001 enum wireless_mode wirelessmode = mac->mode;
2002
2003 if (rtlhal->current_bandtype == BAND_ON_5G)
2004 ratr_value = sta->supp_rates[1] << 4;
2005 else
2006 ratr_value = sta->supp_rates[0];
2007 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2008 sta->ht_cap.mcs.rx_mask[0] << 12);
2009 switch (wirelessmode) {
2010 case WIRELESS_MODE_B:
2011 ratr_value &= 0x0000000D;
2012 break;
2013 case WIRELESS_MODE_G:
2014 ratr_value &= 0x00000FF5;
2015 break;
2016 case WIRELESS_MODE_N_24G:
2017 case WIRELESS_MODE_N_5G:
2018 nmode = 1;
2019 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2020 ratr_value &= 0x0007F005;
2021 } else {
2022 u32 ratr_mask;
2023
2024 if (get_rf_type(rtlphy) == RF_1T2R ||
2025 get_rf_type(rtlphy) == RF_1T1R) {
2026 if (curtxbw_40mhz)
2027 ratr_mask = 0x000ff015;
2028 else
2029 ratr_mask = 0x000ff005;
2030 } else {
2031 if (curtxbw_40mhz)
2032 ratr_mask = 0x0f0ff015;
2033 else
2034 ratr_mask = 0x0f0ff005;
2035 }
2036
2037 ratr_value &= ratr_mask;
2038 }
2039 break;
2040 default:
2041 if (rtlphy->rf_type == RF_1T2R)
2042 ratr_value &= 0x000ff0ff;
2043 else
2044 ratr_value &= 0x0f0ff0ff;
2045
2046 break;
2047 }
2048
2049 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2050 ratr_value &= 0x0FFFFFFF;
2051 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2052 ratr_value &= 0x0FFFFFF0;
2053
2054 if (nmode && ((curtxbw_40mhz &&
2055 curshortgi_40mhz) || (!curtxbw_40mhz &&
2056 curshortgi_20mhz))) {
2057
2058 ratr_value |= 0x10000000;
2059 tmp_ratr_value = (ratr_value >> 12);
2060
2061 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2062 if ((1 << shortgi_rate) & tmp_ratr_value)
2063 break;
2064 }
2065
2066 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2067 (shortgi_rate << 4) | (shortgi_rate);
2068
2069 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2070 }
2071
2072 rtl_write_dword(rtlpriv, ARFR0 + ratr_index * 4, ratr_value);
2073 if (ratr_value & 0xfffff000)
2074 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_N);
2075 else
2076 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_BG);
2077
2078 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2079 ("%x\n", rtl_read_dword(rtlpriv, ARFR0)));
2080 }
2081
2082 static void rtl92se_update_hal_rate_mask(struct ieee80211_hw *hw,
2083 struct ieee80211_sta *sta,
2084 u8 rssi_level)
2085 {
2086 struct rtl_priv *rtlpriv = rtl_priv(hw);
2087 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2088 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2089 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2090 struct rtl_sta_info *sta_entry = NULL;
2091 u32 ratr_bitmap;
2092 u8 ratr_index = 0;
2093 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2094 ? 1 : 0;
2095 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2096 1 : 0;
2097 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2098 1 : 0;
2099 enum wireless_mode wirelessmode = 0;
2100 bool shortgi = false;
2101 u32 ratr_value = 0;
2102 u8 shortgi_rate = 0;
2103 u32 mask = 0;
2104 u32 band = 0;
2105 bool bmulticast = false;
2106 u8 macid = 0;
2107 u8 mimo_ps = IEEE80211_SMPS_OFF;
2108
2109 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2110 wirelessmode = sta_entry->wireless_mode;
2111 if (mac->opmode == NL80211_IFTYPE_STATION)
2112 curtxbw_40mhz = mac->bw_40;
2113 else if (mac->opmode == NL80211_IFTYPE_AP ||
2114 mac->opmode == NL80211_IFTYPE_ADHOC)
2115 macid = sta->aid + 1;
2116
2117 if (rtlhal->current_bandtype == BAND_ON_5G)
2118 ratr_bitmap = sta->supp_rates[1] << 4;
2119 else
2120 ratr_bitmap = sta->supp_rates[0];
2121 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2122 sta->ht_cap.mcs.rx_mask[0] << 12);
2123 switch (wirelessmode) {
2124 case WIRELESS_MODE_B:
2125 band |= WIRELESS_11B;
2126 ratr_index = RATR_INX_WIRELESS_B;
2127 if (ratr_bitmap & 0x0000000c)
2128 ratr_bitmap &= 0x0000000d;
2129 else
2130 ratr_bitmap &= 0x0000000f;
2131 break;
2132 case WIRELESS_MODE_G:
2133 band |= (WIRELESS_11G | WIRELESS_11B);
2134 ratr_index = RATR_INX_WIRELESS_GB;
2135
2136 if (rssi_level == 1)
2137 ratr_bitmap &= 0x00000f00;
2138 else if (rssi_level == 2)
2139 ratr_bitmap &= 0x00000ff0;
2140 else
2141 ratr_bitmap &= 0x00000ff5;
2142 break;
2143 case WIRELESS_MODE_A:
2144 band |= WIRELESS_11A;
2145 ratr_index = RATR_INX_WIRELESS_A;
2146 ratr_bitmap &= 0x00000ff0;
2147 break;
2148 case WIRELESS_MODE_N_24G:
2149 case WIRELESS_MODE_N_5G:
2150 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2151 ratr_index = RATR_INX_WIRELESS_NGB;
2152
2153 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2154 if (rssi_level == 1)
2155 ratr_bitmap &= 0x00070000;
2156 else if (rssi_level == 2)
2157 ratr_bitmap &= 0x0007f000;
2158 else
2159 ratr_bitmap &= 0x0007f005;
2160 } else {
2161 if (rtlphy->rf_type == RF_1T2R ||
2162 rtlphy->rf_type == RF_1T1R) {
2163 if (rssi_level == 1) {
2164 ratr_bitmap &= 0x000f0000;
2165 } else if (rssi_level == 3) {
2166 ratr_bitmap &= 0x000fc000;
2167 } else if (rssi_level == 5) {
2168 ratr_bitmap &= 0x000ff000;
2169 } else {
2170 if (curtxbw_40mhz)
2171 ratr_bitmap &= 0x000ff015;
2172 else
2173 ratr_bitmap &= 0x000ff005;
2174 }
2175 } else {
2176 if (rssi_level == 1) {
2177 ratr_bitmap &= 0x0f8f0000;
2178 } else if (rssi_level == 3) {
2179 ratr_bitmap &= 0x0f8fc000;
2180 } else if (rssi_level == 5) {
2181 ratr_bitmap &= 0x0f8ff000;
2182 } else {
2183 if (curtxbw_40mhz)
2184 ratr_bitmap &= 0x0f8ff015;
2185 else
2186 ratr_bitmap &= 0x0f8ff005;
2187 }
2188 }
2189 }
2190
2191 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2192 (!curtxbw_40mhz && curshortgi_20mhz)) {
2193 if (macid == 0)
2194 shortgi = true;
2195 else if (macid == 1)
2196 shortgi = false;
2197 }
2198 break;
2199 default:
2200 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2201 ratr_index = RATR_INX_WIRELESS_NGB;
2202
2203 if (rtlphy->rf_type == RF_1T2R)
2204 ratr_bitmap &= 0x000ff0ff;
2205 else
2206 ratr_bitmap &= 0x0f8ff0ff;
2207 break;
2208 }
2209
2210 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2211 ratr_bitmap &= 0x0FFFFFFF;
2212 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2213 ratr_bitmap &= 0x0FFFFFF0;
2214
2215 if (shortgi) {
2216 ratr_bitmap |= 0x10000000;
2217 /* Get MAX MCS available. */
2218 ratr_value = (ratr_bitmap >> 12);
2219 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2220 if ((1 << shortgi_rate) & ratr_value)
2221 break;
2222 }
2223
2224 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2225 (shortgi_rate << 4) | (shortgi_rate);
2226 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2227 }
2228
2229 mask |= (bmulticast ? 1 : 0) << 9 | (macid & 0x1f) << 4 | (band & 0xf);
2230
2231 RT_TRACE(rtlpriv, COMP_RATR, DBG_TRACE, ("mask = %x, bitmap = %x\n",
2232 mask, ratr_bitmap));
2233 rtl_write_dword(rtlpriv, 0x2c4, ratr_bitmap);
2234 rtl_write_dword(rtlpriv, WFM5, (FW_RA_UPDATE_MASK | (mask << 8)));
2235
2236 if (macid != 0)
2237 sta_entry->ratr_index = ratr_index;
2238 }
2239
2240 void rtl92se_update_hal_rate_tbl(struct ieee80211_hw *hw,
2241 struct ieee80211_sta *sta, u8 rssi_level)
2242 {
2243 struct rtl_priv *rtlpriv = rtl_priv(hw);
2244
2245 if (rtlpriv->dm.useramask)
2246 rtl92se_update_hal_rate_mask(hw, sta, rssi_level);
2247 else
2248 rtl92se_update_hal_rate_table(hw, sta);
2249 }
2250
2251 void rtl92se_update_channel_access_setting(struct ieee80211_hw *hw)
2252 {
2253 struct rtl_priv *rtlpriv = rtl_priv(hw);
2254 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2255 u16 sifs_timer;
2256
2257 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2258 (u8 *)&mac->slot_time);
2259 sifs_timer = 0x0e0e;
2260 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2261
2262 }
2263
2264 /* this ifunction is for RFKILL, it's different with windows,
2265 * because UI will disable wireless when GPIO Radio Off.
2266 * And here we not check or Disable/Enable ASPM like windows*/
2267 bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2268 {
2269 struct rtl_priv *rtlpriv = rtl_priv(hw);
2270 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2271 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2272 enum rf_pwrstate rfpwr_toset /*, cur_rfstate */;
2273 unsigned long flag = 0;
2274 bool actuallyset = false;
2275 bool turnonbypowerdomain = false;
2276
2277 /* just 8191se can check gpio before firstup, 92c/92d have fixed it */
2278 if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter))
2279 return false;
2280
2281 if (ppsc->swrf_processing)
2282 return false;
2283
2284 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2285 if (ppsc->rfchange_inprogress) {
2286 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2287 return false;
2288 } else {
2289 ppsc->rfchange_inprogress = true;
2290 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2291 }
2292
2293 /* cur_rfstate = ppsc->rfpwr_state;*/
2294
2295 /* because after _rtl92s_phy_set_rfhalt, all power
2296 * closed, so we must open some power for GPIO check,
2297 * or we will always check GPIO RFOFF here,
2298 * And we should close power after GPIO check */
2299 if (RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
2300 _rtl92se_power_domain_init(hw);
2301 turnonbypowerdomain = true;
2302 }
2303
2304 rfpwr_toset = _rtl92se_rf_onoff_detect(hw);
2305
2306 if ((ppsc->hwradiooff) && (rfpwr_toset == ERFON)) {
2307 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2308 ("RFKILL-HW Radio ON, RF ON\n"));
2309
2310 rfpwr_toset = ERFON;
2311 ppsc->hwradiooff = false;
2312 actuallyset = true;
2313 } else if ((ppsc->hwradiooff == false) && (rfpwr_toset == ERFOFF)) {
2314 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2315 ("RFKILL-HW Radio OFF, RF OFF\n"));
2316
2317 rfpwr_toset = ERFOFF;
2318 ppsc->hwradiooff = true;
2319 actuallyset = true;
2320 }
2321
2322 if (actuallyset) {
2323 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2324 ppsc->rfchange_inprogress = false;
2325 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2326
2327 /* this not include ifconfig wlan0 down case */
2328 /* } else if (rfpwr_toset == ERFOFF || cur_rfstate == ERFOFF) { */
2329 } else {
2330 /* because power_domain_init may be happen when
2331 * _rtl92s_phy_set_rfhalt, this will open some powers
2332 * and cause current increasing about 40 mA for ips,
2333 * rfoff and ifconfig down, so we set
2334 * _rtl92s_phy_set_rfhalt again here */
2335 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC &&
2336 turnonbypowerdomain) {
2337 _rtl92s_phy_set_rfhalt(hw);
2338 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2339 }
2340
2341 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2342 ppsc->rfchange_inprogress = false;
2343 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2344 }
2345
2346 *valid = 1;
2347 return !ppsc->hwradiooff;
2348
2349 }
2350
2351 /* Is_wepkey just used for WEP used as group & pairwise key
2352 * if pairwise is AES ang group is WEP Is_wepkey == false.*/
2353 void rtl92se_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr,
2354 bool is_group, u8 enc_algo, bool is_wepkey, bool clear_all)
2355 {
2356 struct rtl_priv *rtlpriv = rtl_priv(hw);
2357 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2358 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2359 u8 *macaddr = p_macaddr;
2360
2361 u32 entry_id = 0;
2362 bool is_pairwise = false;
2363
2364 static u8 cam_const_addr[4][6] = {
2365 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2366 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2367 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2368 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2369 };
2370 static u8 cam_const_broad[] = {
2371 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2372 };
2373
2374 if (clear_all) {
2375 u8 idx = 0;
2376 u8 cam_offset = 0;
2377 u8 clear_number = 5;
2378
2379 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("clear_all\n"));
2380
2381 for (idx = 0; idx < clear_number; idx++) {
2382 rtl_cam_mark_invalid(hw, cam_offset + idx);
2383 rtl_cam_empty_entry(hw, cam_offset + idx);
2384
2385 if (idx < 5) {
2386 memset(rtlpriv->sec.key_buf[idx], 0,
2387 MAX_KEY_LEN);
2388 rtlpriv->sec.key_len[idx] = 0;
2389 }
2390 }
2391
2392 } else {
2393 switch (enc_algo) {
2394 case WEP40_ENCRYPTION:
2395 enc_algo = CAM_WEP40;
2396 break;
2397 case WEP104_ENCRYPTION:
2398 enc_algo = CAM_WEP104;
2399 break;
2400 case TKIP_ENCRYPTION:
2401 enc_algo = CAM_TKIP;
2402 break;
2403 case AESCCMP_ENCRYPTION:
2404 enc_algo = CAM_AES;
2405 break;
2406 default:
2407 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2408 ("switch case not process\n"));
2409 enc_algo = CAM_TKIP;
2410 break;
2411 }
2412
2413 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2414 macaddr = cam_const_addr[key_index];
2415 entry_id = key_index;
2416 } else {
2417 if (is_group) {
2418 macaddr = cam_const_broad;
2419 entry_id = key_index;
2420 } else {
2421 if (mac->opmode == NL80211_IFTYPE_AP) {
2422 entry_id = rtl_cam_get_free_entry(hw,
2423 p_macaddr);
2424 if (entry_id >= TOTAL_CAM_ENTRY) {
2425 RT_TRACE(rtlpriv,
2426 COMP_SEC, DBG_EMERG,
2427 ("Can not find free hw"
2428 " security cam entry\n"));
2429 return;
2430 }
2431 } else {
2432 entry_id = CAM_PAIRWISE_KEY_POSITION;
2433 }
2434
2435 key_index = PAIRWISE_KEYIDX;
2436 is_pairwise = true;
2437 }
2438 }
2439
2440 if (rtlpriv->sec.key_len[key_index] == 0) {
2441 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2442 ("delete one entry, entry_id is %d\n",
2443 entry_id));
2444 if (mac->opmode == NL80211_IFTYPE_AP)
2445 rtl_cam_del_entry(hw, p_macaddr);
2446 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2447 } else {
2448 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2449 ("The insert KEY length is %d\n",
2450 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]));
2451 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2452 ("The insert KEY is %x %x\n",
2453 rtlpriv->sec.key_buf[0][0],
2454 rtlpriv->sec.key_buf[0][1]));
2455
2456 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2457 ("add one entry\n"));
2458 if (is_pairwise) {
2459 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2460 "Pairwiase Key content :",
2461 rtlpriv->sec.pairwise_key,
2462 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2463
2464 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2465 ("set Pairwiase key\n"));
2466
2467 rtl_cam_add_one_entry(hw, macaddr, key_index,
2468 entry_id, enc_algo,
2469 CAM_CONFIG_NO_USEDK,
2470 rtlpriv->sec.key_buf[key_index]);
2471 } else {
2472 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2473 ("set group key\n"));
2474
2475 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2476 rtl_cam_add_one_entry(hw,
2477 rtlefuse->dev_addr,
2478 PAIRWISE_KEYIDX,
2479 CAM_PAIRWISE_KEY_POSITION,
2480 enc_algo, CAM_CONFIG_NO_USEDK,
2481 rtlpriv->sec.key_buf[entry_id]);
2482 }
2483
2484 rtl_cam_add_one_entry(hw, macaddr, key_index,
2485 entry_id, enc_algo,
2486 CAM_CONFIG_NO_USEDK,
2487 rtlpriv->sec.key_buf[entry_id]);
2488 }
2489
2490 }
2491 }
2492 }
2493
2494 void rtl92se_suspend(struct ieee80211_hw *hw)
2495 {
2496 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2497
2498 rtlpci->up_first_time = true;
2499 }
2500
2501 void rtl92se_resume(struct ieee80211_hw *hw)
2502 {
2503 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2504 u32 val;
2505
2506 pci_read_config_dword(rtlpci->pdev, 0x40, &val);
2507 if ((val & 0x0000ff00) != 0)
2508 pci_write_config_dword(rtlpci->pdev, 0x40,
2509 val & 0xffff00ff);
2510 }