drivers/net/wireless/wl12xx/boot.c

   1 /*
   2  * This file is part of wl1271
   3  *
   4  * Copyright (C) 2008-2010 Nokia Corporation
   5  *
   6  * Contact: Luciano Coelho <luciano.coelho@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/slab.h>
  25 #include <linux/wl12xx.h>
  26 #include <linux/export.h>
  27
  28 #include "debug.h"
  29 #include "acx.h"
  30 #include "reg.h"
  31 #include "boot.h"
  32 #include "io.h"
  33 #include "event.h"
  34 #include "rx.h"
  35
  36 static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
  37         [PART_DOWN] = {
  38                 .mem = {
  39                         .start = 0x00000000,
  40                         .size  = 0x000177c0
  41                 },
  42                 .reg = {
  43                         .start = REGISTERS_BASE,
  44                         .size  = 0x00008800
  45                 },
  46                 .mem2 = {
  47                         .start = 0x00000000,
  48                         .size  = 0x00000000
  49                 },
  50                 .mem3 = {
  51                         .start = 0x00000000,
  52                         .size  = 0x00000000
  53                 },
  54         },
  55
  56         [PART_WORK] = {
  57                 .mem = {
  58                         .start = 0x00040000,
  59                         .size  = 0x00014fc0
  60                 },
  61                 .reg = {
  62                         .start = REGISTERS_BASE,
  63                         .size  = 0x0000a000
  64                 },
  65                 .mem2 = {
  66                         .start = 0x003004f8,
  67                         .size  = 0x00000004
  68                 },
  69                 .mem3 = {
  70                         .start = 0x00040404,
  71                         .size  = 0x00000000
  72                 },
  73         },
  74
  75         [PART_DRPW] = {
  76                 .mem = {
  77                         .start = 0x00040000,
  78                         .size  = 0x00014fc0
  79                 },
  80                 .reg = {
  81                         .start = DRPW_BASE,
  82                         .size  = 0x00006000
  83                 },
  84                 .mem2 = {
  85                         .start = 0x00000000,
  86                         .size  = 0x00000000
  87                 },
  88                 .mem3 = {
  89                         .start = 0x00000000,
  90                         .size  = 0x00000000
  91                 }
  92         }
  93 };
  94
  95 static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
  96 {
  97         u32 cpu_ctrl;
  98
  99         /* 10.5.0 run the firmware (I) */
 100         cpu_ctrl = wl1271_read32(wl, ACX_REG_ECPU_CONTROL);
 101
 102         /* 10.5.1 run the firmware (II) */
 103         cpu_ctrl |= flag;
 104         wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
 105 }
 106
 107 static unsigned int wl12xx_get_fw_ver_quirks(struct wl1271 *wl)
 108 {
 109         unsigned int quirks = 0;
 110         unsigned int *fw_ver = wl->chip.fw_ver;
 111
 112         /* Only new station firmwares support routing fw logs to the host */
 113         if ((fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_STA) &&
 114             (fw_ver[FW_VER_MINOR] < FW_VER_MINOR_FWLOG_STA_MIN))
 115                 quirks |= WL12XX_QUIRK_FWLOG_NOT_IMPLEMENTED;
 116
 117         /* This feature is not yet supported for AP mode */
 118         if (fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_AP)
 119                 quirks |= WL12XX_QUIRK_FWLOG_NOT_IMPLEMENTED;
 120
 121         return quirks;
 122 }
 123
 124 static void wl1271_parse_fw_ver(struct wl1271 *wl)
 125 {
 126         int ret;
 127
 128         ret = sscanf(wl->chip.fw_ver_str + 4, "%u.%u.%u.%u.%u",
 129                      &wl->chip.fw_ver[0], &wl->chip.fw_ver[1],
 130                      &wl->chip.fw_ver[2], &wl->chip.fw_ver[3],
 131                      &wl->chip.fw_ver[4]);
 132
 133         if (ret != 5) {
 134                 wl1271_warning("fw version incorrect value");
 135                 memset(wl->chip.fw_ver, 0, sizeof(wl->chip.fw_ver));
 136                 return;
 137         }
 138
 139         /* Check if any quirks are needed with older fw versions */
 140         wl->quirks |= wl12xx_get_fw_ver_quirks(wl);
 141 }
 142
 143 static void wl1271_boot_fw_version(struct wl1271 *wl)
 144 {
 145         struct wl1271_static_data static_data;
 146
 147         wl1271_read(wl, wl->cmd_box_addr, &static_data, sizeof(static_data),
 148                     false);
 149
 150         strncpy(wl->chip.fw_ver_str, static_data.fw_version,
 151                 sizeof(wl->chip.fw_ver_str));
 152
 153         /* make sure the string is NULL-terminated */
 154         wl->chip.fw_ver_str[sizeof(wl->chip.fw_ver_str) - 1] = '\0';
 155
 156         wl1271_parse_fw_ver(wl);
 157 }
 158
 159 static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
 160                                              size_t fw_data_len, u32 dest)
 161 {
 162         struct wl1271_partition_set partition;
 163         int addr, chunk_num, partition_limit;
 164         u8 *p, *chunk;
 165
 166         /* whal_FwCtrl_LoadFwImageSm() */
 167
 168         wl1271_debug(DEBUG_BOOT, "starting firmware upload");
 169
 170         wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
 171                      fw_data_len, CHUNK_SIZE);
 172
 173         if ((fw_data_len % 4) != 0) {
 174                 wl1271_error("firmware length not multiple of four");
 175                 return -EIO;
 176         }
 177
 178         chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
 179         if (!chunk) {
 180                 wl1271_error("allocation for firmware upload chunk failed");
 181                 return -ENOMEM;
 182         }
 183
 184         memcpy(&partition, &part_table[PART_DOWN], sizeof(partition));
 185         partition.mem.start = dest;
 186         wl1271_set_partition(wl, &partition);
 187
 188         /* 10.1 set partition limit and chunk num */
 189         chunk_num = 0;
 190         partition_limit = part_table[PART_DOWN].mem.size;
 191
 192         while (chunk_num < fw_data_len / CHUNK_SIZE) {
 193                 /* 10.2 update partition, if needed */
 194                 addr = dest + (chunk_num + 2) * CHUNK_SIZE;
 195                 if (addr > partition_limit) {
 196                         addr = dest + chunk_num * CHUNK_SIZE;
 197                         partition_limit = chunk_num * CHUNK_SIZE +
 198                                 part_table[PART_DOWN].mem.size;
 199                         partition.mem.start = addr;
 200                         wl1271_set_partition(wl, &partition);
 201                 }
 202
 203                 /* 10.3 upload the chunk */
 204                 addr = dest + chunk_num * CHUNK_SIZE;
 205                 p = buf + chunk_num * CHUNK_SIZE;
 206                 memcpy(chunk, p, CHUNK_SIZE);
 207                 wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
 208                              p, addr);
 209                 wl1271_write(wl, addr, chunk, CHUNK_SIZE, false);
 210
 211                 chunk_num++;
 212         }
 213
 214         /* 10.4 upload the last chunk */
 215         addr = dest + chunk_num * CHUNK_SIZE;
 216         p = buf + chunk_num * CHUNK_SIZE;
 217         memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
 218         wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
 219                      fw_data_len % CHUNK_SIZE, p, addr);
 220         wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);
 221
 222         kfree(chunk);
 223         return 0;
 224 }
 225
 226 static int wl1271_boot_upload_firmware(struct wl1271 *wl)
 227 {
 228         u32 chunks, addr, len;
 229         int ret = 0;
 230         u8 *fw;
 231
 232         fw = wl->fw;
 233         chunks = be32_to_cpup((__be32 *) fw);
 234         fw += sizeof(u32);
 235
 236         wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);
 237
 238         while (chunks--) {
 239                 addr = be32_to_cpup((__be32 *) fw);
 240                 fw += sizeof(u32);
 241                 len = be32_to_cpup((__be32 *) fw);
 242                 fw += sizeof(u32);
 243
 244                 if (len > 300000) {
 245                         wl1271_info("firmware chunk too long: %u", len);
 246                         return -EINVAL;
 247                 }
 248                 wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
 249                              chunks, addr, len);
 250                 ret = wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
 251                 if (ret != 0)
 252                         break;
 253                 fw += len;
 254         }
 255
 256         return ret;
 257 }
 258
 259 static int wl1271_boot_upload_nvs(struct wl1271 *wl)
 260 {
 261         size_t nvs_len, burst_len;
 262         int i;
 263         u32 dest_addr, val;
 264         u8 *nvs_ptr, *nvs_aligned;
 265
 266         if (wl->nvs == NULL)
 267                 return -ENODEV;
 268
 269         if (wl->chip.id == CHIP_ID_1283_PG20) {
 270                 struct wl128x_nvs_file *nvs = (struct wl128x_nvs_file *)wl->nvs;
 271
 272                 if (wl->nvs_len == sizeof(struct wl128x_nvs_file)) {
 273                         if (nvs->general_params.dual_mode_select)
 274                                 wl->enable_11a = true;
 275                 } else {
 276                         wl1271_error("nvs size is not as expected: %zu != %zu",
 277                                      wl->nvs_len,
 278                                      sizeof(struct wl128x_nvs_file));
 279                         kfree(wl->nvs);
 280                         wl->nvs = NULL;
 281                         wl->nvs_len = 0;
 282                         return -EILSEQ;
 283                 }
 284
 285                 /* only the first part of the NVS needs to be uploaded */
 286                 nvs_len = sizeof(nvs->nvs);
 287                 nvs_ptr = (u8 *)nvs->nvs;
 288
 289         } else {
 290                 struct wl1271_nvs_file *nvs =
 291                         (struct wl1271_nvs_file *)wl->nvs;
 292                 /*
 293                  * FIXME: the LEGACY NVS image support (NVS's missing the 5GHz
 294                  * band configurations) can be removed when those NVS files stop
 295                  * floating around.
 296                  */
 297                 if (wl->nvs_len == sizeof(struct wl1271_nvs_file) ||
 298                     wl->nvs_len == WL1271_INI_LEGACY_NVS_FILE_SIZE) {
 299                         if (nvs->general_params.dual_mode_select)
 300                                 wl->enable_11a = true;
 301                 }
 302
 303                 if (wl->nvs_len != sizeof(struct wl1271_nvs_file) &&
 304                     (wl->nvs_len != WL1271_INI_LEGACY_NVS_FILE_SIZE ||
 305                      wl->enable_11a)) {
 306                         wl1271_error("nvs size is not as expected: %zu != %zu",
 307                                 wl->nvs_len, sizeof(struct wl1271_nvs_file));
 308                         kfree(wl->nvs);
 309                         wl->nvs = NULL;
 310                         wl->nvs_len = 0;
 311                         return -EILSEQ;
 312                 }
 313
 314                 /* only the first part of the NVS needs to be uploaded */
 315                 nvs_len = sizeof(nvs->nvs);
 316                 nvs_ptr = (u8 *) nvs->nvs;
 317         }
 318
 319         /* update current MAC address to NVS */
 320         nvs_ptr[11] = wl->mac_addr[0];
 321         nvs_ptr[10] = wl->mac_addr[1];
 322         nvs_ptr[6] = wl->mac_addr[2];
 323         nvs_ptr[5] = wl->mac_addr[3];
 324         nvs_ptr[4] = wl->mac_addr[4];
 325         nvs_ptr[3] = wl->mac_addr[5];
 326
 327         /*
 328          * Layout before the actual NVS tables:
 329          * 1 byte : burst length.
 330          * 2 bytes: destination address.
 331          * n bytes: data to burst copy.
 332          *
 333          * This is ended by a 0 length, then the NVS tables.
 334          */
 335
 336         /* FIXME: Do we need to check here whether the LSB is 1? */
 337         while (nvs_ptr[0]) {
 338                 burst_len = nvs_ptr[0];
 339                 dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
 340
 341                 /*
 342                  * Due to our new wl1271_translate_reg_addr function,
 343                  * we need to add the REGISTER_BASE to the destination
 344                  */
 345                 dest_addr += REGISTERS_BASE;
 346
 347                 /* We move our pointer to the data */
 348                 nvs_ptr += 3;
 349
 350                 for (i = 0; i < burst_len; i++) {
 351                         if (nvs_ptr + 3 >= (u8 *) wl->nvs + nvs_len)
 352                                 goto out_badnvs;
 353
 354                         val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
 355                                | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
 356
 357                         wl1271_debug(DEBUG_BOOT,
 358                                      "nvs burst write 0x%x: 0x%x",
 359                                      dest_addr, val);
 360                         wl1271_write32(wl, dest_addr, val);
 361
 362                         nvs_ptr += 4;
 363                         dest_addr += 4;
 364                 }
 365
 366                 if (nvs_ptr >= (u8 *) wl->nvs + nvs_len)
 367                         goto out_badnvs;
 368         }
 369
 370         /*
 371          * We've reached the first zero length, the first NVS table
 372          * is located at an aligned offset which is at least 7 bytes further.
 373          * NOTE: The wl->nvs->nvs element must be first, in order to
 374          * simplify the casting, we assume it is at the beginning of
 375          * the wl->nvs structure.
 376          */
 377         nvs_ptr = (u8 *)wl->nvs +
 378                         ALIGN(nvs_ptr - (u8 *)wl->nvs + 7, 4);
 379
 380         if (nvs_ptr >= (u8 *) wl->nvs + nvs_len)
 381                 goto out_badnvs;
 382
 383         nvs_len -= nvs_ptr - (u8 *)wl->nvs;
 384
 385         /* Now we must set the partition correctly */
 386         wl1271_set_partition(wl, &part_table[PART_WORK]);
 387
 388         /* Copy the NVS tables to a new block to ensure alignment */
 389         nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL);
 390         if (!nvs_aligned)
 391                 return -ENOMEM;
 392
 393         /* And finally we upload the NVS tables */
 394         wl1271_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false);
 395
 396         kfree(nvs_aligned);
 397         return 0;
 398
 399 out_badnvs:
 400         wl1271_error("nvs data is malformed");
 401         return -EILSEQ;
 402 }
 403
 404 static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
 405 {
 406         wl1271_enable_interrupts(wl);
 407         wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
 408                        WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
 409         wl1271_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
 410 }
 411
 412 static int wl1271_boot_soft_reset(struct wl1271 *wl)
 413 {
 414         unsigned long timeout;
 415         u32 boot_data;
 416
 417         /* perform soft reset */
 418         wl1271_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
 419
 420         /* SOFT_RESET is self clearing */
 421         timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
 422         while (1) {
 423                 boot_data = wl1271_read32(wl, ACX_REG_SLV_SOFT_RESET);
 424                 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
 425                 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
 426                         break;
 427
 428                 if (time_after(jiffies, timeout)) {
 429                         /* 1.2 check pWhalBus->uSelfClearTime if the
 430                          * timeout was reached */
 431                         wl1271_error("soft reset timeout");
 432                         return -1;
 433                 }
 434
 435                 udelay(SOFT_RESET_STALL_TIME);
 436         }
 437
 438         /* disable Rx/Tx */
 439         wl1271_write32(wl, ENABLE, 0x0);
 440
 441         /* disable auto calibration on start*/
 442         wl1271_write32(wl, SPARE_A2, 0xffff);
 443
 444         return 0;
 445 }
 446
 447 static int wl1271_boot_run_firmware(struct wl1271 *wl)
 448 {
 449         int loop, ret;
 450         u32 chip_id, intr;
 451
 452         wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
 453
 454         chip_id = wl1271_read32(wl, CHIP_ID_B);
 455
 456         wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
 457
 458         if (chip_id != wl->chip.id) {
 459                 wl1271_error("chip id doesn't match after firmware boot");
 460                 return -EIO;
 461         }
 462
 463         /* wait for init to complete */
 464         loop = 0;
 465         while (loop++ < INIT_LOOP) {
 466                 udelay(INIT_LOOP_DELAY);
 467                 intr = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
 468
 469                 if (intr == 0xffffffff) {
 470                         wl1271_error("error reading hardware complete "
 471                                      "init indication");
 472                         return -EIO;
 473                 }
 474                 /* check that ACX_INTR_INIT_COMPLETE is enabled */
 475                 else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) {
 476                         wl1271_write32(wl, ACX_REG_INTERRUPT_ACK,
 477                                        WL1271_ACX_INTR_INIT_COMPLETE);
 478                         break;
 479                 }
 480         }
 481
 482         if (loop > INIT_LOOP) {
 483                 wl1271_error("timeout waiting for the hardware to "
 484                              "complete initialization");
 485                 return -EIO;
 486         }
 487
 488         /* get hardware config command mail box */
 489         wl->cmd_box_addr = wl1271_read32(wl, REG_COMMAND_MAILBOX_PTR);
 490
 491         /* get hardware config event mail box */
 492         wl->event_box_addr = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR);
 493
 494         /* set the working partition to its "running" mode offset */
 495         wl1271_set_partition(wl, &part_table[PART_WORK]);
 496
 497         wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
 498                      wl->cmd_box_addr, wl->event_box_addr);
 499
 500         wl1271_boot_fw_version(wl);
 501
 502         /*
 503          * in case of full asynchronous mode the firmware event must be
 504          * ready to receive event from the command mailbox
 505          */
 506
 507         /* unmask required mbox events  */
 508         wl->event_mask = BSS_LOSE_EVENT_ID |
 509                 SCAN_COMPLETE_EVENT_ID |
 510                 PS_REPORT_EVENT_ID |
 511                 DISCONNECT_EVENT_COMPLETE_ID |
 512                 RSSI_SNR_TRIGGER_0_EVENT_ID |
 513                 PSPOLL_DELIVERY_FAILURE_EVENT_ID |
 514                 SOFT_GEMINI_SENSE_EVENT_ID |
 515                 PERIODIC_SCAN_REPORT_EVENT_ID |
 516                 PERIODIC_SCAN_COMPLETE_EVENT_ID |
 517                 DUMMY_PACKET_EVENT_ID |
 518                 PEER_REMOVE_COMPLETE_EVENT_ID |
 519                 BA_SESSION_RX_CONSTRAINT_EVENT_ID |
 520                 REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID |
 521                 INACTIVE_STA_EVENT_ID |
 522                 MAX_TX_RETRY_EVENT_ID |
 523                 CHANNEL_SWITCH_COMPLETE_EVENT_ID;
 524
 525         ret = wl1271_event_unmask(wl);
 526         if (ret < 0) {
 527                 wl1271_error("EVENT mask setting failed");
 528                 return ret;
 529         }
 530
 531         wl1271_event_mbox_config(wl);
 532
 533         /* firmware startup completed */
 534         return 0;
 535 }
 536
 537 static int wl1271_boot_write_irq_polarity(struct wl1271 *wl)
 538 {
 539         u32 polarity;
 540
 541         polarity = wl1271_top_reg_read(wl, OCP_REG_POLARITY);
 542
 543         /* We use HIGH polarity, so unset the LOW bit */
 544         polarity &= ~POLARITY_LOW;
 545         wl1271_top_reg_write(wl, OCP_REG_POLARITY, polarity);
 546
 547         return 0;
 548 }
 549
 550 static void wl1271_boot_hw_version(struct wl1271 *wl)
 551 {
 552         u32 fuse;
 553
 554         if (wl->chip.id == CHIP_ID_1283_PG20)
 555                 fuse = wl1271_top_reg_read(wl, WL128X_REG_FUSE_DATA_2_1);
 556         else
 557                 fuse = wl1271_top_reg_read(wl, WL127X_REG_FUSE_DATA_2_1);
 558         fuse = (fuse & PG_VER_MASK) >> PG_VER_OFFSET;
 559
 560         wl->hw_pg_ver = (s8)fuse;
 561 }
 562
 563 static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl)
 564 {
 565         u16 spare_reg;
 566
 567         /* Mask bits [2] & [8:4] in the sys_clk_cfg register */
 568         spare_reg = wl1271_top_reg_read(wl, WL_SPARE_REG);
 569         if (spare_reg == 0xFFFF)
 570                 return -EFAULT;
 571         spare_reg |= (BIT(3) | BIT(5) | BIT(6));
 572         wl1271_top_reg_write(wl, WL_SPARE_REG, spare_reg);
 573
 574         /* Enable FREF_CLK_REQ & mux MCS and coex PLLs to FREF */
 575         wl1271_top_reg_write(wl, SYS_CLK_CFG_REG,
 576                              WL_CLK_REQ_TYPE_PG2 | MCS_PLL_CLK_SEL_FREF);
 577
 578         /* Delay execution for 15msec, to let the HW settle */
 579         mdelay(15);
 580
 581         return 0;
 582 }
 583
 584 static bool wl128x_is_tcxo_valid(struct wl1271 *wl)
 585 {
 586         u16 tcxo_detection;
 587
 588         tcxo_detection = wl1271_top_reg_read(wl, TCXO_CLK_DETECT_REG);
 589         if (tcxo_detection & TCXO_DET_FAILED)
 590                 return false;
 591
 592         return true;
 593 }
 594
 595 static bool wl128x_is_fref_valid(struct wl1271 *wl)
 596 {
 597         u16 fref_detection;
 598
 599         fref_detection = wl1271_top_reg_read(wl, FREF_CLK_DETECT_REG);
 600         if (fref_detection & FREF_CLK_DETECT_FAIL)
 601                 return false;
 602
 603         return true;
 604 }
 605
 606 static int wl128x_manually_configure_mcs_pll(struct wl1271 *wl)
 607 {
 608         wl1271_top_reg_write(wl, MCS_PLL_M_REG, MCS_PLL_M_REG_VAL);
 609         wl1271_top_reg_write(wl, MCS_PLL_N_REG, MCS_PLL_N_REG_VAL);
 610         wl1271_top_reg_write(wl, MCS_PLL_CONFIG_REG, MCS_PLL_CONFIG_REG_VAL);
 611
 612         return 0;
 613 }
 614
 615 static int wl128x_configure_mcs_pll(struct wl1271 *wl, int clk)
 616 {
 617         u16 spare_reg;
 618         u16 pll_config;
 619         u8 input_freq;
 620
 621         /* Mask bits [3:1] in the sys_clk_cfg register */
 622         spare_reg = wl1271_top_reg_read(wl, WL_SPARE_REG);
 623         if (spare_reg == 0xFFFF)
 624                 return -EFAULT;
 625         spare_reg |= BIT(2);
 626         wl1271_top_reg_write(wl, WL_SPARE_REG, spare_reg);
 627
 628         /* Handle special cases of the TCXO clock */
 629         if (wl->tcxo_clock == WL12XX_TCXOCLOCK_16_8 ||
 630             wl->tcxo_clock == WL12XX_TCXOCLOCK_33_6)
 631                 return wl128x_manually_configure_mcs_pll(wl);
 632
 633         /* Set the input frequency according to the selected clock source */
 634         input_freq = (clk & 1) + 1;
 635
 636         pll_config = wl1271_top_reg_read(wl, MCS_PLL_CONFIG_REG);
 637         if (pll_config == 0xFFFF)
 638                 return -EFAULT;
 639         pll_config |= (input_freq << MCS_SEL_IN_FREQ_SHIFT);
 640         pll_config |= MCS_PLL_ENABLE_HP;
 641         wl1271_top_reg_write(wl, MCS_PLL_CONFIG_REG, pll_config);
 642
 643         return 0;
 644 }
 645
 646 /*
 647  * WL128x has two clocks input - TCXO and FREF.
 648  * TCXO is the main clock of the device, while FREF is used to sync
 649  * between the GPS and the cellular modem.
 650  * In cases where TCXO is 32.736MHz or 16.368MHz, the FREF will be used
 651  * as the WLAN/BT main clock.
 652  */
 653 static int wl128x_boot_clk(struct wl1271 *wl, int *selected_clock)
 654 {
 655         u16 sys_clk_cfg;
 656
 657         /* For XTAL-only modes, FREF will be used after switching from TCXO */
 658         if (wl->ref_clock == WL12XX_REFCLOCK_26_XTAL ||
 659             wl->ref_clock == WL12XX_REFCLOCK_38_XTAL) {
 660                 if (!wl128x_switch_tcxo_to_fref(wl))
 661                         return -EINVAL;
 662                 goto fref_clk;
 663         }
 664
 665         /* Query the HW, to determine which clock source we should use */
 666         sys_clk_cfg = wl1271_top_reg_read(wl, SYS_CLK_CFG_REG);
 667         if (sys_clk_cfg == 0xFFFF)
 668                 return -EINVAL;
 669         if (sys_clk_cfg & PRCM_CM_EN_MUX_WLAN_FREF)
 670                 goto fref_clk;
 671
 672         /* If TCXO is either 32.736MHz or 16.368MHz, switch to FREF */
 673         if (wl->tcxo_clock == WL12XX_TCXOCLOCK_16_368 ||
 674             wl->tcxo_clock == WL12XX_TCXOCLOCK_32_736) {
 675                 if (!wl128x_switch_tcxo_to_fref(wl))
 676                         return -EINVAL;
 677                 goto fref_clk;
 678         }
 679
 680         /* TCXO clock is selected */
 681         if (!wl128x_is_tcxo_valid(wl))
 682                 return -EINVAL;
 683         *selected_clock = wl->tcxo_clock;
 684         goto config_mcs_pll;
 685
 686 fref_clk:
 687         /* FREF clock is selected */
 688         if (!wl128x_is_fref_valid(wl))
 689                 return -EINVAL;
 690         *selected_clock = wl->ref_clock;
 691
 692 config_mcs_pll:
 693         return wl128x_configure_mcs_pll(wl, *selected_clock);
 694 }
 695
 696 static int wl127x_boot_clk(struct wl1271 *wl)
 697 {
 698         u32 pause;
 699         u32 clk;
 700
 701         if (((wl->hw_pg_ver & PG_MAJOR_VER_MASK) >> PG_MAJOR_VER_OFFSET) < 3)
 702                 wl->quirks |= WL12XX_QUIRK_END_OF_TRANSACTION;
 703
 704         if (wl->ref_clock == CONF_REF_CLK_19_2_E ||
 705             wl->ref_clock == CONF_REF_CLK_38_4_E ||
 706             wl->ref_clock == CONF_REF_CLK_38_4_M_XTAL)
 707                 /* ref clk: 19.2/38.4/38.4-XTAL */
 708                 clk = 0x3;
 709         else if (wl->ref_clock == CONF_REF_CLK_26_E ||
 710                  wl->ref_clock == CONF_REF_CLK_52_E)
 711                 /* ref clk: 26/52 */
 712                 clk = 0x5;
 713         else
 714                 return -EINVAL;
 715
 716         if (wl->ref_clock != CONF_REF_CLK_19_2_E) {
 717                 u16 val;
 718                 /* Set clock type (open drain) */
 719                 val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
 720                 val &= FREF_CLK_TYPE_BITS;
 721                 wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
 722
 723                 /* Set clock pull mode (no pull) */
 724                 val = wl1271_top_reg_read(wl, OCP_REG_CLK_PULL);
 725                 val |= NO_PULL;
 726                 wl1271_top_reg_write(wl, OCP_REG_CLK_PULL, val);
 727         } else {
 728                 u16 val;
 729                 /* Set clock polarity */
 730                 val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY);
 731                 val &= FREF_CLK_POLARITY_BITS;
 732                 val |= CLK_REQ_OUTN_SEL;
 733                 wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
 734         }
 735
 736         wl1271_write32(wl, PLL_PARAMETERS, clk);
 737
 738         pause = wl1271_read32(wl, PLL_PARAMETERS);
 739
 740         wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
 741
 742         pause &= ~(WU_COUNTER_PAUSE_VAL);
 743         pause |= WU_COUNTER_PAUSE_VAL;
 744         wl1271_write32(wl, WU_COUNTER_PAUSE, pause);
 745
 746         return 0;
 747 }
 748
 749 /* uploads NVS and firmware */
 750 int wl1271_load_firmware(struct wl1271 *wl)
 751 {
 752         int ret = 0;
 753         u32 tmp, clk;
 754         int selected_clock = -1;
 755
 756         wl1271_boot_hw_version(wl);
 757
 758         if (wl->chip.id == CHIP_ID_1283_PG20) {
 759                 ret = wl128x_boot_clk(wl, &selected_clock);
 760                 if (ret < 0)
 761                         goto out;
 762         } else {
 763                 ret = wl127x_boot_clk(wl);
 764                 if (ret < 0)
 765                         goto out;
 766         }
 767
 768         /* Continue the ELP wake up sequence */
 769         wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
 770         udelay(500);
 771
 772         wl1271_set_partition(wl, &part_table[PART_DRPW]);
 773
 774         /* Read-modify-write DRPW_SCRATCH_START register (see next state)
 775            to be used by DRPw FW. The RTRIM value will be added by the FW
 776            before taking DRPw out of reset */
 777
 778         wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
 779         clk = wl1271_read32(wl, DRPW_SCRATCH_START);
 780
 781         wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
 782
 783         if (wl->chip.id == CHIP_ID_1283_PG20) {
 784                 clk |= ((selected_clock & 0x3) << 1) << 4;
 785         } else {
 786                 clk |= (wl->ref_clock << 1) << 4;
 787         }
 788
 789         wl1271_write32(wl, DRPW_SCRATCH_START, clk);
 790
 791         wl1271_set_partition(wl, &part_table[PART_WORK]);
 792
 793         /* Disable interrupts */
 794         wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
 795
 796         ret = wl1271_boot_soft_reset(wl);
 797         if (ret < 0)
 798                 goto out;
 799
 800         /* 2. start processing NVS file */
 801         ret = wl1271_boot_upload_nvs(wl);
 802         if (ret < 0)
 803                 goto out;
 804
 805         /* write firmware's last address (ie. it's length) to
 806          * ACX_EEPROMLESS_IND_REG */
 807         wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
 808
 809         wl1271_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);
 810
 811         tmp = wl1271_read32(wl, CHIP_ID_B);
 812
 813         wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
 814
 815         /* 6. read the EEPROM parameters */
 816         tmp = wl1271_read32(wl, SCR_PAD2);
 817
 818         /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
 819          * to upload_fw) */
 820
 821         if (wl->chip.id == CHIP_ID_1283_PG20)
 822                 wl1271_top_reg_write(wl, SDIO_IO_DS, wl->conf.hci_io_ds);
 823
 824         ret = wl1271_boot_upload_firmware(wl);
 825         if (ret < 0)
 826                 goto out;
 827
 828 out:
 829         return ret;
 830 }
 831 EXPORT_SYMBOL_GPL(wl1271_load_firmware);
 832
 833 int wl1271_boot(struct wl1271 *wl)
 834 {
 835         int ret;
 836
 837         /* upload NVS and firmware */
 838         ret = wl1271_load_firmware(wl);
 839         if (ret)
 840                 return ret;
 841
 842         /* 10.5 start firmware */
 843         ret = wl1271_boot_run_firmware(wl);
 844         if (ret < 0)
 845                 goto out;
 846
 847         ret = wl1271_boot_write_irq_polarity(wl);
 848         if (ret < 0)
 849                 goto out;
 850
 851         wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
 852                        WL1271_ACX_ALL_EVENTS_VECTOR);
 853
 854         /* Enable firmware interrupts now */
 855         wl1271_boot_enable_interrupts(wl);
 856
 857         wl1271_event_mbox_config(wl);
 858
 859 out:
 860         return ret;
 861 }