?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
OMAPDSS: VENC: fix NULL pointer dereference in DSS2 VENC sysfs debug attr on OMAP4
[zen-stable.git] / drivers / scsi / pm8001 / pm8001_hwi.c
blobb7b92f7be2aa440afd1613149049f7bb5ea3993f
1 /*
2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm8001_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
45
46 /**
47 * read_main_config_table - read the configure table and save it.
48 * @pm8001_ha: our hba card information
49 */
50 static void __devinit read_main_config_table(struct pm8001_hba_info *pm8001_ha)
51 {
52 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
53 pm8001_ha->main_cfg_tbl.signature = pm8001_mr32(address, 0x00);
54 pm8001_ha->main_cfg_tbl.interface_rev = pm8001_mr32(address, 0x04);
55 pm8001_ha->main_cfg_tbl.firmware_rev = pm8001_mr32(address, 0x08);
56 pm8001_ha->main_cfg_tbl.max_out_io = pm8001_mr32(address, 0x0C);
57 pm8001_ha->main_cfg_tbl.max_sgl = pm8001_mr32(address, 0x10);
58 pm8001_ha->main_cfg_tbl.ctrl_cap_flag = pm8001_mr32(address, 0x14);
59 pm8001_ha->main_cfg_tbl.gst_offset = pm8001_mr32(address, 0x18);
60 pm8001_ha->main_cfg_tbl.inbound_queue_offset =
61 pm8001_mr32(address, MAIN_IBQ_OFFSET);
62 pm8001_ha->main_cfg_tbl.outbound_queue_offset =
63 pm8001_mr32(address, MAIN_OBQ_OFFSET);
64 pm8001_ha->main_cfg_tbl.hda_mode_flag =
65 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
66
67 /* read analog Setting offset from the configuration table */
68 pm8001_ha->main_cfg_tbl.anolog_setup_table_offset =
69 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
70
71 /* read Error Dump Offset and Length */
72 pm8001_ha->main_cfg_tbl.fatal_err_dump_offset0 =
73 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
74 pm8001_ha->main_cfg_tbl.fatal_err_dump_length0 =
75 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
76 pm8001_ha->main_cfg_tbl.fatal_err_dump_offset1 =
77 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
78 pm8001_ha->main_cfg_tbl.fatal_err_dump_length1 =
79 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
80 }
81
82 /**
83 * read_general_status_table - read the general status table and save it.
84 * @pm8001_ha: our hba card information
85 */
86 static void __devinit
87 read_general_status_table(struct pm8001_hba_info *pm8001_ha)
88 {
89 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
90 pm8001_ha->gs_tbl.gst_len_mpistate = pm8001_mr32(address, 0x00);
91 pm8001_ha->gs_tbl.iq_freeze_state0 = pm8001_mr32(address, 0x04);
92 pm8001_ha->gs_tbl.iq_freeze_state1 = pm8001_mr32(address, 0x08);
93 pm8001_ha->gs_tbl.msgu_tcnt = pm8001_mr32(address, 0x0C);
94 pm8001_ha->gs_tbl.iop_tcnt = pm8001_mr32(address, 0x10);
95 pm8001_ha->gs_tbl.reserved = pm8001_mr32(address, 0x14);
96 pm8001_ha->gs_tbl.phy_state[0] = pm8001_mr32(address, 0x18);
97 pm8001_ha->gs_tbl.phy_state[1] = pm8001_mr32(address, 0x1C);
98 pm8001_ha->gs_tbl.phy_state[2] = pm8001_mr32(address, 0x20);
99 pm8001_ha->gs_tbl.phy_state[3] = pm8001_mr32(address, 0x24);
100 pm8001_ha->gs_tbl.phy_state[4] = pm8001_mr32(address, 0x28);
101 pm8001_ha->gs_tbl.phy_state[5] = pm8001_mr32(address, 0x2C);
102 pm8001_ha->gs_tbl.phy_state[6] = pm8001_mr32(address, 0x30);
103 pm8001_ha->gs_tbl.phy_state[7] = pm8001_mr32(address, 0x34);
104 pm8001_ha->gs_tbl.reserved1 = pm8001_mr32(address, 0x38);
105 pm8001_ha->gs_tbl.reserved2 = pm8001_mr32(address, 0x3C);
106 pm8001_ha->gs_tbl.reserved3 = pm8001_mr32(address, 0x40);
107 pm8001_ha->gs_tbl.recover_err_info[0] = pm8001_mr32(address, 0x44);
108 pm8001_ha->gs_tbl.recover_err_info[1] = pm8001_mr32(address, 0x48);
109 pm8001_ha->gs_tbl.recover_err_info[2] = pm8001_mr32(address, 0x4C);
110 pm8001_ha->gs_tbl.recover_err_info[3] = pm8001_mr32(address, 0x50);
111 pm8001_ha->gs_tbl.recover_err_info[4] = pm8001_mr32(address, 0x54);
112 pm8001_ha->gs_tbl.recover_err_info[5] = pm8001_mr32(address, 0x58);
113 pm8001_ha->gs_tbl.recover_err_info[6] = pm8001_mr32(address, 0x5C);
114 pm8001_ha->gs_tbl.recover_err_info[7] = pm8001_mr32(address, 0x60);
115 }
116
117 /**
118 * read_inbnd_queue_table - read the inbound queue table and save it.
119 * @pm8001_ha: our hba card information
120 */
121 static void __devinit
122 read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
123 {
124 int inbQ_num = 1;
125 int i;
126 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
127 for (i = 0; i < inbQ_num; i++) {
128 u32 offset = i * 0x20;
129 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
130 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
131 pm8001_ha->inbnd_q_tbl[i].pi_offset =
132 pm8001_mr32(address, (offset + 0x18));
133 }
134 }
135
136 /**
137 * read_outbnd_queue_table - read the outbound queue table and save it.
138 * @pm8001_ha: our hba card information
139 */
140 static void __devinit
141 read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
142 {
143 int outbQ_num = 1;
144 int i;
145 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
146 for (i = 0; i < outbQ_num; i++) {
147 u32 offset = i * 0x24;
148 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
149 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
150 pm8001_ha->outbnd_q_tbl[i].ci_offset =
151 pm8001_mr32(address, (offset + 0x18));
152 }
153 }
154
155 /**
156 * init_default_table_values - init the default table.
157 * @pm8001_ha: our hba card information
158 */
159 static void __devinit
160 init_default_table_values(struct pm8001_hba_info *pm8001_ha)
161 {
162 int qn = 1;
163 int i;
164 u32 offsetib, offsetob;
165 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
166 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
167
168 pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd = 0;
169 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3 = 0;
170 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7 = 0;
171 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3 = 0;
172 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7 = 0;
173 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3 = 0;
174 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7 = 0;
175 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
176 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
177 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3 = 0;
178 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7 = 0;
179
180 pm8001_ha->main_cfg_tbl.upper_event_log_addr =
181 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
182 pm8001_ha->main_cfg_tbl.lower_event_log_addr =
183 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
184 pm8001_ha->main_cfg_tbl.event_log_size = PM8001_EVENT_LOG_SIZE;
185 pm8001_ha->main_cfg_tbl.event_log_option = 0x01;
186 pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr =
187 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
188 pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr =
189 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
190 pm8001_ha->main_cfg_tbl.iop_event_log_size = PM8001_EVENT_LOG_SIZE;
191 pm8001_ha->main_cfg_tbl.iop_event_log_option = 0x01;
192 pm8001_ha->main_cfg_tbl.fatal_err_interrupt = 0x01;
193 for (i = 0; i < qn; i++) {
194 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
195 0x00000100 | (0x00000040 << 16) | (0x00<<30);
196 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
197 pm8001_ha->memoryMap.region[IB].phys_addr_hi;
198 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
199 pm8001_ha->memoryMap.region[IB].phys_addr_lo;
200 pm8001_ha->inbnd_q_tbl[i].base_virt =
201 (u8 *)pm8001_ha->memoryMap.region[IB].virt_ptr;
202 pm8001_ha->inbnd_q_tbl[i].total_length =
203 pm8001_ha->memoryMap.region[IB].total_len;
204 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
205 pm8001_ha->memoryMap.region[CI].phys_addr_hi;
206 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
207 pm8001_ha->memoryMap.region[CI].phys_addr_lo;
208 pm8001_ha->inbnd_q_tbl[i].ci_virt =
209 pm8001_ha->memoryMap.region[CI].virt_ptr;
210 offsetib = i * 0x20;
211 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
212 get_pci_bar_index(pm8001_mr32(addressib,
213 (offsetib + 0x14)));
214 pm8001_ha->inbnd_q_tbl[i].pi_offset =
215 pm8001_mr32(addressib, (offsetib + 0x18));
216 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
217 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
218 }
219 for (i = 0; i < qn; i++) {
220 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
221 256 | (64 << 16) | (1<<30);
222 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
223 pm8001_ha->memoryMap.region[OB].phys_addr_hi;
224 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
225 pm8001_ha->memoryMap.region[OB].phys_addr_lo;
226 pm8001_ha->outbnd_q_tbl[i].base_virt =
227 (u8 *)pm8001_ha->memoryMap.region[OB].virt_ptr;
228 pm8001_ha->outbnd_q_tbl[i].total_length =
229 pm8001_ha->memoryMap.region[OB].total_len;
230 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
231 pm8001_ha->memoryMap.region[PI].phys_addr_hi;
232 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
233 pm8001_ha->memoryMap.region[PI].phys_addr_lo;
234 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay =
235 0 | (10 << 16) | (0 << 24);
236 pm8001_ha->outbnd_q_tbl[i].pi_virt =
237 pm8001_ha->memoryMap.region[PI].virt_ptr;
238 offsetob = i * 0x24;
239 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
240 get_pci_bar_index(pm8001_mr32(addressob,
241 offsetob + 0x14));
242 pm8001_ha->outbnd_q_tbl[i].ci_offset =
243 pm8001_mr32(addressob, (offsetob + 0x18));
244 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
245 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
246 }
247 }
248
249 /**
250 * update_main_config_table - update the main default table to the HBA.
251 * @pm8001_ha: our hba card information
252 */
253 static void __devinit
254 update_main_config_table(struct pm8001_hba_info *pm8001_ha)
255 {
256 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
257 pm8001_mw32(address, 0x24,
258 pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd);
259 pm8001_mw32(address, 0x28,
260 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3);
261 pm8001_mw32(address, 0x2C,
262 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7);
263 pm8001_mw32(address, 0x30,
264 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3);
265 pm8001_mw32(address, 0x34,
266 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7);
267 pm8001_mw32(address, 0x38,
268 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3);
269 pm8001_mw32(address, 0x3C,
270 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7);
271 pm8001_mw32(address, 0x40,
272 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3);
273 pm8001_mw32(address, 0x44,
274 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7);
275 pm8001_mw32(address, 0x48,
276 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3);
277 pm8001_mw32(address, 0x4C,
278 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7);
279 pm8001_mw32(address, 0x50,
280 pm8001_ha->main_cfg_tbl.upper_event_log_addr);
281 pm8001_mw32(address, 0x54,
282 pm8001_ha->main_cfg_tbl.lower_event_log_addr);
283 pm8001_mw32(address, 0x58, pm8001_ha->main_cfg_tbl.event_log_size);
284 pm8001_mw32(address, 0x5C, pm8001_ha->main_cfg_tbl.event_log_option);
285 pm8001_mw32(address, 0x60,
286 pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr);
287 pm8001_mw32(address, 0x64,
288 pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr);
289 pm8001_mw32(address, 0x68, pm8001_ha->main_cfg_tbl.iop_event_log_size);
290 pm8001_mw32(address, 0x6C,
291 pm8001_ha->main_cfg_tbl.iop_event_log_option);
292 pm8001_mw32(address, 0x70,
293 pm8001_ha->main_cfg_tbl.fatal_err_interrupt);
294 }
295
296 /**
297 * update_inbnd_queue_table - update the inbound queue table to the HBA.
298 * @pm8001_ha: our hba card information
299 */
300 static void __devinit
301 update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number)
302 {
303 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
304 u16 offset = number * 0x20;
305 pm8001_mw32(address, offset + 0x00,
306 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
307 pm8001_mw32(address, offset + 0x04,
308 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
309 pm8001_mw32(address, offset + 0x08,
310 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
311 pm8001_mw32(address, offset + 0x0C,
312 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
313 pm8001_mw32(address, offset + 0x10,
314 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
315 }
316
317 /**
318 * update_outbnd_queue_table - update the outbound queue table to the HBA.
319 * @pm8001_ha: our hba card information
320 */
321 static void __devinit
322 update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number)
323 {
324 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
325 u16 offset = number * 0x24;
326 pm8001_mw32(address, offset + 0x00,
327 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
328 pm8001_mw32(address, offset + 0x04,
329 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
330 pm8001_mw32(address, offset + 0x08,
331 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
332 pm8001_mw32(address, offset + 0x0C,
333 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
334 pm8001_mw32(address, offset + 0x10,
335 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
336 pm8001_mw32(address, offset + 0x1C,
337 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
338 }
339
340 /**
341 * bar4_shift - function is called to shift BAR base address
342 * @pm8001_ha : our hba card information
343 * @shiftValue : shifting value in memory bar.
344 */
345 static int bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
346 {
347 u32 regVal;
348 u32 max_wait_count;
349
350 /* program the inbound AXI translation Lower Address */
351 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
352
353 /* confirm the setting is written */
354 max_wait_count = 1 * 1000 * 1000; /* 1 sec */
355 do {
356 udelay(1);
357 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
358 } while ((regVal != shiftValue) && (--max_wait_count));
359
360 if (!max_wait_count) {
361 PM8001_INIT_DBG(pm8001_ha,
362 pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW"
363 " = 0x%x\n", regVal));
364 return -1;
365 }
366 return 0;
367 }
368
369 /**
370 * mpi_set_phys_g3_with_ssc
371 * @pm8001_ha: our hba card information
372 * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
373 */
374 static void __devinit
375 mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha, u32 SSCbit)
376 {
377 u32 value, offset, i;
378
379 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
380 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
381 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
382 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
383 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
384 #define PHY_G3_WITH_SSC_BIT_SHIFT 13
385 #define SNW3_PHY_CAPABILITIES_PARITY 31
386
387 /*
388 * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
389 * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
390 */
391 if (-1 == bar4_shift(pm8001_ha, SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR))
392 return;
393
394 for (i = 0; i < 4; i++) {
395 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
396 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
397 }
398 /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
399 if (-1 == bar4_shift(pm8001_ha, SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR))
400 return;
401 for (i = 4; i < 8; i++) {
402 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
403 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
404 }
405 /*************************************************************
406 Change the SSC upspreading value to 0x0 so that upspreading is disabled.
407 Device MABC SMOD0 Controls
408 Address: (via MEMBASE-III):
409 Using shifted destination address 0x0_0000: with Offset 0xD8
410
411 31:28 R/W Reserved Do not change
412 27:24 R/W SAS_SMOD_SPRDUP 0000
413 23:20 R/W SAS_SMOD_SPRDDN 0000
414 19:0 R/W Reserved Do not change
415 Upon power-up this register will read as 0x8990c016,
416 and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
417 so that the written value will be 0x8090c016.
418 This will ensure only down-spreading SSC is enabled on the SPC.
419 *************************************************************/
420 value = pm8001_cr32(pm8001_ha, 2, 0xd8);
421 pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
422
423 /*set the shifted destination address to 0x0 to avoid error operation */
424 bar4_shift(pm8001_ha, 0x0);
425 return;
426 }
427
428 /**
429 * mpi_set_open_retry_interval_reg
430 * @pm8001_ha: our hba card information
431 * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us.
432 */
433 static void __devinit
434 mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
435 u32 interval)
436 {
437 u32 offset;
438 u32 value;
439 u32 i;
440
441 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
442 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
443 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
444 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
445 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
446
447 value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
448 /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
449 if (-1 == bar4_shift(pm8001_ha,
450 OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR))
451 return;
452 for (i = 0; i < 4; i++) {
453 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
454 pm8001_cw32(pm8001_ha, 2, offset, value);
455 }
456
457 if (-1 == bar4_shift(pm8001_ha,
458 OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR))
459 return;
460 for (i = 4; i < 8; i++) {
461 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
462 pm8001_cw32(pm8001_ha, 2, offset, value);
463 }
464 /*set the shifted destination address to 0x0 to avoid error operation */
465 bar4_shift(pm8001_ha, 0x0);
466 return;
467 }
468
469 /**
470 * mpi_init_check - check firmware initialization status.
471 * @pm8001_ha: our hba card information
472 */
473 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
474 {
475 u32 max_wait_count;
476 u32 value;
477 u32 gst_len_mpistate;
478 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
479 table is updated */
480 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
481 /* wait until Inbound DoorBell Clear Register toggled */
482 max_wait_count = 1 * 1000 * 1000;/* 1 sec */
483 do {
484 udelay(1);
485 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
486 value &= SPC_MSGU_CFG_TABLE_UPDATE;
487 } while ((value != 0) && (--max_wait_count));
488
489 if (!max_wait_count)
490 return -1;
491 /* check the MPI-State for initialization */
492 gst_len_mpistate =
493 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
494 GST_GSTLEN_MPIS_OFFSET);
495 if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
496 return -1;
497 /* check MPI Initialization error */
498 gst_len_mpistate = gst_len_mpistate >> 16;
499 if (0x0000 != gst_len_mpistate)
500 return -1;
501 return 0;
502 }
503
504 /**
505 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
506 * @pm8001_ha: our hba card information
507 */
508 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
509 {
510 u32 value, value1;
511 u32 max_wait_count;
512 /* check error state */
513 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
514 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
515 /* check AAP error */
516 if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
517 /* error state */
518 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
519 return -1;
520 }
521
522 /* check IOP error */
523 if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
524 /* error state */
525 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
526 return -1;
527 }
528
529 /* bit 4-31 of scratch pad1 should be zeros if it is not
530 in error state*/
531 if (value & SCRATCH_PAD1_STATE_MASK) {
532 /* error case */
533 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
534 return -1;
535 }
536
537 /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
538 in error state */
539 if (value1 & SCRATCH_PAD2_STATE_MASK) {
540 /* error case */
541 return -1;
542 }
543
544 max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
545
546 /* wait until scratch pad 1 and 2 registers in ready state */
547 do {
548 udelay(1);
549 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
550 & SCRATCH_PAD1_RDY;
551 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
552 & SCRATCH_PAD2_RDY;
553 if ((--max_wait_count) == 0)
554 return -1;
555 } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
556 return 0;
557 }
558
559 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
560 {
561 void __iomem *base_addr;
562 u32 value;
563 u32 offset;
564 u32 pcibar;
565 u32 pcilogic;
566
567 value = pm8001_cr32(pm8001_ha, 0, 0x44);
568 offset = value & 0x03FFFFFF;
569 PM8001_INIT_DBG(pm8001_ha,
570 pm8001_printk("Scratchpad 0 Offset: %x\n", offset));
571 pcilogic = (value & 0xFC000000) >> 26;
572 pcibar = get_pci_bar_index(pcilogic);
573 PM8001_INIT_DBG(pm8001_ha,
574 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
575 pm8001_ha->main_cfg_tbl_addr = base_addr =
576 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
577 pm8001_ha->general_stat_tbl_addr =
578 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
579 pm8001_ha->inbnd_q_tbl_addr =
580 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
581 pm8001_ha->outbnd_q_tbl_addr =
582 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
583 }
584
585 /**
586 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
587 * @pm8001_ha: our hba card information
588 */
589 static int __devinit pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
590 {
591 /* check the firmware status */
592 if (-1 == check_fw_ready(pm8001_ha)) {
593 PM8001_FAIL_DBG(pm8001_ha,
594 pm8001_printk("Firmware is not ready!\n"));
595 return -EBUSY;
596 }
597
598 /* Initialize pci space address eg: mpi offset */
599 init_pci_device_addresses(pm8001_ha);
600 init_default_table_values(pm8001_ha);
601 read_main_config_table(pm8001_ha);
602 read_general_status_table(pm8001_ha);
603 read_inbnd_queue_table(pm8001_ha);
604 read_outbnd_queue_table(pm8001_ha);
605 /* update main config table ,inbound table and outbound table */
606 update_main_config_table(pm8001_ha);
607 update_inbnd_queue_table(pm8001_ha, 0);
608 update_outbnd_queue_table(pm8001_ha, 0);
609 mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
610 mpi_set_open_retry_interval_reg(pm8001_ha, 7);
611 /* notify firmware update finished and check initialization status */
612 if (0 == mpi_init_check(pm8001_ha)) {
613 PM8001_INIT_DBG(pm8001_ha,
614 pm8001_printk("MPI initialize successful!\n"));
615 } else
616 return -EBUSY;
617 /*This register is a 16-bit timer with a resolution of 1us. This is the
618 timer used for interrupt delay/coalescing in the PCIe Application Layer.
619 Zero is not a valid value. A value of 1 in the register will cause the
620 interrupts to be normal. A value greater than 1 will cause coalescing
621 delays.*/
622 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
623 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
624 return 0;
625 }
626
627 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
628 {
629 u32 max_wait_count;
630 u32 value;
631 u32 gst_len_mpistate;
632 init_pci_device_addresses(pm8001_ha);
633 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
634 table is stop */
635 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
636
637 /* wait until Inbound DoorBell Clear Register toggled */
638 max_wait_count = 1 * 1000 * 1000;/* 1 sec */
639 do {
640 udelay(1);
641 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
642 value &= SPC_MSGU_CFG_TABLE_RESET;
643 } while ((value != 0) && (--max_wait_count));
644
645 if (!max_wait_count) {
646 PM8001_FAIL_DBG(pm8001_ha,
647 pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value));
648 return -1;
649 }
650
651 /* check the MPI-State for termination in progress */
652 /* wait until Inbound DoorBell Clear Register toggled */
653 max_wait_count = 1 * 1000 * 1000; /* 1 sec */
654 do {
655 udelay(1);
656 gst_len_mpistate =
657 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
658 GST_GSTLEN_MPIS_OFFSET);
659 if (GST_MPI_STATE_UNINIT ==
660 (gst_len_mpistate & GST_MPI_STATE_MASK))
661 break;
662 } while (--max_wait_count);
663 if (!max_wait_count) {
664 PM8001_FAIL_DBG(pm8001_ha,
665 pm8001_printk(" TIME OUT MPI State = 0x%x\n",
666 gst_len_mpistate & GST_MPI_STATE_MASK));
667 return -1;
668 }
669 return 0;
670 }
671
672 /**
673 * soft_reset_ready_check - Function to check FW is ready for soft reset.
674 * @pm8001_ha: our hba card information
675 */
676 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
677 {
678 u32 regVal, regVal1, regVal2;
679 if (mpi_uninit_check(pm8001_ha) != 0) {
680 PM8001_FAIL_DBG(pm8001_ha,
681 pm8001_printk("MPI state is not ready\n"));
682 return -1;
683 }
684 /* read the scratch pad 2 register bit 2 */
685 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
686 & SCRATCH_PAD2_FWRDY_RST;
687 if (regVal == SCRATCH_PAD2_FWRDY_RST) {
688 PM8001_INIT_DBG(pm8001_ha,
689 pm8001_printk("Firmware is ready for reset .\n"));
690 } else {
691 /* Trigger NMI twice via RB6 */
692 if (-1 == bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
693 PM8001_FAIL_DBG(pm8001_ha,
694 pm8001_printk("Shift Bar4 to 0x%x failed\n",
695 RB6_ACCESS_REG));
696 return -1;
697 }
698 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
699 RB6_MAGIC_NUMBER_RST);
700 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
701 /* wait for 100 ms */
702 mdelay(100);
703 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
704 SCRATCH_PAD2_FWRDY_RST;
705 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
706 regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
707 regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
708 PM8001_FAIL_DBG(pm8001_ha,
709 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1"
710 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
711 regVal1, regVal2));
712 PM8001_FAIL_DBG(pm8001_ha,
713 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
714 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
715 PM8001_FAIL_DBG(pm8001_ha,
716 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
717 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
718 return -1;
719 }
720 }
721 return 0;
722 }
723
724 /**
725 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
726 * the FW register status to the originated status.
727 * @pm8001_ha: our hba card information
728 * @signature: signature in host scratch pad0 register.
729 */
730 static int
731 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature)
732 {
733 u32 regVal, toggleVal;
734 u32 max_wait_count;
735 u32 regVal1, regVal2, regVal3;
736
737 /* step1: Check FW is ready for soft reset */
738 if (soft_reset_ready_check(pm8001_ha) != 0) {
739 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n"));
740 return -1;
741 }
742
743 /* step 2: clear NMI status register on AAP1 and IOP, write the same
744 value to clear */
745 /* map 0x60000 to BAR4(0x20), BAR2(win) */
746 if (-1 == bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
747 PM8001_FAIL_DBG(pm8001_ha,
748 pm8001_printk("Shift Bar4 to 0x%x failed\n",
749 MBIC_AAP1_ADDR_BASE));
750 return -1;
751 }
752 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
753 PM8001_INIT_DBG(pm8001_ha,
754 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal));
755 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
756 /* map 0x70000 to BAR4(0x20), BAR2(win) */
757 if (-1 == bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
758 PM8001_FAIL_DBG(pm8001_ha,
759 pm8001_printk("Shift Bar4 to 0x%x failed\n",
760 MBIC_IOP_ADDR_BASE));
761 return -1;
762 }
763 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
764 PM8001_INIT_DBG(pm8001_ha,
765 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal));
766 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
767
768 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
769 PM8001_INIT_DBG(pm8001_ha,
770 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal));
771 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
772
773 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
774 PM8001_INIT_DBG(pm8001_ha,
775 pm8001_printk("PCIE - Event Interrupt = 0x%x\n", regVal));
776 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
777
778 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
779 PM8001_INIT_DBG(pm8001_ha,
780 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal));
781 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
782
783 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
784 PM8001_INIT_DBG(pm8001_ha,
785 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal));
786 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
787
788 /* read the scratch pad 1 register bit 2 */
789 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
790 & SCRATCH_PAD1_RST;
791 toggleVal = regVal ^ SCRATCH_PAD1_RST;
792
793 /* set signature in host scratch pad0 register to tell SPC that the
794 host performs the soft reset */
795 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
796
797 /* read required registers for confirmming */
798 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
799 if (-1 == bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
800 PM8001_FAIL_DBG(pm8001_ha,
801 pm8001_printk("Shift Bar4 to 0x%x failed\n",
802 GSM_ADDR_BASE));
803 return -1;
804 }
805 PM8001_INIT_DBG(pm8001_ha,
806 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and"
807 " Reset = 0x%x\n",
808 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
809
810 /* step 3: host read GSM Configuration and Reset register */
811 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
812 /* Put those bits to low */
813 /* GSM XCBI offset = 0x70 0000
814 0x00 Bit 13 COM_SLV_SW_RSTB 1
815 0x00 Bit 12 QSSP_SW_RSTB 1
816 0x00 Bit 11 RAAE_SW_RSTB 1
817 0x00 Bit 9 RB_1_SW_RSTB 1
818 0x00 Bit 8 SM_SW_RSTB 1
819 */
820 regVal &= ~(0x00003b00);
821 /* host write GSM Configuration and Reset register */
822 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
823 PM8001_INIT_DBG(pm8001_ha,
824 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM "
825 "Configuration and Reset is set to = 0x%x\n",
826 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
827
828 /* step 4: */
829 /* disable GSM - Read Address Parity Check */
830 regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
831 PM8001_INIT_DBG(pm8001_ha,
832 pm8001_printk("GSM 0x700038 - Read Address Parity Check "
833 "Enable = 0x%x\n", regVal1));
834 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
835 PM8001_INIT_DBG(pm8001_ha,
836 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
837 "is set to = 0x%x\n",
838 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
839
840 /* disable GSM - Write Address Parity Check */
841 regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
842 PM8001_INIT_DBG(pm8001_ha,
843 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
844 " Enable = 0x%x\n", regVal2));
845 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
846 PM8001_INIT_DBG(pm8001_ha,
847 pm8001_printk("GSM 0x700040 - Write Address Parity Check "
848 "Enable is set to = 0x%x\n",
849 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
850
851 /* disable GSM - Write Data Parity Check */
852 regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
853 PM8001_INIT_DBG(pm8001_ha,
854 pm8001_printk("GSM 0x300048 - Write Data Parity Check"
855 " Enable = 0x%x\n", regVal3));
856 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
857 PM8001_INIT_DBG(pm8001_ha,
858 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable"
859 "is set to = 0x%x\n",
860 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
861
862 /* step 5: delay 10 usec */
863 udelay(10);
864 /* step 5-b: set GPIO-0 output control to tristate anyway */
865 if (-1 == bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
866 PM8001_INIT_DBG(pm8001_ha,
867 pm8001_printk("Shift Bar4 to 0x%x failed\n",
868 GPIO_ADDR_BASE));
869 return -1;
870 }
871 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
872 PM8001_INIT_DBG(pm8001_ha,
873 pm8001_printk("GPIO Output Control Register:"
874 " = 0x%x\n", regVal));
875 /* set GPIO-0 output control to tri-state */
876 regVal &= 0xFFFFFFFC;
877 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
878
879 /* Step 6: Reset the IOP and AAP1 */
880 /* map 0x00000 to BAR4(0x20), BAR2(win) */
881 if (-1 == bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
882 PM8001_FAIL_DBG(pm8001_ha,
883 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
884 SPC_TOP_LEVEL_ADDR_BASE));
885 return -1;
886 }
887 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
888 PM8001_INIT_DBG(pm8001_ha,
889 pm8001_printk("Top Register before resetting IOP/AAP1"
890 ":= 0x%x\n", regVal));
891 regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
892 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
893
894 /* step 7: Reset the BDMA/OSSP */
895 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
896 PM8001_INIT_DBG(pm8001_ha,
897 pm8001_printk("Top Register before resetting BDMA/OSSP"
898 ": = 0x%x\n", regVal));
899 regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
900 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
901
902 /* step 8: delay 10 usec */
903 udelay(10);
904
905 /* step 9: bring the BDMA and OSSP out of reset */
906 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
907 PM8001_INIT_DBG(pm8001_ha,
908 pm8001_printk("Top Register before bringing up BDMA/OSSP"
909 ":= 0x%x\n", regVal));
910 regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
911 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
912
913 /* step 10: delay 10 usec */
914 udelay(10);
915
916 /* step 11: reads and sets the GSM Configuration and Reset Register */
917 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
918 if (-1 == bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
919 PM8001_FAIL_DBG(pm8001_ha,
920 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
921 GSM_ADDR_BASE));
922 return -1;
923 }
924 PM8001_INIT_DBG(pm8001_ha,
925 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and "
926 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
927 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
928 /* Put those bits to high */
929 /* GSM XCBI offset = 0x70 0000
930 0x00 Bit 13 COM_SLV_SW_RSTB 1
931 0x00 Bit 12 QSSP_SW_RSTB 1
932 0x00 Bit 11 RAAE_SW_RSTB 1
933 0x00 Bit 9 RB_1_SW_RSTB 1
934 0x00 Bit 8 SM_SW_RSTB 1
935 */
936 regVal |= (GSM_CONFIG_RESET_VALUE);
937 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
938 PM8001_INIT_DBG(pm8001_ha,
939 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM"
940 " Configuration and Reset is set to = 0x%x\n",
941 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
942
943 /* step 12: Restore GSM - Read Address Parity Check */
944 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
945 /* just for debugging */
946 PM8001_INIT_DBG(pm8001_ha,
947 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
948 " = 0x%x\n", regVal));
949 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
950 PM8001_INIT_DBG(pm8001_ha,
951 pm8001_printk("GSM 0x700038 - Read Address Parity"
952 " Check Enable is set to = 0x%x\n",
953 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
954 /* Restore GSM - Write Address Parity Check */
955 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
956 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
957 PM8001_INIT_DBG(pm8001_ha,
958 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
959 " Enable is set to = 0x%x\n",
960 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
961 /* Restore GSM - Write Data Parity Check */
962 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
963 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
964 PM8001_INIT_DBG(pm8001_ha,
965 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable"
966 "is set to = 0x%x\n",
967 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
968
969 /* step 13: bring the IOP and AAP1 out of reset */
970 /* map 0x00000 to BAR4(0x20), BAR2(win) */
971 if (-1 == bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
972 PM8001_FAIL_DBG(pm8001_ha,
973 pm8001_printk("Shift Bar4 to 0x%x failed\n",
974 SPC_TOP_LEVEL_ADDR_BASE));
975 return -1;
976 }
977 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
978 regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
979 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
980
981 /* step 14: delay 10 usec - Normal Mode */
982 udelay(10);
983 /* check Soft Reset Normal mode or Soft Reset HDA mode */
984 if (signature == SPC_SOFT_RESET_SIGNATURE) {
985 /* step 15 (Normal Mode): wait until scratch pad1 register
986 bit 2 toggled */
987 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
988 do {
989 udelay(1);
990 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
991 SCRATCH_PAD1_RST;
992 } while ((regVal != toggleVal) && (--max_wait_count));
993
994 if (!max_wait_count) {
995 regVal = pm8001_cr32(pm8001_ha, 0,
996 MSGU_SCRATCH_PAD_1);
997 PM8001_FAIL_DBG(pm8001_ha,
998 pm8001_printk("TIMEOUT : ToggleVal 0x%x,"
999 "MSGU_SCRATCH_PAD1 = 0x%x\n",
1000 toggleVal, regVal));
1001 PM8001_FAIL_DBG(pm8001_ha,
1002 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1003 pm8001_cr32(pm8001_ha, 0,
1004 MSGU_SCRATCH_PAD_0)));
1005 PM8001_FAIL_DBG(pm8001_ha,
1006 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n",
1007 pm8001_cr32(pm8001_ha, 0,
1008 MSGU_SCRATCH_PAD_2)));
1009 PM8001_FAIL_DBG(pm8001_ha,
1010 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1011 pm8001_cr32(pm8001_ha, 0,
1012 MSGU_SCRATCH_PAD_3)));
1013 return -1;
1014 }
1015
1016 /* step 16 (Normal) - Clear ODMR and ODCR */
1017 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1018 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1019
1020 /* step 17 (Normal Mode): wait for the FW and IOP to get
1021 ready - 1 sec timeout */
1022 /* Wait for the SPC Configuration Table to be ready */
1023 if (check_fw_ready(pm8001_ha) == -1) {
1024 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1025 /* return error if MPI Configuration Table not ready */
1026 PM8001_INIT_DBG(pm8001_ha,
1027 pm8001_printk("FW not ready SCRATCH_PAD1"
1028 " = 0x%x\n", regVal));
1029 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1030 /* return error if MPI Configuration Table not ready */
1031 PM8001_INIT_DBG(pm8001_ha,
1032 pm8001_printk("FW not ready SCRATCH_PAD2"
1033 " = 0x%x\n", regVal));
1034 PM8001_INIT_DBG(pm8001_ha,
1035 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1036 pm8001_cr32(pm8001_ha, 0,
1037 MSGU_SCRATCH_PAD_0)));
1038 PM8001_INIT_DBG(pm8001_ha,
1039 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1040 pm8001_cr32(pm8001_ha, 0,
1041 MSGU_SCRATCH_PAD_3)));
1042 return -1;
1043 }
1044 }
1045
1046 PM8001_INIT_DBG(pm8001_ha,
1047 pm8001_printk("SPC soft reset Complete\n"));
1048 return 0;
1049 }
1050
1051 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1052 {
1053 u32 i;
1054 u32 regVal;
1055 PM8001_INIT_DBG(pm8001_ha,
1056 pm8001_printk("chip reset start\n"));
1057
1058 /* do SPC chip reset. */
1059 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1060 regVal &= ~(SPC_REG_RESET_DEVICE);
1061 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1062
1063 /* delay 10 usec */
1064 udelay(10);
1065
1066 /* bring chip reset out of reset */
1067 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1068 regVal |= SPC_REG_RESET_DEVICE;
1069 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1070
1071 /* delay 10 usec */
1072 udelay(10);
1073
1074 /* wait for 20 msec until the firmware gets reloaded */
1075 i = 20;
1076 do {
1077 mdelay(1);
1078 } while ((--i) != 0);
1079
1080 PM8001_INIT_DBG(pm8001_ha,
1081 pm8001_printk("chip reset finished\n"));
1082 }
1083
1084 /**
1085 * pm8001_chip_iounmap - which maped when initialized.
1086 * @pm8001_ha: our hba card information
1087 */
1088 static void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1089 {
1090 s8 bar, logical = 0;
1091 for (bar = 0; bar < 6; bar++) {
1092 /*
1093 ** logical BARs for SPC:
1094 ** bar 0 and 1 - logical BAR0
1095 ** bar 2 and 3 - logical BAR1
1096 ** bar4 - logical BAR2
1097 ** bar5 - logical BAR3
1098 ** Skip the appropriate assignments:
1099 */
1100 if ((bar == 1) || (bar == 3))
1101 continue;
1102 if (pm8001_ha->io_mem[logical].memvirtaddr) {
1103 iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1104 logical++;
1105 }
1106 }
1107 }
1108
1109 /**
1110 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1111 * @pm8001_ha: our hba card information
1112 */
1113 static void
1114 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1115 {
1116 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1117 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1118 }
1119
1120 /**
1121 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1122 * @pm8001_ha: our hba card information
1123 */
1124 static void
1125 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1126 {
1127 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1128 }
1129
1130 /**
1131 * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1132 * @pm8001_ha: our hba card information
1133 */
1134 static void
1135 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1136 u32 int_vec_idx)
1137 {
1138 u32 msi_index;
1139 u32 value;
1140 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1141 msi_index += MSIX_TABLE_BASE;
1142 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1143 value = (1 << int_vec_idx);
1144 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value);
1145
1146 }
1147
1148 /**
1149 * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1150 * @pm8001_ha: our hba card information
1151 */
1152 static void
1153 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1154 u32 int_vec_idx)
1155 {
1156 u32 msi_index;
1157 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1158 msi_index += MSIX_TABLE_BASE;
1159 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE);
1160
1161 }
1162 /**
1163 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1164 * @pm8001_ha: our hba card information
1165 */
1166 static void
1167 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1168 {
1169 #ifdef PM8001_USE_MSIX
1170 pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1171 return;
1172 #endif
1173 pm8001_chip_intx_interrupt_enable(pm8001_ha);
1174
1175 }
1176
1177 /**
1178 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1179 * @pm8001_ha: our hba card information
1180 */
1181 static void
1182 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1183 {
1184 #ifdef PM8001_USE_MSIX
1185 pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1186 return;
1187 #endif
1188 pm8001_chip_intx_interrupt_disable(pm8001_ha);
1189
1190 }
1191
1192 /**
1193 * mpi_msg_free_get- get the free message buffer for transfer inbound queue.
1194 * @circularQ: the inbound queue we want to transfer to HBA.
1195 * @messageSize: the message size of this transfer, normally it is 64 bytes
1196 * @messagePtr: the pointer to message.
1197 */
1198 static int mpi_msg_free_get(struct inbound_queue_table *circularQ,
1199 u16 messageSize, void **messagePtr)
1200 {
1201 u32 offset, consumer_index;
1202 struct mpi_msg_hdr *msgHeader;
1203 u8 bcCount = 1; /* only support single buffer */
1204
1205 /* Checks is the requested message size can be allocated in this queue*/
1206 if (messageSize > 64) {
1207 *messagePtr = NULL;
1208 return -1;
1209 }
1210
1211 /* Stores the new consumer index */
1212 consumer_index = pm8001_read_32(circularQ->ci_virt);
1213 circularQ->consumer_index = cpu_to_le32(consumer_index);
1214 if (((circularQ->producer_idx + bcCount) % 256) ==
1215 circularQ->consumer_index) {
1216 *messagePtr = NULL;
1217 return -1;
1218 }
1219 /* get memory IOMB buffer address */
1220 offset = circularQ->producer_idx * 64;
1221 /* increment to next bcCount element */
1222 circularQ->producer_idx = (circularQ->producer_idx + bcCount) % 256;
1223 /* Adds that distance to the base of the region virtual address plus
1224 the message header size*/
1225 msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
1226 *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1227 return 0;
1228 }
1229
1230 /**
1231 * mpi_build_cmd- build the message queue for transfer, update the PI to FW
1232 * to tell the fw to get this message from IOMB.
1233 * @pm8001_ha: our hba card information
1234 * @circularQ: the inbound queue we want to transfer to HBA.
1235 * @opCode: the operation code represents commands which LLDD and fw recognized.
1236 * @payload: the command payload of each operation command.
1237 */
1238 static int mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1239 struct inbound_queue_table *circularQ,
1240 u32 opCode, void *payload)
1241 {
1242 u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1243 u32 responseQueue = 0;
1244 void *pMessage;
1245
1246 if (mpi_msg_free_get(circularQ, 64, &pMessage) < 0) {
1247 PM8001_IO_DBG(pm8001_ha,
1248 pm8001_printk("No free mpi buffer\n"));
1249 return -1;
1250 }
1251 BUG_ON(!payload);
1252 /*Copy to the payload*/
1253 memcpy(pMessage, payload, (64 - sizeof(struct mpi_msg_hdr)));
1254
1255 /*Build the header*/
1256 Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1257 | ((responseQueue & 0x3F) << 16)
1258 | ((category & 0xF) << 12) | (opCode & 0xFFF));
1259
1260 pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1261 /*Update the PI to the firmware*/
1262 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1263 circularQ->pi_offset, circularQ->producer_idx);
1264 PM8001_IO_DBG(pm8001_ha,
1265 pm8001_printk("after PI= %d CI= %d\n", circularQ->producer_idx,
1266 circularQ->consumer_index));
1267 return 0;
1268 }
1269
1270 static u32 mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
1271 struct outbound_queue_table *circularQ, u8 bc)
1272 {
1273 u32 producer_index;
1274 struct mpi_msg_hdr *msgHeader;
1275 struct mpi_msg_hdr *pOutBoundMsgHeader;
1276
1277 msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
1278 pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
1279 circularQ->consumer_idx * 64);
1280 if (pOutBoundMsgHeader != msgHeader) {
1281 PM8001_FAIL_DBG(pm8001_ha,
1282 pm8001_printk("consumer_idx = %d msgHeader = %p\n",
1283 circularQ->consumer_idx, msgHeader));
1284
1285 /* Update the producer index from SPC */
1286 producer_index = pm8001_read_32(circularQ->pi_virt);
1287 circularQ->producer_index = cpu_to_le32(producer_index);
1288 PM8001_FAIL_DBG(pm8001_ha,
1289 pm8001_printk("consumer_idx = %d producer_index = %d"
1290 "msgHeader = %p\n", circularQ->consumer_idx,
1291 circularQ->producer_index, msgHeader));
1292 return 0;
1293 }
1294 /* free the circular queue buffer elements associated with the message*/
1295 circularQ->consumer_idx = (circularQ->consumer_idx + bc) % 256;
1296 /* update the CI of outbound queue */
1297 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1298 circularQ->consumer_idx);
1299 /* Update the producer index from SPC*/
1300 producer_index = pm8001_read_32(circularQ->pi_virt);
1301 circularQ->producer_index = cpu_to_le32(producer_index);
1302 PM8001_IO_DBG(pm8001_ha,
1303 pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx,
1304 circularQ->producer_index));
1305 return 0;
1306 }
1307
1308 /**
1309 * mpi_msg_consume- get the MPI message from outbound queue message table.
1310 * @pm8001_ha: our hba card information
1311 * @circularQ: the outbound queue table.
1312 * @messagePtr1: the message contents of this outbound message.
1313 * @pBC: the message size.
1314 */
1315 static u32 mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1316 struct outbound_queue_table *circularQ,
1317 void **messagePtr1, u8 *pBC)
1318 {
1319 struct mpi_msg_hdr *msgHeader;
1320 __le32 msgHeader_tmp;
1321 u32 header_tmp;
1322 do {
1323 /* If there are not-yet-delivered messages ... */
1324 if (circularQ->producer_index != circularQ->consumer_idx) {
1325 /*Get the pointer to the circular queue buffer element*/
1326 msgHeader = (struct mpi_msg_hdr *)
1327 (circularQ->base_virt +
1328 circularQ->consumer_idx * 64);
1329 /* read header */
1330 header_tmp = pm8001_read_32(msgHeader);
1331 msgHeader_tmp = cpu_to_le32(header_tmp);
1332 if (0 != (msgHeader_tmp & 0x80000000)) {
1333 if (OPC_OUB_SKIP_ENTRY !=
1334 (msgHeader_tmp & 0xfff)) {
1335 *messagePtr1 =
1336 ((u8 *)msgHeader) +
1337 sizeof(struct mpi_msg_hdr);
1338 *pBC = (u8)((msgHeader_tmp >> 24) &
1339 0x1f);
1340 PM8001_IO_DBG(pm8001_ha,
1341 pm8001_printk(": CI=%d PI=%d "
1342 "msgHeader=%x\n",
1343 circularQ->consumer_idx,
1344 circularQ->producer_index,
1345 msgHeader_tmp));
1346 return MPI_IO_STATUS_SUCCESS;
1347 } else {
1348 circularQ->consumer_idx =
1349 (circularQ->consumer_idx +
1350 ((msgHeader_tmp >> 24) & 0x1f))
1351 % 256;
1352 msgHeader_tmp = 0;
1353 pm8001_write_32(msgHeader, 0, 0);
1354 /* update the CI of outbound queue */
1355 pm8001_cw32(pm8001_ha,
1356 circularQ->ci_pci_bar,
1357 circularQ->ci_offset,
1358 circularQ->consumer_idx);
1359 }
1360 } else {
1361 circularQ->consumer_idx =
1362 (circularQ->consumer_idx +
1363 ((msgHeader_tmp >> 24) & 0x1f)) % 256;
1364 msgHeader_tmp = 0;
1365 pm8001_write_32(msgHeader, 0, 0);
1366 /* update the CI of outbound queue */
1367 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
1368 circularQ->ci_offset,
1369 circularQ->consumer_idx);
1370 return MPI_IO_STATUS_FAIL;
1371 }
1372 } else {
1373 u32 producer_index;
1374 void *pi_virt = circularQ->pi_virt;
1375 /* Update the producer index from SPC */
1376 producer_index = pm8001_read_32(pi_virt);
1377 circularQ->producer_index = cpu_to_le32(producer_index);
1378 }
1379 } while (circularQ->producer_index != circularQ->consumer_idx);
1380 /* while we don't have any more not-yet-delivered message */
1381 /* report empty */
1382 return MPI_IO_STATUS_BUSY;
1383 }
1384
1385 static void pm8001_work_fn(struct work_struct *work)
1386 {
1387 struct pm8001_work *pw = container_of(work, struct pm8001_work, work);
1388 struct pm8001_device *pm8001_dev;
1389 struct domain_device *dev;
1390
1391 switch (pw->handler) {
1392 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1393 pm8001_dev = pw->data;
1394 dev = pm8001_dev->sas_device;
1395 pm8001_I_T_nexus_reset(dev);
1396 break;
1397 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1398 pm8001_dev = pw->data;
1399 dev = pm8001_dev->sas_device;
1400 pm8001_I_T_nexus_reset(dev);
1401 break;
1402 case IO_DS_IN_ERROR:
1403 pm8001_dev = pw->data;
1404 dev = pm8001_dev->sas_device;
1405 pm8001_I_T_nexus_reset(dev);
1406 break;
1407 case IO_DS_NON_OPERATIONAL:
1408 pm8001_dev = pw->data;
1409 dev = pm8001_dev->sas_device;
1410 pm8001_I_T_nexus_reset(dev);
1411 break;
1412 }
1413 kfree(pw);
1414 }
1415
1416 static int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1417 int handler)
1418 {
1419 struct pm8001_work *pw;
1420 int ret = 0;
1421
1422 pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC);
1423 if (pw) {
1424 pw->pm8001_ha = pm8001_ha;
1425 pw->data = data;
1426 pw->handler = handler;
1427 INIT_WORK(&pw->work, pm8001_work_fn);
1428 queue_work(pm8001_wq, &pw->work);
1429 } else
1430 ret = -ENOMEM;
1431
1432 return ret;
1433 }
1434
1435 /**
1436 * mpi_ssp_completion- process the event that FW response to the SSP request.
1437 * @pm8001_ha: our hba card information
1438 * @piomb: the message contents of this outbound message.
1439 *
1440 * When FW has completed a ssp request for example a IO request, after it has
1441 * filled the SG data with the data, it will trigger this event represent
1442 * that he has finished the job,please check the coresponding buffer.
1443 * So we will tell the caller who maybe waiting the result to tell upper layer
1444 * that the task has been finished.
1445 */
1446 static void
1447 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1448 {
1449 struct sas_task *t;
1450 struct pm8001_ccb_info *ccb;
1451 unsigned long flags;
1452 u32 status;
1453 u32 param;
1454 u32 tag;
1455 struct ssp_completion_resp *psspPayload;
1456 struct task_status_struct *ts;
1457 struct ssp_response_iu *iu;
1458 struct pm8001_device *pm8001_dev;
1459 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1460 status = le32_to_cpu(psspPayload->status);
1461 tag = le32_to_cpu(psspPayload->tag);
1462 ccb = &pm8001_ha->ccb_info[tag];
1463 pm8001_dev = ccb->device;
1464 param = le32_to_cpu(psspPayload->param);
1465
1466 t = ccb->task;
1467
1468 if (status && status != IO_UNDERFLOW)
1469 PM8001_FAIL_DBG(pm8001_ha,
1470 pm8001_printk("sas IO status 0x%x\n", status));
1471 if (unlikely(!t || !t->lldd_task || !t->dev))
1472 return;
1473 ts = &t->task_status;
1474 switch (status) {
1475 case IO_SUCCESS:
1476 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS"
1477 ",param = %d\n", param));
1478 if (param == 0) {
1479 ts->resp = SAS_TASK_COMPLETE;
1480 ts->stat = SAM_STAT_GOOD;
1481 } else {
1482 ts->resp = SAS_TASK_COMPLETE;
1483 ts->stat = SAS_PROTO_RESPONSE;
1484 ts->residual = param;
1485 iu = &psspPayload->ssp_resp_iu;
1486 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1487 }
1488 if (pm8001_dev)
1489 pm8001_dev->running_req--;
1490 break;
1491 case IO_ABORTED:
1492 PM8001_IO_DBG(pm8001_ha,
1493 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1494 ts->resp = SAS_TASK_COMPLETE;
1495 ts->stat = SAS_ABORTED_TASK;
1496 break;
1497 case IO_UNDERFLOW:
1498 /* SSP Completion with error */
1499 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW"
1500 ",param = %d\n", param));
1501 ts->resp = SAS_TASK_COMPLETE;
1502 ts->stat = SAS_DATA_UNDERRUN;
1503 ts->residual = param;
1504 if (pm8001_dev)
1505 pm8001_dev->running_req--;
1506 break;
1507 case IO_NO_DEVICE:
1508 PM8001_IO_DBG(pm8001_ha,
1509 pm8001_printk("IO_NO_DEVICE\n"));
1510 ts->resp = SAS_TASK_UNDELIVERED;
1511 ts->stat = SAS_PHY_DOWN;
1512 break;
1513 case IO_XFER_ERROR_BREAK:
1514 PM8001_IO_DBG(pm8001_ha,
1515 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1516 ts->resp = SAS_TASK_COMPLETE;
1517 ts->stat = SAS_OPEN_REJECT;
1518 break;
1519 case IO_XFER_ERROR_PHY_NOT_READY:
1520 PM8001_IO_DBG(pm8001_ha,
1521 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1522 ts->resp = SAS_TASK_COMPLETE;
1523 ts->stat = SAS_OPEN_REJECT;
1524 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1525 break;
1526 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1527 PM8001_IO_DBG(pm8001_ha,
1528 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1529 ts->resp = SAS_TASK_COMPLETE;
1530 ts->stat = SAS_OPEN_REJECT;
1531 ts->open_rej_reason = SAS_OREJ_EPROTO;
1532 break;
1533 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1534 PM8001_IO_DBG(pm8001_ha,
1535 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1536 ts->resp = SAS_TASK_COMPLETE;
1537 ts->stat = SAS_OPEN_REJECT;
1538 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1539 break;
1540 case IO_OPEN_CNX_ERROR_BREAK:
1541 PM8001_IO_DBG(pm8001_ha,
1542 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1543 ts->resp = SAS_TASK_COMPLETE;
1544 ts->stat = SAS_OPEN_REJECT;
1545 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1546 break;
1547 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1548 PM8001_IO_DBG(pm8001_ha,
1549 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1550 ts->resp = SAS_TASK_COMPLETE;
1551 ts->stat = SAS_OPEN_REJECT;
1552 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1553 if (!t->uldd_task)
1554 pm8001_handle_event(pm8001_ha,
1555 pm8001_dev,
1556 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1557 break;
1558 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1559 PM8001_IO_DBG(pm8001_ha,
1560 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1561 ts->resp = SAS_TASK_COMPLETE;
1562 ts->stat = SAS_OPEN_REJECT;
1563 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1564 break;
1565 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1566 PM8001_IO_DBG(pm8001_ha,
1567 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1568 "NOT_SUPPORTED\n"));
1569 ts->resp = SAS_TASK_COMPLETE;
1570 ts->stat = SAS_OPEN_REJECT;
1571 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1572 break;
1573 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1574 PM8001_IO_DBG(pm8001_ha,
1575 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1576 ts->resp = SAS_TASK_UNDELIVERED;
1577 ts->stat = SAS_OPEN_REJECT;
1578 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1579 break;
1580 case IO_XFER_ERROR_NAK_RECEIVED:
1581 PM8001_IO_DBG(pm8001_ha,
1582 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1583 ts->resp = SAS_TASK_COMPLETE;
1584 ts->stat = SAS_OPEN_REJECT;
1585 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1586 break;
1587 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1588 PM8001_IO_DBG(pm8001_ha,
1589 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1590 ts->resp = SAS_TASK_COMPLETE;
1591 ts->stat = SAS_NAK_R_ERR;
1592 break;
1593 case IO_XFER_ERROR_DMA:
1594 PM8001_IO_DBG(pm8001_ha,
1595 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1596 ts->resp = SAS_TASK_COMPLETE;
1597 ts->stat = SAS_OPEN_REJECT;
1598 break;
1599 case IO_XFER_OPEN_RETRY_TIMEOUT:
1600 PM8001_IO_DBG(pm8001_ha,
1601 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1602 ts->resp = SAS_TASK_COMPLETE;
1603 ts->stat = SAS_OPEN_REJECT;
1604 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1605 break;
1606 case IO_XFER_ERROR_OFFSET_MISMATCH:
1607 PM8001_IO_DBG(pm8001_ha,
1608 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1609 ts->resp = SAS_TASK_COMPLETE;
1610 ts->stat = SAS_OPEN_REJECT;
1611 break;
1612 case IO_PORT_IN_RESET:
1613 PM8001_IO_DBG(pm8001_ha,
1614 pm8001_printk("IO_PORT_IN_RESET\n"));
1615 ts->resp = SAS_TASK_COMPLETE;
1616 ts->stat = SAS_OPEN_REJECT;
1617 break;
1618 case IO_DS_NON_OPERATIONAL:
1619 PM8001_IO_DBG(pm8001_ha,
1620 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1621 ts->resp = SAS_TASK_COMPLETE;
1622 ts->stat = SAS_OPEN_REJECT;
1623 if (!t->uldd_task)
1624 pm8001_handle_event(pm8001_ha,
1625 pm8001_dev,
1626 IO_DS_NON_OPERATIONAL);
1627 break;
1628 case IO_DS_IN_RECOVERY:
1629 PM8001_IO_DBG(pm8001_ha,
1630 pm8001_printk("IO_DS_IN_RECOVERY\n"));
1631 ts->resp = SAS_TASK_COMPLETE;
1632 ts->stat = SAS_OPEN_REJECT;
1633 break;
1634 case IO_TM_TAG_NOT_FOUND:
1635 PM8001_IO_DBG(pm8001_ha,
1636 pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1637 ts->resp = SAS_TASK_COMPLETE;
1638 ts->stat = SAS_OPEN_REJECT;
1639 break;
1640 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1641 PM8001_IO_DBG(pm8001_ha,
1642 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1643 ts->resp = SAS_TASK_COMPLETE;
1644 ts->stat = SAS_OPEN_REJECT;
1645 break;
1646 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1647 PM8001_IO_DBG(pm8001_ha,
1648 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1649 ts->resp = SAS_TASK_COMPLETE;
1650 ts->stat = SAS_OPEN_REJECT;
1651 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1652 break;
1653 default:
1654 PM8001_IO_DBG(pm8001_ha,
1655 pm8001_printk("Unknown status 0x%x\n", status));
1656 /* not allowed case. Therefore, return failed status */
1657 ts->resp = SAS_TASK_COMPLETE;
1658 ts->stat = SAS_OPEN_REJECT;
1659 break;
1660 }
1661 PM8001_IO_DBG(pm8001_ha,
1662 pm8001_printk("scsi_status = %x \n ",
1663 psspPayload->ssp_resp_iu.status));
1664 spin_lock_irqsave(&t->task_state_lock, flags);
1665 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1666 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1667 t->task_state_flags |= SAS_TASK_STATE_DONE;
1668 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1669 spin_unlock_irqrestore(&t->task_state_lock, flags);
1670 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
1671 " io_status 0x%x resp 0x%x "
1672 "stat 0x%x but aborted by upper layer!\n",
1673 t, status, ts->resp, ts->stat));
1674 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1675 } else {
1676 spin_unlock_irqrestore(&t->task_state_lock, flags);
1677 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1678 mb();/* in order to force CPU ordering */
1679 t->task_done(t);
1680 }
1681 }
1682
1683 /*See the comments for mpi_ssp_completion */
1684 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1685 {
1686 struct sas_task *t;
1687 unsigned long flags;
1688 struct task_status_struct *ts;
1689 struct pm8001_ccb_info *ccb;
1690 struct pm8001_device *pm8001_dev;
1691 struct ssp_event_resp *psspPayload =
1692 (struct ssp_event_resp *)(piomb + 4);
1693 u32 event = le32_to_cpu(psspPayload->event);
1694 u32 tag = le32_to_cpu(psspPayload->tag);
1695 u32 port_id = le32_to_cpu(psspPayload->port_id);
1696 u32 dev_id = le32_to_cpu(psspPayload->device_id);
1697
1698 ccb = &pm8001_ha->ccb_info[tag];
1699 t = ccb->task;
1700 pm8001_dev = ccb->device;
1701 if (event)
1702 PM8001_FAIL_DBG(pm8001_ha,
1703 pm8001_printk("sas IO status 0x%x\n", event));
1704 if (unlikely(!t || !t->lldd_task || !t->dev))
1705 return;
1706 ts = &t->task_status;
1707 PM8001_IO_DBG(pm8001_ha,
1708 pm8001_printk("port_id = %x,device_id = %x\n",
1709 port_id, dev_id));
1710 switch (event) {
1711 case IO_OVERFLOW:
1712 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1713 ts->resp = SAS_TASK_COMPLETE;
1714 ts->stat = SAS_DATA_OVERRUN;
1715 ts->residual = 0;
1716 if (pm8001_dev)
1717 pm8001_dev->running_req--;
1718 break;
1719 case IO_XFER_ERROR_BREAK:
1720 PM8001_IO_DBG(pm8001_ha,
1721 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1722 ts->resp = SAS_TASK_COMPLETE;
1723 ts->stat = SAS_INTERRUPTED;
1724 break;
1725 case IO_XFER_ERROR_PHY_NOT_READY:
1726 PM8001_IO_DBG(pm8001_ha,
1727 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1728 ts->resp = SAS_TASK_COMPLETE;
1729 ts->stat = SAS_OPEN_REJECT;
1730 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1731 break;
1732 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1733 PM8001_IO_DBG(pm8001_ha,
1734 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
1735 "_SUPPORTED\n"));
1736 ts->resp = SAS_TASK_COMPLETE;
1737 ts->stat = SAS_OPEN_REJECT;
1738 ts->open_rej_reason = SAS_OREJ_EPROTO;
1739 break;
1740 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1741 PM8001_IO_DBG(pm8001_ha,
1742 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1743 ts->resp = SAS_TASK_COMPLETE;
1744 ts->stat = SAS_OPEN_REJECT;
1745 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1746 break;
1747 case IO_OPEN_CNX_ERROR_BREAK:
1748 PM8001_IO_DBG(pm8001_ha,
1749 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1750 ts->resp = SAS_TASK_COMPLETE;
1751 ts->stat = SAS_OPEN_REJECT;
1752 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1753 break;
1754 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1755 PM8001_IO_DBG(pm8001_ha,
1756 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1757 ts->resp = SAS_TASK_COMPLETE;
1758 ts->stat = SAS_OPEN_REJECT;
1759 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1760 if (!t->uldd_task)
1761 pm8001_handle_event(pm8001_ha,
1762 pm8001_dev,
1763 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1764 break;
1765 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1766 PM8001_IO_DBG(pm8001_ha,
1767 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1768 ts->resp = SAS_TASK_COMPLETE;
1769 ts->stat = SAS_OPEN_REJECT;
1770 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1771 break;
1772 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1773 PM8001_IO_DBG(pm8001_ha,
1774 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1775 "NOT_SUPPORTED\n"));
1776 ts->resp = SAS_TASK_COMPLETE;
1777 ts->stat = SAS_OPEN_REJECT;
1778 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1779 break;
1780 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1781 PM8001_IO_DBG(pm8001_ha,
1782 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1783 ts->resp = SAS_TASK_COMPLETE;
1784 ts->stat = SAS_OPEN_REJECT;
1785 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1786 break;
1787 case IO_XFER_ERROR_NAK_RECEIVED:
1788 PM8001_IO_DBG(pm8001_ha,
1789 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1790 ts->resp = SAS_TASK_COMPLETE;
1791 ts->stat = SAS_OPEN_REJECT;
1792 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1793 break;
1794 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1795 PM8001_IO_DBG(pm8001_ha,
1796 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1797 ts->resp = SAS_TASK_COMPLETE;
1798 ts->stat = SAS_NAK_R_ERR;
1799 break;
1800 case IO_XFER_OPEN_RETRY_TIMEOUT:
1801 PM8001_IO_DBG(pm8001_ha,
1802 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1803 ts->resp = SAS_TASK_COMPLETE;
1804 ts->stat = SAS_OPEN_REJECT;
1805 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1806 break;
1807 case IO_XFER_ERROR_UNEXPECTED_PHASE:
1808 PM8001_IO_DBG(pm8001_ha,
1809 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
1810 ts->resp = SAS_TASK_COMPLETE;
1811 ts->stat = SAS_DATA_OVERRUN;
1812 break;
1813 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
1814 PM8001_IO_DBG(pm8001_ha,
1815 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
1816 ts->resp = SAS_TASK_COMPLETE;
1817 ts->stat = SAS_DATA_OVERRUN;
1818 break;
1819 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
1820 PM8001_IO_DBG(pm8001_ha,
1821 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
1822 ts->resp = SAS_TASK_COMPLETE;
1823 ts->stat = SAS_DATA_OVERRUN;
1824 break;
1825 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
1826 PM8001_IO_DBG(pm8001_ha,
1827 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
1828 ts->resp = SAS_TASK_COMPLETE;
1829 ts->stat = SAS_DATA_OVERRUN;
1830 break;
1831 case IO_XFER_ERROR_OFFSET_MISMATCH:
1832 PM8001_IO_DBG(pm8001_ha,
1833 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1834 ts->resp = SAS_TASK_COMPLETE;
1835 ts->stat = SAS_DATA_OVERRUN;
1836 break;
1837 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
1838 PM8001_IO_DBG(pm8001_ha,
1839 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
1840 ts->resp = SAS_TASK_COMPLETE;
1841 ts->stat = SAS_DATA_OVERRUN;
1842 break;
1843 case IO_XFER_CMD_FRAME_ISSUED:
1844 PM8001_IO_DBG(pm8001_ha,
1845 pm8001_printk(" IO_XFER_CMD_FRAME_ISSUED\n"));
1846 return;
1847 default:
1848 PM8001_IO_DBG(pm8001_ha,
1849 pm8001_printk("Unknown status 0x%x\n", event));
1850 /* not allowed case. Therefore, return failed status */
1851 ts->resp = SAS_TASK_COMPLETE;
1852 ts->stat = SAS_DATA_OVERRUN;
1853 break;
1854 }
1855 spin_lock_irqsave(&t->task_state_lock, flags);
1856 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1857 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1858 t->task_state_flags |= SAS_TASK_STATE_DONE;
1859 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1860 spin_unlock_irqrestore(&t->task_state_lock, flags);
1861 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
1862 " event 0x%x resp 0x%x "
1863 "stat 0x%x but aborted by upper layer!\n",
1864 t, event, ts->resp, ts->stat));
1865 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1866 } else {
1867 spin_unlock_irqrestore(&t->task_state_lock, flags);
1868 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1869 mb();/* in order to force CPU ordering */
1870 t->task_done(t);
1871 }
1872 }
1873
1874 /*See the comments for mpi_ssp_completion */
1875 static void
1876 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1877 {
1878 struct sas_task *t;
1879 struct pm8001_ccb_info *ccb;
1880 unsigned long flags = 0;
1881 u32 param;
1882 u32 status;
1883 u32 tag;
1884 struct sata_completion_resp *psataPayload;
1885 struct task_status_struct *ts;
1886 struct ata_task_resp *resp ;
1887 u32 *sata_resp;
1888 struct pm8001_device *pm8001_dev;
1889
1890 psataPayload = (struct sata_completion_resp *)(piomb + 4);
1891 status = le32_to_cpu(psataPayload->status);
1892 tag = le32_to_cpu(psataPayload->tag);
1893
1894 ccb = &pm8001_ha->ccb_info[tag];
1895 param = le32_to_cpu(psataPayload->param);
1896 t = ccb->task;
1897 ts = &t->task_status;
1898 pm8001_dev = ccb->device;
1899 if (status)
1900 PM8001_FAIL_DBG(pm8001_ha,
1901 pm8001_printk("sata IO status 0x%x\n", status));
1902 if (unlikely(!t || !t->lldd_task || !t->dev))
1903 return;
1904
1905 switch (status) {
1906 case IO_SUCCESS:
1907 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
1908 if (param == 0) {
1909 ts->resp = SAS_TASK_COMPLETE;
1910 ts->stat = SAM_STAT_GOOD;
1911 } else {
1912 u8 len;
1913 ts->resp = SAS_TASK_COMPLETE;
1914 ts->stat = SAS_PROTO_RESPONSE;
1915 ts->residual = param;
1916 PM8001_IO_DBG(pm8001_ha,
1917 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
1918 param));
1919 sata_resp = &psataPayload->sata_resp[0];
1920 resp = (struct ata_task_resp *)ts->buf;
1921 if (t->ata_task.dma_xfer == 0 &&
1922 t->data_dir == PCI_DMA_FROMDEVICE) {
1923 len = sizeof(struct pio_setup_fis);
1924 PM8001_IO_DBG(pm8001_ha,
1925 pm8001_printk("PIO read len = %d\n", len));
1926 } else if (t->ata_task.use_ncq) {
1927 len = sizeof(struct set_dev_bits_fis);
1928 PM8001_IO_DBG(pm8001_ha,
1929 pm8001_printk("FPDMA len = %d\n", len));
1930 } else {
1931 len = sizeof(struct dev_to_host_fis);
1932 PM8001_IO_DBG(pm8001_ha,
1933 pm8001_printk("other len = %d\n", len));
1934 }
1935 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
1936 resp->frame_len = len;
1937 memcpy(&resp->ending_fis[0], sata_resp, len);
1938 ts->buf_valid_size = sizeof(*resp);
1939 } else
1940 PM8001_IO_DBG(pm8001_ha,
1941 pm8001_printk("response to large\n"));
1942 }
1943 if (pm8001_dev)
1944 pm8001_dev->running_req--;
1945 break;
1946 case IO_ABORTED:
1947 PM8001_IO_DBG(pm8001_ha,
1948 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1949 ts->resp = SAS_TASK_COMPLETE;
1950 ts->stat = SAS_ABORTED_TASK;
1951 if (pm8001_dev)
1952 pm8001_dev->running_req--;
1953 break;
1954 /* following cases are to do cases */
1955 case IO_UNDERFLOW:
1956 /* SATA Completion with error */
1957 PM8001_IO_DBG(pm8001_ha,
1958 pm8001_printk("IO_UNDERFLOW param = %d\n", param));
1959 ts->resp = SAS_TASK_COMPLETE;
1960 ts->stat = SAS_DATA_UNDERRUN;
1961 ts->residual = param;
1962 if (pm8001_dev)
1963 pm8001_dev->running_req--;
1964 break;
1965 case IO_NO_DEVICE:
1966 PM8001_IO_DBG(pm8001_ha,
1967 pm8001_printk("IO_NO_DEVICE\n"));
1968 ts->resp = SAS_TASK_UNDELIVERED;
1969 ts->stat = SAS_PHY_DOWN;
1970 break;
1971 case IO_XFER_ERROR_BREAK:
1972 PM8001_IO_DBG(pm8001_ha,
1973 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1974 ts->resp = SAS_TASK_COMPLETE;
1975 ts->stat = SAS_INTERRUPTED;
1976 break;
1977 case IO_XFER_ERROR_PHY_NOT_READY:
1978 PM8001_IO_DBG(pm8001_ha,
1979 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1980 ts->resp = SAS_TASK_COMPLETE;
1981 ts->stat = SAS_OPEN_REJECT;
1982 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1983 break;
1984 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1985 PM8001_IO_DBG(pm8001_ha,
1986 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
1987 "_SUPPORTED\n"));
1988 ts->resp = SAS_TASK_COMPLETE;
1989 ts->stat = SAS_OPEN_REJECT;
1990 ts->open_rej_reason = SAS_OREJ_EPROTO;
1991 break;
1992 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1993 PM8001_IO_DBG(pm8001_ha,
1994 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1995 ts->resp = SAS_TASK_COMPLETE;
1996 ts->stat = SAS_OPEN_REJECT;
1997 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1998 break;
1999 case IO_OPEN_CNX_ERROR_BREAK:
2000 PM8001_IO_DBG(pm8001_ha,
2001 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2002 ts->resp = SAS_TASK_COMPLETE;
2003 ts->stat = SAS_OPEN_REJECT;
2004 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2005 break;
2006 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2007 PM8001_IO_DBG(pm8001_ha,
2008 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2009 ts->resp = SAS_TASK_COMPLETE;
2010 ts->stat = SAS_DEV_NO_RESPONSE;
2011 if (!t->uldd_task) {
2012 pm8001_handle_event(pm8001_ha,
2013 pm8001_dev,
2014 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2015 ts->resp = SAS_TASK_UNDELIVERED;
2016 ts->stat = SAS_QUEUE_FULL;
2017 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2018 mb();/*in order to force CPU ordering*/
2019 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2020 t->task_done(t);
2021 spin_lock_irqsave(&pm8001_ha->lock, flags);
2022 return;
2023 }
2024 break;
2025 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2026 PM8001_IO_DBG(pm8001_ha,
2027 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2028 ts->resp = SAS_TASK_UNDELIVERED;
2029 ts->stat = SAS_OPEN_REJECT;
2030 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2031 if (!t->uldd_task) {
2032 pm8001_handle_event(pm8001_ha,
2033 pm8001_dev,
2034 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2035 ts->resp = SAS_TASK_UNDELIVERED;
2036 ts->stat = SAS_QUEUE_FULL;
2037 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2038 mb();/*ditto*/
2039 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2040 t->task_done(t);
2041 spin_lock_irqsave(&pm8001_ha->lock, flags);
2042 return;
2043 }
2044 break;
2045 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2046 PM8001_IO_DBG(pm8001_ha,
2047 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2048 "NOT_SUPPORTED\n"));
2049 ts->resp = SAS_TASK_COMPLETE;
2050 ts->stat = SAS_OPEN_REJECT;
2051 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2052 break;
2053 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2054 PM8001_IO_DBG(pm8001_ha,
2055 pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES"
2056 "_BUSY\n"));
2057 ts->resp = SAS_TASK_COMPLETE;
2058 ts->stat = SAS_DEV_NO_RESPONSE;
2059 if (!t->uldd_task) {
2060 pm8001_handle_event(pm8001_ha,
2061 pm8001_dev,
2062 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2063 ts->resp = SAS_TASK_UNDELIVERED;
2064 ts->stat = SAS_QUEUE_FULL;
2065 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2066 mb();/* ditto*/
2067 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2068 t->task_done(t);
2069 spin_lock_irqsave(&pm8001_ha->lock, flags);
2070 return;
2071 }
2072 break;
2073 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2074 PM8001_IO_DBG(pm8001_ha,
2075 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2076 ts->resp = SAS_TASK_COMPLETE;
2077 ts->stat = SAS_OPEN_REJECT;
2078 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2079 break;
2080 case IO_XFER_ERROR_NAK_RECEIVED:
2081 PM8001_IO_DBG(pm8001_ha,
2082 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2083 ts->resp = SAS_TASK_COMPLETE;
2084 ts->stat = SAS_NAK_R_ERR;
2085 break;
2086 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2087 PM8001_IO_DBG(pm8001_ha,
2088 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2089 ts->resp = SAS_TASK_COMPLETE;
2090 ts->stat = SAS_NAK_R_ERR;
2091 break;
2092 case IO_XFER_ERROR_DMA:
2093 PM8001_IO_DBG(pm8001_ha,
2094 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2095 ts->resp = SAS_TASK_COMPLETE;
2096 ts->stat = SAS_ABORTED_TASK;
2097 break;
2098 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2099 PM8001_IO_DBG(pm8001_ha,
2100 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2101 ts->resp = SAS_TASK_UNDELIVERED;
2102 ts->stat = SAS_DEV_NO_RESPONSE;
2103 break;
2104 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2105 PM8001_IO_DBG(pm8001_ha,
2106 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2107 ts->resp = SAS_TASK_COMPLETE;
2108 ts->stat = SAS_DATA_UNDERRUN;
2109 break;
2110 case IO_XFER_OPEN_RETRY_TIMEOUT:
2111 PM8001_IO_DBG(pm8001_ha,
2112 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2113 ts->resp = SAS_TASK_COMPLETE;
2114 ts->stat = SAS_OPEN_TO;
2115 break;
2116 case IO_PORT_IN_RESET:
2117 PM8001_IO_DBG(pm8001_ha,
2118 pm8001_printk("IO_PORT_IN_RESET\n"));
2119 ts->resp = SAS_TASK_COMPLETE;
2120 ts->stat = SAS_DEV_NO_RESPONSE;
2121 break;
2122 case IO_DS_NON_OPERATIONAL:
2123 PM8001_IO_DBG(pm8001_ha,
2124 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2125 ts->resp = SAS_TASK_COMPLETE;
2126 ts->stat = SAS_DEV_NO_RESPONSE;
2127 if (!t->uldd_task) {
2128 pm8001_handle_event(pm8001_ha, pm8001_dev,
2129 IO_DS_NON_OPERATIONAL);
2130 ts->resp = SAS_TASK_UNDELIVERED;
2131 ts->stat = SAS_QUEUE_FULL;
2132 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2133 mb();/*ditto*/
2134 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2135 t->task_done(t);
2136 spin_lock_irqsave(&pm8001_ha->lock, flags);
2137 return;
2138 }
2139 break;
2140 case IO_DS_IN_RECOVERY:
2141 PM8001_IO_DBG(pm8001_ha,
2142 pm8001_printk(" IO_DS_IN_RECOVERY\n"));
2143 ts->resp = SAS_TASK_COMPLETE;
2144 ts->stat = SAS_DEV_NO_RESPONSE;
2145 break;
2146 case IO_DS_IN_ERROR:
2147 PM8001_IO_DBG(pm8001_ha,
2148 pm8001_printk("IO_DS_IN_ERROR\n"));
2149 ts->resp = SAS_TASK_COMPLETE;
2150 ts->stat = SAS_DEV_NO_RESPONSE;
2151 if (!t->uldd_task) {
2152 pm8001_handle_event(pm8001_ha, pm8001_dev,
2153 IO_DS_IN_ERROR);
2154 ts->resp = SAS_TASK_UNDELIVERED;
2155 ts->stat = SAS_QUEUE_FULL;
2156 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2157 mb();/*ditto*/
2158 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2159 t->task_done(t);
2160 spin_lock_irqsave(&pm8001_ha->lock, flags);
2161 return;
2162 }
2163 break;
2164 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2165 PM8001_IO_DBG(pm8001_ha,
2166 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2167 ts->resp = SAS_TASK_COMPLETE;
2168 ts->stat = SAS_OPEN_REJECT;
2169 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2170 default:
2171 PM8001_IO_DBG(pm8001_ha,
2172 pm8001_printk("Unknown status 0x%x\n", status));
2173 /* not allowed case. Therefore, return failed status */
2174 ts->resp = SAS_TASK_COMPLETE;
2175 ts->stat = SAS_DEV_NO_RESPONSE;
2176 break;
2177 }
2178 spin_lock_irqsave(&t->task_state_lock, flags);
2179 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2180 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2181 t->task_state_flags |= SAS_TASK_STATE_DONE;
2182 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2183 spin_unlock_irqrestore(&t->task_state_lock, flags);
2184 PM8001_FAIL_DBG(pm8001_ha,
2185 pm8001_printk("task 0x%p done with io_status 0x%x"
2186 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2187 t, status, ts->resp, ts->stat));
2188 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2189 } else if (t->uldd_task) {
2190 spin_unlock_irqrestore(&t->task_state_lock, flags);
2191 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2192 mb();/* ditto */
2193 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2194 t->task_done(t);
2195 spin_lock_irqsave(&pm8001_ha->lock, flags);
2196 } else if (!t->uldd_task) {
2197 spin_unlock_irqrestore(&t->task_state_lock, flags);
2198 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2199 mb();/*ditto*/
2200 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2201 t->task_done(t);
2202 spin_lock_irqsave(&pm8001_ha->lock, flags);
2203 }
2204 }
2205
2206 /*See the comments for mpi_ssp_completion */
2207 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2208 {
2209 struct sas_task *t;
2210 unsigned long flags = 0;
2211 struct task_status_struct *ts;
2212 struct pm8001_ccb_info *ccb;
2213 struct pm8001_device *pm8001_dev;
2214 struct sata_event_resp *psataPayload =
2215 (struct sata_event_resp *)(piomb + 4);
2216 u32 event = le32_to_cpu(psataPayload->event);
2217 u32 tag = le32_to_cpu(psataPayload->tag);
2218 u32 port_id = le32_to_cpu(psataPayload->port_id);
2219 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2220
2221 ccb = &pm8001_ha->ccb_info[tag];
2222 t = ccb->task;
2223 pm8001_dev = ccb->device;
2224 if (event)
2225 PM8001_FAIL_DBG(pm8001_ha,
2226 pm8001_printk("sata IO status 0x%x\n", event));
2227 if (unlikely(!t || !t->lldd_task || !t->dev))
2228 return;
2229 ts = &t->task_status;
2230 PM8001_IO_DBG(pm8001_ha,
2231 pm8001_printk("port_id = %x,device_id = %x\n",
2232 port_id, dev_id));
2233 switch (event) {
2234 case IO_OVERFLOW:
2235 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2236 ts->resp = SAS_TASK_COMPLETE;
2237 ts->stat = SAS_DATA_OVERRUN;
2238 ts->residual = 0;
2239 if (pm8001_dev)
2240 pm8001_dev->running_req--;
2241 break;
2242 case IO_XFER_ERROR_BREAK:
2243 PM8001_IO_DBG(pm8001_ha,
2244 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2245 ts->resp = SAS_TASK_COMPLETE;
2246 ts->stat = SAS_INTERRUPTED;
2247 break;
2248 case IO_XFER_ERROR_PHY_NOT_READY:
2249 PM8001_IO_DBG(pm8001_ha,
2250 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2251 ts->resp = SAS_TASK_COMPLETE;
2252 ts->stat = SAS_OPEN_REJECT;
2253 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2254 break;
2255 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2256 PM8001_IO_DBG(pm8001_ha,
2257 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2258 "_SUPPORTED\n"));
2259 ts->resp = SAS_TASK_COMPLETE;
2260 ts->stat = SAS_OPEN_REJECT;
2261 ts->open_rej_reason = SAS_OREJ_EPROTO;
2262 break;
2263 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2264 PM8001_IO_DBG(pm8001_ha,
2265 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2266 ts->resp = SAS_TASK_COMPLETE;
2267 ts->stat = SAS_OPEN_REJECT;
2268 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2269 break;
2270 case IO_OPEN_CNX_ERROR_BREAK:
2271 PM8001_IO_DBG(pm8001_ha,
2272 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2273 ts->resp = SAS_TASK_COMPLETE;
2274 ts->stat = SAS_OPEN_REJECT;
2275 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2276 break;
2277 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2278 PM8001_IO_DBG(pm8001_ha,
2279 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2280 ts->resp = SAS_TASK_UNDELIVERED;
2281 ts->stat = SAS_DEV_NO_RESPONSE;
2282 if (!t->uldd_task) {
2283 pm8001_handle_event(pm8001_ha,
2284 pm8001_dev,
2285 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2286 ts->resp = SAS_TASK_COMPLETE;
2287 ts->stat = SAS_QUEUE_FULL;
2288 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2289 mb();/*ditto*/
2290 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2291 t->task_done(t);
2292 spin_lock_irqsave(&pm8001_ha->lock, flags);
2293 return;
2294 }
2295 break;
2296 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2297 PM8001_IO_DBG(pm8001_ha,
2298 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2299 ts->resp = SAS_TASK_UNDELIVERED;
2300 ts->stat = SAS_OPEN_REJECT;
2301 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2302 break;
2303 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2304 PM8001_IO_DBG(pm8001_ha,
2305 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2306 "NOT_SUPPORTED\n"));
2307 ts->resp = SAS_TASK_COMPLETE;
2308 ts->stat = SAS_OPEN_REJECT;
2309 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2310 break;
2311 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2312 PM8001_IO_DBG(pm8001_ha,
2313 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2314 ts->resp = SAS_TASK_COMPLETE;
2315 ts->stat = SAS_OPEN_REJECT;
2316 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2317 break;
2318 case IO_XFER_ERROR_NAK_RECEIVED:
2319 PM8001_IO_DBG(pm8001_ha,
2320 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2321 ts->resp = SAS_TASK_COMPLETE;
2322 ts->stat = SAS_NAK_R_ERR;
2323 break;
2324 case IO_XFER_ERROR_PEER_ABORTED:
2325 PM8001_IO_DBG(pm8001_ha,
2326 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2327 ts->resp = SAS_TASK_COMPLETE;
2328 ts->stat = SAS_NAK_R_ERR;
2329 break;
2330 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2331 PM8001_IO_DBG(pm8001_ha,
2332 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2333 ts->resp = SAS_TASK_COMPLETE;
2334 ts->stat = SAS_DATA_UNDERRUN;
2335 break;
2336 case IO_XFER_OPEN_RETRY_TIMEOUT:
2337 PM8001_IO_DBG(pm8001_ha,
2338 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2339 ts->resp = SAS_TASK_COMPLETE;
2340 ts->stat = SAS_OPEN_TO;
2341 break;
2342 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2343 PM8001_IO_DBG(pm8001_ha,
2344 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2345 ts->resp = SAS_TASK_COMPLETE;
2346 ts->stat = SAS_OPEN_TO;
2347 break;
2348 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2349 PM8001_IO_DBG(pm8001_ha,
2350 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2351 ts->resp = SAS_TASK_COMPLETE;
2352 ts->stat = SAS_OPEN_TO;
2353 break;
2354 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2355 PM8001_IO_DBG(pm8001_ha,
2356 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2357 ts->resp = SAS_TASK_COMPLETE;
2358 ts->stat = SAS_OPEN_TO;
2359 break;
2360 case IO_XFER_ERROR_OFFSET_MISMATCH:
2361 PM8001_IO_DBG(pm8001_ha,
2362 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2363 ts->resp = SAS_TASK_COMPLETE;
2364 ts->stat = SAS_OPEN_TO;
2365 break;
2366 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2367 PM8001_IO_DBG(pm8001_ha,
2368 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2369 ts->resp = SAS_TASK_COMPLETE;
2370 ts->stat = SAS_OPEN_TO;
2371 break;
2372 case IO_XFER_CMD_FRAME_ISSUED:
2373 PM8001_IO_DBG(pm8001_ha,
2374 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2375 break;
2376 case IO_XFER_PIO_SETUP_ERROR:
2377 PM8001_IO_DBG(pm8001_ha,
2378 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2379 ts->resp = SAS_TASK_COMPLETE;
2380 ts->stat = SAS_OPEN_TO;
2381 break;
2382 default:
2383 PM8001_IO_DBG(pm8001_ha,
2384 pm8001_printk("Unknown status 0x%x\n", event));
2385 /* not allowed case. Therefore, return failed status */
2386 ts->resp = SAS_TASK_COMPLETE;
2387 ts->stat = SAS_OPEN_TO;
2388 break;
2389 }
2390 spin_lock_irqsave(&t->task_state_lock, flags);
2391 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2392 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2393 t->task_state_flags |= SAS_TASK_STATE_DONE;
2394 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2395 spin_unlock_irqrestore(&t->task_state_lock, flags);
2396 PM8001_FAIL_DBG(pm8001_ha,
2397 pm8001_printk("task 0x%p done with io_status 0x%x"
2398 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2399 t, event, ts->resp, ts->stat));
2400 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2401 } else if (t->uldd_task) {
2402 spin_unlock_irqrestore(&t->task_state_lock, flags);
2403 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2404 mb();/* ditto */
2405 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2406 t->task_done(t);
2407 spin_lock_irqsave(&pm8001_ha->lock, flags);
2408 } else if (!t->uldd_task) {
2409 spin_unlock_irqrestore(&t->task_state_lock, flags);
2410 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2411 mb();/*ditto*/
2412 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2413 t->task_done(t);
2414 spin_lock_irqsave(&pm8001_ha->lock, flags);
2415 }
2416 }
2417
2418 /*See the comments for mpi_ssp_completion */
2419 static void
2420 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2421 {
2422 u32 param;
2423 struct sas_task *t;
2424 struct pm8001_ccb_info *ccb;
2425 unsigned long flags;
2426 u32 status;
2427 u32 tag;
2428 struct smp_completion_resp *psmpPayload;
2429 struct task_status_struct *ts;
2430 struct pm8001_device *pm8001_dev;
2431
2432 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2433 status = le32_to_cpu(psmpPayload->status);
2434 tag = le32_to_cpu(psmpPayload->tag);
2435
2436 ccb = &pm8001_ha->ccb_info[tag];
2437 param = le32_to_cpu(psmpPayload->param);
2438 t = ccb->task;
2439 ts = &t->task_status;
2440 pm8001_dev = ccb->device;
2441 if (status)
2442 PM8001_FAIL_DBG(pm8001_ha,
2443 pm8001_printk("smp IO status 0x%x\n", status));
2444 if (unlikely(!t || !t->lldd_task || !t->dev))
2445 return;
2446
2447 switch (status) {
2448 case IO_SUCCESS:
2449 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2450 ts->resp = SAS_TASK_COMPLETE;
2451 ts->stat = SAM_STAT_GOOD;
2452 if (pm8001_dev)
2453 pm8001_dev->running_req--;
2454 break;
2455 case IO_ABORTED:
2456 PM8001_IO_DBG(pm8001_ha,
2457 pm8001_printk("IO_ABORTED IOMB\n"));
2458 ts->resp = SAS_TASK_COMPLETE;
2459 ts->stat = SAS_ABORTED_TASK;
2460 if (pm8001_dev)
2461 pm8001_dev->running_req--;
2462 break;
2463 case IO_OVERFLOW:
2464 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2465 ts->resp = SAS_TASK_COMPLETE;
2466 ts->stat = SAS_DATA_OVERRUN;
2467 ts->residual = 0;
2468 if (pm8001_dev)
2469 pm8001_dev->running_req--;
2470 break;
2471 case IO_NO_DEVICE:
2472 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2473 ts->resp = SAS_TASK_COMPLETE;
2474 ts->stat = SAS_PHY_DOWN;
2475 break;
2476 case IO_ERROR_HW_TIMEOUT:
2477 PM8001_IO_DBG(pm8001_ha,
2478 pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2479 ts->resp = SAS_TASK_COMPLETE;
2480 ts->stat = SAM_STAT_BUSY;
2481 break;
2482 case IO_XFER_ERROR_BREAK:
2483 PM8001_IO_DBG(pm8001_ha,
2484 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2485 ts->resp = SAS_TASK_COMPLETE;
2486 ts->stat = SAM_STAT_BUSY;
2487 break;
2488 case IO_XFER_ERROR_PHY_NOT_READY:
2489 PM8001_IO_DBG(pm8001_ha,
2490 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2491 ts->resp = SAS_TASK_COMPLETE;
2492 ts->stat = SAM_STAT_BUSY;
2493 break;
2494 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2495 PM8001_IO_DBG(pm8001_ha,
2496 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2497 ts->resp = SAS_TASK_COMPLETE;
2498 ts->stat = SAS_OPEN_REJECT;
2499 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2500 break;
2501 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2502 PM8001_IO_DBG(pm8001_ha,
2503 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2504 ts->resp = SAS_TASK_COMPLETE;
2505 ts->stat = SAS_OPEN_REJECT;
2506 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2507 break;
2508 case IO_OPEN_CNX_ERROR_BREAK:
2509 PM8001_IO_DBG(pm8001_ha,
2510 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2511 ts->resp = SAS_TASK_COMPLETE;
2512 ts->stat = SAS_OPEN_REJECT;
2513 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2514 break;
2515 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2516 PM8001_IO_DBG(pm8001_ha,
2517 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2518 ts->resp = SAS_TASK_COMPLETE;
2519 ts->stat = SAS_OPEN_REJECT;
2520 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2521 pm8001_handle_event(pm8001_ha,
2522 pm8001_dev,
2523 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2524 break;
2525 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2526 PM8001_IO_DBG(pm8001_ha,
2527 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2528 ts->resp = SAS_TASK_COMPLETE;
2529 ts->stat = SAS_OPEN_REJECT;
2530 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2531 break;
2532 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2533 PM8001_IO_DBG(pm8001_ha,
2534 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2535 "NOT_SUPPORTED\n"));
2536 ts->resp = SAS_TASK_COMPLETE;
2537 ts->stat = SAS_OPEN_REJECT;
2538 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2539 break;
2540 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2541 PM8001_IO_DBG(pm8001_ha,
2542 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2543 ts->resp = SAS_TASK_COMPLETE;
2544 ts->stat = SAS_OPEN_REJECT;
2545 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2546 break;
2547 case IO_XFER_ERROR_RX_FRAME:
2548 PM8001_IO_DBG(pm8001_ha,
2549 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2550 ts->resp = SAS_TASK_COMPLETE;
2551 ts->stat = SAS_DEV_NO_RESPONSE;
2552 break;
2553 case IO_XFER_OPEN_RETRY_TIMEOUT:
2554 PM8001_IO_DBG(pm8001_ha,
2555 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2556 ts->resp = SAS_TASK_COMPLETE;
2557 ts->stat = SAS_OPEN_REJECT;
2558 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2559 break;
2560 case IO_ERROR_INTERNAL_SMP_RESOURCE:
2561 PM8001_IO_DBG(pm8001_ha,
2562 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2563 ts->resp = SAS_TASK_COMPLETE;
2564 ts->stat = SAS_QUEUE_FULL;
2565 break;
2566 case IO_PORT_IN_RESET:
2567 PM8001_IO_DBG(pm8001_ha,
2568 pm8001_printk("IO_PORT_IN_RESET\n"));
2569 ts->resp = SAS_TASK_COMPLETE;
2570 ts->stat = SAS_OPEN_REJECT;
2571 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2572 break;
2573 case IO_DS_NON_OPERATIONAL:
2574 PM8001_IO_DBG(pm8001_ha,
2575 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2576 ts->resp = SAS_TASK_COMPLETE;
2577 ts->stat = SAS_DEV_NO_RESPONSE;
2578 break;
2579 case IO_DS_IN_RECOVERY:
2580 PM8001_IO_DBG(pm8001_ha,
2581 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2582 ts->resp = SAS_TASK_COMPLETE;
2583 ts->stat = SAS_OPEN_REJECT;
2584 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2585 break;
2586 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2587 PM8001_IO_DBG(pm8001_ha,
2588 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2589 ts->resp = SAS_TASK_COMPLETE;
2590 ts->stat = SAS_OPEN_REJECT;
2591 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2592 break;
2593 default:
2594 PM8001_IO_DBG(pm8001_ha,
2595 pm8001_printk("Unknown status 0x%x\n", status));
2596 ts->resp = SAS_TASK_COMPLETE;
2597 ts->stat = SAS_DEV_NO_RESPONSE;
2598 /* not allowed case. Therefore, return failed status */
2599 break;
2600 }
2601 spin_lock_irqsave(&t->task_state_lock, flags);
2602 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2603 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2604 t->task_state_flags |= SAS_TASK_STATE_DONE;
2605 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2606 spin_unlock_irqrestore(&t->task_state_lock, flags);
2607 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2608 " io_status 0x%x resp 0x%x "
2609 "stat 0x%x but aborted by upper layer!\n",
2610 t, status, ts->resp, ts->stat));
2611 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2612 } else {
2613 spin_unlock_irqrestore(&t->task_state_lock, flags);
2614 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2615 mb();/* in order to force CPU ordering */
2616 t->task_done(t);
2617 }
2618 }
2619
2620 static void
2621 mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2622 {
2623 struct set_dev_state_resp *pPayload =
2624 (struct set_dev_state_resp *)(piomb + 4);
2625 u32 tag = le32_to_cpu(pPayload->tag);
2626 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2627 struct pm8001_device *pm8001_dev = ccb->device;
2628 u32 status = le32_to_cpu(pPayload->status);
2629 u32 device_id = le32_to_cpu(pPayload->device_id);
2630 u8 pds = le32_to_cpu(pPayload->pds_nds) | PDS_BITS;
2631 u8 nds = le32_to_cpu(pPayload->pds_nds) | NDS_BITS;
2632 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state "
2633 "from 0x%x to 0x%x status = 0x%x!\n",
2634 device_id, pds, nds, status));
2635 complete(pm8001_dev->setds_completion);
2636 ccb->task = NULL;
2637 ccb->ccb_tag = 0xFFFFFFFF;
2638 pm8001_ccb_free(pm8001_ha, tag);
2639 }
2640
2641 static void
2642 mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2643 {
2644 struct get_nvm_data_resp *pPayload =
2645 (struct get_nvm_data_resp *)(piomb + 4);
2646 u32 tag = le32_to_cpu(pPayload->tag);
2647 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2648 u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2649 complete(pm8001_ha->nvmd_completion);
2650 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n"));
2651 if ((dlen_status & NVMD_STAT) != 0) {
2652 PM8001_FAIL_DBG(pm8001_ha,
2653 pm8001_printk("Set nvm data error!\n"));
2654 return;
2655 }
2656 ccb->task = NULL;
2657 ccb->ccb_tag = 0xFFFFFFFF;
2658 pm8001_ccb_free(pm8001_ha, tag);
2659 }
2660
2661 static void
2662 mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2663 {
2664 struct fw_control_ex *fw_control_context;
2665 struct get_nvm_data_resp *pPayload =
2666 (struct get_nvm_data_resp *)(piomb + 4);
2667 u32 tag = le32_to_cpu(pPayload->tag);
2668 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2669 u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2670 u32 ir_tds_bn_dps_das_nvm =
2671 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
2672 void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
2673 fw_control_context = ccb->fw_control_context;
2674
2675 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n"));
2676 if ((dlen_status & NVMD_STAT) != 0) {
2677 PM8001_FAIL_DBG(pm8001_ha,
2678 pm8001_printk("Get nvm data error!\n"));
2679 complete(pm8001_ha->nvmd_completion);
2680 return;
2681 }
2682
2683 if (ir_tds_bn_dps_das_nvm & IPMode) {
2684 /* indirect mode - IR bit set */
2685 PM8001_MSG_DBG(pm8001_ha,
2686 pm8001_printk("Get NVMD success, IR=1\n"));
2687 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
2688 if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
2689 memcpy(pm8001_ha->sas_addr,
2690 ((u8 *)virt_addr + 4),
2691 SAS_ADDR_SIZE);
2692 PM8001_MSG_DBG(pm8001_ha,
2693 pm8001_printk("Get SAS address"
2694 " from VPD successfully!\n"));
2695 }
2696 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
2697 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
2698 ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
2699 ;
2700 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
2701 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
2702 ;
2703 } else {
2704 /* Should not be happened*/
2705 PM8001_MSG_DBG(pm8001_ha,
2706 pm8001_printk("(IR=1)Wrong Device type 0x%x\n",
2707 ir_tds_bn_dps_das_nvm));
2708 }
2709 } else /* direct mode */{
2710 PM8001_MSG_DBG(pm8001_ha,
2711 pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n",
2712 (dlen_status & NVMD_LEN) >> 24));
2713 }
2714 memcpy(fw_control_context->usrAddr,
2715 pm8001_ha->memoryMap.region[NVMD].virt_ptr,
2716 fw_control_context->len);
2717 complete(pm8001_ha->nvmd_completion);
2718 ccb->task = NULL;
2719 ccb->ccb_tag = 0xFFFFFFFF;
2720 pm8001_ccb_free(pm8001_ha, tag);
2721 }
2722
2723 static int mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
2724 {
2725 struct local_phy_ctl_resp *pPayload =
2726 (struct local_phy_ctl_resp *)(piomb + 4);
2727 u32 status = le32_to_cpu(pPayload->status);
2728 u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
2729 u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
2730 if (status != 0) {
2731 PM8001_MSG_DBG(pm8001_ha,
2732 pm8001_printk("%x phy execute %x phy op failed!\n",
2733 phy_id, phy_op));
2734 } else
2735 PM8001_MSG_DBG(pm8001_ha,
2736 pm8001_printk("%x phy execute %x phy op success!\n",
2737 phy_id, phy_op));
2738 return 0;
2739 }
2740
2741 /**
2742 * pm8001_bytes_dmaed - one of the interface function communication with libsas
2743 * @pm8001_ha: our hba card information
2744 * @i: which phy that received the event.
2745 *
2746 * when HBA driver received the identify done event or initiate FIS received
2747 * event(for SATA), it will invoke this function to notify the sas layer that
2748 * the sas toplogy has formed, please discover the the whole sas domain,
2749 * while receive a broadcast(change) primitive just tell the sas
2750 * layer to discover the changed domain rather than the whole domain.
2751 */
2752 static void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
2753 {
2754 struct pm8001_phy *phy = &pm8001_ha->phy[i];
2755 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2756 struct sas_ha_struct *sas_ha;
2757 if (!phy->phy_attached)
2758 return;
2759
2760 sas_ha = pm8001_ha->sas;
2761 if (sas_phy->phy) {
2762 struct sas_phy *sphy = sas_phy->phy;
2763 sphy->negotiated_linkrate = sas_phy->linkrate;
2764 sphy->minimum_linkrate = phy->minimum_linkrate;
2765 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
2766 sphy->maximum_linkrate = phy->maximum_linkrate;
2767 sphy->maximum_linkrate_hw = phy->maximum_linkrate;
2768 }
2769
2770 if (phy->phy_type & PORT_TYPE_SAS) {
2771 struct sas_identify_frame *id;
2772 id = (struct sas_identify_frame *)phy->frame_rcvd;
2773 id->dev_type = phy->identify.device_type;
2774 id->initiator_bits = SAS_PROTOCOL_ALL;
2775 id->target_bits = phy->identify.target_port_protocols;
2776 } else if (phy->phy_type & PORT_TYPE_SATA) {
2777 /*Nothing*/
2778 }
2779 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i));
2780
2781 sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
2782 pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED);
2783 }
2784
2785 /* Get the link rate speed */
2786 static void get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
2787 {
2788 struct sas_phy *sas_phy = phy->sas_phy.phy;
2789
2790 switch (link_rate) {
2791 case PHY_SPEED_60:
2792 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
2793 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
2794 break;
2795 case PHY_SPEED_30:
2796 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
2797 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
2798 break;
2799 case PHY_SPEED_15:
2800 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
2801 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
2802 break;
2803 }
2804 sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
2805 sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
2806 sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
2807 sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
2808 sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
2809 }
2810
2811 /**
2812 * asd_get_attached_sas_addr -- extract/generate attached SAS address
2813 * @phy: pointer to asd_phy
2814 * @sas_addr: pointer to buffer where the SAS address is to be written
2815 *
2816 * This function extracts the SAS address from an IDENTIFY frame
2817 * received. If OOB is SATA, then a SAS address is generated from the
2818 * HA tables.
2819 *
2820 * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
2821 * buffer.
2822 */
2823 static void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
2824 u8 *sas_addr)
2825 {
2826 if (phy->sas_phy.frame_rcvd[0] == 0x34
2827 && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
2828 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
2829 /* FIS device-to-host */
2830 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
2831 addr += phy->sas_phy.id;
2832 *(__be64 *)sas_addr = cpu_to_be64(addr);
2833 } else {
2834 struct sas_identify_frame *idframe =
2835 (void *) phy->sas_phy.frame_rcvd;
2836 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
2837 }
2838 }
2839
2840 /**
2841 * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
2842 * @pm8001_ha: our hba card information
2843 * @Qnum: the outbound queue message number.
2844 * @SEA: source of event to ack
2845 * @port_id: port id.
2846 * @phyId: phy id.
2847 * @param0: parameter 0.
2848 * @param1: parameter 1.
2849 */
2850 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
2851 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
2852 {
2853 struct hw_event_ack_req payload;
2854 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
2855
2856 struct inbound_queue_table *circularQ;
2857
2858 memset((u8 *)&payload, 0, sizeof(payload));
2859 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
2860 payload.tag = 1;
2861 payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
2862 ((phyId & 0x0F) << 4) | (port_id & 0x0F));
2863 payload.param0 = cpu_to_le32(param0);
2864 payload.param1 = cpu_to_le32(param1);
2865 mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
2866 }
2867
2868 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
2869 u32 phyId, u32 phy_op);
2870
2871 /**
2872 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
2873 * @pm8001_ha: our hba card information
2874 * @piomb: IO message buffer
2875 */
2876 static void
2877 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2878 {
2879 struct hw_event_resp *pPayload =
2880 (struct hw_event_resp *)(piomb + 4);
2881 u32 lr_evt_status_phyid_portid =
2882 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
2883 u8 link_rate =
2884 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
2885 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
2886 u8 phy_id =
2887 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
2888 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
2889 u8 portstate = (u8)(npip_portstate & 0x0000000F);
2890 struct pm8001_port *port = &pm8001_ha->port[port_id];
2891 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2892 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2893 unsigned long flags;
2894 u8 deviceType = pPayload->sas_identify.dev_type;
2895 port->port_state = portstate;
2896 PM8001_MSG_DBG(pm8001_ha,
2897 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
2898 port_id, phy_id));
2899
2900 switch (deviceType) {
2901 case SAS_PHY_UNUSED:
2902 PM8001_MSG_DBG(pm8001_ha,
2903 pm8001_printk("device type no device.\n"));
2904 break;
2905 case SAS_END_DEVICE:
2906 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
2907 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
2908 PHY_NOTIFY_ENABLE_SPINUP);
2909 port->port_attached = 1;
2910 get_lrate_mode(phy, link_rate);
2911 break;
2912 case SAS_EDGE_EXPANDER_DEVICE:
2913 PM8001_MSG_DBG(pm8001_ha,
2914 pm8001_printk("expander device.\n"));
2915 port->port_attached = 1;
2916 get_lrate_mode(phy, link_rate);
2917 break;
2918 case SAS_FANOUT_EXPANDER_DEVICE:
2919 PM8001_MSG_DBG(pm8001_ha,
2920 pm8001_printk("fanout expander device.\n"));
2921 port->port_attached = 1;
2922 get_lrate_mode(phy, link_rate);
2923 break;
2924 default:
2925 PM8001_MSG_DBG(pm8001_ha,
2926 pm8001_printk("unknown device type(%x)\n", deviceType));
2927 break;
2928 }
2929 phy->phy_type |= PORT_TYPE_SAS;
2930 phy->identify.device_type = deviceType;
2931 phy->phy_attached = 1;
2932 if (phy->identify.device_type == SAS_END_DEV)
2933 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
2934 else if (phy->identify.device_type != NO_DEVICE)
2935 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
2936 phy->sas_phy.oob_mode = SAS_OOB_MODE;
2937 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2938 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2939 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
2940 sizeof(struct sas_identify_frame)-4);
2941 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
2942 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2943 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2944 if (pm8001_ha->flags == PM8001F_RUN_TIME)
2945 mdelay(200);/*delay a moment to wait disk to spinup*/
2946 pm8001_bytes_dmaed(pm8001_ha, phy_id);
2947 }
2948
2949 /**
2950 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
2951 * @pm8001_ha: our hba card information
2952 * @piomb: IO message buffer
2953 */
2954 static void
2955 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2956 {
2957 struct hw_event_resp *pPayload =
2958 (struct hw_event_resp *)(piomb + 4);
2959 u32 lr_evt_status_phyid_portid =
2960 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
2961 u8 link_rate =
2962 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
2963 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
2964 u8 phy_id =
2965 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
2966 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
2967 u8 portstate = (u8)(npip_portstate & 0x0000000F);
2968 struct pm8001_port *port = &pm8001_ha->port[port_id];
2969 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2970 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2971 unsigned long flags;
2972 PM8001_MSG_DBG(pm8001_ha,
2973 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d,"
2974 " phy id = %d\n", port_id, phy_id));
2975 port->port_state = portstate;
2976 port->port_attached = 1;
2977 get_lrate_mode(phy, link_rate);
2978 phy->phy_type |= PORT_TYPE_SATA;
2979 phy->phy_attached = 1;
2980 phy->sas_phy.oob_mode = SATA_OOB_MODE;
2981 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2982 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2983 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
2984 sizeof(struct dev_to_host_fis));
2985 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
2986 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
2987 phy->identify.device_type = SATA_DEV;
2988 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2989 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2990 pm8001_bytes_dmaed(pm8001_ha, phy_id);
2991 }
2992
2993 /**
2994 * hw_event_phy_down -we should notify the libsas the phy is down.
2995 * @pm8001_ha: our hba card information
2996 * @piomb: IO message buffer
2997 */
2998 static void
2999 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3000 {
3001 struct hw_event_resp *pPayload =
3002 (struct hw_event_resp *)(piomb + 4);
3003 u32 lr_evt_status_phyid_portid =
3004 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3005 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3006 u8 phy_id =
3007 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3008 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3009 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3010 struct pm8001_port *port = &pm8001_ha->port[port_id];
3011 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3012 port->port_state = portstate;
3013 phy->phy_type = 0;
3014 phy->identify.device_type = 0;
3015 phy->phy_attached = 0;
3016 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3017 switch (portstate) {
3018 case PORT_VALID:
3019 break;
3020 case PORT_INVALID:
3021 PM8001_MSG_DBG(pm8001_ha,
3022 pm8001_printk(" PortInvalid portID %d\n", port_id));
3023 PM8001_MSG_DBG(pm8001_ha,
3024 pm8001_printk(" Last phy Down and port invalid\n"));
3025 port->port_attached = 0;
3026 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3027 port_id, phy_id, 0, 0);
3028 break;
3029 case PORT_IN_RESET:
3030 PM8001_MSG_DBG(pm8001_ha,
3031 pm8001_printk(" Port In Reset portID %d\n", port_id));
3032 break;
3033 case PORT_NOT_ESTABLISHED:
3034 PM8001_MSG_DBG(pm8001_ha,
3035 pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
3036 port->port_attached = 0;
3037 break;
3038 case PORT_LOSTCOMM:
3039 PM8001_MSG_DBG(pm8001_ha,
3040 pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
3041 PM8001_MSG_DBG(pm8001_ha,
3042 pm8001_printk(" Last phy Down and port invalid\n"));
3043 port->port_attached = 0;
3044 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3045 port_id, phy_id, 0, 0);
3046 break;
3047 default:
3048 port->port_attached = 0;
3049 PM8001_MSG_DBG(pm8001_ha,
3050 pm8001_printk(" phy Down and(default) = %x\n",
3051 portstate));
3052 break;
3053
3054 }
3055 }
3056
3057 /**
3058 * mpi_reg_resp -process register device ID response.
3059 * @pm8001_ha: our hba card information
3060 * @piomb: IO message buffer
3061 *
3062 * when sas layer find a device it will notify LLDD, then the driver register
3063 * the domain device to FW, this event is the return device ID which the FW
3064 * has assigned, from now,inter-communication with FW is no longer using the
3065 * SAS address, use device ID which FW assigned.
3066 */
3067 static int mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3068 {
3069 u32 status;
3070 u32 device_id;
3071 u32 htag;
3072 struct pm8001_ccb_info *ccb;
3073 struct pm8001_device *pm8001_dev;
3074 struct dev_reg_resp *registerRespPayload =
3075 (struct dev_reg_resp *)(piomb + 4);
3076
3077 htag = le32_to_cpu(registerRespPayload->tag);
3078 ccb = &pm8001_ha->ccb_info[registerRespPayload->tag];
3079 pm8001_dev = ccb->device;
3080 status = le32_to_cpu(registerRespPayload->status);
3081 device_id = le32_to_cpu(registerRespPayload->device_id);
3082 PM8001_MSG_DBG(pm8001_ha,
3083 pm8001_printk(" register device is status = %d\n", status));
3084 switch (status) {
3085 case DEVREG_SUCCESS:
3086 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n"));
3087 pm8001_dev->device_id = device_id;
3088 break;
3089 case DEVREG_FAILURE_OUT_OF_RESOURCE:
3090 PM8001_MSG_DBG(pm8001_ha,
3091 pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n"));
3092 break;
3093 case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3094 PM8001_MSG_DBG(pm8001_ha,
3095 pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n"));
3096 break;
3097 case DEVREG_FAILURE_INVALID_PHY_ID:
3098 PM8001_MSG_DBG(pm8001_ha,
3099 pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n"));
3100 break;
3101 case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3102 PM8001_MSG_DBG(pm8001_ha,
3103 pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n"));
3104 break;
3105 case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3106 PM8001_MSG_DBG(pm8001_ha,
3107 pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n"));
3108 break;
3109 case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3110 PM8001_MSG_DBG(pm8001_ha,
3111 pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n"));
3112 break;
3113 case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3114 PM8001_MSG_DBG(pm8001_ha,
3115 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n"));
3116 break;
3117 default:
3118 PM8001_MSG_DBG(pm8001_ha,
3119 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_UNSORPORTED\n"));
3120 break;
3121 }
3122 complete(pm8001_dev->dcompletion);
3123 ccb->task = NULL;
3124 ccb->ccb_tag = 0xFFFFFFFF;
3125 pm8001_ccb_free(pm8001_ha, htag);
3126 return 0;
3127 }
3128
3129 static int mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3130 {
3131 u32 status;
3132 u32 device_id;
3133 struct dev_reg_resp *registerRespPayload =
3134 (struct dev_reg_resp *)(piomb + 4);
3135
3136 status = le32_to_cpu(registerRespPayload->status);
3137 device_id = le32_to_cpu(registerRespPayload->device_id);
3138 if (status != 0)
3139 PM8001_MSG_DBG(pm8001_ha,
3140 pm8001_printk(" deregister device failed ,status = %x"
3141 ", device_id = %x\n", status, device_id));
3142 return 0;
3143 }
3144
3145 static int
3146 mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3147 {
3148 u32 status;
3149 struct fw_control_ex fw_control_context;
3150 struct fw_flash_Update_resp *ppayload =
3151 (struct fw_flash_Update_resp *)(piomb + 4);
3152 u32 tag = le32_to_cpu(ppayload->tag);
3153 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3154 status = le32_to_cpu(ppayload->status);
3155 memcpy(&fw_control_context,
3156 ccb->fw_control_context,
3157 sizeof(fw_control_context));
3158 switch (status) {
3159 case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3160 PM8001_MSG_DBG(pm8001_ha,
3161 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n"));
3162 break;
3163 case FLASH_UPDATE_IN_PROGRESS:
3164 PM8001_MSG_DBG(pm8001_ha,
3165 pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n"));
3166 break;
3167 case FLASH_UPDATE_HDR_ERR:
3168 PM8001_MSG_DBG(pm8001_ha,
3169 pm8001_printk(": FLASH_UPDATE_HDR_ERR\n"));
3170 break;
3171 case FLASH_UPDATE_OFFSET_ERR:
3172 PM8001_MSG_DBG(pm8001_ha,
3173 pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n"));
3174 break;
3175 case FLASH_UPDATE_CRC_ERR:
3176 PM8001_MSG_DBG(pm8001_ha,
3177 pm8001_printk(": FLASH_UPDATE_CRC_ERR\n"));
3178 break;
3179 case FLASH_UPDATE_LENGTH_ERR:
3180 PM8001_MSG_DBG(pm8001_ha,
3181 pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n"));
3182 break;
3183 case FLASH_UPDATE_HW_ERR:
3184 PM8001_MSG_DBG(pm8001_ha,
3185 pm8001_printk(": FLASH_UPDATE_HW_ERR\n"));
3186 break;
3187 case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3188 PM8001_MSG_DBG(pm8001_ha,
3189 pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n"));
3190 break;
3191 case FLASH_UPDATE_DISABLED:
3192 PM8001_MSG_DBG(pm8001_ha,
3193 pm8001_printk(": FLASH_UPDATE_DISABLED\n"));
3194 break;
3195 default:
3196 PM8001_MSG_DBG(pm8001_ha,
3197 pm8001_printk("No matched status = %d\n", status));
3198 break;
3199 }
3200 ccb->fw_control_context->fw_control->retcode = status;
3201 pci_free_consistent(pm8001_ha->pdev,
3202 fw_control_context.len,
3203 fw_control_context.virtAddr,
3204 fw_control_context.phys_addr);
3205 complete(pm8001_ha->nvmd_completion);
3206 ccb->task = NULL;
3207 ccb->ccb_tag = 0xFFFFFFFF;
3208 pm8001_ccb_free(pm8001_ha, tag);
3209 return 0;
3210 }
3211
3212 static int
3213 mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
3214 {
3215 u32 status;
3216 int i;
3217 struct general_event_resp *pPayload =
3218 (struct general_event_resp *)(piomb + 4);
3219 status = le32_to_cpu(pPayload->status);
3220 PM8001_MSG_DBG(pm8001_ha,
3221 pm8001_printk(" status = 0x%x\n", status));
3222 for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3223 PM8001_MSG_DBG(pm8001_ha,
3224 pm8001_printk("inb_IOMB_payload[0x%x] 0x%x,\n", i,
3225 pPayload->inb_IOMB_payload[i]));
3226 return 0;
3227 }
3228
3229 static int
3230 mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3231 {
3232 struct sas_task *t;
3233 struct pm8001_ccb_info *ccb;
3234 unsigned long flags;
3235 u32 status ;
3236 u32 tag, scp;
3237 struct task_status_struct *ts;
3238
3239 struct task_abort_resp *pPayload =
3240 (struct task_abort_resp *)(piomb + 4);
3241 ccb = &pm8001_ha->ccb_info[pPayload->tag];
3242 t = ccb->task;
3243
3244
3245 status = le32_to_cpu(pPayload->status);
3246 tag = le32_to_cpu(pPayload->tag);
3247 scp = le32_to_cpu(pPayload->scp);
3248 PM8001_IO_DBG(pm8001_ha,
3249 pm8001_printk(" status = 0x%x\n", status));
3250 if (t == NULL)
3251 return -1;
3252 ts = &t->task_status;
3253 if (status != 0)
3254 PM8001_FAIL_DBG(pm8001_ha,
3255 pm8001_printk("task abort failed status 0x%x ,"
3256 "tag = 0x%x, scp= 0x%x\n", status, tag, scp));
3257 switch (status) {
3258 case IO_SUCCESS:
3259 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
3260 ts->resp = SAS_TASK_COMPLETE;
3261 ts->stat = SAM_STAT_GOOD;
3262 break;
3263 case IO_NOT_VALID:
3264 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n"));
3265 ts->resp = TMF_RESP_FUNC_FAILED;
3266 break;
3267 }
3268 spin_lock_irqsave(&t->task_state_lock, flags);
3269 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3270 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3271 t->task_state_flags |= SAS_TASK_STATE_DONE;
3272 spin_unlock_irqrestore(&t->task_state_lock, flags);
3273 pm8001_ccb_task_free(pm8001_ha, t, ccb, pPayload->tag);
3274 mb();
3275 t->task_done(t);
3276 return 0;
3277 }
3278
3279 /**
3280 * mpi_hw_event -The hw event has come.
3281 * @pm8001_ha: our hba card information
3282 * @piomb: IO message buffer
3283 */
3284 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb)
3285 {
3286 unsigned long flags;
3287 struct hw_event_resp *pPayload =
3288 (struct hw_event_resp *)(piomb + 4);
3289 u32 lr_evt_status_phyid_portid =
3290 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3291 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3292 u8 phy_id =
3293 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3294 u16 eventType =
3295 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3296 u8 status =
3297 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3298 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3299 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3300 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3301 PM8001_MSG_DBG(pm8001_ha,
3302 pm8001_printk("outbound queue HW event & event type : "));
3303 switch (eventType) {
3304 case HW_EVENT_PHY_START_STATUS:
3305 PM8001_MSG_DBG(pm8001_ha,
3306 pm8001_printk("HW_EVENT_PHY_START_STATUS"
3307 " status = %x\n", status));
3308 if (status == 0) {
3309 phy->phy_state = 1;
3310 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3311 complete(phy->enable_completion);
3312 }
3313 break;
3314 case HW_EVENT_SAS_PHY_UP:
3315 PM8001_MSG_DBG(pm8001_ha,
3316 pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3317 hw_event_sas_phy_up(pm8001_ha, piomb);
3318 break;
3319 case HW_EVENT_SATA_PHY_UP:
3320 PM8001_MSG_DBG(pm8001_ha,
3321 pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3322 hw_event_sata_phy_up(pm8001_ha, piomb);
3323 break;
3324 case HW_EVENT_PHY_STOP_STATUS:
3325 PM8001_MSG_DBG(pm8001_ha,
3326 pm8001_printk("HW_EVENT_PHY_STOP_STATUS "
3327 "status = %x\n", status));
3328 if (status == 0)
3329 phy->phy_state = 0;
3330 break;
3331 case HW_EVENT_SATA_SPINUP_HOLD:
3332 PM8001_MSG_DBG(pm8001_ha,
3333 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3334 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3335 break;
3336 case HW_EVENT_PHY_DOWN:
3337 PM8001_MSG_DBG(pm8001_ha,
3338 pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3339 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3340 phy->phy_attached = 0;
3341 phy->phy_state = 0;
3342 hw_event_phy_down(pm8001_ha, piomb);
3343 break;
3344 case HW_EVENT_PORT_INVALID:
3345 PM8001_MSG_DBG(pm8001_ha,
3346 pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3347 sas_phy_disconnected(sas_phy);
3348 phy->phy_attached = 0;
3349 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3350 break;
3351 /* the broadcast change primitive received, tell the LIBSAS this event
3352 to revalidate the sas domain*/
3353 case HW_EVENT_BROADCAST_CHANGE:
3354 PM8001_MSG_DBG(pm8001_ha,
3355 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3356 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3357 port_id, phy_id, 1, 0);
3358 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3359 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3360 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3361 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3362 break;
3363 case HW_EVENT_PHY_ERROR:
3364 PM8001_MSG_DBG(pm8001_ha,
3365 pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3366 sas_phy_disconnected(&phy->sas_phy);
3367 phy->phy_attached = 0;
3368 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3369 break;
3370 case HW_EVENT_BROADCAST_EXP:
3371 PM8001_MSG_DBG(pm8001_ha,
3372 pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3373 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3374 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3375 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3376 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3377 break;
3378 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3379 PM8001_MSG_DBG(pm8001_ha,
3380 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3381 pm8001_hw_event_ack_req(pm8001_ha, 0,
3382 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3383 sas_phy_disconnected(sas_phy);
3384 phy->phy_attached = 0;
3385 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3386 break;
3387 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3388 PM8001_MSG_DBG(pm8001_ha,
3389 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3390 pm8001_hw_event_ack_req(pm8001_ha, 0,
3391 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3392 port_id, phy_id, 0, 0);
3393 sas_phy_disconnected(sas_phy);
3394 phy->phy_attached = 0;
3395 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3396 break;
3397 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3398 PM8001_MSG_DBG(pm8001_ha,
3399 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3400 pm8001_hw_event_ack_req(pm8001_ha, 0,
3401 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3402 port_id, phy_id, 0, 0);
3403 sas_phy_disconnected(sas_phy);
3404 phy->phy_attached = 0;
3405 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3406 break;
3407 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3408 PM8001_MSG_DBG(pm8001_ha,
3409 pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3410 pm8001_hw_event_ack_req(pm8001_ha, 0,
3411 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3412 port_id, phy_id, 0, 0);
3413 sas_phy_disconnected(sas_phy);
3414 phy->phy_attached = 0;
3415 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3416 break;
3417 case HW_EVENT_MALFUNCTION:
3418 PM8001_MSG_DBG(pm8001_ha,
3419 pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3420 break;
3421 case HW_EVENT_BROADCAST_SES:
3422 PM8001_MSG_DBG(pm8001_ha,
3423 pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3424 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3425 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3426 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3427 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3428 break;
3429 case HW_EVENT_INBOUND_CRC_ERROR:
3430 PM8001_MSG_DBG(pm8001_ha,
3431 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3432 pm8001_hw_event_ack_req(pm8001_ha, 0,
3433 HW_EVENT_INBOUND_CRC_ERROR,
3434 port_id, phy_id, 0, 0);
3435 break;
3436 case HW_EVENT_HARD_RESET_RECEIVED:
3437 PM8001_MSG_DBG(pm8001_ha,
3438 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3439 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3440 break;
3441 case HW_EVENT_ID_FRAME_TIMEOUT:
3442 PM8001_MSG_DBG(pm8001_ha,
3443 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3444 sas_phy_disconnected(sas_phy);
3445 phy->phy_attached = 0;
3446 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3447 break;
3448 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3449 PM8001_MSG_DBG(pm8001_ha,
3450 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3451 pm8001_hw_event_ack_req(pm8001_ha, 0,
3452 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3453 port_id, phy_id, 0, 0);
3454 sas_phy_disconnected(sas_phy);
3455 phy->phy_attached = 0;
3456 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3457 break;
3458 case HW_EVENT_PORT_RESET_TIMER_TMO:
3459 PM8001_MSG_DBG(pm8001_ha,
3460 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3461 sas_phy_disconnected(sas_phy);
3462 phy->phy_attached = 0;
3463 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3464 break;
3465 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3466 PM8001_MSG_DBG(pm8001_ha,
3467 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3468 sas_phy_disconnected(sas_phy);
3469 phy->phy_attached = 0;
3470 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3471 break;
3472 case HW_EVENT_PORT_RECOVER:
3473 PM8001_MSG_DBG(pm8001_ha,
3474 pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3475 break;
3476 case HW_EVENT_PORT_RESET_COMPLETE:
3477 PM8001_MSG_DBG(pm8001_ha,
3478 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3479 break;
3480 case EVENT_BROADCAST_ASYNCH_EVENT:
3481 PM8001_MSG_DBG(pm8001_ha,
3482 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3483 break;
3484 default:
3485 PM8001_MSG_DBG(pm8001_ha,
3486 pm8001_printk("Unknown event type = %x\n", eventType));
3487 break;
3488 }
3489 return 0;
3490 }
3491
3492 /**
3493 * process_one_iomb - process one outbound Queue memory block
3494 * @pm8001_ha: our hba card information
3495 * @piomb: IO message buffer
3496 */
3497 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3498 {
3499 u32 pHeader = (u32)*(u32 *)piomb;
3500 u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
3501
3502 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:"));
3503
3504 switch (opc) {
3505 case OPC_OUB_ECHO:
3506 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3507 break;
3508 case OPC_OUB_HW_EVENT:
3509 PM8001_MSG_DBG(pm8001_ha,
3510 pm8001_printk("OPC_OUB_HW_EVENT\n"));
3511 mpi_hw_event(pm8001_ha, piomb);
3512 break;
3513 case OPC_OUB_SSP_COMP:
3514 PM8001_MSG_DBG(pm8001_ha,
3515 pm8001_printk("OPC_OUB_SSP_COMP\n"));
3516 mpi_ssp_completion(pm8001_ha, piomb);
3517 break;
3518 case OPC_OUB_SMP_COMP:
3519 PM8001_MSG_DBG(pm8001_ha,
3520 pm8001_printk("OPC_OUB_SMP_COMP\n"));
3521 mpi_smp_completion(pm8001_ha, piomb);
3522 break;
3523 case OPC_OUB_LOCAL_PHY_CNTRL:
3524 PM8001_MSG_DBG(pm8001_ha,
3525 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3526 mpi_local_phy_ctl(pm8001_ha, piomb);
3527 break;
3528 case OPC_OUB_DEV_REGIST:
3529 PM8001_MSG_DBG(pm8001_ha,
3530 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3531 mpi_reg_resp(pm8001_ha, piomb);
3532 break;
3533 case OPC_OUB_DEREG_DEV:
3534 PM8001_MSG_DBG(pm8001_ha,
3535 pm8001_printk("unresgister the deviece\n"));
3536 mpi_dereg_resp(pm8001_ha, piomb);
3537 break;
3538 case OPC_OUB_GET_DEV_HANDLE:
3539 PM8001_MSG_DBG(pm8001_ha,
3540 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3541 break;
3542 case OPC_OUB_SATA_COMP:
3543 PM8001_MSG_DBG(pm8001_ha,
3544 pm8001_printk("OPC_OUB_SATA_COMP\n"));
3545 mpi_sata_completion(pm8001_ha, piomb);
3546 break;
3547 case OPC_OUB_SATA_EVENT:
3548 PM8001_MSG_DBG(pm8001_ha,
3549 pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3550 mpi_sata_event(pm8001_ha, piomb);
3551 break;
3552 case OPC_OUB_SSP_EVENT:
3553 PM8001_MSG_DBG(pm8001_ha,
3554 pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3555 mpi_ssp_event(pm8001_ha, piomb);
3556 break;
3557 case OPC_OUB_DEV_HANDLE_ARRIV:
3558 PM8001_MSG_DBG(pm8001_ha,
3559 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3560 /*This is for target*/
3561 break;
3562 case OPC_OUB_SSP_RECV_EVENT:
3563 PM8001_MSG_DBG(pm8001_ha,
3564 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3565 /*This is for target*/
3566 break;
3567 case OPC_OUB_DEV_INFO:
3568 PM8001_MSG_DBG(pm8001_ha,
3569 pm8001_printk("OPC_OUB_DEV_INFO\n"));
3570 break;
3571 case OPC_OUB_FW_FLASH_UPDATE:
3572 PM8001_MSG_DBG(pm8001_ha,
3573 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3574 mpi_fw_flash_update_resp(pm8001_ha, piomb);
3575 break;
3576 case OPC_OUB_GPIO_RESPONSE:
3577 PM8001_MSG_DBG(pm8001_ha,
3578 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3579 break;
3580 case OPC_OUB_GPIO_EVENT:
3581 PM8001_MSG_DBG(pm8001_ha,
3582 pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3583 break;
3584 case OPC_OUB_GENERAL_EVENT:
3585 PM8001_MSG_DBG(pm8001_ha,
3586 pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3587 mpi_general_event(pm8001_ha, piomb);
3588 break;
3589 case OPC_OUB_SSP_ABORT_RSP:
3590 PM8001_MSG_DBG(pm8001_ha,
3591 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3592 mpi_task_abort_resp(pm8001_ha, piomb);
3593 break;
3594 case OPC_OUB_SATA_ABORT_RSP:
3595 PM8001_MSG_DBG(pm8001_ha,
3596 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3597 mpi_task_abort_resp(pm8001_ha, piomb);
3598 break;
3599 case OPC_OUB_SAS_DIAG_MODE_START_END:
3600 PM8001_MSG_DBG(pm8001_ha,
3601 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3602 break;
3603 case OPC_OUB_SAS_DIAG_EXECUTE:
3604 PM8001_MSG_DBG(pm8001_ha,
3605 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3606 break;
3607 case OPC_OUB_GET_TIME_STAMP:
3608 PM8001_MSG_DBG(pm8001_ha,
3609 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3610 break;
3611 case OPC_OUB_SAS_HW_EVENT_ACK:
3612 PM8001_MSG_DBG(pm8001_ha,
3613 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3614 break;
3615 case OPC_OUB_PORT_CONTROL:
3616 PM8001_MSG_DBG(pm8001_ha,
3617 pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3618 break;
3619 case OPC_OUB_SMP_ABORT_RSP:
3620 PM8001_MSG_DBG(pm8001_ha,
3621 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3622 mpi_task_abort_resp(pm8001_ha, piomb);
3623 break;
3624 case OPC_OUB_GET_NVMD_DATA:
3625 PM8001_MSG_DBG(pm8001_ha,
3626 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3627 mpi_get_nvmd_resp(pm8001_ha, piomb);
3628 break;
3629 case OPC_OUB_SET_NVMD_DATA:
3630 PM8001_MSG_DBG(pm8001_ha,
3631 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3632 mpi_set_nvmd_resp(pm8001_ha, piomb);
3633 break;
3634 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3635 PM8001_MSG_DBG(pm8001_ha,
3636 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3637 break;
3638 case OPC_OUB_SET_DEVICE_STATE:
3639 PM8001_MSG_DBG(pm8001_ha,
3640 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3641 mpi_set_dev_state_resp(pm8001_ha, piomb);
3642 break;
3643 case OPC_OUB_GET_DEVICE_STATE:
3644 PM8001_MSG_DBG(pm8001_ha,
3645 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3646 break;
3647 case OPC_OUB_SET_DEV_INFO:
3648 PM8001_MSG_DBG(pm8001_ha,
3649 pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3650 break;
3651 case OPC_OUB_SAS_RE_INITIALIZE:
3652 PM8001_MSG_DBG(pm8001_ha,
3653 pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n"));
3654 break;
3655 default:
3656 PM8001_MSG_DBG(pm8001_ha,
3657 pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n",
3658 opc));
3659 break;
3660 }
3661 }
3662
3663 static int process_oq(struct pm8001_hba_info *pm8001_ha)
3664 {
3665 struct outbound_queue_table *circularQ;
3666 void *pMsg1 = NULL;
3667 u8 bc = 0;
3668 u32 ret = MPI_IO_STATUS_FAIL;
3669
3670 circularQ = &pm8001_ha->outbnd_q_tbl[0];
3671 do {
3672 ret = mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3673 if (MPI_IO_STATUS_SUCCESS == ret) {
3674 /* process the outbound message */
3675 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3676 /* free the message from the outbound circular buffer */
3677 mpi_msg_free_set(pm8001_ha, pMsg1, circularQ, bc);
3678 }
3679 if (MPI_IO_STATUS_BUSY == ret) {
3680 u32 producer_idx;
3681 /* Update the producer index from SPC */
3682 producer_idx = pm8001_read_32(circularQ->pi_virt);
3683 circularQ->producer_index = cpu_to_le32(producer_idx);
3684 if (circularQ->producer_index ==
3685 circularQ->consumer_idx)
3686 /* OQ is empty */
3687 break;
3688 }
3689 } while (1);
3690 return ret;
3691 }
3692
3693 /* PCI_DMA_... to our direction translation. */
3694 static const u8 data_dir_flags[] = {
3695 [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3696 [PCI_DMA_TODEVICE] = DATA_DIR_OUT,/* OUTBOUND */
3697 [PCI_DMA_FROMDEVICE] = DATA_DIR_IN,/* INBOUND */
3698 [PCI_DMA_NONE] = DATA_DIR_NONE,/* NO TRANSFER */
3699 };
3700 static void
3701 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
3702 {
3703 int i;
3704 struct scatterlist *sg;
3705 struct pm8001_prd *buf_prd = prd;
3706
3707 for_each_sg(scatter, sg, nr, i) {
3708 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
3709 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
3710 buf_prd->im_len.e = 0;
3711 buf_prd++;
3712 }
3713 }
3714
3715 static void build_smp_cmd(u32 deviceID, u32 hTag, struct smp_req *psmp_cmd)
3716 {
3717 psmp_cmd->tag = cpu_to_le32(hTag);
3718 psmp_cmd->device_id = cpu_to_le32(deviceID);
3719 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3720 }
3721
3722 /**
3723 * pm8001_chip_smp_req - send a SMP task to FW
3724 * @pm8001_ha: our hba card information.
3725 * @ccb: the ccb information this request used.
3726 */
3727 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3728 struct pm8001_ccb_info *ccb)
3729 {
3730 int elem, rc;
3731 struct sas_task *task = ccb->task;
3732 struct domain_device *dev = task->dev;
3733 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3734 struct scatterlist *sg_req, *sg_resp;
3735 u32 req_len, resp_len;
3736 struct smp_req smp_cmd;
3737 u32 opc;
3738 struct inbound_queue_table *circularQ;
3739
3740 memset(&smp_cmd, 0, sizeof(smp_cmd));
3741 /*
3742 * DMA-map SMP request, response buffers
3743 */
3744 sg_req = &task->smp_task.smp_req;
3745 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3746 if (!elem)
3747 return -ENOMEM;
3748 req_len = sg_dma_len(sg_req);
3749
3750 sg_resp = &task->smp_task.smp_resp;
3751 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
3752 if (!elem) {
3753 rc = -ENOMEM;
3754 goto err_out;
3755 }
3756 resp_len = sg_dma_len(sg_resp);
3757 /* must be in dwords */
3758 if ((req_len & 0x3) || (resp_len & 0x3)) {
3759 rc = -EINVAL;
3760 goto err_out_2;
3761 }
3762
3763 opc = OPC_INB_SMP_REQUEST;
3764 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3765 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
3766 smp_cmd.long_smp_req.long_req_addr =
3767 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
3768 smp_cmd.long_smp_req.long_req_size =
3769 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
3770 smp_cmd.long_smp_req.long_resp_addr =
3771 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
3772 smp_cmd.long_smp_req.long_resp_size =
3773 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
3774 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
3775 mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd);
3776 return 0;
3777
3778 err_out_2:
3779 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
3780 PCI_DMA_FROMDEVICE);
3781 err_out:
3782 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
3783 PCI_DMA_TODEVICE);
3784 return rc;
3785 }
3786
3787 /**
3788 * pm8001_chip_ssp_io_req - send a SSP task to FW
3789 * @pm8001_ha: our hba card information.
3790 * @ccb: the ccb information this request used.
3791 */
3792 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
3793 struct pm8001_ccb_info *ccb)
3794 {
3795 struct sas_task *task = ccb->task;
3796 struct domain_device *dev = task->dev;
3797 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3798 struct ssp_ini_io_start_req ssp_cmd;
3799 u32 tag = ccb->ccb_tag;
3800 int ret;
3801 __le64 phys_addr;
3802 struct inbound_queue_table *circularQ;
3803 u32 opc = OPC_INB_SSPINIIOSTART;
3804 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
3805 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
3806 ssp_cmd.dir_m_tlr =
3807 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
3808 SAS 1.1 compatible TLR*/
3809 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3810 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
3811 ssp_cmd.tag = cpu_to_le32(tag);
3812 if (task->ssp_task.enable_first_burst)
3813 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
3814 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
3815 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
3816 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cdb, 16);
3817 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3818
3819 /* fill in PRD (scatter/gather) table, if any */
3820 if (task->num_scatter > 1) {
3821 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
3822 phys_addr = cpu_to_le64(ccb->ccb_dma_handle +
3823 offsetof(struct pm8001_ccb_info, buf_prd[0]));
3824 ssp_cmd.addr_low = lower_32_bits(phys_addr);
3825 ssp_cmd.addr_high = upper_32_bits(phys_addr);
3826 ssp_cmd.esgl = cpu_to_le32(1<<31);
3827 } else if (task->num_scatter == 1) {
3828 __le64 dma_addr = cpu_to_le64(sg_dma_address(task->scatter));
3829 ssp_cmd.addr_low = lower_32_bits(dma_addr);
3830 ssp_cmd.addr_high = upper_32_bits(dma_addr);
3831 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
3832 ssp_cmd.esgl = 0;
3833 } else if (task->num_scatter == 0) {
3834 ssp_cmd.addr_low = 0;
3835 ssp_cmd.addr_high = 0;
3836 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
3837 ssp_cmd.esgl = 0;
3838 }
3839 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd);
3840 return ret;
3841 }
3842
3843 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
3844 struct pm8001_ccb_info *ccb)
3845 {
3846 struct sas_task *task = ccb->task;
3847 struct domain_device *dev = task->dev;
3848 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
3849 u32 tag = ccb->ccb_tag;
3850 int ret;
3851 struct sata_start_req sata_cmd;
3852 u32 hdr_tag, ncg_tag = 0;
3853 __le64 phys_addr;
3854 u32 ATAP = 0x0;
3855 u32 dir;
3856 struct inbound_queue_table *circularQ;
3857 u32 opc = OPC_INB_SATA_HOST_OPSTART;
3858 memset(&sata_cmd, 0, sizeof(sata_cmd));
3859 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3860 if (task->data_dir == PCI_DMA_NONE) {
3861 ATAP = 0x04; /* no data*/
3862 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
3863 } else if (likely(!task->ata_task.device_control_reg_update)) {
3864 if (task->ata_task.dma_xfer) {
3865 ATAP = 0x06; /* DMA */
3866 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
3867 } else {
3868 ATAP = 0x05; /* PIO*/
3869 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
3870 }
3871 if (task->ata_task.use_ncq &&
3872 dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
3873 ATAP = 0x07; /* FPDMA */
3874 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
3875 }
3876 }
3877 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag))
3878 ncg_tag = hdr_tag;
3879 dir = data_dir_flags[task->data_dir] << 8;
3880 sata_cmd.tag = cpu_to_le32(tag);
3881 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
3882 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3883 sata_cmd.ncqtag_atap_dir_m =
3884 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
3885 sata_cmd.sata_fis = task->ata_task.fis;
3886 if (likely(!task->ata_task.device_control_reg_update))
3887 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
3888 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
3889 /* fill in PRD (scatter/gather) table, if any */
3890 if (task->num_scatter > 1) {
3891 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
3892 phys_addr = cpu_to_le64(ccb->ccb_dma_handle +
3893 offsetof(struct pm8001_ccb_info, buf_prd[0]));
3894 sata_cmd.addr_low = lower_32_bits(phys_addr);
3895 sata_cmd.addr_high = upper_32_bits(phys_addr);
3896 sata_cmd.esgl = cpu_to_le32(1 << 31);
3897 } else if (task->num_scatter == 1) {
3898 __le64 dma_addr = cpu_to_le64(sg_dma_address(task->scatter));
3899 sata_cmd.addr_low = lower_32_bits(dma_addr);
3900 sata_cmd.addr_high = upper_32_bits(dma_addr);
3901 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
3902 sata_cmd.esgl = 0;
3903 } else if (task->num_scatter == 0) {
3904 sata_cmd.addr_low = 0;
3905 sata_cmd.addr_high = 0;
3906 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
3907 sata_cmd.esgl = 0;
3908 }
3909 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd);
3910 return ret;
3911 }
3912
3913 /**
3914 * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
3915 * @pm8001_ha: our hba card information.
3916 * @num: the inbound queue number
3917 * @phy_id: the phy id which we wanted to start up.
3918 */
3919 static int
3920 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
3921 {
3922 struct phy_start_req payload;
3923 struct inbound_queue_table *circularQ;
3924 int ret;
3925 u32 tag = 0x01;
3926 u32 opcode = OPC_INB_PHYSTART;
3927 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3928 memset(&payload, 0, sizeof(payload));
3929 payload.tag = cpu_to_le32(tag);
3930 /*
3931 ** [0:7] PHY Identifier
3932 ** [8:11] link rate 1.5G, 3G, 6G
3933 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
3934 ** [14] 0b disable spin up hold; 1b enable spin up hold
3935 */
3936 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
3937 LINKMODE_AUTO | LINKRATE_15 |
3938 LINKRATE_30 | LINKRATE_60 | phy_id);
3939 payload.sas_identify.dev_type = SAS_END_DEV;
3940 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
3941 memcpy(payload.sas_identify.sas_addr,
3942 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
3943 payload.sas_identify.phy_id = phy_id;
3944 ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload);
3945 return ret;
3946 }
3947
3948 /**
3949 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
3950 * @pm8001_ha: our hba card information.
3951 * @num: the inbound queue number
3952 * @phy_id: the phy id which we wanted to start up.
3953 */
3954 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
3955 u8 phy_id)
3956 {
3957 struct phy_stop_req payload;
3958 struct inbound_queue_table *circularQ;
3959 int ret;
3960 u32 tag = 0x01;
3961 u32 opcode = OPC_INB_PHYSTOP;
3962 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3963 memset(&payload, 0, sizeof(payload));
3964 payload.tag = cpu_to_le32(tag);
3965 payload.phy_id = cpu_to_le32(phy_id);
3966 ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload);
3967 return ret;
3968 }
3969
3970 /**
3971 * see comments on mpi_reg_resp.
3972 */
3973 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
3974 struct pm8001_device *pm8001_dev, u32 flag)
3975 {
3976 struct reg_dev_req payload;
3977 u32 opc;
3978 u32 stp_sspsmp_sata = 0x4;
3979 struct inbound_queue_table *circularQ;
3980 u32 linkrate, phy_id;
3981 int rc, tag = 0xdeadbeef;
3982 struct pm8001_ccb_info *ccb;
3983 u8 retryFlag = 0x1;
3984 u16 firstBurstSize = 0;
3985 u16 ITNT = 2000;
3986 struct domain_device *dev = pm8001_dev->sas_device;
3987 struct domain_device *parent_dev = dev->parent;
3988 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3989
3990 memset(&payload, 0, sizeof(payload));
3991 rc = pm8001_tag_alloc(pm8001_ha, &tag);
3992 if (rc)
3993 return rc;
3994 ccb = &pm8001_ha->ccb_info[tag];
3995 ccb->device = pm8001_dev;
3996 ccb->ccb_tag = tag;
3997 payload.tag = cpu_to_le32(tag);
3998 if (flag == 1)
3999 stp_sspsmp_sata = 0x02; /*direct attached sata */
4000 else {
4001 if (pm8001_dev->dev_type == SATA_DEV)
4002 stp_sspsmp_sata = 0x00; /* stp*/
4003 else if (pm8001_dev->dev_type == SAS_END_DEV ||
4004 pm8001_dev->dev_type == EDGE_DEV ||
4005 pm8001_dev->dev_type == FANOUT_DEV)
4006 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4007 }
4008 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4009 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4010 else
4011 phy_id = pm8001_dev->attached_phy;
4012 opc = OPC_INB_REG_DEV;
4013 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4014 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4015 payload.phyid_portid =
4016 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) |
4017 ((phy_id & 0x0F) << 4));
4018 payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
4019 ((linkrate & 0x0F) * 0x1000000) |
4020 ((stp_sspsmp_sata & 0x03) * 0x10000000));
4021 payload.firstburstsize_ITNexustimeout =
4022 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4023 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4024 SAS_ADDR_SIZE);
4025 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4026 return rc;
4027 }
4028
4029 /**
4030 * see comments on mpi_reg_resp.
4031 */
4032 static int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
4033 u32 device_id)
4034 {
4035 struct dereg_dev_req payload;
4036 u32 opc = OPC_INB_DEREG_DEV_HANDLE;
4037 int ret;
4038 struct inbound_queue_table *circularQ;
4039
4040 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4041 memset(&payload, 0, sizeof(payload));
4042 payload.tag = 1;
4043 payload.device_id = cpu_to_le32(device_id);
4044 PM8001_MSG_DBG(pm8001_ha,
4045 pm8001_printk("unregister device device_id = %d\n", device_id));
4046 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4047 return ret;
4048 }
4049
4050 /**
4051 * pm8001_chip_phy_ctl_req - support the local phy operation
4052 * @pm8001_ha: our hba card information.
4053 * @num: the inbound queue number
4054 * @phy_id: the phy id which we wanted to operate
4055 * @phy_op:
4056 */
4057 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4058 u32 phyId, u32 phy_op)
4059 {
4060 struct local_phy_ctl_req payload;
4061 struct inbound_queue_table *circularQ;
4062 int ret;
4063 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4064 memset(&payload, 0, sizeof(payload));
4065 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4066 payload.tag = 1;
4067 payload.phyop_phyid =
4068 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
4069 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4070 return ret;
4071 }
4072
4073 static u32 pm8001_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4074 {
4075 u32 value;
4076 #ifdef PM8001_USE_MSIX
4077 return 1;
4078 #endif
4079 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4080 if (value)
4081 return 1;
4082 return 0;
4083
4084 }
4085
4086 /**
4087 * pm8001_chip_isr - PM8001 isr handler.
4088 * @pm8001_ha: our hba card information.
4089 * @irq: irq number.
4090 * @stat: stat.
4091 */
4092 static irqreturn_t
4093 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha)
4094 {
4095 unsigned long flags;
4096 spin_lock_irqsave(&pm8001_ha->lock, flags);
4097 pm8001_chip_interrupt_disable(pm8001_ha);
4098 process_oq(pm8001_ha);
4099 pm8001_chip_interrupt_enable(pm8001_ha);
4100 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
4101 return IRQ_HANDLED;
4102 }
4103
4104 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4105 u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
4106 {
4107 struct task_abort_req task_abort;
4108 struct inbound_queue_table *circularQ;
4109 int ret;
4110 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4111 memset(&task_abort, 0, sizeof(task_abort));
4112 if (ABORT_SINGLE == (flag & ABORT_MASK)) {
4113 task_abort.abort_all = 0;
4114 task_abort.device_id = cpu_to_le32(dev_id);
4115 task_abort.tag_to_abort = cpu_to_le32(task_tag);
4116 task_abort.tag = cpu_to_le32(cmd_tag);
4117 } else if (ABORT_ALL == (flag & ABORT_MASK)) {
4118 task_abort.abort_all = cpu_to_le32(1);
4119 task_abort.device_id = cpu_to_le32(dev_id);
4120 task_abort.tag = cpu_to_le32(cmd_tag);
4121 }
4122 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort);
4123 return ret;
4124 }
4125
4126 /**
4127 * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4128 * @task: the task we wanted to aborted.
4129 * @flag: the abort flag.
4130 */
4131 static int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
4132 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
4133 {
4134 u32 opc, device_id;
4135 int rc = TMF_RESP_FUNC_FAILED;
4136 PM8001_EH_DBG(pm8001_ha, pm8001_printk("cmd_tag = %x, abort task tag"
4137 " = %x", cmd_tag, task_tag));
4138 if (pm8001_dev->dev_type == SAS_END_DEV)
4139 opc = OPC_INB_SSP_ABORT;
4140 else if (pm8001_dev->dev_type == SATA_DEV)
4141 opc = OPC_INB_SATA_ABORT;
4142 else
4143 opc = OPC_INB_SMP_ABORT;/* SMP */
4144 device_id = pm8001_dev->device_id;
4145 rc = send_task_abort(pm8001_ha, opc, device_id, flag,
4146 task_tag, cmd_tag);
4147 if (rc != TMF_RESP_FUNC_COMPLETE)
4148 PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc));
4149 return rc;
4150 }
4151
4152 /**
4153 * pm8001_chip_ssp_tm_req - built the task management command.
4154 * @pm8001_ha: our hba card information.
4155 * @ccb: the ccb information.
4156 * @tmf: task management function.
4157 */
4158 static int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
4159 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
4160 {
4161 struct sas_task *task = ccb->task;
4162 struct domain_device *dev = task->dev;
4163 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4164 u32 opc = OPC_INB_SSPINITMSTART;
4165 struct inbound_queue_table *circularQ;
4166 struct ssp_ini_tm_start_req sspTMCmd;
4167 int ret;
4168
4169 memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4170 sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4171 sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
4172 sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
4173 memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4174 sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4175 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4176 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd);
4177 return ret;
4178 }
4179
4180 static int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4181 void *payload)
4182 {
4183 u32 opc = OPC_INB_GET_NVMD_DATA;
4184 u32 nvmd_type;
4185 int rc;
4186 u32 tag;
4187 struct pm8001_ccb_info *ccb;
4188 struct inbound_queue_table *circularQ;
4189 struct get_nvm_data_req nvmd_req;
4190 struct fw_control_ex *fw_control_context;
4191 struct pm8001_ioctl_payload *ioctl_payload = payload;
4192
4193 nvmd_type = ioctl_payload->minor_function;
4194 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4195 if (!fw_control_context)
4196 return -ENOMEM;
4197 fw_control_context->usrAddr = (u8 *)&ioctl_payload->func_specific[0];
4198 fw_control_context->len = ioctl_payload->length;
4199 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4200 memset(&nvmd_req, 0, sizeof(nvmd_req));
4201 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4202 if (rc) {
4203 kfree(fw_control_context);
4204 return rc;
4205 }
4206 ccb = &pm8001_ha->ccb_info[tag];
4207 ccb->ccb_tag = tag;
4208 ccb->fw_control_context = fw_control_context;
4209 nvmd_req.tag = cpu_to_le32(tag);
4210
4211 switch (nvmd_type) {
4212 case TWI_DEVICE: {
4213 u32 twi_addr, twi_page_size;
4214 twi_addr = 0xa8;
4215 twi_page_size = 2;
4216
4217 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4218 twi_page_size << 8 | TWI_DEVICE);
4219 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4220 nvmd_req.resp_addr_hi =
4221 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4222 nvmd_req.resp_addr_lo =
4223 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4224 break;
4225 }
4226 case C_SEEPROM: {
4227 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4228 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4229 nvmd_req.resp_addr_hi =
4230 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4231 nvmd_req.resp_addr_lo =
4232 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4233 break;
4234 }
4235 case VPD_FLASH: {
4236 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4237 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4238 nvmd_req.resp_addr_hi =
4239 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4240 nvmd_req.resp_addr_lo =
4241 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4242 break;
4243 }
4244 case EXPAN_ROM: {
4245 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4246 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4247 nvmd_req.resp_addr_hi =
4248 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4249 nvmd_req.resp_addr_lo =
4250 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4251 break;
4252 }
4253 default:
4254 break;
4255 }
4256 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req);
4257 return rc;
4258 }
4259
4260 static int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4261 void *payload)
4262 {
4263 u32 opc = OPC_INB_SET_NVMD_DATA;
4264 u32 nvmd_type;
4265 int rc;
4266 u32 tag;
4267 struct pm8001_ccb_info *ccb;
4268 struct inbound_queue_table *circularQ;
4269 struct set_nvm_data_req nvmd_req;
4270 struct fw_control_ex *fw_control_context;
4271 struct pm8001_ioctl_payload *ioctl_payload = payload;
4272
4273 nvmd_type = ioctl_payload->minor_function;
4274 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4275 if (!fw_control_context)
4276 return -ENOMEM;
4277 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4278 memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
4279 ioctl_payload->func_specific,
4280 ioctl_payload->length);
4281 memset(&nvmd_req, 0, sizeof(nvmd_req));
4282 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4283 if (rc) {
4284 kfree(fw_control_context);
4285 return rc;
4286 }
4287 ccb = &pm8001_ha->ccb_info[tag];
4288 ccb->fw_control_context = fw_control_context;
4289 ccb->ccb_tag = tag;
4290 nvmd_req.tag = cpu_to_le32(tag);
4291 switch (nvmd_type) {
4292 case TWI_DEVICE: {
4293 u32 twi_addr, twi_page_size;
4294 twi_addr = 0xa8;
4295 twi_page_size = 2;
4296 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4297 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4298 twi_page_size << 8 | TWI_DEVICE);
4299 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4300 nvmd_req.resp_addr_hi =
4301 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4302 nvmd_req.resp_addr_lo =
4303 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4304 break;
4305 }
4306 case C_SEEPROM:
4307 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4308 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4309 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4310 nvmd_req.resp_addr_hi =
4311 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4312 nvmd_req.resp_addr_lo =
4313 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4314 break;
4315 case VPD_FLASH:
4316 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4317 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4318 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4319 nvmd_req.resp_addr_hi =
4320 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4321 nvmd_req.resp_addr_lo =
4322 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4323 break;
4324 case EXPAN_ROM:
4325 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4326 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4327 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4328 nvmd_req.resp_addr_hi =
4329 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4330 nvmd_req.resp_addr_lo =
4331 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4332 break;
4333 default:
4334 break;
4335 }
4336 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req);
4337 return rc;
4338 }
4339
4340 /**
4341 * pm8001_chip_fw_flash_update_build - support the firmware update operation
4342 * @pm8001_ha: our hba card information.
4343 * @fw_flash_updata_info: firmware flash update param
4344 */
4345 static int
4346 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4347 void *fw_flash_updata_info, u32 tag)
4348 {
4349 struct fw_flash_Update_req payload;
4350 struct fw_flash_updata_info *info;
4351 struct inbound_queue_table *circularQ;
4352 int ret;
4353 u32 opc = OPC_INB_FW_FLASH_UPDATE;
4354
4355 memset(&payload, 0, sizeof(struct fw_flash_Update_req));
4356 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4357 info = fw_flash_updata_info;
4358 payload.tag = cpu_to_le32(tag);
4359 payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4360 payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4361 payload.total_image_len = cpu_to_le32(info->total_image_len);
4362 payload.len = info->sgl.im_len.len ;
4363 payload.sgl_addr_lo = lower_32_bits(info->sgl.addr);
4364 payload.sgl_addr_hi = upper_32_bits(info->sgl.addr);
4365 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4366 return ret;
4367 }
4368
4369 static int
4370 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4371 void *payload)
4372 {
4373 struct fw_flash_updata_info flash_update_info;
4374 struct fw_control_info *fw_control;
4375 struct fw_control_ex *fw_control_context;
4376 int rc;
4377 u32 tag;
4378 struct pm8001_ccb_info *ccb;
4379 void *buffer = NULL;
4380 dma_addr_t phys_addr;
4381 u32 phys_addr_hi;
4382 u32 phys_addr_lo;
4383 struct pm8001_ioctl_payload *ioctl_payload = payload;
4384
4385 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4386 if (!fw_control_context)
4387 return -ENOMEM;
4388 fw_control = (struct fw_control_info *)&ioctl_payload->func_specific[0];
4389 if (fw_control->len != 0) {
4390 if (pm8001_mem_alloc(pm8001_ha->pdev,
4391 (void **)&buffer,
4392 &phys_addr,
4393 &phys_addr_hi,
4394 &phys_addr_lo,
4395 fw_control->len, 0) != 0) {
4396 PM8001_FAIL_DBG(pm8001_ha,
4397 pm8001_printk("Mem alloc failure\n"));
4398 kfree(fw_control_context);
4399 return -ENOMEM;
4400 }
4401 }
4402 memcpy(buffer, fw_control->buffer, fw_control->len);
4403 flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
4404 flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
4405 flash_update_info.sgl.im_len.e = 0;
4406 flash_update_info.cur_image_offset = fw_control->offset;
4407 flash_update_info.cur_image_len = fw_control->len;
4408 flash_update_info.total_image_len = fw_control->size;
4409 fw_control_context->fw_control = fw_control;
4410 fw_control_context->virtAddr = buffer;
4411 fw_control_context->len = fw_control->len;
4412 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4413 if (rc) {
4414 kfree(fw_control_context);
4415 return rc;
4416 }
4417 ccb = &pm8001_ha->ccb_info[tag];
4418 ccb->fw_control_context = fw_control_context;
4419 ccb->ccb_tag = tag;
4420 rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
4421 tag);
4422 return rc;
4423 }
4424
4425 static int
4426 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
4427 struct pm8001_device *pm8001_dev, u32 state)
4428 {
4429 struct set_dev_state_req payload;
4430 struct inbound_queue_table *circularQ;
4431 struct pm8001_ccb_info *ccb;
4432 int rc;
4433 u32 tag;
4434 u32 opc = OPC_INB_SET_DEVICE_STATE;
4435 memset(&payload, 0, sizeof(payload));
4436 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4437 if (rc)
4438 return -1;
4439 ccb = &pm8001_ha->ccb_info[tag];
4440 ccb->ccb_tag = tag;
4441 ccb->device = pm8001_dev;
4442 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4443 payload.tag = cpu_to_le32(tag);
4444 payload.device_id = cpu_to_le32(pm8001_dev->device_id);
4445 payload.nds = cpu_to_le32(state);
4446 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4447 return rc;
4448
4449 }
4450
4451 static int
4452 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
4453 {
4454 struct sas_re_initialization_req payload;
4455 struct inbound_queue_table *circularQ;
4456 struct pm8001_ccb_info *ccb;
4457 int rc;
4458 u32 tag;
4459 u32 opc = OPC_INB_SAS_RE_INITIALIZE;
4460 memset(&payload, 0, sizeof(payload));
4461 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4462 if (rc)
4463 return -1;
4464 ccb = &pm8001_ha->ccb_info[tag];
4465 ccb->ccb_tag = tag;
4466 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4467 payload.tag = cpu_to_le32(tag);
4468 payload.SSAHOLT = cpu_to_le32(0xd << 25);
4469 payload.sata_hol_tmo = cpu_to_le32(80);
4470 payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
4471 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4472 return rc;
4473
4474 }
4475
4476 const struct pm8001_dispatch pm8001_8001_dispatch = {
4477 .name = "pmc8001",
4478 .chip_init = pm8001_chip_init,
4479 .chip_soft_rst = pm8001_chip_soft_rst,
4480 .chip_rst = pm8001_hw_chip_rst,
4481 .chip_iounmap = pm8001_chip_iounmap,
4482 .isr = pm8001_chip_isr,
4483 .is_our_interupt = pm8001_chip_is_our_interupt,
4484 .isr_process_oq = process_oq,
4485 .interrupt_enable = pm8001_chip_interrupt_enable,
4486 .interrupt_disable = pm8001_chip_interrupt_disable,
4487 .make_prd = pm8001_chip_make_sg,
4488 .smp_req = pm8001_chip_smp_req,
4489 .ssp_io_req = pm8001_chip_ssp_io_req,
4490 .sata_req = pm8001_chip_sata_req,
4491 .phy_start_req = pm8001_chip_phy_start_req,
4492 .phy_stop_req = pm8001_chip_phy_stop_req,
4493 .reg_dev_req = pm8001_chip_reg_dev_req,
4494 .dereg_dev_req = pm8001_chip_dereg_dev_req,
4495 .phy_ctl_req = pm8001_chip_phy_ctl_req,
4496 .task_abort = pm8001_chip_abort_task,
4497 .ssp_tm_req = pm8001_chip_ssp_tm_req,
4498 .get_nvmd_req = pm8001_chip_get_nvmd_req,
4499 .set_nvmd_req = pm8001_chip_set_nvmd_req,
4500 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
4501 .set_dev_state_req = pm8001_chip_set_dev_state_req,
4502 .sas_re_init_req = pm8001_chip_sas_re_initialization,
4503 };
4504