?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
OMAPDSS: VENC: fix NULL pointer dereference in DSS2 VENC sysfs debug attr on OMAP4
[zen-stable.git] / drivers / tty / serial / msm_serial_hs.c
blob5e85e1e14c44009f80ea2ae8e668b2840efc770d
1 /*
2 * MSM 7k/8k High speed uart driver
3 *
4 * Copyright (c) 2007-2011, Code Aurora Forum. All rights reserved.
5 * Copyright (c) 2008 Google Inc.
6 * Modified: Nick Pelly <npelly@google.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
15 * See the GNU General Public License for more details.
16 *
17 * Has optional support for uart power management independent of linux
18 * suspend/resume:
19 *
20 * RX wakeup.
21 * UART wakeup can be triggered by RX activity (using a wakeup GPIO on the
22 * UART RX pin). This should only be used if there is not a wakeup
23 * GPIO on the UART CTS, and the first RX byte is known (for example, with the
24 * Bluetooth Texas Instruments HCILL protocol), since the first RX byte will
25 * always be lost. RTS will be asserted even while the UART is off in this mode
26 * of operation. See msm_serial_hs_platform_data.rx_wakeup_irq.
27 */
28
29 #include <linux/module.h>
30
31 #include <linux/serial.h>
32 #include <linux/serial_core.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/slab.h>
36 #include <linux/init.h>
37 #include <linux/interrupt.h>
38 #include <linux/irq.h>
39 #include <linux/io.h>
40 #include <linux/ioport.h>
41 #include <linux/kernel.h>
42 #include <linux/timer.h>
43 #include <linux/clk.h>
44 #include <linux/platform_device.h>
45 #include <linux/pm_runtime.h>
46 #include <linux/dma-mapping.h>
47 #include <linux/dmapool.h>
48 #include <linux/wait.h>
49 #include <linux/workqueue.h>
50
51 #include <linux/atomic.h>
52 #include <asm/irq.h>
53 #include <asm/system.h>
54
55 #include <mach/hardware.h>
56 #include <mach/dma.h>
57 #include <linux/platform_data/msm_serial_hs.h>
58
59 /* HSUART Registers */
60 #define UARTDM_MR1_ADDR 0x0
61 #define UARTDM_MR2_ADDR 0x4
62
63 /* Data Mover result codes */
64 #define RSLT_FIFO_CNTR_BMSK (0xE << 28)
65 #define RSLT_VLD BIT(1)
66
67 /* write only register */
68 #define UARTDM_CSR_ADDR 0x8
69 #define UARTDM_CSR_115200 0xFF
70 #define UARTDM_CSR_57600 0xEE
71 #define UARTDM_CSR_38400 0xDD
72 #define UARTDM_CSR_28800 0xCC
73 #define UARTDM_CSR_19200 0xBB
74 #define UARTDM_CSR_14400 0xAA
75 #define UARTDM_CSR_9600 0x99
76 #define UARTDM_CSR_7200 0x88
77 #define UARTDM_CSR_4800 0x77
78 #define UARTDM_CSR_3600 0x66
79 #define UARTDM_CSR_2400 0x55
80 #define UARTDM_CSR_1200 0x44
81 #define UARTDM_CSR_600 0x33
82 #define UARTDM_CSR_300 0x22
83 #define UARTDM_CSR_150 0x11
84 #define UARTDM_CSR_75 0x00
85
86 /* write only register */
87 #define UARTDM_TF_ADDR 0x70
88 #define UARTDM_TF2_ADDR 0x74
89 #define UARTDM_TF3_ADDR 0x78
90 #define UARTDM_TF4_ADDR 0x7C
91
92 /* write only register */
93 #define UARTDM_CR_ADDR 0x10
94 #define UARTDM_IMR_ADDR 0x14
95
96 #define UARTDM_IPR_ADDR 0x18
97 #define UARTDM_TFWR_ADDR 0x1c
98 #define UARTDM_RFWR_ADDR 0x20
99 #define UARTDM_HCR_ADDR 0x24
100 #define UARTDM_DMRX_ADDR 0x34
101 #define UARTDM_IRDA_ADDR 0x38
102 #define UARTDM_DMEN_ADDR 0x3c
103
104 /* UART_DM_NO_CHARS_FOR_TX */
105 #define UARTDM_NCF_TX_ADDR 0x40
106
107 #define UARTDM_BADR_ADDR 0x44
108
109 #define UARTDM_SIM_CFG_ADDR 0x80
110 /* Read Only register */
111 #define UARTDM_SR_ADDR 0x8
112
113 /* Read Only register */
114 #define UARTDM_RF_ADDR 0x70
115 #define UARTDM_RF2_ADDR 0x74
116 #define UARTDM_RF3_ADDR 0x78
117 #define UARTDM_RF4_ADDR 0x7C
118
119 /* Read Only register */
120 #define UARTDM_MISR_ADDR 0x10
121
122 /* Read Only register */
123 #define UARTDM_ISR_ADDR 0x14
124 #define UARTDM_RX_TOTAL_SNAP_ADDR 0x38
125
126 #define UARTDM_RXFS_ADDR 0x50
127
128 /* Register field Mask Mapping */
129 #define UARTDM_SR_PAR_FRAME_BMSK BIT(5)
130 #define UARTDM_SR_OVERRUN_BMSK BIT(4)
131 #define UARTDM_SR_TXEMT_BMSK BIT(3)
132 #define UARTDM_SR_TXRDY_BMSK BIT(2)
133 #define UARTDM_SR_RXRDY_BMSK BIT(0)
134
135 #define UARTDM_CR_TX_DISABLE_BMSK BIT(3)
136 #define UARTDM_CR_RX_DISABLE_BMSK BIT(1)
137 #define UARTDM_CR_TX_EN_BMSK BIT(2)
138 #define UARTDM_CR_RX_EN_BMSK BIT(0)
139
140 /* UARTDM_CR channel_comman bit value (register field is bits 8:4) */
141 #define RESET_RX 0x10
142 #define RESET_TX 0x20
143 #define RESET_ERROR_STATUS 0x30
144 #define RESET_BREAK_INT 0x40
145 #define START_BREAK 0x50
146 #define STOP_BREAK 0x60
147 #define RESET_CTS 0x70
148 #define RESET_STALE_INT 0x80
149 #define RFR_LOW 0xD0
150 #define RFR_HIGH 0xE0
151 #define CR_PROTECTION_EN 0x100
152 #define STALE_EVENT_ENABLE 0x500
153 #define STALE_EVENT_DISABLE 0x600
154 #define FORCE_STALE_EVENT 0x400
155 #define CLEAR_TX_READY 0x300
156 #define RESET_TX_ERROR 0x800
157 #define RESET_TX_DONE 0x810
158
159 #define UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK 0xffffff00
160 #define UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK 0x3f
161 #define UARTDM_MR1_CTS_CTL_BMSK 0x40
162 #define UARTDM_MR1_RX_RDY_CTL_BMSK 0x80
163
164 #define UARTDM_MR2_ERROR_MODE_BMSK 0x40
165 #define UARTDM_MR2_BITS_PER_CHAR_BMSK 0x30
166
167 /* bits per character configuration */
168 #define FIVE_BPC (0 << 4)
169 #define SIX_BPC (1 << 4)
170 #define SEVEN_BPC (2 << 4)
171 #define EIGHT_BPC (3 << 4)
172
173 #define UARTDM_MR2_STOP_BIT_LEN_BMSK 0xc
174 #define STOP_BIT_ONE (1 << 2)
175 #define STOP_BIT_TWO (3 << 2)
176
177 #define UARTDM_MR2_PARITY_MODE_BMSK 0x3
178
179 /* Parity configuration */
180 #define NO_PARITY 0x0
181 #define EVEN_PARITY 0x1
182 #define ODD_PARITY 0x2
183 #define SPACE_PARITY 0x3
184
185 #define UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK 0xffffff80
186 #define UARTDM_IPR_STALE_LSB_BMSK 0x1f
187
188 /* These can be used for both ISR and IMR register */
189 #define UARTDM_ISR_TX_READY_BMSK BIT(7)
190 #define UARTDM_ISR_CURRENT_CTS_BMSK BIT(6)
191 #define UARTDM_ISR_DELTA_CTS_BMSK BIT(5)
192 #define UARTDM_ISR_RXLEV_BMSK BIT(4)
193 #define UARTDM_ISR_RXSTALE_BMSK BIT(3)
194 #define UARTDM_ISR_RXBREAK_BMSK BIT(2)
195 #define UARTDM_ISR_RXHUNT_BMSK BIT(1)
196 #define UARTDM_ISR_TXLEV_BMSK BIT(0)
197
198 /* Field definitions for UART_DM_DMEN*/
199 #define UARTDM_TX_DM_EN_BMSK 0x1
200 #define UARTDM_RX_DM_EN_BMSK 0x2
201
202 #define UART_FIFOSIZE 64
203 #define UARTCLK 7372800
204
205 /* Rx DMA request states */
206 enum flush_reason {
207 FLUSH_NONE,
208 FLUSH_DATA_READY,
209 FLUSH_DATA_INVALID, /* values after this indicate invalid data */
210 FLUSH_IGNORE = FLUSH_DATA_INVALID,
211 FLUSH_STOP,
212 FLUSH_SHUTDOWN,
213 };
214
215 /* UART clock states */
216 enum msm_hs_clk_states_e {
217 MSM_HS_CLK_PORT_OFF, /* port not in use */
218 MSM_HS_CLK_OFF, /* clock disabled */
219 MSM_HS_CLK_REQUEST_OFF, /* disable after TX and RX flushed */
220 MSM_HS_CLK_ON, /* clock enabled */
221 };
222
223 /* Track the forced RXSTALE flush during clock off sequence.
224 * These states are only valid during MSM_HS_CLK_REQUEST_OFF */
225 enum msm_hs_clk_req_off_state_e {
226 CLK_REQ_OFF_START,
227 CLK_REQ_OFF_RXSTALE_ISSUED,
228 CLK_REQ_OFF_FLUSH_ISSUED,
229 CLK_REQ_OFF_RXSTALE_FLUSHED,
230 };
231
232 /**
233 * struct msm_hs_tx
234 * @tx_ready_int_en: ok to dma more tx?
235 * @dma_in_flight: tx dma in progress
236 * @xfer: top level DMA command pointer structure
237 * @command_ptr: third level command struct pointer
238 * @command_ptr_ptr: second level command list struct pointer
239 * @mapped_cmd_ptr: DMA view of third level command struct
240 * @mapped_cmd_ptr_ptr: DMA view of second level command list struct
241 * @tx_count: number of bytes to transfer in DMA transfer
242 * @dma_base: DMA view of UART xmit buffer
243 *
244 * This structure describes a single Tx DMA transaction. MSM DMA
245 * commands have two levels of indirection. The top level command
246 * ptr points to a list of command ptr which in turn points to a
247 * single DMA 'command'. In our case each Tx transaction consists
248 * of a single second level pointer pointing to a 'box type' command.
249 */
250 struct msm_hs_tx {
251 unsigned int tx_ready_int_en;
252 unsigned int dma_in_flight;
253 struct msm_dmov_cmd xfer;
254 dmov_box *command_ptr;
255 u32 *command_ptr_ptr;
256 dma_addr_t mapped_cmd_ptr;
257 dma_addr_t mapped_cmd_ptr_ptr;
258 int tx_count;
259 dma_addr_t dma_base;
260 };
261
262 /**
263 * struct msm_hs_rx
264 * @flush: Rx DMA request state
265 * @xfer: top level DMA command pointer structure
266 * @cmdptr_dmaaddr: DMA view of second level command structure
267 * @command_ptr: third level DMA command pointer structure
268 * @command_ptr_ptr: second level DMA command list pointer
269 * @mapped_cmd_ptr: DMA view of the third level command structure
270 * @wait: wait for DMA completion before shutdown
271 * @buffer: destination buffer for RX DMA
272 * @rbuffer: DMA view of buffer
273 * @pool: dma pool out of which coherent rx buffer is allocated
274 * @tty_work: private work-queue for tty flip buffer push task
275 *
276 * This structure describes a single Rx DMA transaction. Rx DMA
277 * transactions use box mode DMA commands.
278 */
279 struct msm_hs_rx {
280 enum flush_reason flush;
281 struct msm_dmov_cmd xfer;
282 dma_addr_t cmdptr_dmaaddr;
283 dmov_box *command_ptr;
284 u32 *command_ptr_ptr;
285 dma_addr_t mapped_cmd_ptr;
286 wait_queue_head_t wait;
287 dma_addr_t rbuffer;
288 unsigned char *buffer;
289 struct dma_pool *pool;
290 struct work_struct tty_work;
291 };
292
293 /**
294 * struct msm_hs_rx_wakeup
295 * @irq: IRQ line to be configured as interrupt source on Rx activity
296 * @ignore: boolean value. 1 = ignore the wakeup interrupt
297 * @rx_to_inject: extra character to be inserted to Rx tty on wakeup
298 * @inject_rx: 1 = insert rx_to_inject. 0 = do not insert extra character
299 *
300 * This is an optional structure required for UART Rx GPIO IRQ based
301 * wakeup from low power state. UART wakeup can be triggered by RX activity
302 * (using a wakeup GPIO on the UART RX pin). This should only be used if
303 * there is not a wakeup GPIO on the UART CTS, and the first RX byte is
304 * known (eg., with the Bluetooth Texas Instruments HCILL protocol),
305 * since the first RX byte will always be lost. RTS will be asserted even
306 * while the UART is clocked off in this mode of operation.
307 */
308 struct msm_hs_rx_wakeup {
309 int irq; /* < 0 indicates low power wakeup disabled */
310 unsigned char ignore;
311 unsigned char inject_rx;
312 char rx_to_inject;
313 };
314
315 /**
316 * struct msm_hs_port
317 * @uport: embedded uart port structure
318 * @imr_reg: shadow value of UARTDM_IMR
319 * @clk: uart input clock handle
320 * @tx: Tx transaction related data structure
321 * @rx: Rx transaction related data structure
322 * @dma_tx_channel: Tx DMA command channel
323 * @dma_rx_channel Rx DMA command channel
324 * @dma_tx_crci: Tx channel rate control interface number
325 * @dma_rx_crci: Rx channel rate control interface number
326 * @clk_off_timer: Timer to poll DMA event completion before clock off
327 * @clk_off_delay: clk_off_timer poll interval
328 * @clk_state: overall clock state
329 * @clk_req_off_state: post flush clock states
330 * @rx_wakeup: optional rx_wakeup feature related data
331 * @exit_lpm_cb: optional callback to exit low power mode
332 *
333 * Low level serial port structure.
334 */
335 struct msm_hs_port {
336 struct uart_port uport;
337 unsigned long imr_reg;
338 struct clk *clk;
339 struct msm_hs_tx tx;
340 struct msm_hs_rx rx;
341
342 int dma_tx_channel;
343 int dma_rx_channel;
344 int dma_tx_crci;
345 int dma_rx_crci;
346
347 struct hrtimer clk_off_timer;
348 ktime_t clk_off_delay;
349 enum msm_hs_clk_states_e clk_state;
350 enum msm_hs_clk_req_off_state_e clk_req_off_state;
351
352 struct msm_hs_rx_wakeup rx_wakeup;
353 void (*exit_lpm_cb)(struct uart_port *);
354 };
355
356 #define MSM_UARTDM_BURST_SIZE 16 /* DM burst size (in bytes) */
357 #define UARTDM_TX_BUF_SIZE UART_XMIT_SIZE
358 #define UARTDM_RX_BUF_SIZE 512
359
360 #define UARTDM_NR 2
361
362 static struct msm_hs_port q_uart_port[UARTDM_NR];
363 static struct platform_driver msm_serial_hs_platform_driver;
364 static struct uart_driver msm_hs_driver;
365 static struct uart_ops msm_hs_ops;
366 static struct workqueue_struct *msm_hs_workqueue;
367
368 #define UARTDM_TO_MSM(uart_port) \
369 container_of((uart_port), struct msm_hs_port, uport)
370
371 static unsigned int use_low_power_rx_wakeup(struct msm_hs_port
372 *msm_uport)
373 {
374 return (msm_uport->rx_wakeup.irq >= 0);
375 }
376
377 static unsigned int msm_hs_read(struct uart_port *uport,
378 unsigned int offset)
379 {
380 return ioread32(uport->membase + offset);
381 }
382
383 static void msm_hs_write(struct uart_port *uport, unsigned int offset,
384 unsigned int value)
385 {
386 iowrite32(value, uport->membase + offset);
387 }
388
389 static void msm_hs_release_port(struct uart_port *port)
390 {
391 iounmap(port->membase);
392 }
393
394 static int msm_hs_request_port(struct uart_port *port)
395 {
396 port->membase = ioremap(port->mapbase, PAGE_SIZE);
397 if (unlikely(!port->membase))
398 return -ENOMEM;
399
400 /* configure the CR Protection to Enable */
401 msm_hs_write(port, UARTDM_CR_ADDR, CR_PROTECTION_EN);
402 return 0;
403 }
404
405 static int __devexit msm_hs_remove(struct platform_device *pdev)
406 {
407
408 struct msm_hs_port *msm_uport;
409 struct device *dev;
410
411 if (pdev->id < 0 || pdev->id >= UARTDM_NR) {
412 printk(KERN_ERR "Invalid plaform device ID = %d\n", pdev->id);
413 return -EINVAL;
414 }
415
416 msm_uport = &q_uart_port[pdev->id];
417 dev = msm_uport->uport.dev;
418
419 dma_unmap_single(dev, msm_uport->rx.mapped_cmd_ptr, sizeof(dmov_box),
420 DMA_TO_DEVICE);
421 dma_pool_free(msm_uport->rx.pool, msm_uport->rx.buffer,
422 msm_uport->rx.rbuffer);
423 dma_pool_destroy(msm_uport->rx.pool);
424
425 dma_unmap_single(dev, msm_uport->rx.cmdptr_dmaaddr, sizeof(u32),
426 DMA_TO_DEVICE);
427 dma_unmap_single(dev, msm_uport->tx.mapped_cmd_ptr_ptr, sizeof(u32),
428 DMA_TO_DEVICE);
429 dma_unmap_single(dev, msm_uport->tx.mapped_cmd_ptr, sizeof(dmov_box),
430 DMA_TO_DEVICE);
431
432 uart_remove_one_port(&msm_hs_driver, &msm_uport->uport);
433 clk_put(msm_uport->clk);
434
435 /* Free the tx resources */
436 kfree(msm_uport->tx.command_ptr);
437 kfree(msm_uport->tx.command_ptr_ptr);
438
439 /* Free the rx resources */
440 kfree(msm_uport->rx.command_ptr);
441 kfree(msm_uport->rx.command_ptr_ptr);
442
443 iounmap(msm_uport->uport.membase);
444
445 return 0;
446 }
447
448 static int msm_hs_init_clk_locked(struct uart_port *uport)
449 {
450 int ret;
451 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
452
453 ret = clk_enable(msm_uport->clk);
454 if (ret) {
455 printk(KERN_ERR "Error could not turn on UART clk\n");
456 return ret;
457 }
458
459 /* Set up the MREG/NREG/DREG/MNDREG */
460 ret = clk_set_rate(msm_uport->clk, uport->uartclk);
461 if (ret) {
462 printk(KERN_WARNING "Error setting clock rate on UART\n");
463 clk_disable(msm_uport->clk);
464 return ret;
465 }
466
467 msm_uport->clk_state = MSM_HS_CLK_ON;
468 return 0;
469 }
470
471 /* Enable and Disable clocks (Used for power management) */
472 static void msm_hs_pm(struct uart_port *uport, unsigned int state,
473 unsigned int oldstate)
474 {
475 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
476
477 if (use_low_power_rx_wakeup(msm_uport) ||
478 msm_uport->exit_lpm_cb)
479 return; /* ignore linux PM states,
480 use msm_hs_request_clock API */
481
482 switch (state) {
483 case 0:
484 clk_enable(msm_uport->clk);
485 break;
486 case 3:
487 clk_disable(msm_uport->clk);
488 break;
489 default:
490 dev_err(uport->dev, "msm_serial: Unknown PM state %d\n",
491 state);
492 }
493 }
494
495 /*
496 * programs the UARTDM_CSR register with correct bit rates
497 *
498 * Interrupts should be disabled before we are called, as
499 * we modify Set Baud rate
500 * Set receive stale interrupt level, dependent on Bit Rate
501 * Goal is to have around 8 ms before indicate stale.
502 * roundup (((Bit Rate * .008) / 10) + 1
503 */
504 static void msm_hs_set_bps_locked(struct uart_port *uport,
505 unsigned int bps)
506 {
507 unsigned long rxstale;
508 unsigned long data;
509 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
510
511 switch (bps) {
512 case 300:
513 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_75);
514 rxstale = 1;
515 break;
516 case 600:
517 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_150);
518 rxstale = 1;
519 break;
520 case 1200:
521 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_300);
522 rxstale = 1;
523 break;
524 case 2400:
525 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_600);
526 rxstale = 1;
527 break;
528 case 4800:
529 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_1200);
530 rxstale = 1;
531 break;
532 case 9600:
533 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_2400);
534 rxstale = 2;
535 break;
536 case 14400:
537 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_3600);
538 rxstale = 3;
539 break;
540 case 19200:
541 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_4800);
542 rxstale = 4;
543 break;
544 case 28800:
545 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_7200);
546 rxstale = 6;
547 break;
548 case 38400:
549 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_9600);
550 rxstale = 8;
551 break;
552 case 57600:
553 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_14400);
554 rxstale = 16;
555 break;
556 case 76800:
557 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_19200);
558 rxstale = 16;
559 break;
560 case 115200:
561 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_28800);
562 rxstale = 31;
563 break;
564 case 230400:
565 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_57600);
566 rxstale = 31;
567 break;
568 case 460800:
569 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_115200);
570 rxstale = 31;
571 break;
572 case 4000000:
573 case 3686400:
574 case 3200000:
575 case 3500000:
576 case 3000000:
577 case 2500000:
578 case 1500000:
579 case 1152000:
580 case 1000000:
581 case 921600:
582 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_115200);
583 rxstale = 31;
584 break;
585 default:
586 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_2400);
587 /* default to 9600 */
588 bps = 9600;
589 rxstale = 2;
590 break;
591 }
592 if (bps > 460800)
593 uport->uartclk = bps * 16;
594 else
595 uport->uartclk = UARTCLK;
596
597 if (clk_set_rate(msm_uport->clk, uport->uartclk)) {
598 printk(KERN_WARNING "Error setting clock rate on UART\n");
599 return;
600 }
601
602 data = rxstale & UARTDM_IPR_STALE_LSB_BMSK;
603 data |= UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK & (rxstale << 2);
604
605 msm_hs_write(uport, UARTDM_IPR_ADDR, data);
606 }
607
608 /*
609 * termios : new ktermios
610 * oldtermios: old ktermios previous setting
611 *
612 * Configure the serial port
613 */
614 static void msm_hs_set_termios(struct uart_port *uport,
615 struct ktermios *termios,
616 struct ktermios *oldtermios)
617 {
618 unsigned int bps;
619 unsigned long data;
620 unsigned long flags;
621 unsigned int c_cflag = termios->c_cflag;
622 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
623
624 spin_lock_irqsave(&uport->lock, flags);
625 clk_enable(msm_uport->clk);
626
627 /* 300 is the minimum baud support by the driver */
628 bps = uart_get_baud_rate(uport, termios, oldtermios, 200, 4000000);
629
630 /* Temporary remapping 200 BAUD to 3.2 mbps */
631 if (bps == 200)
632 bps = 3200000;
633
634 msm_hs_set_bps_locked(uport, bps);
635
636 data = msm_hs_read(uport, UARTDM_MR2_ADDR);
637 data &= ~UARTDM_MR2_PARITY_MODE_BMSK;
638 /* set parity */
639 if (PARENB == (c_cflag & PARENB)) {
640 if (PARODD == (c_cflag & PARODD))
641 data |= ODD_PARITY;
642 else if (CMSPAR == (c_cflag & CMSPAR))
643 data |= SPACE_PARITY;
644 else
645 data |= EVEN_PARITY;
646 }
647
648 /* Set bits per char */
649 data &= ~UARTDM_MR2_BITS_PER_CHAR_BMSK;
650
651 switch (c_cflag & CSIZE) {
652 case CS5:
653 data |= FIVE_BPC;
654 break;
655 case CS6:
656 data |= SIX_BPC;
657 break;
658 case CS7:
659 data |= SEVEN_BPC;
660 break;
661 default:
662 data |= EIGHT_BPC;
663 break;
664 }
665 /* stop bits */
666 if (c_cflag & CSTOPB) {
667 data |= STOP_BIT_TWO;
668 } else {
669 /* otherwise 1 stop bit */
670 data |= STOP_BIT_ONE;
671 }
672 data |= UARTDM_MR2_ERROR_MODE_BMSK;
673 /* write parity/bits per char/stop bit configuration */
674 msm_hs_write(uport, UARTDM_MR2_ADDR, data);
675
676 /* Configure HW flow control */
677 data = msm_hs_read(uport, UARTDM_MR1_ADDR);
678
679 data &= ~(UARTDM_MR1_CTS_CTL_BMSK | UARTDM_MR1_RX_RDY_CTL_BMSK);
680
681 if (c_cflag & CRTSCTS) {
682 data |= UARTDM_MR1_CTS_CTL_BMSK;
683 data |= UARTDM_MR1_RX_RDY_CTL_BMSK;
684 }
685
686 msm_hs_write(uport, UARTDM_MR1_ADDR, data);
687
688 uport->ignore_status_mask = termios->c_iflag & INPCK;
689 uport->ignore_status_mask |= termios->c_iflag & IGNPAR;
690 uport->read_status_mask = (termios->c_cflag & CREAD);
691
692 msm_hs_write(uport, UARTDM_IMR_ADDR, 0);
693
694 /* Set Transmit software time out */
695 uart_update_timeout(uport, c_cflag, bps);
696
697 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_RX);
698 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_TX);
699
700 if (msm_uport->rx.flush == FLUSH_NONE) {
701 msm_uport->rx.flush = FLUSH_IGNORE;
702 msm_dmov_stop_cmd(msm_uport->dma_rx_channel, NULL, 1);
703 }
704
705 msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
706
707 clk_disable(msm_uport->clk);
708 spin_unlock_irqrestore(&uport->lock, flags);
709 }
710
711 /*
712 * Standard API, Transmitter
713 * Any character in the transmit shift register is sent
714 */
715 static unsigned int msm_hs_tx_empty(struct uart_port *uport)
716 {
717 unsigned int data;
718 unsigned int ret = 0;
719 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
720
721 clk_enable(msm_uport->clk);
722
723 data = msm_hs_read(uport, UARTDM_SR_ADDR);
724 if (data & UARTDM_SR_TXEMT_BMSK)
725 ret = TIOCSER_TEMT;
726
727 clk_disable(msm_uport->clk);
728
729 return ret;
730 }
731
732 /*
733 * Standard API, Stop transmitter.
734 * Any character in the transmit shift register is sent as
735 * well as the current data mover transfer .
736 */
737 static void msm_hs_stop_tx_locked(struct uart_port *uport)
738 {
739 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
740
741 msm_uport->tx.tx_ready_int_en = 0;
742 }
743
744 /*
745 * Standard API, Stop receiver as soon as possible.
746 *
747 * Function immediately terminates the operation of the
748 * channel receiver and any incoming characters are lost. None
749 * of the receiver status bits are affected by this command and
750 * characters that are already in the receive FIFO there.
751 */
752 static void msm_hs_stop_rx_locked(struct uart_port *uport)
753 {
754 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
755 unsigned int data;
756
757 clk_enable(msm_uport->clk);
758
759 /* disable dlink */
760 data = msm_hs_read(uport, UARTDM_DMEN_ADDR);
761 data &= ~UARTDM_RX_DM_EN_BMSK;
762 msm_hs_write(uport, UARTDM_DMEN_ADDR, data);
763
764 /* Disable the receiver */
765 if (msm_uport->rx.flush == FLUSH_NONE)
766 msm_dmov_stop_cmd(msm_uport->dma_rx_channel, NULL, 1);
767
768 if (msm_uport->rx.flush != FLUSH_SHUTDOWN)
769 msm_uport->rx.flush = FLUSH_STOP;
770
771 clk_disable(msm_uport->clk);
772 }
773
774 /* Transmit the next chunk of data */
775 static void msm_hs_submit_tx_locked(struct uart_port *uport)
776 {
777 int left;
778 int tx_count;
779 dma_addr_t src_addr;
780 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
781 struct msm_hs_tx *tx = &msm_uport->tx;
782 struct circ_buf *tx_buf = &msm_uport->uport.state->xmit;
783
784 if (uart_circ_empty(tx_buf) || uport->state->port.tty->stopped) {
785 msm_hs_stop_tx_locked(uport);
786 return;
787 }
788
789 tx->dma_in_flight = 1;
790
791 tx_count = uart_circ_chars_pending(tx_buf);
792
793 if (UARTDM_TX_BUF_SIZE < tx_count)
794 tx_count = UARTDM_TX_BUF_SIZE;
795
796 left = UART_XMIT_SIZE - tx_buf->tail;
797
798 if (tx_count > left)
799 tx_count = left;
800
801 src_addr = tx->dma_base + tx_buf->tail;
802 dma_sync_single_for_device(uport->dev, src_addr, tx_count,
803 DMA_TO_DEVICE);
804
805 tx->command_ptr->num_rows = (((tx_count + 15) >> 4) << 16) |
806 ((tx_count + 15) >> 4);
807 tx->command_ptr->src_row_addr = src_addr;
808
809 dma_sync_single_for_device(uport->dev, tx->mapped_cmd_ptr,
810 sizeof(dmov_box), DMA_TO_DEVICE);
811
812 *tx->command_ptr_ptr = CMD_PTR_LP | DMOV_CMD_ADDR(tx->mapped_cmd_ptr);
813
814 dma_sync_single_for_device(uport->dev, tx->mapped_cmd_ptr_ptr,
815 sizeof(u32), DMA_TO_DEVICE);
816
817 /* Save tx_count to use in Callback */
818 tx->tx_count = tx_count;
819 msm_hs_write(uport, UARTDM_NCF_TX_ADDR, tx_count);
820
821 /* Disable the tx_ready interrupt */
822 msm_uport->imr_reg &= ~UARTDM_ISR_TX_READY_BMSK;
823 msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
824 msm_dmov_enqueue_cmd(msm_uport->dma_tx_channel, &tx->xfer);
825 }
826
827 /* Start to receive the next chunk of data */
828 static void msm_hs_start_rx_locked(struct uart_port *uport)
829 {
830 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
831
832 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_STALE_INT);
833 msm_hs_write(uport, UARTDM_DMRX_ADDR, UARTDM_RX_BUF_SIZE);
834 msm_hs_write(uport, UARTDM_CR_ADDR, STALE_EVENT_ENABLE);
835 msm_uport->imr_reg |= UARTDM_ISR_RXLEV_BMSK;
836 msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
837
838 msm_uport->rx.flush = FLUSH_NONE;
839 msm_dmov_enqueue_cmd(msm_uport->dma_rx_channel, &msm_uport->rx.xfer);
840
841 /* might have finished RX and be ready to clock off */
842 hrtimer_start(&msm_uport->clk_off_timer, msm_uport->clk_off_delay,
843 HRTIMER_MODE_REL);
844 }
845
846 /* Enable the transmitter Interrupt */
847 static void msm_hs_start_tx_locked(struct uart_port *uport)
848 {
849 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
850
851 clk_enable(msm_uport->clk);
852
853 if (msm_uport->exit_lpm_cb)
854 msm_uport->exit_lpm_cb(uport);
855
856 if (msm_uport->tx.tx_ready_int_en == 0) {
857 msm_uport->tx.tx_ready_int_en = 1;
858 msm_hs_submit_tx_locked(uport);
859 }
860
861 clk_disable(msm_uport->clk);
862 }
863
864 /*
865 * This routine is called when we are done with a DMA transfer
866 *
867 * This routine is registered with Data mover when we set
868 * up a Data Mover transfer. It is called from Data mover ISR
869 * when the DMA transfer is done.
870 */
871 static void msm_hs_dmov_tx_callback(struct msm_dmov_cmd *cmd_ptr,
872 unsigned int result,
873 struct msm_dmov_errdata *err)
874 {
875 unsigned long flags;
876 struct msm_hs_port *msm_uport;
877
878 /* DMA did not finish properly */
879 WARN_ON((((result & RSLT_FIFO_CNTR_BMSK) >> 28) == 1) &&
880 !(result & RSLT_VLD));
881
882 msm_uport = container_of(cmd_ptr, struct msm_hs_port, tx.xfer);
883
884 spin_lock_irqsave(&msm_uport->uport.lock, flags);
885 clk_enable(msm_uport->clk);
886
887 msm_uport->imr_reg |= UARTDM_ISR_TX_READY_BMSK;
888 msm_hs_write(&msm_uport->uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
889
890 clk_disable(msm_uport->clk);
891 spin_unlock_irqrestore(&msm_uport->uport.lock, flags);
892 }
893
894 /*
895 * This routine is called when we are done with a DMA transfer or the
896 * a flush has been sent to the data mover driver.
897 *
898 * This routine is registered with Data mover when we set up a Data Mover
899 * transfer. It is called from Data mover ISR when the DMA transfer is done.
900 */
901 static void msm_hs_dmov_rx_callback(struct msm_dmov_cmd *cmd_ptr,
902 unsigned int result,
903 struct msm_dmov_errdata *err)
904 {
905 int retval;
906 int rx_count;
907 unsigned long status;
908 unsigned int error_f = 0;
909 unsigned long flags;
910 unsigned int flush;
911 struct tty_struct *tty;
912 struct uart_port *uport;
913 struct msm_hs_port *msm_uport;
914
915 msm_uport = container_of(cmd_ptr, struct msm_hs_port, rx.xfer);
916 uport = &msm_uport->uport;
917
918 spin_lock_irqsave(&uport->lock, flags);
919 clk_enable(msm_uport->clk);
920
921 tty = uport->state->port.tty;
922
923 msm_hs_write(uport, UARTDM_CR_ADDR, STALE_EVENT_DISABLE);
924
925 status = msm_hs_read(uport, UARTDM_SR_ADDR);
926
927 /* overflow is not connect to data in a FIFO */
928 if (unlikely((status & UARTDM_SR_OVERRUN_BMSK) &&
929 (uport->read_status_mask & CREAD))) {
930 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
931 uport->icount.buf_overrun++;
932 error_f = 1;
933 }
934
935 if (!(uport->ignore_status_mask & INPCK))
936 status = status & ~(UARTDM_SR_PAR_FRAME_BMSK);
937
938 if (unlikely(status & UARTDM_SR_PAR_FRAME_BMSK)) {
939 /* Can not tell difference between parity & frame error */
940 uport->icount.parity++;
941 error_f = 1;
942 if (uport->ignore_status_mask & IGNPAR)
943 tty_insert_flip_char(tty, 0, TTY_PARITY);
944 }
945
946 if (error_f)
947 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_ERROR_STATUS);
948
949 if (msm_uport->clk_req_off_state == CLK_REQ_OFF_FLUSH_ISSUED)
950 msm_uport->clk_req_off_state = CLK_REQ_OFF_RXSTALE_FLUSHED;
951
952 flush = msm_uport->rx.flush;
953 if (flush == FLUSH_IGNORE)
954 msm_hs_start_rx_locked(uport);
955 if (flush == FLUSH_STOP)
956 msm_uport->rx.flush = FLUSH_SHUTDOWN;
957 if (flush >= FLUSH_DATA_INVALID)
958 goto out;
959
960 rx_count = msm_hs_read(uport, UARTDM_RX_TOTAL_SNAP_ADDR);
961
962 if (0 != (uport->read_status_mask & CREAD)) {
963 retval = tty_insert_flip_string(tty, msm_uport->rx.buffer,
964 rx_count);
965 BUG_ON(retval != rx_count);
966 }
967
968 msm_hs_start_rx_locked(uport);
969
970 out:
971 clk_disable(msm_uport->clk);
972
973 spin_unlock_irqrestore(&uport->lock, flags);
974
975 if (flush < FLUSH_DATA_INVALID)
976 queue_work(msm_hs_workqueue, &msm_uport->rx.tty_work);
977 }
978
979 static void msm_hs_tty_flip_buffer_work(struct work_struct *work)
980 {
981 struct msm_hs_port *msm_uport =
982 container_of(work, struct msm_hs_port, rx.tty_work);
983 struct tty_struct *tty = msm_uport->uport.state->port.tty;
984
985 tty_flip_buffer_push(tty);
986 }
987
988 /*
989 * Standard API, Current states of modem control inputs
990 *
991 * Since CTS can be handled entirely by HARDWARE we always
992 * indicate clear to send and count on the TX FIFO to block when
993 * it fills up.
994 *
995 * - TIOCM_DCD
996 * - TIOCM_CTS
997 * - TIOCM_DSR
998 * - TIOCM_RI
999 * (Unsupported) DCD and DSR will return them high. RI will return low.
1000 */
1001 static unsigned int msm_hs_get_mctrl_locked(struct uart_port *uport)
1002 {
1003 return TIOCM_DSR | TIOCM_CAR | TIOCM_CTS;
1004 }
1005
1006 /*
1007 * True enables UART auto RFR, which indicates we are ready for data if the RX
1008 * buffer is not full. False disables auto RFR, and deasserts RFR to indicate
1009 * we are not ready for data. Must be called with UART clock on.
1010 */
1011 static void set_rfr_locked(struct uart_port *uport, int auto_rfr)
1012 {
1013 unsigned int data;
1014
1015 data = msm_hs_read(uport, UARTDM_MR1_ADDR);
1016
1017 if (auto_rfr) {
1018 /* enable auto ready-for-receiving */
1019 data |= UARTDM_MR1_RX_RDY_CTL_BMSK;
1020 msm_hs_write(uport, UARTDM_MR1_ADDR, data);
1021 } else {
1022 /* disable auto ready-for-receiving */
1023 data &= ~UARTDM_MR1_RX_RDY_CTL_BMSK;
1024 msm_hs_write(uport, UARTDM_MR1_ADDR, data);
1025 /* RFR is active low, set high */
1026 msm_hs_write(uport, UARTDM_CR_ADDR, RFR_HIGH);
1027 }
1028 }
1029
1030 /*
1031 * Standard API, used to set or clear RFR
1032 */
1033 static void msm_hs_set_mctrl_locked(struct uart_port *uport,
1034 unsigned int mctrl)
1035 {
1036 unsigned int auto_rfr;
1037 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1038
1039 clk_enable(msm_uport->clk);
1040
1041 auto_rfr = TIOCM_RTS & mctrl ? 1 : 0;
1042 set_rfr_locked(uport, auto_rfr);
1043
1044 clk_disable(msm_uport->clk);
1045 }
1046
1047 /* Standard API, Enable modem status (CTS) interrupt */
1048 static void msm_hs_enable_ms_locked(struct uart_port *uport)
1049 {
1050 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1051
1052 clk_enable(msm_uport->clk);
1053
1054 /* Enable DELTA_CTS Interrupt */
1055 msm_uport->imr_reg |= UARTDM_ISR_DELTA_CTS_BMSK;
1056 msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
1057
1058 clk_disable(msm_uport->clk);
1059
1060 }
1061
1062 /*
1063 * Standard API, Break Signal
1064 *
1065 * Control the transmission of a break signal. ctl eq 0 => break
1066 * signal terminate ctl ne 0 => start break signal
1067 */
1068 static void msm_hs_break_ctl(struct uart_port *uport, int ctl)
1069 {
1070 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1071
1072 clk_enable(msm_uport->clk);
1073 msm_hs_write(uport, UARTDM_CR_ADDR, ctl ? START_BREAK : STOP_BREAK);
1074 clk_disable(msm_uport->clk);
1075 }
1076
1077 static void msm_hs_config_port(struct uart_port *uport, int cfg_flags)
1078 {
1079 unsigned long flags;
1080
1081 spin_lock_irqsave(&uport->lock, flags);
1082 if (cfg_flags & UART_CONFIG_TYPE) {
1083 uport->type = PORT_MSM;
1084 msm_hs_request_port(uport);
1085 }
1086 spin_unlock_irqrestore(&uport->lock, flags);
1087 }
1088
1089 /* Handle CTS changes (Called from interrupt handler) */
1090 static void msm_hs_handle_delta_cts_locked(struct uart_port *uport)
1091 {
1092 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1093
1094 clk_enable(msm_uport->clk);
1095
1096 /* clear interrupt */
1097 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_CTS);
1098 uport->icount.cts++;
1099
1100 clk_disable(msm_uport->clk);
1101
1102 /* clear the IOCTL TIOCMIWAIT if called */
1103 wake_up_interruptible(&uport->state->port.delta_msr_wait);
1104 }
1105
1106 /* check if the TX path is flushed, and if so clock off
1107 * returns 0 did not clock off, need to retry (still sending final byte)
1108 * -1 did not clock off, do not retry
1109 * 1 if we clocked off
1110 */
1111 static int msm_hs_check_clock_off_locked(struct uart_port *uport)
1112 {
1113 unsigned long sr_status;
1114 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1115 struct circ_buf *tx_buf = &uport->state->xmit;
1116
1117 /* Cancel if tx tty buffer is not empty, dma is in flight,
1118 * or tx fifo is not empty, or rx fifo is not empty */
1119 if (msm_uport->clk_state != MSM_HS_CLK_REQUEST_OFF ||
1120 !uart_circ_empty(tx_buf) || msm_uport->tx.dma_in_flight ||
1121 (msm_uport->imr_reg & UARTDM_ISR_TXLEV_BMSK) ||
1122 !(msm_uport->imr_reg & UARTDM_ISR_RXLEV_BMSK)) {
1123 return -1;
1124 }
1125
1126 /* Make sure the uart is finished with the last byte */
1127 sr_status = msm_hs_read(uport, UARTDM_SR_ADDR);
1128 if (!(sr_status & UARTDM_SR_TXEMT_BMSK))
1129 return 0; /* retry */
1130
1131 /* Make sure forced RXSTALE flush complete */
1132 switch (msm_uport->clk_req_off_state) {
1133 case CLK_REQ_OFF_START:
1134 msm_uport->clk_req_off_state = CLK_REQ_OFF_RXSTALE_ISSUED;
1135 msm_hs_write(uport, UARTDM_CR_ADDR, FORCE_STALE_EVENT);
1136 return 0; /* RXSTALE flush not complete - retry */
1137 case CLK_REQ_OFF_RXSTALE_ISSUED:
1138 case CLK_REQ_OFF_FLUSH_ISSUED:
1139 return 0; /* RXSTALE flush not complete - retry */
1140 case CLK_REQ_OFF_RXSTALE_FLUSHED:
1141 break; /* continue */
1142 }
1143
1144 if (msm_uport->rx.flush != FLUSH_SHUTDOWN) {
1145 if (msm_uport->rx.flush == FLUSH_NONE)
1146 msm_hs_stop_rx_locked(uport);
1147 return 0; /* come back later to really clock off */
1148 }
1149
1150 /* we really want to clock off */
1151 clk_disable(msm_uport->clk);
1152 msm_uport->clk_state = MSM_HS_CLK_OFF;
1153
1154 if (use_low_power_rx_wakeup(msm_uport)) {
1155 msm_uport->rx_wakeup.ignore = 1;
1156 enable_irq(msm_uport->rx_wakeup.irq);
1157 }
1158 return 1;
1159 }
1160
1161 static enum hrtimer_restart msm_hs_clk_off_retry(struct hrtimer *timer)
1162 {
1163 unsigned long flags;
1164 int ret = HRTIMER_NORESTART;
1165 struct msm_hs_port *msm_uport = container_of(timer, struct msm_hs_port,
1166 clk_off_timer);
1167 struct uart_port *uport = &msm_uport->uport;
1168
1169 spin_lock_irqsave(&uport->lock, flags);
1170
1171 if (!msm_hs_check_clock_off_locked(uport)) {
1172 hrtimer_forward_now(timer, msm_uport->clk_off_delay);
1173 ret = HRTIMER_RESTART;
1174 }
1175
1176 spin_unlock_irqrestore(&uport->lock, flags);
1177
1178 return ret;
1179 }
1180
1181 static irqreturn_t msm_hs_isr(int irq, void *dev)
1182 {
1183 unsigned long flags;
1184 unsigned long isr_status;
1185 struct msm_hs_port *msm_uport = dev;
1186 struct uart_port *uport = &msm_uport->uport;
1187 struct circ_buf *tx_buf = &uport->state->xmit;
1188 struct msm_hs_tx *tx = &msm_uport->tx;
1189 struct msm_hs_rx *rx = &msm_uport->rx;
1190
1191 spin_lock_irqsave(&uport->lock, flags);
1192
1193 isr_status = msm_hs_read(uport, UARTDM_MISR_ADDR);
1194
1195 /* Uart RX starting */
1196 if (isr_status & UARTDM_ISR_RXLEV_BMSK) {
1197 msm_uport->imr_reg &= ~UARTDM_ISR_RXLEV_BMSK;
1198 msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
1199 }
1200 /* Stale rx interrupt */
1201 if (isr_status & UARTDM_ISR_RXSTALE_BMSK) {
1202 msm_hs_write(uport, UARTDM_CR_ADDR, STALE_EVENT_DISABLE);
1203 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_STALE_INT);
1204
1205 if (msm_uport->clk_req_off_state == CLK_REQ_OFF_RXSTALE_ISSUED)
1206 msm_uport->clk_req_off_state =
1207 CLK_REQ_OFF_FLUSH_ISSUED;
1208 if (rx->flush == FLUSH_NONE) {
1209 rx->flush = FLUSH_DATA_READY;
1210 msm_dmov_stop_cmd(msm_uport->dma_rx_channel, NULL, 1);
1211 }
1212 }
1213 /* tx ready interrupt */
1214 if (isr_status & UARTDM_ISR_TX_READY_BMSK) {
1215 /* Clear TX Ready */
1216 msm_hs_write(uport, UARTDM_CR_ADDR, CLEAR_TX_READY);
1217
1218 if (msm_uport->clk_state == MSM_HS_CLK_REQUEST_OFF) {
1219 msm_uport->imr_reg |= UARTDM_ISR_TXLEV_BMSK;
1220 msm_hs_write(uport, UARTDM_IMR_ADDR,
1221 msm_uport->imr_reg);
1222 }
1223
1224 /* Complete DMA TX transactions and submit new transactions */
1225 tx_buf->tail = (tx_buf->tail + tx->tx_count) & ~UART_XMIT_SIZE;
1226
1227 tx->dma_in_flight = 0;
1228
1229 uport->icount.tx += tx->tx_count;
1230 if (tx->tx_ready_int_en)
1231 msm_hs_submit_tx_locked(uport);
1232
1233 if (uart_circ_chars_pending(tx_buf) < WAKEUP_CHARS)
1234 uart_write_wakeup(uport);
1235 }
1236 if (isr_status & UARTDM_ISR_TXLEV_BMSK) {
1237 /* TX FIFO is empty */
1238 msm_uport->imr_reg &= ~UARTDM_ISR_TXLEV_BMSK;
1239 msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
1240 if (!msm_hs_check_clock_off_locked(uport))
1241 hrtimer_start(&msm_uport->clk_off_timer,
1242 msm_uport->clk_off_delay,
1243 HRTIMER_MODE_REL);
1244 }
1245
1246 /* Change in CTS interrupt */
1247 if (isr_status & UARTDM_ISR_DELTA_CTS_BMSK)
1248 msm_hs_handle_delta_cts_locked(uport);
1249
1250 spin_unlock_irqrestore(&uport->lock, flags);
1251
1252 return IRQ_HANDLED;
1253 }
1254
1255 void msm_hs_request_clock_off_locked(struct uart_port *uport)
1256 {
1257 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1258
1259 if (msm_uport->clk_state == MSM_HS_CLK_ON) {
1260 msm_uport->clk_state = MSM_HS_CLK_REQUEST_OFF;
1261 msm_uport->clk_req_off_state = CLK_REQ_OFF_START;
1262 if (!use_low_power_rx_wakeup(msm_uport))
1263 set_rfr_locked(uport, 0);
1264 msm_uport->imr_reg |= UARTDM_ISR_TXLEV_BMSK;
1265 msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
1266 }
1267 }
1268
1269 /**
1270 * msm_hs_request_clock_off - request to (i.e. asynchronously) turn off uart
1271 * clock once pending TX is flushed and Rx DMA command is terminated.
1272 * @uport: uart_port structure for the device instance.
1273 *
1274 * This functions puts the device into a partially active low power mode. It
1275 * waits to complete all pending tx transactions, flushes ongoing Rx DMA
1276 * command and terminates UART side Rx transaction, puts UART HW in non DMA
1277 * mode and then clocks off the device. A client calls this when no UART
1278 * data is expected. msm_request_clock_on() must be called before any further
1279 * UART can be sent or received.
1280 */
1281 void msm_hs_request_clock_off(struct uart_port *uport)
1282 {
1283 unsigned long flags;
1284
1285 spin_lock_irqsave(&uport->lock, flags);
1286 msm_hs_request_clock_off_locked(uport);
1287 spin_unlock_irqrestore(&uport->lock, flags);
1288 }
1289
1290 void msm_hs_request_clock_on_locked(struct uart_port *uport)
1291 {
1292 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1293 unsigned int data;
1294
1295 switch (msm_uport->clk_state) {
1296 case MSM_HS_CLK_OFF:
1297 clk_enable(msm_uport->clk);
1298 disable_irq_nosync(msm_uport->rx_wakeup.irq);
1299 /* fall-through */
1300 case MSM_HS_CLK_REQUEST_OFF:
1301 if (msm_uport->rx.flush == FLUSH_STOP ||
1302 msm_uport->rx.flush == FLUSH_SHUTDOWN) {
1303 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_RX);
1304 data = msm_hs_read(uport, UARTDM_DMEN_ADDR);
1305 data |= UARTDM_RX_DM_EN_BMSK;
1306 msm_hs_write(uport, UARTDM_DMEN_ADDR, data);
1307 }
1308 hrtimer_try_to_cancel(&msm_uport->clk_off_timer);
1309 if (msm_uport->rx.flush == FLUSH_SHUTDOWN)
1310 msm_hs_start_rx_locked(uport);
1311 if (!use_low_power_rx_wakeup(msm_uport))
1312 set_rfr_locked(uport, 1);
1313 if (msm_uport->rx.flush == FLUSH_STOP)
1314 msm_uport->rx.flush = FLUSH_IGNORE;
1315 msm_uport->clk_state = MSM_HS_CLK_ON;
1316 break;
1317 case MSM_HS_CLK_ON:
1318 break;
1319 case MSM_HS_CLK_PORT_OFF:
1320 break;
1321 }
1322 }
1323
1324 /**
1325 * msm_hs_request_clock_on - Switch the device from partially active low
1326 * power mode to fully active (i.e. clock on) mode.
1327 * @uport: uart_port structure for the device.
1328 *
1329 * This function switches on the input clock, puts UART HW into DMA mode
1330 * and enqueues an Rx DMA command if the device was in partially active
1331 * mode. It has no effect if called with the device in inactive state.
1332 */
1333 void msm_hs_request_clock_on(struct uart_port *uport)
1334 {
1335 unsigned long flags;
1336
1337 spin_lock_irqsave(&uport->lock, flags);
1338 msm_hs_request_clock_on_locked(uport);
1339 spin_unlock_irqrestore(&uport->lock, flags);
1340 }
1341
1342 static irqreturn_t msm_hs_rx_wakeup_isr(int irq, void *dev)
1343 {
1344 unsigned int wakeup = 0;
1345 unsigned long flags;
1346 struct msm_hs_port *msm_uport = dev;
1347 struct uart_port *uport = &msm_uport->uport;
1348 struct tty_struct *tty = NULL;
1349
1350 spin_lock_irqsave(&uport->lock, flags);
1351 if (msm_uport->clk_state == MSM_HS_CLK_OFF) {
1352 /* ignore the first irq - it is a pending irq that occurred
1353 * before enable_irq() */
1354 if (msm_uport->rx_wakeup.ignore)
1355 msm_uport->rx_wakeup.ignore = 0;
1356 else
1357 wakeup = 1;
1358 }
1359
1360 if (wakeup) {
1361 /* the uart was clocked off during an rx, wake up and
1362 * optionally inject char into tty rx */
1363 msm_hs_request_clock_on_locked(uport);
1364 if (msm_uport->rx_wakeup.inject_rx) {
1365 tty = uport->state->port.tty;
1366 tty_insert_flip_char(tty,
1367 msm_uport->rx_wakeup.rx_to_inject,
1368 TTY_NORMAL);
1369 queue_work(msm_hs_workqueue, &msm_uport->rx.tty_work);
1370 }
1371 }
1372
1373 spin_unlock_irqrestore(&uport->lock, flags);
1374
1375 return IRQ_HANDLED;
1376 }
1377
1378 static const char *msm_hs_type(struct uart_port *port)
1379 {
1380 return (port->type == PORT_MSM) ? "MSM_HS_UART" : NULL;
1381 }
1382
1383 /* Called when port is opened */
1384 static int msm_hs_startup(struct uart_port *uport)
1385 {
1386 int ret;
1387 int rfr_level;
1388 unsigned long flags;
1389 unsigned int data;
1390 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1391 struct circ_buf *tx_buf = &uport->state->xmit;
1392 struct msm_hs_tx *tx = &msm_uport->tx;
1393 struct msm_hs_rx *rx = &msm_uport->rx;
1394
1395 rfr_level = uport->fifosize;
1396 if (rfr_level > 16)
1397 rfr_level -= 16;
1398
1399 tx->dma_base = dma_map_single(uport->dev, tx_buf->buf, UART_XMIT_SIZE,
1400 DMA_TO_DEVICE);
1401
1402 /* do not let tty layer execute RX in global workqueue, use a
1403 * dedicated workqueue managed by this driver */
1404 uport->state->port.tty->low_latency = 1;
1405
1406 /* turn on uart clk */
1407 ret = msm_hs_init_clk_locked(uport);
1408 if (unlikely(ret)) {
1409 printk(KERN_ERR "Turning uartclk failed!\n");
1410 goto err_msm_hs_init_clk;
1411 }
1412
1413 /* Set auto RFR Level */
1414 data = msm_hs_read(uport, UARTDM_MR1_ADDR);
1415 data &= ~UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK;
1416 data &= ~UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK;
1417 data |= (UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK & (rfr_level << 2));
1418 data |= (UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK & rfr_level);
1419 msm_hs_write(uport, UARTDM_MR1_ADDR, data);
1420
1421 /* Make sure RXSTALE count is non-zero */
1422 data = msm_hs_read(uport, UARTDM_IPR_ADDR);
1423 if (!data) {
1424 data |= 0x1f & UARTDM_IPR_STALE_LSB_BMSK;
1425 msm_hs_write(uport, UARTDM_IPR_ADDR, data);
1426 }
1427
1428 /* Enable Data Mover Mode */
1429 data = UARTDM_TX_DM_EN_BMSK | UARTDM_RX_DM_EN_BMSK;
1430 msm_hs_write(uport, UARTDM_DMEN_ADDR, data);
1431
1432 /* Reset TX */
1433 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_TX);
1434 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_RX);
1435 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_ERROR_STATUS);
1436 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_BREAK_INT);
1437 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_STALE_INT);
1438 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_CTS);
1439 msm_hs_write(uport, UARTDM_CR_ADDR, RFR_LOW);
1440 /* Turn on Uart Receiver */
1441 msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_RX_EN_BMSK);
1442
1443 /* Turn on Uart Transmitter */
1444 msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_TX_EN_BMSK);
1445
1446 /* Initialize the tx */
1447 tx->tx_ready_int_en = 0;
1448 tx->dma_in_flight = 0;
1449
1450 tx->xfer.complete_func = msm_hs_dmov_tx_callback;
1451 tx->xfer.execute_func = NULL;
1452
1453 tx->command_ptr->cmd = CMD_LC |
1454 CMD_DST_CRCI(msm_uport->dma_tx_crci) | CMD_MODE_BOX;
1455
1456 tx->command_ptr->src_dst_len = (MSM_UARTDM_BURST_SIZE << 16)
1457 | (MSM_UARTDM_BURST_SIZE);
1458
1459 tx->command_ptr->row_offset = (MSM_UARTDM_BURST_SIZE << 16);
1460
1461 tx->command_ptr->dst_row_addr =
1462 msm_uport->uport.mapbase + UARTDM_TF_ADDR;
1463
1464
1465 /* Turn on Uart Receive */
1466 rx->xfer.complete_func = msm_hs_dmov_rx_callback;
1467 rx->xfer.execute_func = NULL;
1468
1469 rx->command_ptr->cmd = CMD_LC |
1470 CMD_SRC_CRCI(msm_uport->dma_rx_crci) | CMD_MODE_BOX;
1471
1472 rx->command_ptr->src_dst_len = (MSM_UARTDM_BURST_SIZE << 16)
1473 | (MSM_UARTDM_BURST_SIZE);
1474 rx->command_ptr->row_offset = MSM_UARTDM_BURST_SIZE;
1475 rx->command_ptr->src_row_addr = uport->mapbase + UARTDM_RF_ADDR;
1476
1477
1478 msm_uport->imr_reg |= UARTDM_ISR_RXSTALE_BMSK;
1479 /* Enable reading the current CTS, no harm even if CTS is ignored */
1480 msm_uport->imr_reg |= UARTDM_ISR_CURRENT_CTS_BMSK;
1481
1482 msm_hs_write(uport, UARTDM_TFWR_ADDR, 0); /* TXLEV on empty TX fifo */
1483
1484
1485 ret = request_irq(uport->irq, msm_hs_isr, IRQF_TRIGGER_HIGH,
1486 "msm_hs_uart", msm_uport);
1487 if (unlikely(ret)) {
1488 printk(KERN_ERR "Request msm_hs_uart IRQ failed!\n");
1489 goto err_request_irq;
1490 }
1491 if (use_low_power_rx_wakeup(msm_uport)) {
1492 ret = request_irq(msm_uport->rx_wakeup.irq,
1493 msm_hs_rx_wakeup_isr,
1494 IRQF_TRIGGER_FALLING,
1495 "msm_hs_rx_wakeup", msm_uport);
1496 if (unlikely(ret)) {
1497 printk(KERN_ERR "Request msm_hs_rx_wakeup IRQ failed!\n");
1498 free_irq(uport->irq, msm_uport);
1499 goto err_request_irq;
1500 }
1501 disable_irq(msm_uport->rx_wakeup.irq);
1502 }
1503
1504 spin_lock_irqsave(&uport->lock, flags);
1505
1506 msm_hs_write(uport, UARTDM_RFWR_ADDR, 0);
1507 msm_hs_start_rx_locked(uport);
1508
1509 spin_unlock_irqrestore(&uport->lock, flags);
1510 ret = pm_runtime_set_active(uport->dev);
1511 if (ret)
1512 dev_err(uport->dev, "set active error:%d\n", ret);
1513 pm_runtime_enable(uport->dev);
1514
1515 return 0;
1516
1517 err_request_irq:
1518 err_msm_hs_init_clk:
1519 dma_unmap_single(uport->dev, tx->dma_base,
1520 UART_XMIT_SIZE, DMA_TO_DEVICE);
1521 return ret;
1522 }
1523
1524 /* Initialize tx and rx data structures */
1525 static int __devinit uartdm_init_port(struct uart_port *uport)
1526 {
1527 int ret = 0;
1528 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1529 struct msm_hs_tx *tx = &msm_uport->tx;
1530 struct msm_hs_rx *rx = &msm_uport->rx;
1531
1532 /* Allocate the command pointer. Needs to be 64 bit aligned */
1533 tx->command_ptr = kmalloc(sizeof(dmov_box), GFP_KERNEL | __GFP_DMA);
1534 if (!tx->command_ptr)
1535 return -ENOMEM;
1536
1537 tx->command_ptr_ptr = kmalloc(sizeof(u32), GFP_KERNEL | __GFP_DMA);
1538 if (!tx->command_ptr_ptr) {
1539 ret = -ENOMEM;
1540 goto err_tx_command_ptr_ptr;
1541 }
1542
1543 tx->mapped_cmd_ptr = dma_map_single(uport->dev, tx->command_ptr,
1544 sizeof(dmov_box), DMA_TO_DEVICE);
1545 tx->mapped_cmd_ptr_ptr = dma_map_single(uport->dev,
1546 tx->command_ptr_ptr,
1547 sizeof(u32), DMA_TO_DEVICE);
1548 tx->xfer.cmdptr = DMOV_CMD_ADDR(tx->mapped_cmd_ptr_ptr);
1549
1550 init_waitqueue_head(&rx->wait);
1551
1552 rx->pool = dma_pool_create("rx_buffer_pool", uport->dev,
1553 UARTDM_RX_BUF_SIZE, 16, 0);
1554 if (!rx->pool) {
1555 pr_err("%s(): cannot allocate rx_buffer_pool", __func__);
1556 ret = -ENOMEM;
1557 goto err_dma_pool_create;
1558 }
1559
1560 rx->buffer = dma_pool_alloc(rx->pool, GFP_KERNEL, &rx->rbuffer);
1561 if (!rx->buffer) {
1562 pr_err("%s(): cannot allocate rx->buffer", __func__);
1563 ret = -ENOMEM;
1564 goto err_dma_pool_alloc;
1565 }
1566
1567 /* Allocate the command pointer. Needs to be 64 bit aligned */
1568 rx->command_ptr = kmalloc(sizeof(dmov_box), GFP_KERNEL | __GFP_DMA);
1569 if (!rx->command_ptr) {
1570 pr_err("%s(): cannot allocate rx->command_ptr", __func__);
1571 ret = -ENOMEM;
1572 goto err_rx_command_ptr;
1573 }
1574
1575 rx->command_ptr_ptr = kmalloc(sizeof(u32), GFP_KERNEL | __GFP_DMA);
1576 if (!rx->command_ptr_ptr) {
1577 pr_err("%s(): cannot allocate rx->command_ptr_ptr", __func__);
1578 ret = -ENOMEM;
1579 goto err_rx_command_ptr_ptr;
1580 }
1581
1582 rx->command_ptr->num_rows = ((UARTDM_RX_BUF_SIZE >> 4) << 16) |
1583 (UARTDM_RX_BUF_SIZE >> 4);
1584
1585 rx->command_ptr->dst_row_addr = rx->rbuffer;
1586
1587 rx->mapped_cmd_ptr = dma_map_single(uport->dev, rx->command_ptr,
1588 sizeof(dmov_box), DMA_TO_DEVICE);
1589
1590 *rx->command_ptr_ptr = CMD_PTR_LP | DMOV_CMD_ADDR(rx->mapped_cmd_ptr);
1591
1592 rx->cmdptr_dmaaddr = dma_map_single(uport->dev, rx->command_ptr_ptr,
1593 sizeof(u32), DMA_TO_DEVICE);
1594 rx->xfer.cmdptr = DMOV_CMD_ADDR(rx->cmdptr_dmaaddr);
1595
1596 INIT_WORK(&rx->tty_work, msm_hs_tty_flip_buffer_work);
1597
1598 return ret;
1599
1600 err_rx_command_ptr_ptr:
1601 kfree(rx->command_ptr);
1602 err_rx_command_ptr:
1603 dma_pool_free(msm_uport->rx.pool, msm_uport->rx.buffer,
1604 msm_uport->rx.rbuffer);
1605 err_dma_pool_alloc:
1606 dma_pool_destroy(msm_uport->rx.pool);
1607 err_dma_pool_create:
1608 dma_unmap_single(uport->dev, msm_uport->tx.mapped_cmd_ptr_ptr,
1609 sizeof(u32), DMA_TO_DEVICE);
1610 dma_unmap_single(uport->dev, msm_uport->tx.mapped_cmd_ptr,
1611 sizeof(dmov_box), DMA_TO_DEVICE);
1612 kfree(msm_uport->tx.command_ptr_ptr);
1613 err_tx_command_ptr_ptr:
1614 kfree(msm_uport->tx.command_ptr);
1615 return ret;
1616 }
1617
1618 static int __devinit msm_hs_probe(struct platform_device *pdev)
1619 {
1620 int ret;
1621 struct uart_port *uport;
1622 struct msm_hs_port *msm_uport;
1623 struct resource *resource;
1624 const struct msm_serial_hs_platform_data *pdata =
1625 pdev->dev.platform_data;
1626
1627 if (pdev->id < 0 || pdev->id >= UARTDM_NR) {
1628 printk(KERN_ERR "Invalid plaform device ID = %d\n", pdev->id);
1629 return -EINVAL;
1630 }
1631
1632 msm_uport = &q_uart_port[pdev->id];
1633 uport = &msm_uport->uport;
1634
1635 uport->dev = &pdev->dev;
1636
1637 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1638 if (unlikely(!resource))
1639 return -ENXIO;
1640
1641 uport->mapbase = resource->start;
1642 uport->irq = platform_get_irq(pdev, 0);
1643 if (unlikely(uport->irq < 0))
1644 return -ENXIO;
1645
1646 if (unlikely(irq_set_irq_wake(uport->irq, 1)))
1647 return -ENXIO;
1648
1649 if (pdata == NULL || pdata->rx_wakeup_irq < 0)
1650 msm_uport->rx_wakeup.irq = -1;
1651 else {
1652 msm_uport->rx_wakeup.irq = pdata->rx_wakeup_irq;
1653 msm_uport->rx_wakeup.ignore = 1;
1654 msm_uport->rx_wakeup.inject_rx = pdata->inject_rx_on_wakeup;
1655 msm_uport->rx_wakeup.rx_to_inject = pdata->rx_to_inject;
1656
1657 if (unlikely(msm_uport->rx_wakeup.irq < 0))
1658 return -ENXIO;
1659
1660 if (unlikely(irq_set_irq_wake(msm_uport->rx_wakeup.irq, 1)))
1661 return -ENXIO;
1662 }
1663
1664 if (pdata == NULL)
1665 msm_uport->exit_lpm_cb = NULL;
1666 else
1667 msm_uport->exit_lpm_cb = pdata->exit_lpm_cb;
1668
1669 resource = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1670 "uartdm_channels");
1671 if (unlikely(!resource))
1672 return -ENXIO;
1673
1674 msm_uport->dma_tx_channel = resource->start;
1675 msm_uport->dma_rx_channel = resource->end;
1676
1677 resource = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1678 "uartdm_crci");
1679 if (unlikely(!resource))
1680 return -ENXIO;
1681
1682 msm_uport->dma_tx_crci = resource->start;
1683 msm_uport->dma_rx_crci = resource->end;
1684
1685 uport->iotype = UPIO_MEM;
1686 uport->fifosize = UART_FIFOSIZE;
1687 uport->ops = &msm_hs_ops;
1688 uport->flags = UPF_BOOT_AUTOCONF;
1689 uport->uartclk = UARTCLK;
1690 msm_uport->imr_reg = 0x0;
1691 msm_uport->clk = clk_get(&pdev->dev, "uartdm_clk");
1692 if (IS_ERR(msm_uport->clk))
1693 return PTR_ERR(msm_uport->clk);
1694
1695 ret = uartdm_init_port(uport);
1696 if (unlikely(ret))
1697 return ret;
1698
1699 msm_uport->clk_state = MSM_HS_CLK_PORT_OFF;
1700 hrtimer_init(&msm_uport->clk_off_timer, CLOCK_MONOTONIC,
1701 HRTIMER_MODE_REL);
1702 msm_uport->clk_off_timer.function = msm_hs_clk_off_retry;
1703 msm_uport->clk_off_delay = ktime_set(0, 1000000); /* 1ms */
1704
1705 uport->line = pdev->id;
1706 return uart_add_one_port(&msm_hs_driver, uport);
1707 }
1708
1709 static int __init msm_serial_hs_init(void)
1710 {
1711 int ret, i;
1712
1713 /* Init all UARTS as non-configured */
1714 for (i = 0; i < UARTDM_NR; i++)
1715 q_uart_port[i].uport.type = PORT_UNKNOWN;
1716
1717 msm_hs_workqueue = create_singlethread_workqueue("msm_serial_hs");
1718 if (unlikely(!msm_hs_workqueue))
1719 return -ENOMEM;
1720
1721 ret = uart_register_driver(&msm_hs_driver);
1722 if (unlikely(ret)) {
1723 printk(KERN_ERR "%s failed to load\n", __func__);
1724 goto err_uart_register_driver;
1725 }
1726
1727 ret = platform_driver_register(&msm_serial_hs_platform_driver);
1728 if (ret) {
1729 printk(KERN_ERR "%s failed to load\n", __func__);
1730 goto err_platform_driver_register;
1731 }
1732
1733 return ret;
1734
1735 err_platform_driver_register:
1736 uart_unregister_driver(&msm_hs_driver);
1737 err_uart_register_driver:
1738 destroy_workqueue(msm_hs_workqueue);
1739 return ret;
1740 }
1741 module_init(msm_serial_hs_init);
1742
1743 /*
1744 * Called by the upper layer when port is closed.
1745 * - Disables the port
1746 * - Unhook the ISR
1747 */
1748 static void msm_hs_shutdown(struct uart_port *uport)
1749 {
1750 unsigned long flags;
1751 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1752
1753 BUG_ON(msm_uport->rx.flush < FLUSH_STOP);
1754
1755 spin_lock_irqsave(&uport->lock, flags);
1756 clk_enable(msm_uport->clk);
1757
1758 /* Disable the transmitter */
1759 msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_TX_DISABLE_BMSK);
1760 /* Disable the receiver */
1761 msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_RX_DISABLE_BMSK);
1762
1763 pm_runtime_disable(uport->dev);
1764 pm_runtime_set_suspended(uport->dev);
1765
1766 /* Free the interrupt */
1767 free_irq(uport->irq, msm_uport);
1768 if (use_low_power_rx_wakeup(msm_uport))
1769 free_irq(msm_uport->rx_wakeup.irq, msm_uport);
1770
1771 msm_uport->imr_reg = 0;
1772 msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
1773
1774 wait_event(msm_uport->rx.wait, msm_uport->rx.flush == FLUSH_SHUTDOWN);
1775
1776 clk_disable(msm_uport->clk); /* to balance local clk_enable() */
1777 if (msm_uport->clk_state != MSM_HS_CLK_OFF)
1778 clk_disable(msm_uport->clk); /* to balance clk_state */
1779 msm_uport->clk_state = MSM_HS_CLK_PORT_OFF;
1780
1781 dma_unmap_single(uport->dev, msm_uport->tx.dma_base,
1782 UART_XMIT_SIZE, DMA_TO_DEVICE);
1783
1784 spin_unlock_irqrestore(&uport->lock, flags);
1785
1786 if (cancel_work_sync(&msm_uport->rx.tty_work))
1787 msm_hs_tty_flip_buffer_work(&msm_uport->rx.tty_work);
1788 }
1789
1790 static void __exit msm_serial_hs_exit(void)
1791 {
1792 flush_workqueue(msm_hs_workqueue);
1793 destroy_workqueue(msm_hs_workqueue);
1794 platform_driver_unregister(&msm_serial_hs_platform_driver);
1795 uart_unregister_driver(&msm_hs_driver);
1796 }
1797 module_exit(msm_serial_hs_exit);
1798
1799 #ifdef CONFIG_PM_RUNTIME
1800 static int msm_hs_runtime_idle(struct device *dev)
1801 {
1802 /*
1803 * returning success from idle results in runtime suspend to be
1804 * called
1805 */
1806 return 0;
1807 }
1808
1809 static int msm_hs_runtime_resume(struct device *dev)
1810 {
1811 struct platform_device *pdev = container_of(dev, struct
1812 platform_device, dev);
1813 struct msm_hs_port *msm_uport = &q_uart_port[pdev->id];
1814
1815 msm_hs_request_clock_on(&msm_uport->uport);
1816 return 0;
1817 }
1818
1819 static int msm_hs_runtime_suspend(struct device *dev)
1820 {
1821 struct platform_device *pdev = container_of(dev, struct
1822 platform_device, dev);
1823 struct msm_hs_port *msm_uport = &q_uart_port[pdev->id];
1824
1825 msm_hs_request_clock_off(&msm_uport->uport);
1826 return 0;
1827 }
1828 #else
1829 #define msm_hs_runtime_idle NULL
1830 #define msm_hs_runtime_resume NULL
1831 #define msm_hs_runtime_suspend NULL
1832 #endif
1833
1834 static const struct dev_pm_ops msm_hs_dev_pm_ops = {
1835 .runtime_suspend = msm_hs_runtime_suspend,
1836 .runtime_resume = msm_hs_runtime_resume,
1837 .runtime_idle = msm_hs_runtime_idle,
1838 };
1839
1840 static struct platform_driver msm_serial_hs_platform_driver = {
1841 .probe = msm_hs_probe,
1842 .remove = __devexit_p(msm_hs_remove),
1843 .driver = {
1844 .name = "msm_serial_hs",
1845 .owner = THIS_MODULE,
1846 .pm = &msm_hs_dev_pm_ops,
1847 },
1848 };
1849
1850 static struct uart_driver msm_hs_driver = {
1851 .owner = THIS_MODULE,
1852 .driver_name = "msm_serial_hs",
1853 .dev_name = "ttyHS",
1854 .nr = UARTDM_NR,
1855 .cons = 0,
1856 };
1857
1858 static struct uart_ops msm_hs_ops = {
1859 .tx_empty = msm_hs_tx_empty,
1860 .set_mctrl = msm_hs_set_mctrl_locked,
1861 .get_mctrl = msm_hs_get_mctrl_locked,
1862 .stop_tx = msm_hs_stop_tx_locked,
1863 .start_tx = msm_hs_start_tx_locked,
1864 .stop_rx = msm_hs_stop_rx_locked,
1865 .enable_ms = msm_hs_enable_ms_locked,
1866 .break_ctl = msm_hs_break_ctl,
1867 .startup = msm_hs_startup,
1868 .shutdown = msm_hs_shutdown,
1869 .set_termios = msm_hs_set_termios,
1870 .pm = msm_hs_pm,
1871 .type = msm_hs_type,
1872 .config_port = msm_hs_config_port,
1873 .release_port = msm_hs_release_port,
1874 .request_port = msm_hs_request_port,
1875 };
1876
1877 MODULE_DESCRIPTION("High Speed UART Driver for the MSM chipset");
1878 MODULE_VERSION("1.2");
1879 MODULE_LICENSE("GPL v2");