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OMAPDSS: VENC: fix NULL pointer dereference in DSS2 VENC sysfs debug attr on OMAP4
[zen-stable.git] / drivers / tty / serial / pch_uart.c
blobd53a8a43388236dd568cbfe1f61c3a62e9a508e3
1 /*
2 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
3 *
4 *This program is free software; you can redistribute it and/or modify
5 *it under the terms of the GNU General Public License as published by
6 *the Free Software Foundation; version 2 of the License.
7 *
8 *This program is distributed in the hope that it will be useful,
9 *but WITHOUT ANY WARRANTY; without even the implied warranty of
10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 *GNU General Public License for more details.
12 *
13 *You should have received a copy of the GNU General Public License
14 *along with this program; if not, write to the Free Software
15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17 #include <linux/kernel.h>
18 #include <linux/serial_reg.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/serial_core.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/interrupt.h>
26 #include <linux/io.h>
27 #include <linux/dmi.h>
28 #include <linux/console.h>
29 #include <linux/nmi.h>
30 #include <linux/delay.h>
31
32 #include <linux/dmaengine.h>
33 #include <linux/pch_dma.h>
34
35 enum {
36 PCH_UART_HANDLED_RX_INT_SHIFT,
37 PCH_UART_HANDLED_TX_INT_SHIFT,
38 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
39 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
40 PCH_UART_HANDLED_MS_INT_SHIFT,
41 };
42
43 enum {
44 PCH_UART_8LINE,
45 PCH_UART_2LINE,
46 };
47
48 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
49
50 /* Set the max number of UART port
51 * Intel EG20T PCH: 4 port
52 * LAPIS Semiconductor ML7213 IOH: 3 port
53 * LAPIS Semiconductor ML7223 IOH: 2 port
54 */
55 #define PCH_UART_NR 4
56
57 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
58 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
59 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
60 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
61 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
62 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
63 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
64
65 #define PCH_UART_RBR 0x00
66 #define PCH_UART_THR 0x00
67
68 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
69 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
70 #define PCH_UART_IER_ERBFI 0x00000001
71 #define PCH_UART_IER_ETBEI 0x00000002
72 #define PCH_UART_IER_ELSI 0x00000004
73 #define PCH_UART_IER_EDSSI 0x00000008
74
75 #define PCH_UART_IIR_IP 0x00000001
76 #define PCH_UART_IIR_IID 0x00000006
77 #define PCH_UART_IIR_MSI 0x00000000
78 #define PCH_UART_IIR_TRI 0x00000002
79 #define PCH_UART_IIR_RRI 0x00000004
80 #define PCH_UART_IIR_REI 0x00000006
81 #define PCH_UART_IIR_TOI 0x00000008
82 #define PCH_UART_IIR_FIFO256 0x00000020
83 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
84 #define PCH_UART_IIR_FE 0x000000C0
85
86 #define PCH_UART_FCR_FIFOE 0x00000001
87 #define PCH_UART_FCR_RFR 0x00000002
88 #define PCH_UART_FCR_TFR 0x00000004
89 #define PCH_UART_FCR_DMS 0x00000008
90 #define PCH_UART_FCR_FIFO256 0x00000020
91 #define PCH_UART_FCR_RFTL 0x000000C0
92
93 #define PCH_UART_FCR_RFTL1 0x00000000
94 #define PCH_UART_FCR_RFTL64 0x00000040
95 #define PCH_UART_FCR_RFTL128 0x00000080
96 #define PCH_UART_FCR_RFTL224 0x000000C0
97 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
98 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
99 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
100 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
101 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
102 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
103 #define PCH_UART_FCR_RFTL_SHIFT 6
104
105 #define PCH_UART_LCR_WLS 0x00000003
106 #define PCH_UART_LCR_STB 0x00000004
107 #define PCH_UART_LCR_PEN 0x00000008
108 #define PCH_UART_LCR_EPS 0x00000010
109 #define PCH_UART_LCR_SP 0x00000020
110 #define PCH_UART_LCR_SB 0x00000040
111 #define PCH_UART_LCR_DLAB 0x00000080
112 #define PCH_UART_LCR_NP 0x00000000
113 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN
114 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
115 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
116 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
117 PCH_UART_LCR_SP)
118
119 #define PCH_UART_LCR_5BIT 0x00000000
120 #define PCH_UART_LCR_6BIT 0x00000001
121 #define PCH_UART_LCR_7BIT 0x00000002
122 #define PCH_UART_LCR_8BIT 0x00000003
123
124 #define PCH_UART_MCR_DTR 0x00000001
125 #define PCH_UART_MCR_RTS 0x00000002
126 #define PCH_UART_MCR_OUT 0x0000000C
127 #define PCH_UART_MCR_LOOP 0x00000010
128 #define PCH_UART_MCR_AFE 0x00000020
129
130 #define PCH_UART_LSR_DR 0x00000001
131 #define PCH_UART_LSR_ERR (1<<7)
132
133 #define PCH_UART_MSR_DCTS 0x00000001
134 #define PCH_UART_MSR_DDSR 0x00000002
135 #define PCH_UART_MSR_TERI 0x00000004
136 #define PCH_UART_MSR_DDCD 0x00000008
137 #define PCH_UART_MSR_CTS 0x00000010
138 #define PCH_UART_MSR_DSR 0x00000020
139 #define PCH_UART_MSR_RI 0x00000040
140 #define PCH_UART_MSR_DCD 0x00000080
141 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
142 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
143
144 #define PCH_UART_DLL 0x00
145 #define PCH_UART_DLM 0x01
146
147 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
148 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
149 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
150 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
151 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
152
153 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
154 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
155 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
156 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
157 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
158 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
159 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
160 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
161 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
162 #define PCH_UART_HAL_STB1 0
163 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
164
165 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
166 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
167 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
168 PCH_UART_HAL_CLR_RX_FIFO)
169
170 #define PCH_UART_HAL_DMA_MODE0 0
171 #define PCH_UART_HAL_FIFO_DIS 0
172 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
173 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
174 PCH_UART_FCR_FIFO256)
175 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
176 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
177 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
178 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
179 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
180 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
181 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
182 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
183 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
184 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
185 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
186 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
187 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
188 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
189
190 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
191 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
192 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
193 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
194 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
195
196 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
197 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
198 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
199 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
200 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
201
202 #define PCI_VENDOR_ID_ROHM 0x10DB
203
204 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
205
206 #define DEFAULT_BAUD_RATE 1843200 /* 1.8432MHz */
207
208 struct pch_uart_buffer {
209 unsigned char *buf;
210 int size;
211 };
212
213 struct eg20t_port {
214 struct uart_port port;
215 int port_type;
216 void __iomem *membase;
217 resource_size_t mapbase;
218 unsigned int iobase;
219 struct pci_dev *pdev;
220 int fifo_size;
221 int base_baud;
222 int start_tx;
223 int start_rx;
224 int tx_empty;
225 int int_dis_flag;
226 int trigger;
227 int trigger_level;
228 struct pch_uart_buffer rxbuf;
229 unsigned int dmsr;
230 unsigned int fcr;
231 unsigned int mcr;
232 unsigned int use_dma;
233 unsigned int use_dma_flag;
234 struct dma_async_tx_descriptor *desc_tx;
235 struct dma_async_tx_descriptor *desc_rx;
236 struct pch_dma_slave param_tx;
237 struct pch_dma_slave param_rx;
238 struct dma_chan *chan_tx;
239 struct dma_chan *chan_rx;
240 struct scatterlist *sg_tx_p;
241 int nent;
242 struct scatterlist sg_rx;
243 int tx_dma_use;
244 void *rx_buf_virt;
245 dma_addr_t rx_buf_dma;
246 };
247
248 /**
249 * struct pch_uart_driver_data - private data structure for UART-DMA
250 * @port_type: The number of DMA channel
251 * @line_no: UART port line number (0, 1, 2...)
252 */
253 struct pch_uart_driver_data {
254 int port_type;
255 int line_no;
256 };
257
258 enum pch_uart_num_t {
259 pch_et20t_uart0 = 0,
260 pch_et20t_uart1,
261 pch_et20t_uart2,
262 pch_et20t_uart3,
263 pch_ml7213_uart0,
264 pch_ml7213_uart1,
265 pch_ml7213_uart2,
266 pch_ml7223_uart0,
267 pch_ml7223_uart1,
268 pch_ml7831_uart0,
269 pch_ml7831_uart1,
270 };
271
272 static struct pch_uart_driver_data drv_dat[] = {
273 [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
274 [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
275 [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
276 [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
277 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
278 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
279 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
280 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
281 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
282 [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
283 [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
284 };
285
286 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
287 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
288 #endif
289 static unsigned int default_baud = 9600;
290 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
291 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
292 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
293 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
294
295 static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize,
296 int base_baud)
297 {
298 struct eg20t_port *priv = pci_get_drvdata(pdev);
299
300 priv->trigger_level = 1;
301 priv->fcr = 0;
302 }
303
304 static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base)
305 {
306 unsigned int msr = ioread8(base + UART_MSR);
307 priv->dmsr |= msr & PCH_UART_MSR_DELTA;
308
309 return msr;
310 }
311
312 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
313 unsigned int flag)
314 {
315 u8 ier = ioread8(priv->membase + UART_IER);
316 ier |= flag & PCH_UART_IER_MASK;
317 iowrite8(ier, priv->membase + UART_IER);
318 }
319
320 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
321 unsigned int flag)
322 {
323 u8 ier = ioread8(priv->membase + UART_IER);
324 ier &= ~(flag & PCH_UART_IER_MASK);
325 iowrite8(ier, priv->membase + UART_IER);
326 }
327
328 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
329 unsigned int parity, unsigned int bits,
330 unsigned int stb)
331 {
332 unsigned int dll, dlm, lcr;
333 int div;
334
335 div = DIV_ROUND_CLOSEST(priv->base_baud / 16, baud);
336 if (div < 0 || USHRT_MAX <= div) {
337 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
338 return -EINVAL;
339 }
340
341 dll = (unsigned int)div & 0x00FFU;
342 dlm = ((unsigned int)div >> 8) & 0x00FFU;
343
344 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
345 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
346 return -EINVAL;
347 }
348
349 if (bits & ~PCH_UART_LCR_WLS) {
350 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
351 return -EINVAL;
352 }
353
354 if (stb & ~PCH_UART_LCR_STB) {
355 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
356 return -EINVAL;
357 }
358
359 lcr = parity;
360 lcr |= bits;
361 lcr |= stb;
362
363 dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
364 __func__, baud, div, lcr, jiffies);
365 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
366 iowrite8(dll, priv->membase + PCH_UART_DLL);
367 iowrite8(dlm, priv->membase + PCH_UART_DLM);
368 iowrite8(lcr, priv->membase + UART_LCR);
369
370 return 0;
371 }
372
373 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
374 unsigned int flag)
375 {
376 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
377 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
378 __func__, flag);
379 return -EINVAL;
380 }
381
382 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
383 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
384 priv->membase + UART_FCR);
385 iowrite8(priv->fcr, priv->membase + UART_FCR);
386
387 return 0;
388 }
389
390 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
391 unsigned int dmamode,
392 unsigned int fifo_size, unsigned int trigger)
393 {
394 u8 fcr;
395
396 if (dmamode & ~PCH_UART_FCR_DMS) {
397 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
398 __func__, dmamode);
399 return -EINVAL;
400 }
401
402 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
403 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
404 __func__, fifo_size);
405 return -EINVAL;
406 }
407
408 if (trigger & ~PCH_UART_FCR_RFTL) {
409 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
410 __func__, trigger);
411 return -EINVAL;
412 }
413
414 switch (priv->fifo_size) {
415 case 256:
416 priv->trigger_level =
417 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
418 break;
419 case 64:
420 priv->trigger_level =
421 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
422 break;
423 case 16:
424 priv->trigger_level =
425 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
426 break;
427 default:
428 priv->trigger_level =
429 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
430 break;
431 }
432 fcr =
433 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
434 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
435 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
436 priv->membase + UART_FCR);
437 iowrite8(fcr, priv->membase + UART_FCR);
438 priv->fcr = fcr;
439
440 return 0;
441 }
442
443 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
444 {
445 priv->dmsr = 0;
446 return get_msr(priv, priv->membase);
447 }
448
449 static void pch_uart_hal_write(struct eg20t_port *priv,
450 const unsigned char *buf, int tx_size)
451 {
452 int i;
453 unsigned int thr;
454
455 for (i = 0; i < tx_size;) {
456 thr = buf[i++];
457 iowrite8(thr, priv->membase + PCH_UART_THR);
458 }
459 }
460
461 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
462 int rx_size)
463 {
464 int i;
465 u8 rbr, lsr;
466
467 lsr = ioread8(priv->membase + UART_LSR);
468 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
469 i < rx_size && lsr & UART_LSR_DR;
470 lsr = ioread8(priv->membase + UART_LSR)) {
471 rbr = ioread8(priv->membase + PCH_UART_RBR);
472 buf[i++] = rbr;
473 }
474 return i;
475 }
476
477 static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv)
478 {
479 unsigned int iir;
480 int ret;
481
482 iir = ioread8(priv->membase + UART_IIR);
483 ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP));
484 return ret;
485 }
486
487 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
488 {
489 return ioread8(priv->membase + UART_LSR);
490 }
491
492 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
493 {
494 unsigned int lcr;
495
496 lcr = ioread8(priv->membase + UART_LCR);
497 if (on)
498 lcr |= PCH_UART_LCR_SB;
499 else
500 lcr &= ~PCH_UART_LCR_SB;
501
502 iowrite8(lcr, priv->membase + UART_LCR);
503 }
504
505 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
506 int size)
507 {
508 struct uart_port *port;
509 struct tty_struct *tty;
510
511 port = &priv->port;
512 tty = tty_port_tty_get(&port->state->port);
513 if (!tty) {
514 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
515 return -EBUSY;
516 }
517
518 tty_insert_flip_string(tty, buf, size);
519 tty_flip_buffer_push(tty);
520 tty_kref_put(tty);
521
522 return 0;
523 }
524
525 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
526 {
527 int ret;
528 struct uart_port *port = &priv->port;
529
530 if (port->x_char) {
531 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
532 __func__, port->x_char, jiffies);
533 buf[0] = port->x_char;
534 port->x_char = 0;
535 ret = 1;
536 } else {
537 ret = 0;
538 }
539
540 return ret;
541 }
542
543 static int dma_push_rx(struct eg20t_port *priv, int size)
544 {
545 struct tty_struct *tty;
546 int room;
547 struct uart_port *port = &priv->port;
548
549 port = &priv->port;
550 tty = tty_port_tty_get(&port->state->port);
551 if (!tty) {
552 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
553 return 0;
554 }
555
556 room = tty_buffer_request_room(tty, size);
557
558 if (room < size)
559 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
560 size - room);
561 if (!room)
562 return room;
563
564 tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size);
565
566 port->icount.rx += room;
567 tty_kref_put(tty);
568
569 return room;
570 }
571
572 static void pch_free_dma(struct uart_port *port)
573 {
574 struct eg20t_port *priv;
575 priv = container_of(port, struct eg20t_port, port);
576
577 if (priv->chan_tx) {
578 dma_release_channel(priv->chan_tx);
579 priv->chan_tx = NULL;
580 }
581 if (priv->chan_rx) {
582 dma_release_channel(priv->chan_rx);
583 priv->chan_rx = NULL;
584 }
585 if (sg_dma_address(&priv->sg_rx))
586 dma_free_coherent(port->dev, port->fifosize,
587 sg_virt(&priv->sg_rx),
588 sg_dma_address(&priv->sg_rx));
589
590 return;
591 }
592
593 static bool filter(struct dma_chan *chan, void *slave)
594 {
595 struct pch_dma_slave *param = slave;
596
597 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
598 chan->device->dev)) {
599 chan->private = param;
600 return true;
601 } else {
602 return false;
603 }
604 }
605
606 static void pch_request_dma(struct uart_port *port)
607 {
608 dma_cap_mask_t mask;
609 struct dma_chan *chan;
610 struct pci_dev *dma_dev;
611 struct pch_dma_slave *param;
612 struct eg20t_port *priv =
613 container_of(port, struct eg20t_port, port);
614 dma_cap_zero(mask);
615 dma_cap_set(DMA_SLAVE, mask);
616
617 dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number,
618 PCI_DEVFN(0xa, 0)); /* Get DMA's dev
619 information */
620 /* Set Tx DMA */
621 param = &priv->param_tx;
622 param->dma_dev = &dma_dev->dev;
623 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
624
625 param->tx_reg = port->mapbase + UART_TX;
626 chan = dma_request_channel(mask, filter, param);
627 if (!chan) {
628 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
629 __func__);
630 return;
631 }
632 priv->chan_tx = chan;
633
634 /* Set Rx DMA */
635 param = &priv->param_rx;
636 param->dma_dev = &dma_dev->dev;
637 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
638
639 param->rx_reg = port->mapbase + UART_RX;
640 chan = dma_request_channel(mask, filter, param);
641 if (!chan) {
642 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
643 __func__);
644 dma_release_channel(priv->chan_tx);
645 priv->chan_tx = NULL;
646 return;
647 }
648
649 /* Get Consistent memory for DMA */
650 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
651 &priv->rx_buf_dma, GFP_KERNEL);
652 priv->chan_rx = chan;
653 }
654
655 static void pch_dma_rx_complete(void *arg)
656 {
657 struct eg20t_port *priv = arg;
658 struct uart_port *port = &priv->port;
659 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
660 int count;
661
662 if (!tty) {
663 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
664 return;
665 }
666
667 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
668 count = dma_push_rx(priv, priv->trigger_level);
669 if (count)
670 tty_flip_buffer_push(tty);
671 tty_kref_put(tty);
672 async_tx_ack(priv->desc_rx);
673 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
674 }
675
676 static void pch_dma_tx_complete(void *arg)
677 {
678 struct eg20t_port *priv = arg;
679 struct uart_port *port = &priv->port;
680 struct circ_buf *xmit = &port->state->xmit;
681 struct scatterlist *sg = priv->sg_tx_p;
682 int i;
683
684 for (i = 0; i < priv->nent; i++, sg++) {
685 xmit->tail += sg_dma_len(sg);
686 port->icount.tx += sg_dma_len(sg);
687 }
688 xmit->tail &= UART_XMIT_SIZE - 1;
689 async_tx_ack(priv->desc_tx);
690 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
691 priv->tx_dma_use = 0;
692 priv->nent = 0;
693 kfree(priv->sg_tx_p);
694 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
695 }
696
697 static int pop_tx(struct eg20t_port *priv, int size)
698 {
699 int count = 0;
700 struct uart_port *port = &priv->port;
701 struct circ_buf *xmit = &port->state->xmit;
702
703 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
704 goto pop_tx_end;
705
706 do {
707 int cnt_to_end =
708 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
709 int sz = min(size - count, cnt_to_end);
710 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
711 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
712 count += sz;
713 } while (!uart_circ_empty(xmit) && count < size);
714
715 pop_tx_end:
716 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
717 count, size - count, jiffies);
718
719 return count;
720 }
721
722 static int handle_rx_to(struct eg20t_port *priv)
723 {
724 struct pch_uart_buffer *buf;
725 int rx_size;
726 int ret;
727 if (!priv->start_rx) {
728 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
729 return 0;
730 }
731 buf = &priv->rxbuf;
732 do {
733 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
734 ret = push_rx(priv, buf->buf, rx_size);
735 if (ret)
736 return 0;
737 } while (rx_size == buf->size);
738
739 return PCH_UART_HANDLED_RX_INT;
740 }
741
742 static int handle_rx(struct eg20t_port *priv)
743 {
744 return handle_rx_to(priv);
745 }
746
747 static int dma_handle_rx(struct eg20t_port *priv)
748 {
749 struct uart_port *port = &priv->port;
750 struct dma_async_tx_descriptor *desc;
751 struct scatterlist *sg;
752
753 priv = container_of(port, struct eg20t_port, port);
754 sg = &priv->sg_rx;
755
756 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
757
758 sg_dma_len(sg) = priv->trigger_level;
759
760 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
761 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
762 ~PAGE_MASK);
763
764 sg_dma_address(sg) = priv->rx_buf_dma;
765
766 desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx,
767 sg, 1, DMA_DEV_TO_MEM,
768 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
769
770 if (!desc)
771 return 0;
772
773 priv->desc_rx = desc;
774 desc->callback = pch_dma_rx_complete;
775 desc->callback_param = priv;
776 desc->tx_submit(desc);
777 dma_async_issue_pending(priv->chan_rx);
778
779 return PCH_UART_HANDLED_RX_INT;
780 }
781
782 static unsigned int handle_tx(struct eg20t_port *priv)
783 {
784 struct uart_port *port = &priv->port;
785 struct circ_buf *xmit = &port->state->xmit;
786 int fifo_size;
787 int tx_size;
788 int size;
789 int tx_empty;
790
791 if (!priv->start_tx) {
792 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
793 __func__, jiffies);
794 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
795 priv->tx_empty = 1;
796 return 0;
797 }
798
799 fifo_size = max(priv->fifo_size, 1);
800 tx_empty = 1;
801 if (pop_tx_x(priv, xmit->buf)) {
802 pch_uart_hal_write(priv, xmit->buf, 1);
803 port->icount.tx++;
804 tx_empty = 0;
805 fifo_size--;
806 }
807 size = min(xmit->head - xmit->tail, fifo_size);
808 if (size < 0)
809 size = fifo_size;
810
811 tx_size = pop_tx(priv, size);
812 if (tx_size > 0) {
813 port->icount.tx += tx_size;
814 tx_empty = 0;
815 }
816
817 priv->tx_empty = tx_empty;
818
819 if (tx_empty) {
820 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
821 uart_write_wakeup(port);
822 }
823
824 return PCH_UART_HANDLED_TX_INT;
825 }
826
827 static unsigned int dma_handle_tx(struct eg20t_port *priv)
828 {
829 struct uart_port *port = &priv->port;
830 struct circ_buf *xmit = &port->state->xmit;
831 struct scatterlist *sg;
832 int nent;
833 int fifo_size;
834 int tx_empty;
835 struct dma_async_tx_descriptor *desc;
836 int num;
837 int i;
838 int bytes;
839 int size;
840 int rem;
841
842 if (!priv->start_tx) {
843 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
844 __func__, jiffies);
845 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
846 priv->tx_empty = 1;
847 return 0;
848 }
849
850 if (priv->tx_dma_use) {
851 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
852 __func__, jiffies);
853 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
854 priv->tx_empty = 1;
855 return 0;
856 }
857
858 fifo_size = max(priv->fifo_size, 1);
859 tx_empty = 1;
860 if (pop_tx_x(priv, xmit->buf)) {
861 pch_uart_hal_write(priv, xmit->buf, 1);
862 port->icount.tx++;
863 tx_empty = 0;
864 fifo_size--;
865 }
866
867 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
868 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
869 xmit->tail, UART_XMIT_SIZE));
870 if (!bytes) {
871 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
872 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
873 uart_write_wakeup(port);
874 return 0;
875 }
876
877 if (bytes > fifo_size) {
878 num = bytes / fifo_size + 1;
879 size = fifo_size;
880 rem = bytes % fifo_size;
881 } else {
882 num = 1;
883 size = bytes;
884 rem = bytes;
885 }
886
887 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
888 __func__, num, size, rem);
889
890 priv->tx_dma_use = 1;
891
892 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
893
894 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
895 sg = priv->sg_tx_p;
896
897 for (i = 0; i < num; i++, sg++) {
898 if (i == (num - 1))
899 sg_set_page(sg, virt_to_page(xmit->buf),
900 rem, fifo_size * i);
901 else
902 sg_set_page(sg, virt_to_page(xmit->buf),
903 size, fifo_size * i);
904 }
905
906 sg = priv->sg_tx_p;
907 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
908 if (!nent) {
909 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
910 return 0;
911 }
912 priv->nent = nent;
913
914 for (i = 0; i < nent; i++, sg++) {
915 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
916 fifo_size * i;
917 sg_dma_address(sg) = (sg_dma_address(sg) &
918 ~(UART_XMIT_SIZE - 1)) + sg->offset;
919 if (i == (nent - 1))
920 sg_dma_len(sg) = rem;
921 else
922 sg_dma_len(sg) = size;
923 }
924
925 desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx,
926 priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
927 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
928 if (!desc) {
929 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
930 __func__);
931 return 0;
932 }
933 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
934 priv->desc_tx = desc;
935 desc->callback = pch_dma_tx_complete;
936 desc->callback_param = priv;
937
938 desc->tx_submit(desc);
939
940 dma_async_issue_pending(priv->chan_tx);
941
942 return PCH_UART_HANDLED_TX_INT;
943 }
944
945 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
946 {
947 u8 fcr = ioread8(priv->membase + UART_FCR);
948
949 /* Reset FIFO */
950 fcr |= UART_FCR_CLEAR_RCVR;
951 iowrite8(fcr, priv->membase + UART_FCR);
952
953 if (lsr & PCH_UART_LSR_ERR)
954 dev_err(&priv->pdev->dev, "Error data in FIFO\n");
955
956 if (lsr & UART_LSR_FE)
957 dev_err(&priv->pdev->dev, "Framing Error\n");
958
959 if (lsr & UART_LSR_PE)
960 dev_err(&priv->pdev->dev, "Parity Error\n");
961
962 if (lsr & UART_LSR_OE)
963 dev_err(&priv->pdev->dev, "Overrun Error\n");
964 }
965
966 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
967 {
968 struct eg20t_port *priv = dev_id;
969 unsigned int handled;
970 u8 lsr;
971 int ret = 0;
972 unsigned int iid;
973 unsigned long flags;
974
975 spin_lock_irqsave(&priv->port.lock, flags);
976 handled = 0;
977 while ((iid = pch_uart_hal_get_iid(priv)) > 1) {
978 switch (iid) {
979 case PCH_UART_IID_RLS: /* Receiver Line Status */
980 lsr = pch_uart_hal_get_line_status(priv);
981 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
982 UART_LSR_PE | UART_LSR_OE)) {
983 pch_uart_err_ir(priv, lsr);
984 ret = PCH_UART_HANDLED_RX_ERR_INT;
985 }
986 break;
987 case PCH_UART_IID_RDR: /* Received Data Ready */
988 if (priv->use_dma) {
989 pch_uart_hal_disable_interrupt(priv,
990 PCH_UART_HAL_RX_INT);
991 ret = dma_handle_rx(priv);
992 if (!ret)
993 pch_uart_hal_enable_interrupt(priv,
994 PCH_UART_HAL_RX_INT);
995 } else {
996 ret = handle_rx(priv);
997 }
998 break;
999 case PCH_UART_IID_RDR_TO: /* Received Data Ready
1000 (FIFO Timeout) */
1001 ret = handle_rx_to(priv);
1002 break;
1003 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1004 Empty */
1005 if (priv->use_dma)
1006 ret = dma_handle_tx(priv);
1007 else
1008 ret = handle_tx(priv);
1009 break;
1010 case PCH_UART_IID_MS: /* Modem Status */
1011 ret = PCH_UART_HANDLED_MS_INT;
1012 break;
1013 default: /* Never junp to this label */
1014 dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__,
1015 iid, jiffies);
1016 ret = -1;
1017 break;
1018 }
1019 handled |= (unsigned int)ret;
1020 }
1021 if (handled == 0 && iid <= 1) {
1022 if (priv->int_dis_flag)
1023 priv->int_dis_flag = 0;
1024 }
1025
1026 spin_unlock_irqrestore(&priv->port.lock, flags);
1027 return IRQ_RETVAL(handled);
1028 }
1029
1030 /* This function tests whether the transmitter fifo and shifter for the port
1031 described by 'port' is empty. */
1032 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1033 {
1034 struct eg20t_port *priv;
1035 int ret;
1036 priv = container_of(port, struct eg20t_port, port);
1037 if (priv->tx_empty)
1038 ret = TIOCSER_TEMT;
1039 else
1040 ret = 0;
1041
1042 return ret;
1043 }
1044
1045 /* Returns the current state of modem control inputs. */
1046 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1047 {
1048 struct eg20t_port *priv;
1049 u8 modem;
1050 unsigned int ret = 0;
1051
1052 priv = container_of(port, struct eg20t_port, port);
1053 modem = pch_uart_hal_get_modem(priv);
1054
1055 if (modem & UART_MSR_DCD)
1056 ret |= TIOCM_CAR;
1057
1058 if (modem & UART_MSR_RI)
1059 ret |= TIOCM_RNG;
1060
1061 if (modem & UART_MSR_DSR)
1062 ret |= TIOCM_DSR;
1063
1064 if (modem & UART_MSR_CTS)
1065 ret |= TIOCM_CTS;
1066
1067 return ret;
1068 }
1069
1070 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1071 {
1072 u32 mcr = 0;
1073 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1074
1075 if (mctrl & TIOCM_DTR)
1076 mcr |= UART_MCR_DTR;
1077 if (mctrl & TIOCM_RTS)
1078 mcr |= UART_MCR_RTS;
1079 if (mctrl & TIOCM_LOOP)
1080 mcr |= UART_MCR_LOOP;
1081
1082 if (priv->mcr & UART_MCR_AFE)
1083 mcr |= UART_MCR_AFE;
1084
1085 if (mctrl)
1086 iowrite8(mcr, priv->membase + UART_MCR);
1087 }
1088
1089 static void pch_uart_stop_tx(struct uart_port *port)
1090 {
1091 struct eg20t_port *priv;
1092 priv = container_of(port, struct eg20t_port, port);
1093 priv->start_tx = 0;
1094 priv->tx_dma_use = 0;
1095 }
1096
1097 static void pch_uart_start_tx(struct uart_port *port)
1098 {
1099 struct eg20t_port *priv;
1100
1101 priv = container_of(port, struct eg20t_port, port);
1102
1103 if (priv->use_dma) {
1104 if (priv->tx_dma_use) {
1105 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1106 __func__);
1107 return;
1108 }
1109 }
1110
1111 priv->start_tx = 1;
1112 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1113 }
1114
1115 static void pch_uart_stop_rx(struct uart_port *port)
1116 {
1117 struct eg20t_port *priv;
1118 priv = container_of(port, struct eg20t_port, port);
1119 priv->start_rx = 0;
1120 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
1121 priv->int_dis_flag = 1;
1122 }
1123
1124 /* Enable the modem status interrupts. */
1125 static void pch_uart_enable_ms(struct uart_port *port)
1126 {
1127 struct eg20t_port *priv;
1128 priv = container_of(port, struct eg20t_port, port);
1129 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1130 }
1131
1132 /* Control the transmission of a break signal. */
1133 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1134 {
1135 struct eg20t_port *priv;
1136 unsigned long flags;
1137
1138 priv = container_of(port, struct eg20t_port, port);
1139 spin_lock_irqsave(&port->lock, flags);
1140 pch_uart_hal_set_break(priv, ctl);
1141 spin_unlock_irqrestore(&port->lock, flags);
1142 }
1143
1144 /* Grab any interrupt resources and initialise any low level driver state. */
1145 static int pch_uart_startup(struct uart_port *port)
1146 {
1147 struct eg20t_port *priv;
1148 int ret;
1149 int fifo_size;
1150 int trigger_level;
1151
1152 priv = container_of(port, struct eg20t_port, port);
1153 priv->tx_empty = 1;
1154
1155 if (port->uartclk)
1156 priv->base_baud = port->uartclk;
1157 else
1158 port->uartclk = priv->base_baud;
1159
1160 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1161 ret = pch_uart_hal_set_line(priv, default_baud,
1162 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1163 PCH_UART_HAL_STB1);
1164 if (ret)
1165 return ret;
1166
1167 switch (priv->fifo_size) {
1168 case 256:
1169 fifo_size = PCH_UART_HAL_FIFO256;
1170 break;
1171 case 64:
1172 fifo_size = PCH_UART_HAL_FIFO64;
1173 break;
1174 case 16:
1175 fifo_size = PCH_UART_HAL_FIFO16;
1176 case 1:
1177 default:
1178 fifo_size = PCH_UART_HAL_FIFO_DIS;
1179 break;
1180 }
1181
1182 switch (priv->trigger) {
1183 case PCH_UART_HAL_TRIGGER1:
1184 trigger_level = 1;
1185 break;
1186 case PCH_UART_HAL_TRIGGER_L:
1187 trigger_level = priv->fifo_size / 4;
1188 break;
1189 case PCH_UART_HAL_TRIGGER_M:
1190 trigger_level = priv->fifo_size / 2;
1191 break;
1192 case PCH_UART_HAL_TRIGGER_H:
1193 default:
1194 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1195 break;
1196 }
1197
1198 priv->trigger_level = trigger_level;
1199 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1200 fifo_size, priv->trigger);
1201 if (ret < 0)
1202 return ret;
1203
1204 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1205 KBUILD_MODNAME, priv);
1206 if (ret < 0)
1207 return ret;
1208
1209 if (priv->use_dma)
1210 pch_request_dma(port);
1211
1212 priv->start_rx = 1;
1213 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
1214 uart_update_timeout(port, CS8, default_baud);
1215
1216 return 0;
1217 }
1218
1219 static void pch_uart_shutdown(struct uart_port *port)
1220 {
1221 struct eg20t_port *priv;
1222 int ret;
1223
1224 priv = container_of(port, struct eg20t_port, port);
1225 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1226 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1227 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1228 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1229 if (ret)
1230 dev_err(priv->port.dev,
1231 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1232
1233 pch_free_dma(port);
1234
1235 free_irq(priv->port.irq, priv);
1236 }
1237
1238 /* Change the port parameters, including word length, parity, stop
1239 *bits. Update read_status_mask and ignore_status_mask to indicate
1240 *the types of events we are interested in receiving. */
1241 static void pch_uart_set_termios(struct uart_port *port,
1242 struct ktermios *termios, struct ktermios *old)
1243 {
1244 int baud;
1245 int rtn;
1246 unsigned int parity, bits, stb;
1247 struct eg20t_port *priv;
1248 unsigned long flags;
1249
1250 priv = container_of(port, struct eg20t_port, port);
1251 switch (termios->c_cflag & CSIZE) {
1252 case CS5:
1253 bits = PCH_UART_HAL_5BIT;
1254 break;
1255 case CS6:
1256 bits = PCH_UART_HAL_6BIT;
1257 break;
1258 case CS7:
1259 bits = PCH_UART_HAL_7BIT;
1260 break;
1261 default: /* CS8 */
1262 bits = PCH_UART_HAL_8BIT;
1263 break;
1264 }
1265 if (termios->c_cflag & CSTOPB)
1266 stb = PCH_UART_HAL_STB2;
1267 else
1268 stb = PCH_UART_HAL_STB1;
1269
1270 if (termios->c_cflag & PARENB) {
1271 if (!(termios->c_cflag & PARODD))
1272 parity = PCH_UART_HAL_PARITY_ODD;
1273 else
1274 parity = PCH_UART_HAL_PARITY_EVEN;
1275
1276 } else {
1277 parity = PCH_UART_HAL_PARITY_NONE;
1278 }
1279
1280 /* Only UART0 has auto hardware flow function */
1281 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1282 priv->mcr |= UART_MCR_AFE;
1283 else
1284 priv->mcr &= ~UART_MCR_AFE;
1285
1286 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1287
1288 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1289
1290 spin_lock_irqsave(&port->lock, flags);
1291
1292 uart_update_timeout(port, termios->c_cflag, baud);
1293 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1294 if (rtn)
1295 goto out;
1296
1297 pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1298 /* Don't rewrite B0 */
1299 if (tty_termios_baud_rate(termios))
1300 tty_termios_encode_baud_rate(termios, baud, baud);
1301
1302 out:
1303 spin_unlock_irqrestore(&port->lock, flags);
1304 }
1305
1306 static const char *pch_uart_type(struct uart_port *port)
1307 {
1308 return KBUILD_MODNAME;
1309 }
1310
1311 static void pch_uart_release_port(struct uart_port *port)
1312 {
1313 struct eg20t_port *priv;
1314
1315 priv = container_of(port, struct eg20t_port, port);
1316 pci_iounmap(priv->pdev, priv->membase);
1317 pci_release_regions(priv->pdev);
1318 }
1319
1320 static int pch_uart_request_port(struct uart_port *port)
1321 {
1322 struct eg20t_port *priv;
1323 int ret;
1324 void __iomem *membase;
1325
1326 priv = container_of(port, struct eg20t_port, port);
1327 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1328 if (ret < 0)
1329 return -EBUSY;
1330
1331 membase = pci_iomap(priv->pdev, 1, 0);
1332 if (!membase) {
1333 pci_release_regions(priv->pdev);
1334 return -EBUSY;
1335 }
1336 priv->membase = port->membase = membase;
1337
1338 return 0;
1339 }
1340
1341 static void pch_uart_config_port(struct uart_port *port, int type)
1342 {
1343 struct eg20t_port *priv;
1344
1345 priv = container_of(port, struct eg20t_port, port);
1346 if (type & UART_CONFIG_TYPE) {
1347 port->type = priv->port_type;
1348 pch_uart_request_port(port);
1349 }
1350 }
1351
1352 static int pch_uart_verify_port(struct uart_port *port,
1353 struct serial_struct *serinfo)
1354 {
1355 struct eg20t_port *priv;
1356
1357 priv = container_of(port, struct eg20t_port, port);
1358 if (serinfo->flags & UPF_LOW_LATENCY) {
1359 dev_info(priv->port.dev,
1360 "PCH UART : Use PIO Mode (without DMA)\n");
1361 priv->use_dma = 0;
1362 serinfo->flags &= ~UPF_LOW_LATENCY;
1363 } else {
1364 #ifndef CONFIG_PCH_DMA
1365 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1366 __func__);
1367 return -EOPNOTSUPP;
1368 #endif
1369 priv->use_dma_flag = 1;
1370 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1371 if (!priv->use_dma)
1372 pch_request_dma(port);
1373 priv->use_dma = 1;
1374 }
1375
1376 return 0;
1377 }
1378
1379 static struct uart_ops pch_uart_ops = {
1380 .tx_empty = pch_uart_tx_empty,
1381 .set_mctrl = pch_uart_set_mctrl,
1382 .get_mctrl = pch_uart_get_mctrl,
1383 .stop_tx = pch_uart_stop_tx,
1384 .start_tx = pch_uart_start_tx,
1385 .stop_rx = pch_uart_stop_rx,
1386 .enable_ms = pch_uart_enable_ms,
1387 .break_ctl = pch_uart_break_ctl,
1388 .startup = pch_uart_startup,
1389 .shutdown = pch_uart_shutdown,
1390 .set_termios = pch_uart_set_termios,
1391 /* .pm = pch_uart_pm, Not supported yet */
1392 /* .set_wake = pch_uart_set_wake, Not supported yet */
1393 .type = pch_uart_type,
1394 .release_port = pch_uart_release_port,
1395 .request_port = pch_uart_request_port,
1396 .config_port = pch_uart_config_port,
1397 .verify_port = pch_uart_verify_port
1398 };
1399
1400 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1401
1402 /*
1403 * Wait for transmitter & holding register to empty
1404 */
1405 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1406 {
1407 unsigned int status, tmout = 10000;
1408
1409 /* Wait up to 10ms for the character(s) to be sent. */
1410 for (;;) {
1411 status = ioread8(up->membase + UART_LSR);
1412
1413 if ((status & bits) == bits)
1414 break;
1415 if (--tmout == 0)
1416 break;
1417 udelay(1);
1418 }
1419
1420 /* Wait up to 1s for flow control if necessary */
1421 if (up->port.flags & UPF_CONS_FLOW) {
1422 unsigned int tmout;
1423 for (tmout = 1000000; tmout; tmout--) {
1424 unsigned int msr = ioread8(up->membase + UART_MSR);
1425 if (msr & UART_MSR_CTS)
1426 break;
1427 udelay(1);
1428 touch_nmi_watchdog();
1429 }
1430 }
1431 }
1432
1433 static void pch_console_putchar(struct uart_port *port, int ch)
1434 {
1435 struct eg20t_port *priv =
1436 container_of(port, struct eg20t_port, port);
1437
1438 wait_for_xmitr(priv, UART_LSR_THRE);
1439 iowrite8(ch, priv->membase + PCH_UART_THR);
1440 }
1441
1442 /*
1443 * Print a string to the serial port trying not to disturb
1444 * any possible real use of the port...
1445 *
1446 * The console_lock must be held when we get here.
1447 */
1448 static void
1449 pch_console_write(struct console *co, const char *s, unsigned int count)
1450 {
1451 struct eg20t_port *priv;
1452
1453 unsigned long flags;
1454 u8 ier;
1455 int locked = 1;
1456
1457 priv = pch_uart_ports[co->index];
1458
1459 touch_nmi_watchdog();
1460
1461 local_irq_save(flags);
1462 if (priv->port.sysrq) {
1463 /* serial8250_handle_port() already took the lock */
1464 locked = 0;
1465 } else if (oops_in_progress) {
1466 locked = spin_trylock(&priv->port.lock);
1467 } else
1468 spin_lock(&priv->port.lock);
1469
1470 /*
1471 * First save the IER then disable the interrupts
1472 */
1473 ier = ioread8(priv->membase + UART_IER);
1474
1475 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1476
1477 uart_console_write(&priv->port, s, count, pch_console_putchar);
1478
1479 /*
1480 * Finally, wait for transmitter to become empty
1481 * and restore the IER
1482 */
1483 wait_for_xmitr(priv, BOTH_EMPTY);
1484 iowrite8(ier, priv->membase + UART_IER);
1485
1486 if (locked)
1487 spin_unlock(&priv->port.lock);
1488 local_irq_restore(flags);
1489 }
1490
1491 static int __init pch_console_setup(struct console *co, char *options)
1492 {
1493 struct uart_port *port;
1494 int baud = 9600;
1495 int bits = 8;
1496 int parity = 'n';
1497 int flow = 'n';
1498
1499 /*
1500 * Check whether an invalid uart number has been specified, and
1501 * if so, search for the first available port that does have
1502 * console support.
1503 */
1504 if (co->index >= PCH_UART_NR)
1505 co->index = 0;
1506 port = &pch_uart_ports[co->index]->port;
1507
1508 if (!port || (!port->iobase && !port->membase))
1509 return -ENODEV;
1510
1511 /* setup uartclock */
1512 port->uartclk = DEFAULT_BAUD_RATE;
1513
1514 if (options)
1515 uart_parse_options(options, &baud, &parity, &bits, &flow);
1516
1517 return uart_set_options(port, co, baud, parity, bits, flow);
1518 }
1519
1520 static struct uart_driver pch_uart_driver;
1521
1522 static struct console pch_console = {
1523 .name = PCH_UART_DRIVER_DEVICE,
1524 .write = pch_console_write,
1525 .device = uart_console_device,
1526 .setup = pch_console_setup,
1527 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1528 .index = -1,
1529 .data = &pch_uart_driver,
1530 };
1531
1532 #define PCH_CONSOLE (&pch_console)
1533 #else
1534 #define PCH_CONSOLE NULL
1535 #endif
1536
1537 static struct uart_driver pch_uart_driver = {
1538 .owner = THIS_MODULE,
1539 .driver_name = KBUILD_MODNAME,
1540 .dev_name = PCH_UART_DRIVER_DEVICE,
1541 .major = 0,
1542 .minor = 0,
1543 .nr = PCH_UART_NR,
1544 .cons = PCH_CONSOLE,
1545 };
1546
1547 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1548 const struct pci_device_id *id)
1549 {
1550 struct eg20t_port *priv;
1551 int ret;
1552 unsigned int iobase;
1553 unsigned int mapbase;
1554 unsigned char *rxbuf;
1555 int fifosize, base_baud;
1556 int port_type;
1557 struct pch_uart_driver_data *board;
1558 const char *board_name;
1559
1560 board = &drv_dat[id->driver_data];
1561 port_type = board->port_type;
1562
1563 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1564 if (priv == NULL)
1565 goto init_port_alloc_err;
1566
1567 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1568 if (!rxbuf)
1569 goto init_port_free_txbuf;
1570
1571 base_baud = DEFAULT_BAUD_RATE;
1572
1573 /* quirk for CM-iTC board */
1574 board_name = dmi_get_system_info(DMI_BOARD_NAME);
1575 if (board_name && strstr(board_name, "CM-iTC"))
1576 base_baud = 192000000; /* 192.0MHz */
1577
1578 switch (port_type) {
1579 case PORT_UNKNOWN:
1580 fifosize = 256; /* EG20T/ML7213: UART0 */
1581 break;
1582 case PORT_8250:
1583 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
1584 break;
1585 default:
1586 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1587 goto init_port_hal_free;
1588 }
1589
1590 pci_enable_msi(pdev);
1591 pci_set_master(pdev);
1592
1593 iobase = pci_resource_start(pdev, 0);
1594 mapbase = pci_resource_start(pdev, 1);
1595 priv->mapbase = mapbase;
1596 priv->iobase = iobase;
1597 priv->pdev = pdev;
1598 priv->tx_empty = 1;
1599 priv->rxbuf.buf = rxbuf;
1600 priv->rxbuf.size = PAGE_SIZE;
1601
1602 priv->fifo_size = fifosize;
1603 priv->base_baud = base_baud;
1604 priv->port_type = PORT_MAX_8250 + port_type + 1;
1605 priv->port.dev = &pdev->dev;
1606 priv->port.iobase = iobase;
1607 priv->port.membase = NULL;
1608 priv->port.mapbase = mapbase;
1609 priv->port.irq = pdev->irq;
1610 priv->port.iotype = UPIO_PORT;
1611 priv->port.ops = &pch_uart_ops;
1612 priv->port.flags = UPF_BOOT_AUTOCONF;
1613 priv->port.fifosize = fifosize;
1614 priv->port.line = board->line_no;
1615 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1616
1617 spin_lock_init(&priv->port.lock);
1618
1619 pci_set_drvdata(pdev, priv);
1620 pch_uart_hal_request(pdev, fifosize, base_baud);
1621
1622 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1623 pch_uart_ports[board->line_no] = priv;
1624 #endif
1625 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1626 if (ret < 0)
1627 goto init_port_hal_free;
1628
1629 return priv;
1630
1631 init_port_hal_free:
1632 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1633 pch_uart_ports[board->line_no] = NULL;
1634 #endif
1635 free_page((unsigned long)rxbuf);
1636 init_port_free_txbuf:
1637 kfree(priv);
1638 init_port_alloc_err:
1639
1640 return NULL;
1641 }
1642
1643 static void pch_uart_exit_port(struct eg20t_port *priv)
1644 {
1645 uart_remove_one_port(&pch_uart_driver, &priv->port);
1646 pci_set_drvdata(priv->pdev, NULL);
1647 free_page((unsigned long)priv->rxbuf.buf);
1648 }
1649
1650 static void pch_uart_pci_remove(struct pci_dev *pdev)
1651 {
1652 struct eg20t_port *priv;
1653
1654 priv = (struct eg20t_port *)pci_get_drvdata(pdev);
1655
1656 pci_disable_msi(pdev);
1657
1658 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1659 pch_uart_ports[priv->port.line] = NULL;
1660 #endif
1661 pch_uart_exit_port(priv);
1662 pci_disable_device(pdev);
1663 kfree(priv);
1664 return;
1665 }
1666 #ifdef CONFIG_PM
1667 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1668 {
1669 struct eg20t_port *priv = pci_get_drvdata(pdev);
1670
1671 uart_suspend_port(&pch_uart_driver, &priv->port);
1672
1673 pci_save_state(pdev);
1674 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1675 return 0;
1676 }
1677
1678 static int pch_uart_pci_resume(struct pci_dev *pdev)
1679 {
1680 struct eg20t_port *priv = pci_get_drvdata(pdev);
1681 int ret;
1682
1683 pci_set_power_state(pdev, PCI_D0);
1684 pci_restore_state(pdev);
1685
1686 ret = pci_enable_device(pdev);
1687 if (ret) {
1688 dev_err(&pdev->dev,
1689 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1690 return ret;
1691 }
1692
1693 uart_resume_port(&pch_uart_driver, &priv->port);
1694
1695 return 0;
1696 }
1697 #else
1698 #define pch_uart_pci_suspend NULL
1699 #define pch_uart_pci_resume NULL
1700 #endif
1701
1702 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1703 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1704 .driver_data = pch_et20t_uart0},
1705 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1706 .driver_data = pch_et20t_uart1},
1707 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1708 .driver_data = pch_et20t_uart2},
1709 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1710 .driver_data = pch_et20t_uart3},
1711 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1712 .driver_data = pch_ml7213_uart0},
1713 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1714 .driver_data = pch_ml7213_uart1},
1715 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1716 .driver_data = pch_ml7213_uart2},
1717 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1718 .driver_data = pch_ml7223_uart0},
1719 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1720 .driver_data = pch_ml7223_uart1},
1721 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1722 .driver_data = pch_ml7831_uart0},
1723 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1724 .driver_data = pch_ml7831_uart1},
1725 {0,},
1726 };
1727
1728 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
1729 const struct pci_device_id *id)
1730 {
1731 int ret;
1732 struct eg20t_port *priv;
1733
1734 ret = pci_enable_device(pdev);
1735 if (ret < 0)
1736 goto probe_error;
1737
1738 priv = pch_uart_init_port(pdev, id);
1739 if (!priv) {
1740 ret = -EBUSY;
1741 goto probe_disable_device;
1742 }
1743 pci_set_drvdata(pdev, priv);
1744
1745 return ret;
1746
1747 probe_disable_device:
1748 pci_disable_msi(pdev);
1749 pci_disable_device(pdev);
1750 probe_error:
1751 return ret;
1752 }
1753
1754 static struct pci_driver pch_uart_pci_driver = {
1755 .name = "pch_uart",
1756 .id_table = pch_uart_pci_id,
1757 .probe = pch_uart_pci_probe,
1758 .remove = __devexit_p(pch_uart_pci_remove),
1759 .suspend = pch_uart_pci_suspend,
1760 .resume = pch_uart_pci_resume,
1761 };
1762
1763 static int __init pch_uart_module_init(void)
1764 {
1765 int ret;
1766
1767 /* register as UART driver */
1768 ret = uart_register_driver(&pch_uart_driver);
1769 if (ret < 0)
1770 return ret;
1771
1772 /* register as PCI driver */
1773 ret = pci_register_driver(&pch_uart_pci_driver);
1774 if (ret < 0)
1775 uart_unregister_driver(&pch_uart_driver);
1776
1777 return ret;
1778 }
1779 module_init(pch_uart_module_init);
1780
1781 static void __exit pch_uart_module_exit(void)
1782 {
1783 pci_unregister_driver(&pch_uart_pci_driver);
1784 uart_unregister_driver(&pch_uart_driver);
1785 }
1786 module_exit(pch_uart_module_exit);
1787
1788 MODULE_LICENSE("GPL v2");
1789 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1790 module_param(default_baud, uint, S_IRUGO);